1 // SPDX-License-Identifier: GPL-2.0
3 * Pin Control driver for SuperH Pin Function Controller.
5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
7 * Copyright (C) 2008 Magnus Damm
8 * Copyright (C) 2009 - 2012 Paul Mundt
9 * Copyright (C) 2017 Marek Vasut
12 #define DRV_NAME "sh-pfc"
17 #include <dm/device_compat.h>
18 #include <dm/devres.h>
19 #include <dm/pinctrl.h>
20 #include <linux/bitops.h>
21 #include <linux/bug.h>
23 #include <linux/sizes.h>
43 struct sh_pfc_pin_config {
47 struct sh_pfc_pinctrl {
50 struct sh_pfc_pin_config *configs;
52 const char *func_prop_name;
53 const char *groups_prop_name;
54 const char *pins_prop_name;
57 struct sh_pfc_pin_range {
62 struct sh_pfc_pinctrl_priv {
64 struct sh_pfc_pinctrl pmx;
67 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
72 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
73 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
75 if (pin <= range->end)
76 return pin >= range->start
77 ? offset + pin - range->start : -1;
79 offset += range->end - range->start + 1;
85 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
87 if (enum_id < r->begin)
96 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
100 return readb(mapped_reg);
102 return readw(mapped_reg);
104 return readl(mapped_reg);
111 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
116 writeb(data, mapped_reg);
119 writew(data, mapped_reg);
122 writel(data, mapped_reg);
129 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
131 return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
134 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
136 void __iomem *unlock_reg =
137 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
139 if (pfc->info->unlock_reg)
140 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
142 sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
145 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
146 const struct pinmux_cfg_reg *crp,
148 void __iomem **mapped_regp, u32 *maskp,
153 *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
155 if (crp->field_width) {
156 *maskp = (1 << crp->field_width) - 1;
157 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
159 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
160 *posp = crp->reg_width;
161 for (k = 0; k <= in_pos; k++)
162 *posp -= crp->var_field_width[k];
166 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
167 const struct pinmux_cfg_reg *crp,
168 unsigned int field, u32 value)
170 void __iomem *mapped_reg;
171 void __iomem *unlock_reg =
172 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
176 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
178 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
179 "r_width = %u, f_width = %u\n",
180 crp->reg, value, field, crp->reg_width, crp->field_width);
182 mask = ~(mask << pos);
183 value = value << pos;
185 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
189 if (pfc->info->unlock_reg)
190 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
192 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
195 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
196 const struct pinmux_cfg_reg **crp,
197 unsigned int *fieldp, u32 *valuep)
202 const struct pinmux_cfg_reg *config_reg =
203 pfc->info->cfg_regs + k;
204 unsigned int r_width = config_reg->reg_width;
205 unsigned int f_width = config_reg->field_width;
206 unsigned int curr_width;
207 unsigned int bit_pos;
208 unsigned int pos = 0;
214 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
219 curr_width = f_width;
221 curr_width = config_reg->var_field_width[m];
223 ncomb = 1 << curr_width;
224 for (n = 0; n < ncomb; n++) {
225 if (config_reg->enum_ids[pos + n] == enum_id) {
241 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
244 const u16 *data = pfc->info->pinmux_data;
248 *enum_idp = data[pos + 1];
252 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
253 if (data[k] == mark) {
254 *enum_idp = data[k + 1];
259 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
264 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
266 const struct pinmux_range *range;
269 switch (pinmux_type) {
270 case PINMUX_TYPE_GPIO:
271 case PINMUX_TYPE_FUNCTION:
275 case PINMUX_TYPE_OUTPUT:
276 range = &pfc->info->output;
279 case PINMUX_TYPE_INPUT:
280 range = &pfc->info->input;
287 /* Iterate over all the configuration fields we need to update. */
289 const struct pinmux_cfg_reg *cr;
296 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
303 /* Check if the configuration field selects a function. If it
304 * doesn't, skip the field if it's not applicable to the
305 * requested pinmux type.
307 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
309 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
310 /* Functions are allowed to modify all
314 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
315 /* Input/output types can only modify fields
316 * that correspond to their respective ranges.
318 in_range = sh_pfc_enum_in_range(enum_id, range);
321 * special case pass through for fixed
322 * input-only or output-only pins without
323 * function enum register association.
325 if (in_range && enum_id == range->force)
328 /* GPIOs are only allowed to modify function fields. */
334 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
338 sh_pfc_write_config_reg(pfc, cr, field, value);
344 const struct pinmux_bias_reg *
345 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
350 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
351 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
352 if (pfc->info->bias_regs[i].pins[j] == pin) {
354 return &pfc->info->bias_regs[i];
359 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
364 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
366 struct sh_pfc_pin_range *range;
367 unsigned int nr_ranges;
370 if (pfc->info->pins[0].pin == (u16)-1) {
371 /* Pin number -1 denotes that the SoC doesn't report pin numbers
372 * in its pin arrays yet. Consider the pin numbers range as
373 * continuous and allocate a single range.
376 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
377 if (pfc->ranges == NULL)
380 pfc->ranges->start = 0;
381 pfc->ranges->end = pfc->info->nr_pins - 1;
382 pfc->nr_gpio_pins = pfc->info->nr_pins;
387 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
388 * be sorted by pin numbers, and pins without a GPIO port must come
391 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
392 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
396 pfc->nr_ranges = nr_ranges;
397 pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
398 if (pfc->ranges == NULL)
402 range->start = pfc->info->pins[0].pin;
404 for (i = 1; i < pfc->info->nr_pins; ++i) {
405 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
408 range->end = pfc->info->pins[i-1].pin;
409 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
410 pfc->nr_gpio_pins = range->end + 1;
413 range->start = pfc->info->pins[i].pin;
416 range->end = pfc->info->pins[i-1].pin;
417 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
418 pfc->nr_gpio_pins = range->end + 1;
423 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
425 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
427 return priv->pfc.info->nr_pins;
430 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
433 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
435 return priv->pfc.info->pins[selector].name;
438 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
440 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
442 return priv->pfc.info->nr_groups;
445 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
448 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
450 return priv->pfc.info->groups[selector].name;
453 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
455 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
457 return priv->pfc.info->nr_functions;
460 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
463 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
465 return priv->pfc.info->functions[selector].name;
468 static int sh_pfc_gpio_request_enable(struct udevice *dev,
469 unsigned pin_selector)
471 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
472 struct sh_pfc_pinctrl *pmx = &priv->pmx;
473 struct sh_pfc *pfc = &priv->pfc;
474 struct sh_pfc_pin_config *cfg;
475 const struct sh_pfc_pin *pin = NULL;
478 for (i = 0; i < pfc->info->nr_pins; i++) {
479 if (priv->pfc.info->pins[i].pin != pin_selector)
482 pin = &priv->pfc.info->pins[i];
489 idx = sh_pfc_get_pin_index(pfc, pin->pin);
490 cfg = &pmx->configs[idx];
492 if (cfg->type != PINMUX_TYPE_NONE)
495 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
499 cfg->type = PINMUX_TYPE_GPIO;
504 static int sh_pfc_gpio_disable_free(struct udevice *dev,
505 unsigned pin_selector)
507 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
508 struct sh_pfc_pinctrl *pmx = &priv->pmx;
509 struct sh_pfc *pfc = &priv->pfc;
510 struct sh_pfc_pin_config *cfg;
511 const struct sh_pfc_pin *pin = NULL;
514 for (i = 0; i < pfc->info->nr_pins; i++) {
515 if (priv->pfc.info->pins[i].pin != pin_selector)
518 pin = &priv->pfc.info->pins[i];
525 idx = sh_pfc_get_pin_index(pfc, pin->pin);
526 cfg = &pmx->configs[idx];
528 cfg->type = PINMUX_TYPE_NONE;
533 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
534 unsigned func_selector)
536 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
537 struct sh_pfc_pinctrl *pmx = &priv->pmx;
538 struct sh_pfc *pfc = &priv->pfc;
539 const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
540 int idx = sh_pfc_get_pin_index(pfc, pin->pin);
541 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
543 if (cfg->type != PINMUX_TYPE_NONE)
546 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
549 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
550 unsigned func_selector)
552 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
553 struct sh_pfc_pinctrl *pmx = &priv->pmx;
554 struct sh_pfc *pfc = &priv->pfc;
555 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
559 for (i = 0; i < grp->nr_pins; ++i) {
560 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
561 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
563 if (cfg->type != PINMUX_TYPE_NONE) {
569 for (i = 0; i < grp->nr_pins; ++i) {
570 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
578 #if CONFIG_IS_ENABLED(PINCONF)
579 static const struct pinconf_param sh_pfc_pinconf_params[] = {
580 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
581 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
582 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
583 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
584 { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 },
587 static void __iomem *
588 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
589 unsigned int *offset, unsigned int *size)
591 const struct pinmux_drive_reg_field *field;
592 const struct pinmux_drive_reg *reg;
595 for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
596 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
597 field = ®->fields[i];
599 if (field->size && field->pin == pin) {
600 *offset = field->offset;
603 return (void __iomem *)(uintptr_t)reg->reg;
611 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
612 unsigned int pin, u16 strength)
618 void __iomem *unlock_reg =
619 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
622 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
626 step = size == 2 ? 6 : 3;
628 if (strength < step || strength > 24)
631 /* Convert the value from mA based on a full drive strength value of
632 * 24mA. We can make the full value configurable later if needed.
634 strength = strength / step - 1;
636 val = sh_pfc_read_raw_reg(reg, 32);
637 val &= ~GENMASK(offset + 4 - 1, offset);
638 val |= strength << offset;
641 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
643 sh_pfc_write_raw_reg(reg, 32, val);
648 /* Check whether the requested parameter is supported for a pin. */
649 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
652 int idx = sh_pfc_get_pin_index(pfc, _pin);
653 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
656 case PIN_CONFIG_BIAS_DISABLE:
657 return pin->configs &
658 (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
660 case PIN_CONFIG_BIAS_PULL_UP:
661 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
663 case PIN_CONFIG_BIAS_PULL_DOWN:
664 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
666 case PIN_CONFIG_DRIVE_STRENGTH:
667 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
669 case PIN_CONFIG_POWER_SOURCE:
670 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
677 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
678 unsigned int param, unsigned int arg)
680 struct sh_pfc *pfc = pmx->pfc;
681 void __iomem *pocctrl;
682 void __iomem *unlock_reg =
683 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
687 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
691 case PIN_CONFIG_BIAS_PULL_UP:
692 case PIN_CONFIG_BIAS_PULL_DOWN:
693 case PIN_CONFIG_BIAS_DISABLE:
694 if (!pfc->info->ops || !pfc->info->ops->set_bias)
697 pfc->info->ops->set_bias(pfc, _pin, param);
701 case PIN_CONFIG_DRIVE_STRENGTH:
702 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
708 case PIN_CONFIG_POWER_SOURCE:
709 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
712 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
714 printf("invalid pin %#x", _pin);
718 if (arg != 1800 && arg != 3300)
721 pocctrl = (void __iomem *)(uintptr_t)addr;
723 val = sh_pfc_read_raw_reg(pocctrl, 32);
730 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
732 sh_pfc_write_raw_reg(pocctrl, 32, val);
743 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
744 unsigned int pin_selector,
745 unsigned int param, unsigned int arg)
747 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
748 struct sh_pfc_pinctrl *pmx = &priv->pmx;
749 struct sh_pfc *pfc = &priv->pfc;
750 const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
752 sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
757 static int sh_pfc_pinconf_group_set(struct udevice *dev,
758 unsigned int group_selector,
759 unsigned int param, unsigned int arg)
761 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
762 struct sh_pfc_pinctrl *pmx = &priv->pmx;
763 struct sh_pfc *pfc = &priv->pfc;
764 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
767 for (i = 0; i < grp->nr_pins; i++)
768 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
774 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
775 .get_pins_count = sh_pfc_pinctrl_get_pins_count,
776 .get_pin_name = sh_pfc_pinctrl_get_pin_name,
777 .get_groups_count = sh_pfc_pinctrl_get_groups_count,
778 .get_group_name = sh_pfc_pinctrl_get_group_name,
779 .get_functions_count = sh_pfc_pinctrl_get_functions_count,
780 .get_function_name = sh_pfc_pinctrl_get_function_name,
782 #if CONFIG_IS_ENABLED(PINCONF)
783 .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
784 .pinconf_params = sh_pfc_pinconf_params,
785 .pinconf_set = sh_pfc_pinconf_pin_set,
786 .pinconf_group_set = sh_pfc_pinconf_group_set,
788 .pinmux_set = sh_pfc_pinctrl_pin_set,
789 .pinmux_group_set = sh_pfc_pinctrl_group_set,
790 .set_state = pinctrl_generic_set_state,
792 .gpio_request_enable = sh_pfc_gpio_request_enable,
793 .gpio_disable_free = sh_pfc_gpio_disable_free,
796 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
800 /* Allocate and initialize the pins and configs arrays. */
801 pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
803 if (unlikely(!pmx->configs))
806 for (i = 0; i < pfc->info->nr_pins; ++i) {
807 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
808 cfg->type = PINMUX_TYPE_NONE;
815 static int sh_pfc_pinctrl_probe(struct udevice *dev)
817 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
818 enum sh_pfc_model model = dev_get_driver_data(dev);
821 base = dev_read_addr(dev);
822 if (base == FDT_ADDR_T_NONE)
825 priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
829 #ifdef CONFIG_PINCTRL_PFC_R8A7790
830 if (model == SH_PFC_R8A7790)
831 priv->pfc.info = &r8a7790_pinmux_info;
833 #ifdef CONFIG_PINCTRL_PFC_R8A7791
834 if (model == SH_PFC_R8A7791)
835 priv->pfc.info = &r8a7791_pinmux_info;
837 #ifdef CONFIG_PINCTRL_PFC_R8A7792
838 if (model == SH_PFC_R8A7792)
839 priv->pfc.info = &r8a7792_pinmux_info;
841 #ifdef CONFIG_PINCTRL_PFC_R8A7793
842 if (model == SH_PFC_R8A7793)
843 priv->pfc.info = &r8a7793_pinmux_info;
845 #ifdef CONFIG_PINCTRL_PFC_R8A7794
846 if (model == SH_PFC_R8A7794)
847 priv->pfc.info = &r8a7794_pinmux_info;
849 #ifdef CONFIG_PINCTRL_PFC_R8A7795
850 if (model == SH_PFC_R8A7795)
851 priv->pfc.info = &r8a7795_pinmux_info;
853 #ifdef CONFIG_PINCTRL_PFC_R8A7796
854 if (model == SH_PFC_R8A7796)
855 priv->pfc.info = &r8a7796_pinmux_info;
857 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
858 if (model == SH_PFC_R8A774A1)
859 priv->pfc.info = &r8a774a1_pinmux_info;
861 #ifdef CONFIG_PINCTRL_PFC_R8A77965
862 if (model == SH_PFC_R8A77965)
863 priv->pfc.info = &r8a77965_pinmux_info;
865 #ifdef CONFIG_PINCTRL_PFC_R8A77970
866 if (model == SH_PFC_R8A77970)
867 priv->pfc.info = &r8a77970_pinmux_info;
869 #ifdef CONFIG_PINCTRL_PFC_R8A77980
870 if (model == SH_PFC_R8A77980)
871 priv->pfc.info = &r8a77980_pinmux_info;
873 #ifdef CONFIG_PINCTRL_PFC_R8A77990
874 if (model == SH_PFC_R8A77990)
875 priv->pfc.info = &r8a77990_pinmux_info;
877 #ifdef CONFIG_PINCTRL_PFC_R8A77995
878 if (model == SH_PFC_R8A77995)
879 priv->pfc.info = &r8a77995_pinmux_info;
882 priv->pmx.pfc = &priv->pfc;
883 sh_pfc_init_ranges(&priv->pfc);
884 sh_pfc_map_pins(&priv->pfc, &priv->pmx);
889 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
890 #ifdef CONFIG_PINCTRL_PFC_R8A7790
892 .compatible = "renesas,pfc-r8a7790",
893 .data = SH_PFC_R8A7790,
896 #ifdef CONFIG_PINCTRL_PFC_R8A7791
898 .compatible = "renesas,pfc-r8a7791",
899 .data = SH_PFC_R8A7791,
902 #ifdef CONFIG_PINCTRL_PFC_R8A7792
904 .compatible = "renesas,pfc-r8a7792",
905 .data = SH_PFC_R8A7792,
908 #ifdef CONFIG_PINCTRL_PFC_R8A7793
910 .compatible = "renesas,pfc-r8a7793",
911 .data = SH_PFC_R8A7793,
914 #ifdef CONFIG_PINCTRL_PFC_R8A7794
916 .compatible = "renesas,pfc-r8a7794",
917 .data = SH_PFC_R8A7794,
920 #ifdef CONFIG_PINCTRL_PFC_R8A7795
922 .compatible = "renesas,pfc-r8a7795",
923 .data = SH_PFC_R8A7795,
926 #ifdef CONFIG_PINCTRL_PFC_R8A7796
928 .compatible = "renesas,pfc-r8a7796",
929 .data = SH_PFC_R8A7796,
932 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
934 .compatible = "renesas,pfc-r8a774a1",
935 .data = SH_PFC_R8A774A1,
938 #ifdef CONFIG_PINCTRL_PFC_R8A77965
940 .compatible = "renesas,pfc-r8a77965",
941 .data = SH_PFC_R8A77965,
944 #ifdef CONFIG_PINCTRL_PFC_R8A77970
946 .compatible = "renesas,pfc-r8a77970",
947 .data = SH_PFC_R8A77970,
950 #ifdef CONFIG_PINCTRL_PFC_R8A77980
952 .compatible = "renesas,pfc-r8a77980",
953 .data = SH_PFC_R8A77980,
956 #ifdef CONFIG_PINCTRL_PFC_R8A77990
958 .compatible = "renesas,pfc-r8a77990",
959 .data = SH_PFC_R8A77990,
962 #ifdef CONFIG_PINCTRL_PFC_R8A77995
964 .compatible = "renesas,pfc-r8a77995",
965 .data = SH_PFC_R8A77995,
971 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
972 .name = "sh_pfc_pinctrl",
973 .id = UCLASS_PINCTRL,
974 .of_match = sh_pfc_pinctrl_ids,
975 .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
976 .ops = &sh_pfc_pinctrl_ops,
977 .probe = sh_pfc_pinctrl_probe,