1 // SPDX-License-Identifier: GPL-2.0
3 * Pin Control driver for SuperH Pin Function Controller.
5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
7 * Copyright (C) 2008 Magnus Damm
8 * Copyright (C) 2009 - 2012 Paul Mundt
9 * Copyright (C) 2017 Marek Vasut
12 #define DRV_NAME "sh-pfc"
17 #include <dm/device_compat.h>
18 #include <dm/devres.h>
19 #include <dm/pinctrl.h>
20 #include <linux/bitops.h>
21 #include <linux/bug.h>
23 #include <linux/sizes.h>
45 struct sh_pfc_pin_config {
49 struct sh_pfc_pinctrl {
52 struct sh_pfc_pin_config *configs;
55 struct sh_pfc_pin_range {
60 struct sh_pfc_pinctrl_priv {
62 struct sh_pfc_pinctrl pmx;
65 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
70 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
71 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
73 if (pin <= range->end)
74 return pin >= range->start
75 ? offset + pin - range->start : -1;
77 offset += range->end - range->start + 1;
83 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
85 if (enum_id < r->begin)
94 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
98 return readb(mapped_reg);
100 return readw(mapped_reg);
102 return readl(mapped_reg);
109 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
114 writeb(data, mapped_reg);
117 writew(data, mapped_reg);
120 writel(data, mapped_reg);
127 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
129 return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
132 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
134 void __iomem *unlock_reg =
135 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
137 if (pfc->info->unlock_reg)
138 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
140 sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
143 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
144 const struct pinmux_cfg_reg *crp,
146 void __iomem **mapped_regp, u32 *maskp,
151 *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
153 if (crp->field_width) {
154 *maskp = (1 << crp->field_width) - 1;
155 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
157 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
158 *posp = crp->reg_width;
159 for (k = 0; k <= in_pos; k++)
160 *posp -= crp->var_field_width[k];
164 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
165 const struct pinmux_cfg_reg *crp,
166 unsigned int field, u32 value)
168 void __iomem *mapped_reg;
169 void __iomem *unlock_reg =
170 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
174 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
176 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
177 "r_width = %u, f_width = %u\n",
178 crp->reg, value, field, crp->reg_width, crp->field_width);
180 mask = ~(mask << pos);
181 value = value << pos;
183 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
187 if (pfc->info->unlock_reg)
188 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
190 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
193 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
194 const struct pinmux_cfg_reg **crp,
195 unsigned int *fieldp, u32 *valuep)
200 const struct pinmux_cfg_reg *config_reg =
201 pfc->info->cfg_regs + k;
202 unsigned int r_width = config_reg->reg_width;
203 unsigned int f_width = config_reg->field_width;
204 unsigned int curr_width;
205 unsigned int bit_pos;
206 unsigned int pos = 0;
212 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
217 curr_width = f_width;
219 curr_width = config_reg->var_field_width[m];
221 ncomb = 1 << curr_width;
222 for (n = 0; n < ncomb; n++) {
223 if (config_reg->enum_ids[pos + n] == enum_id) {
239 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
242 const u16 *data = pfc->info->pinmux_data;
246 *enum_idp = data[pos + 1];
250 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
251 if (data[k] == mark) {
252 *enum_idp = data[k + 1];
257 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
262 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
264 const struct pinmux_range *range;
267 switch (pinmux_type) {
268 case PINMUX_TYPE_GPIO:
269 case PINMUX_TYPE_FUNCTION:
273 case PINMUX_TYPE_OUTPUT:
274 range = &pfc->info->output;
277 case PINMUX_TYPE_INPUT:
278 range = &pfc->info->input;
285 /* Iterate over all the configuration fields we need to update. */
287 const struct pinmux_cfg_reg *cr;
294 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
301 /* Check if the configuration field selects a function. If it
302 * doesn't, skip the field if it's not applicable to the
303 * requested pinmux type.
305 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
307 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
308 /* Functions are allowed to modify all
312 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
313 /* Input/output types can only modify fields
314 * that correspond to their respective ranges.
316 in_range = sh_pfc_enum_in_range(enum_id, range);
319 * special case pass through for fixed
320 * input-only or output-only pins without
321 * function enum register association.
323 if (in_range && enum_id == range->force)
326 /* GPIOs are only allowed to modify function fields. */
332 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
336 sh_pfc_write_config_reg(pfc, cr, field, value);
342 const struct pinmux_bias_reg *
343 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
348 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
349 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
350 if (pfc->info->bias_regs[i].pins[j] == pin) {
352 return &pfc->info->bias_regs[i];
357 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
362 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
364 struct sh_pfc_pin_range *range;
365 unsigned int nr_ranges;
368 if (pfc->info->pins[0].pin == (u16)-1) {
369 /* Pin number -1 denotes that the SoC doesn't report pin numbers
370 * in its pin arrays yet. Consider the pin numbers range as
371 * continuous and allocate a single range.
374 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
375 if (pfc->ranges == NULL)
378 pfc->ranges->start = 0;
379 pfc->ranges->end = pfc->info->nr_pins - 1;
380 pfc->nr_gpio_pins = pfc->info->nr_pins;
385 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
386 * be sorted by pin numbers, and pins without a GPIO port must come
389 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
390 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
394 pfc->nr_ranges = nr_ranges;
395 pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
396 if (pfc->ranges == NULL)
400 range->start = pfc->info->pins[0].pin;
402 for (i = 1; i < pfc->info->nr_pins; ++i) {
403 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
406 range->end = pfc->info->pins[i-1].pin;
407 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
408 pfc->nr_gpio_pins = range->end + 1;
411 range->start = pfc->info->pins[i].pin;
414 range->end = pfc->info->pins[i-1].pin;
415 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
416 pfc->nr_gpio_pins = range->end + 1;
421 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
423 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
425 return priv->pfc.info->nr_pins;
428 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
431 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
433 return priv->pfc.info->pins[selector].name;
436 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
438 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
440 return priv->pfc.info->nr_groups;
443 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
446 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
448 return priv->pfc.info->groups[selector].name;
451 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
453 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
455 return priv->pfc.info->nr_functions;
458 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
461 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
463 return priv->pfc.info->functions[selector].name;
466 static int sh_pfc_gpio_request_enable(struct udevice *dev,
467 unsigned pin_selector)
469 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
470 struct sh_pfc_pinctrl *pmx = &priv->pmx;
471 struct sh_pfc *pfc = &priv->pfc;
472 struct sh_pfc_pin_config *cfg;
473 const struct sh_pfc_pin *pin = NULL;
476 for (i = 0; i < pfc->info->nr_pins; i++) {
477 if (priv->pfc.info->pins[i].pin != pin_selector)
480 pin = &priv->pfc.info->pins[i];
487 idx = sh_pfc_get_pin_index(pfc, pin->pin);
488 cfg = &pmx->configs[idx];
490 if (cfg->type != PINMUX_TYPE_NONE)
493 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
497 cfg->type = PINMUX_TYPE_GPIO;
502 static int sh_pfc_gpio_disable_free(struct udevice *dev,
503 unsigned pin_selector)
505 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
506 struct sh_pfc_pinctrl *pmx = &priv->pmx;
507 struct sh_pfc *pfc = &priv->pfc;
508 struct sh_pfc_pin_config *cfg;
509 const struct sh_pfc_pin *pin = NULL;
512 for (i = 0; i < pfc->info->nr_pins; i++) {
513 if (priv->pfc.info->pins[i].pin != pin_selector)
516 pin = &priv->pfc.info->pins[i];
523 idx = sh_pfc_get_pin_index(pfc, pin->pin);
524 cfg = &pmx->configs[idx];
526 cfg->type = PINMUX_TYPE_NONE;
531 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
532 unsigned func_selector)
534 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
535 struct sh_pfc_pinctrl *pmx = &priv->pmx;
536 struct sh_pfc *pfc = &priv->pfc;
537 const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
538 int idx = sh_pfc_get_pin_index(pfc, pin->pin);
539 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
541 if (cfg->type != PINMUX_TYPE_NONE)
544 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
547 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
548 unsigned func_selector)
550 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
551 struct sh_pfc_pinctrl *pmx = &priv->pmx;
552 struct sh_pfc *pfc = &priv->pfc;
553 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
557 for (i = 0; i < grp->nr_pins; ++i) {
558 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
559 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
561 if (cfg->type != PINMUX_TYPE_NONE) {
567 for (i = 0; i < grp->nr_pins; ++i) {
568 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
576 #if CONFIG_IS_ENABLED(PINCONF)
577 static const struct pinconf_param sh_pfc_pinconf_params[] = {
578 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
579 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
580 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
581 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
582 { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 },
585 static void __iomem *
586 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
587 unsigned int *offset, unsigned int *size)
589 const struct pinmux_drive_reg_field *field;
590 const struct pinmux_drive_reg *reg;
593 for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
594 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
595 field = ®->fields[i];
597 if (field->size && field->pin == pin) {
598 *offset = field->offset;
601 return (void __iomem *)(uintptr_t)reg->reg;
609 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
610 unsigned int pin, u16 strength)
616 void __iomem *unlock_reg =
617 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
620 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
624 step = size == 2 ? 6 : 3;
626 if (strength < step || strength > 24)
629 /* Convert the value from mA based on a full drive strength value of
630 * 24mA. We can make the full value configurable later if needed.
632 strength = strength / step - 1;
634 val = sh_pfc_read_raw_reg(reg, 32);
635 val &= ~GENMASK(offset + 4 - 1, offset);
636 val |= strength << offset;
639 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
641 sh_pfc_write_raw_reg(reg, 32, val);
646 /* Check whether the requested parameter is supported for a pin. */
647 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
650 int idx = sh_pfc_get_pin_index(pfc, _pin);
651 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
654 case PIN_CONFIG_BIAS_DISABLE:
655 return pin->configs &
656 (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
658 case PIN_CONFIG_BIAS_PULL_UP:
659 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
661 case PIN_CONFIG_BIAS_PULL_DOWN:
662 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
664 case PIN_CONFIG_DRIVE_STRENGTH:
665 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
667 case PIN_CONFIG_POWER_SOURCE:
668 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
675 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
676 unsigned int param, unsigned int arg)
678 struct sh_pfc *pfc = pmx->pfc;
679 void __iomem *pocctrl;
680 void __iomem *unlock_reg =
681 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
685 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
689 case PIN_CONFIG_BIAS_PULL_UP:
690 case PIN_CONFIG_BIAS_PULL_DOWN:
691 case PIN_CONFIG_BIAS_DISABLE:
692 if (!pfc->info->ops || !pfc->info->ops->set_bias)
695 pfc->info->ops->set_bias(pfc, _pin, param);
699 case PIN_CONFIG_DRIVE_STRENGTH:
700 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
706 case PIN_CONFIG_POWER_SOURCE:
707 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
710 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
712 printf("invalid pin %#x", _pin);
716 if (arg != 1800 && arg != 3300)
719 pocctrl = (void __iomem *)(uintptr_t)addr;
721 val = sh_pfc_read_raw_reg(pocctrl, 32);
728 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
730 sh_pfc_write_raw_reg(pocctrl, 32, val);
741 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
742 unsigned int pin_selector,
743 unsigned int param, unsigned int arg)
745 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
746 struct sh_pfc_pinctrl *pmx = &priv->pmx;
747 struct sh_pfc *pfc = &priv->pfc;
748 const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
750 sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
755 static int sh_pfc_pinconf_group_set(struct udevice *dev,
756 unsigned int group_selector,
757 unsigned int param, unsigned int arg)
759 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
760 struct sh_pfc_pinctrl *pmx = &priv->pmx;
761 struct sh_pfc *pfc = &priv->pfc;
762 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
765 for (i = 0; i < grp->nr_pins; i++)
766 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
772 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
773 .get_pins_count = sh_pfc_pinctrl_get_pins_count,
774 .get_pin_name = sh_pfc_pinctrl_get_pin_name,
775 .get_groups_count = sh_pfc_pinctrl_get_groups_count,
776 .get_group_name = sh_pfc_pinctrl_get_group_name,
777 .get_functions_count = sh_pfc_pinctrl_get_functions_count,
778 .get_function_name = sh_pfc_pinctrl_get_function_name,
780 #if CONFIG_IS_ENABLED(PINCONF)
781 .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
782 .pinconf_params = sh_pfc_pinconf_params,
783 .pinconf_set = sh_pfc_pinconf_pin_set,
784 .pinconf_group_set = sh_pfc_pinconf_group_set,
786 .pinmux_set = sh_pfc_pinctrl_pin_set,
787 .pinmux_group_set = sh_pfc_pinctrl_group_set,
788 .set_state = pinctrl_generic_set_state,
790 .gpio_request_enable = sh_pfc_gpio_request_enable,
791 .gpio_disable_free = sh_pfc_gpio_disable_free,
794 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
798 /* Allocate and initialize the pins and configs arrays. */
799 pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
801 if (unlikely(!pmx->configs))
804 for (i = 0; i < pfc->info->nr_pins; ++i) {
805 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
806 cfg->type = PINMUX_TYPE_NONE;
813 static int sh_pfc_pinctrl_probe(struct udevice *dev)
815 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
816 enum sh_pfc_model model = dev_get_driver_data(dev);
819 base = dev_read_addr(dev);
820 if (base == FDT_ADDR_T_NONE)
823 priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
827 #ifdef CONFIG_PINCTRL_PFC_R8A7790
828 if (model == SH_PFC_R8A7790)
829 priv->pfc.info = &r8a7790_pinmux_info;
831 #ifdef CONFIG_PINCTRL_PFC_R8A7791
832 if (model == SH_PFC_R8A7791)
833 priv->pfc.info = &r8a7791_pinmux_info;
835 #ifdef CONFIG_PINCTRL_PFC_R8A7792
836 if (model == SH_PFC_R8A7792)
837 priv->pfc.info = &r8a7792_pinmux_info;
839 #ifdef CONFIG_PINCTRL_PFC_R8A7793
840 if (model == SH_PFC_R8A7793)
841 priv->pfc.info = &r8a7793_pinmux_info;
843 #ifdef CONFIG_PINCTRL_PFC_R8A7794
844 if (model == SH_PFC_R8A7794)
845 priv->pfc.info = &r8a7794_pinmux_info;
847 #ifdef CONFIG_PINCTRL_PFC_R8A7795
848 if (model == SH_PFC_R8A7795)
849 priv->pfc.info = &r8a7795_pinmux_info;
851 #ifdef CONFIG_PINCTRL_PFC_R8A7796
852 if (model == SH_PFC_R8A7796)
853 priv->pfc.info = &r8a7796_pinmux_info;
855 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
856 if (model == SH_PFC_R8A774A1)
857 priv->pfc.info = &r8a774a1_pinmux_info;
859 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
860 if (model == SH_PFC_R8A774B1)
861 priv->pfc.info = &r8a774b1_pinmux_info;
863 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
864 if (model == SH_PFC_R8A774E1)
865 priv->pfc.info = &r8a774e1_pinmux_info;
867 #ifdef CONFIG_PINCTRL_PFC_R8A77965
868 if (model == SH_PFC_R8A77965)
869 priv->pfc.info = &r8a77965_pinmux_info;
871 #ifdef CONFIG_PINCTRL_PFC_R8A77970
872 if (model == SH_PFC_R8A77970)
873 priv->pfc.info = &r8a77970_pinmux_info;
875 #ifdef CONFIG_PINCTRL_PFC_R8A77980
876 if (model == SH_PFC_R8A77980)
877 priv->pfc.info = &r8a77980_pinmux_info;
879 #ifdef CONFIG_PINCTRL_PFC_R8A77990
880 if (model == SH_PFC_R8A77990)
881 priv->pfc.info = &r8a77990_pinmux_info;
883 #ifdef CONFIG_PINCTRL_PFC_R8A77995
884 if (model == SH_PFC_R8A77995)
885 priv->pfc.info = &r8a77995_pinmux_info;
888 priv->pmx.pfc = &priv->pfc;
889 sh_pfc_init_ranges(&priv->pfc);
890 sh_pfc_map_pins(&priv->pfc, &priv->pmx);
895 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
896 #ifdef CONFIG_PINCTRL_PFC_R8A7790
898 .compatible = "renesas,pfc-r8a7790",
899 .data = SH_PFC_R8A7790,
902 #ifdef CONFIG_PINCTRL_PFC_R8A7791
904 .compatible = "renesas,pfc-r8a7791",
905 .data = SH_PFC_R8A7791,
908 #ifdef CONFIG_PINCTRL_PFC_R8A7792
910 .compatible = "renesas,pfc-r8a7792",
911 .data = SH_PFC_R8A7792,
914 #ifdef CONFIG_PINCTRL_PFC_R8A7793
916 .compatible = "renesas,pfc-r8a7793",
917 .data = SH_PFC_R8A7793,
920 #ifdef CONFIG_PINCTRL_PFC_R8A7794
922 .compatible = "renesas,pfc-r8a7794",
923 .data = SH_PFC_R8A7794,
926 #ifdef CONFIG_PINCTRL_PFC_R8A7795
928 .compatible = "renesas,pfc-r8a7795",
929 .data = SH_PFC_R8A7795,
932 #ifdef CONFIG_PINCTRL_PFC_R8A7796
934 .compatible = "renesas,pfc-r8a7796",
935 .data = SH_PFC_R8A7796,
938 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
940 .compatible = "renesas,pfc-r8a774a1",
941 .data = SH_PFC_R8A774A1,
944 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
946 .compatible = "renesas,pfc-r8a774b1",
947 .data = SH_PFC_R8A774B1,
950 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
952 .compatible = "renesas,pfc-r8a774e1",
953 .data = SH_PFC_R8A774E1,
956 #ifdef CONFIG_PINCTRL_PFC_R8A77965
958 .compatible = "renesas,pfc-r8a77965",
959 .data = SH_PFC_R8A77965,
962 #ifdef CONFIG_PINCTRL_PFC_R8A77970
964 .compatible = "renesas,pfc-r8a77970",
965 .data = SH_PFC_R8A77970,
968 #ifdef CONFIG_PINCTRL_PFC_R8A77980
970 .compatible = "renesas,pfc-r8a77980",
971 .data = SH_PFC_R8A77980,
974 #ifdef CONFIG_PINCTRL_PFC_R8A77990
976 .compatible = "renesas,pfc-r8a77990",
977 .data = SH_PFC_R8A77990,
980 #ifdef CONFIG_PINCTRL_PFC_R8A77995
982 .compatible = "renesas,pfc-r8a77995",
983 .data = SH_PFC_R8A77995,
989 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
990 .name = "sh_pfc_pinctrl",
991 .id = UCLASS_PINCTRL,
992 .of_match = sh_pfc_pinctrl_ids,
993 .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
994 .ops = &sh_pfc_pinctrl_ops,
995 .probe = sh_pfc_pinctrl_probe,