drivers/pinctrl/renesas/pfc.c

   1 /*
   2  * Pin Control driver for SuperH Pin Function Controller.
   3  *
   4  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   5  *
   6  * Copyright (C) 2008 Magnus Damm
   7  * Copyright (C) 2009 - 2012 Paul Mundt
   8  * Copyright (C) 2017 Marek Vasut
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0
  11  */
  12
  13 #define DRV_NAME "sh-pfc"
  14
  15 #include <common.h>
  16 #include <dm.h>
  17 #include <errno.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/io.h>
  20 #include <linux/sizes.h>
  21
  22 #include "sh_pfc.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 enum sh_pfc_model {
  27         SH_PFC_R8A7790 = 0,
  28         SH_PFC_R8A7795,
  29         SH_PFC_R8A7796,
  30         SH_PFC_R8A77970,
  31         SH_PFC_R8A77995,
  32 };
  33
  34 struct sh_pfc_pin_config {
  35         u32 type;
  36 };
  37
  38 struct sh_pfc_pinctrl {
  39         struct sh_pfc *pfc;
  40
  41         struct sh_pfc_pin_config *configs;
  42
  43         const char *func_prop_name;
  44         const char *groups_prop_name;
  45         const char *pins_prop_name;
  46 };
  47
  48 struct sh_pfc_pin_range {
  49         u16 start;
  50         u16 end;
  51 };
  52
  53 struct sh_pfc_pinctrl_priv {
  54         struct sh_pfc                   pfc;
  55         struct sh_pfc_pinctrl           pmx;
  56 };
  57
  58 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
  59 {
  60         unsigned int offset;
  61         unsigned int i;
  62
  63         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
  64                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
  65
  66                 if (pin <= range->end)
  67                         return pin >= range->start
  68                              ? offset + pin - range->start : -1;
  69
  70                 offset += range->end - range->start + 1;
  71         }
  72
  73         return -EINVAL;
  74 }
  75
  76 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
  77 {
  78         if (enum_id < r->begin)
  79                 return 0;
  80
  81         if (enum_id > r->end)
  82                 return 0;
  83
  84         return 1;
  85 }
  86
  87 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
  88 {
  89         switch (reg_width) {
  90         case 8:
  91                 return readb(mapped_reg);
  92         case 16:
  93                 return readw(mapped_reg);
  94         case 32:
  95                 return readl(mapped_reg);
  96         }
  97
  98         BUG();
  99         return 0;
 100 }
 101
 102 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 103                           u32 data)
 104 {
 105         switch (reg_width) {
 106         case 8:
 107                 writeb(data, mapped_reg);
 108                 return;
 109         case 16:
 110                 writew(data, mapped_reg);
 111                 return;
 112         case 32:
 113                 writel(data, mapped_reg);
 114                 return;
 115         }
 116
 117         BUG();
 118 }
 119
 120 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
 121 {
 122         return sh_pfc_read_raw_reg(pfc->regs + reg, width);
 123 }
 124
 125 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
 126 {
 127         void __iomem *unlock_reg =
 128                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 129
 130         if (pfc->info->unlock_reg)
 131                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 132
 133         sh_pfc_write_raw_reg(pfc->regs + reg, width, data);
 134 }
 135
 136 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 137                                      const struct pinmux_cfg_reg *crp,
 138                                      unsigned int in_pos,
 139                                      void __iomem **mapped_regp, u32 *maskp,
 140                                      unsigned int *posp)
 141 {
 142         unsigned int k;
 143
 144         *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
 145
 146         if (crp->field_width) {
 147                 *maskp = (1 << crp->field_width) - 1;
 148                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 149         } else {
 150                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 151                 *posp = crp->reg_width;
 152                 for (k = 0; k <= in_pos; k++)
 153                         *posp -= crp->var_field_width[k];
 154         }
 155 }
 156
 157 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 158                                     const struct pinmux_cfg_reg *crp,
 159                                     unsigned int field, u32 value)
 160 {
 161         void __iomem *mapped_reg;
 162         void __iomem *unlock_reg =
 163                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 164         unsigned int pos;
 165         u32 mask, data;
 166
 167         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 168
 169         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 170                 "r_width = %u, f_width = %u\n",
 171                 crp->reg, value, field, crp->reg_width, crp->field_width);
 172
 173         mask = ~(mask << pos);
 174         value = value << pos;
 175
 176         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 177         data &= mask;
 178         data |= value;
 179
 180         if (pfc->info->unlock_reg)
 181                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 182
 183         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 184 }
 185
 186 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 187                                  const struct pinmux_cfg_reg **crp,
 188                                  unsigned int *fieldp, u32 *valuep)
 189 {
 190         unsigned int k = 0;
 191
 192         while (1) {
 193                 const struct pinmux_cfg_reg *config_reg =
 194                         pfc->info->cfg_regs + k;
 195                 unsigned int r_width = config_reg->reg_width;
 196                 unsigned int f_width = config_reg->field_width;
 197                 unsigned int curr_width;
 198                 unsigned int bit_pos;
 199                 unsigned int pos = 0;
 200                 unsigned int m = 0;
 201
 202                 if (!r_width)
 203                         break;
 204
 205                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 206                         u32 ncomb;
 207                         u32 n;
 208
 209                         if (f_width)
 210                                 curr_width = f_width;
 211                         else
 212                                 curr_width = config_reg->var_field_width[m];
 213
 214                         ncomb = 1 << curr_width;
 215                         for (n = 0; n < ncomb; n++) {
 216                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 217                                         *crp = config_reg;
 218                                         *fieldp = m;
 219                                         *valuep = n;
 220                                         return 0;
 221                                 }
 222                         }
 223                         pos += ncomb;
 224                         m++;
 225                 }
 226                 k++;
 227         }
 228
 229         return -EINVAL;
 230 }
 231
 232 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 233                               u16 *enum_idp)
 234 {
 235         const u16 *data = pfc->info->pinmux_data;
 236         unsigned int k;
 237
 238         if (pos) {
 239                 *enum_idp = data[pos + 1];
 240                 return pos + 1;
 241         }
 242
 243         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 244                 if (data[k] == mark) {
 245                         *enum_idp = data[k + 1];
 246                         return k + 1;
 247                 }
 248         }
 249
 250         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 251                 mark);
 252         return -EINVAL;
 253 }
 254
 255 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 256 {
 257         const struct pinmux_range *range;
 258         int pos = 0;
 259
 260         switch (pinmux_type) {
 261         case PINMUX_TYPE_GPIO:
 262         case PINMUX_TYPE_FUNCTION:
 263                 range = NULL;
 264                 break;
 265
 266         case PINMUX_TYPE_OUTPUT:
 267                 range = &pfc->info->output;
 268                 break;
 269
 270         case PINMUX_TYPE_INPUT:
 271                 range = &pfc->info->input;
 272                 break;
 273
 274         default:
 275                 return -EINVAL;
 276         }
 277
 278         /* Iterate over all the configuration fields we need to update. */
 279         while (1) {
 280                 const struct pinmux_cfg_reg *cr;
 281                 unsigned int field;
 282                 u16 enum_id;
 283                 u32 value;
 284                 int in_range;
 285                 int ret;
 286
 287                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 288                 if (pos < 0)
 289                         return pos;
 290
 291                 if (!enum_id)
 292                         break;
 293
 294                 /* Check if the configuration field selects a function. If it
 295                  * doesn't, skip the field if it's not applicable to the
 296                  * requested pinmux type.
 297                  */
 298                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 299                 if (!in_range) {
 300                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 301                                 /* Functions are allowed to modify all
 302                                  * fields.
 303                                  */
 304                                 in_range = 1;
 305                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 306                                 /* Input/output types can only modify fields
 307                                  * that correspond to their respective ranges.
 308                                  */
 309                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 310
 311                                 /*
 312                                  * special case pass through for fixed
 313                                  * input-only or output-only pins without
 314                                  * function enum register association.
 315                                  */
 316                                 if (in_range && enum_id == range->force)
 317                                         continue;
 318                         }
 319                         /* GPIOs are only allowed to modify function fields. */
 320                 }
 321
 322                 if (!in_range)
 323                         continue;
 324
 325                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 326                 if (ret < 0)
 327                         return ret;
 328
 329                 sh_pfc_write_config_reg(pfc, cr, field, value);
 330         }
 331
 332         return 0;
 333 }
 334
 335 const struct sh_pfc_bias_info *
 336 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
 337                         unsigned int num, unsigned int pin)
 338 {
 339         unsigned int i;
 340
 341         for (i = 0; i < num; i++)
 342                 if (info[i].pin == pin)
 343                         return &info[i];
 344
 345         printf("Pin %u is not in bias info list\n", pin);
 346
 347         return NULL;
 348 }
 349
 350 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 351 {
 352         struct sh_pfc_pin_range *range;
 353         unsigned int nr_ranges;
 354         unsigned int i;
 355
 356         if (pfc->info->pins[0].pin == (u16)-1) {
 357                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 358                  * in its pin arrays yet. Consider the pin numbers range as
 359                  * continuous and allocate a single range.
 360                  */
 361                 pfc->nr_ranges = 1;
 362                 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
 363                 if (pfc->ranges == NULL)
 364                         return -ENOMEM;
 365
 366                 pfc->ranges->start = 0;
 367                 pfc->ranges->end = pfc->info->nr_pins - 1;
 368                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 369
 370                 return 0;
 371         }
 372
 373         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 374          * be sorted by pin numbers, and pins without a GPIO port must come
 375          * last.
 376          */
 377         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 378                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 379                         nr_ranges++;
 380         }
 381
 382         pfc->nr_ranges = nr_ranges;
 383         pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
 384         if (pfc->ranges == NULL)
 385                 return -ENOMEM;
 386
 387         range = pfc->ranges;
 388         range->start = pfc->info->pins[0].pin;
 389
 390         for (i = 1; i < pfc->info->nr_pins; ++i) {
 391                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 392                         continue;
 393
 394                 range->end = pfc->info->pins[i-1].pin;
 395                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 396                         pfc->nr_gpio_pins = range->end + 1;
 397
 398                 range++;
 399                 range->start = pfc->info->pins[i].pin;
 400         }
 401
 402         range->end = pfc->info->pins[i-1].pin;
 403         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 404                 pfc->nr_gpio_pins = range->end + 1;
 405
 406         return 0;
 407 }
 408
 409 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
 410 {
 411         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 412
 413         return priv->pfc.info->nr_pins;
 414 }
 415
 416 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
 417                                                   unsigned selector)
 418 {
 419         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 420
 421         return priv->pfc.info->pins[selector].name;
 422 }
 423
 424 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
 425 {
 426         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 427
 428         return priv->pfc.info->nr_groups;
 429 }
 430
 431 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
 432                                                   unsigned selector)
 433 {
 434         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 435
 436         return priv->pfc.info->groups[selector].name;
 437 }
 438
 439 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
 440 {
 441         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 442
 443         return priv->pfc.info->nr_functions;
 444 }
 445
 446 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
 447                                                   unsigned selector)
 448 {
 449         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 450
 451         return priv->pfc.info->functions[selector].name;
 452 }
 453
 454 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
 455 {
 456         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 457         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 458         struct sh_pfc *pfc = &priv->pfc;
 459         struct sh_pfc_pin_config *cfg;
 460         const struct sh_pfc_pin *pin = NULL;
 461         int i, idx;
 462
 463         for (i = 1; i < pfc->info->nr_pins; i++) {
 464                 if (priv->pfc.info->pins[i].pin != pin_selector)
 465                         continue;
 466
 467                 pin = &priv->pfc.info->pins[i];
 468                 break;
 469         }
 470
 471         if (!pin)
 472                 return -EINVAL;
 473
 474         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 475         cfg = &pmx->configs[idx];
 476
 477         if (cfg->type != PINMUX_TYPE_NONE)
 478                 return -EBUSY;
 479
 480         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
 481 }
 482
 483 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
 484                                   unsigned func_selector)
 485 {
 486         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 487         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 488         struct sh_pfc *pfc = &priv->pfc;
 489         const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
 490         int idx = sh_pfc_get_pin_index(pfc, pin->pin);
 491         struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 492
 493         if (cfg->type != PINMUX_TYPE_NONE)
 494                 return -EBUSY;
 495
 496         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
 497 }
 498
 499 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
 500                                      unsigned func_selector)
 501 {
 502         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 503         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 504         struct sh_pfc *pfc = &priv->pfc;
 505         const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
 506         unsigned int i;
 507         int ret = 0;
 508
 509         for (i = 0; i < grp->nr_pins; ++i) {
 510                 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
 511                 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 512
 513                 if (cfg->type != PINMUX_TYPE_NONE) {
 514                         ret = -EBUSY;
 515                         goto done;
 516                 }
 517         }
 518
 519         for (i = 0; i < grp->nr_pins; ++i) {
 520                 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
 521                 if (ret < 0)
 522                         break;
 523         }
 524
 525 done:
 526         return ret;
 527 }
 528 #if CONFIG_IS_ENABLED(PINCONF)
 529 static const struct pinconf_param sh_pfc_pinconf_params[] = {
 530         { "bias-disable",       PIN_CONFIG_BIAS_DISABLE,        0 },
 531         { "bias-pull-up",       PIN_CONFIG_BIAS_PULL_UP,        1 },
 532         { "bias-pull-down",     PIN_CONFIG_BIAS_PULL_DOWN,      1 },
 533         { "drive-strength",     PIN_CONFIG_DRIVE_STRENGTH,      0 },
 534         { "power-source",       PIN_CONFIG_POWER_SOURCE,        3300 },
 535 };
 536
 537 static void __iomem *
 538 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
 539                                        unsigned int *offset, unsigned int *size)
 540 {
 541         const struct pinmux_drive_reg_field *field;
 542         const struct pinmux_drive_reg *reg;
 543         unsigned int i;
 544
 545         for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
 546                 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
 547                         field = &reg->fields[i];
 548
 549                         if (field->size && field->pin == pin) {
 550                                 *offset = field->offset;
 551                                 *size = field->size;
 552
 553                                 return (void __iomem *)(uintptr_t)reg->reg;
 554                         }
 555                 }
 556         }
 557
 558         return NULL;
 559 }
 560
 561 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
 562                                              unsigned int pin, u16 strength)
 563 {
 564         unsigned int offset;
 565         unsigned int size;
 566         unsigned int step;
 567         void __iomem *reg;
 568         void __iomem *unlock_reg =
 569                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 570         u32 val;
 571
 572         reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
 573         if (!reg)
 574                 return -EINVAL;
 575
 576         step = size == 2 ? 6 : 3;
 577
 578         if (strength < step || strength > 24)
 579                 return -EINVAL;
 580
 581         /* Convert the value from mA based on a full drive strength value of
 582          * 24mA. We can make the full value configurable later if needed.
 583          */
 584         strength = strength / step - 1;
 585
 586         val = sh_pfc_read_raw_reg(reg, 32);
 587         val &= ~GENMASK(offset + size - 1, offset);
 588         val |= strength << offset;
 589
 590         if (unlock_reg)
 591                 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 592
 593         sh_pfc_write_raw_reg(reg, 32, val);
 594
 595         return 0;
 596 }
 597
 598 /* Check whether the requested parameter is supported for a pin. */
 599 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
 600                                     unsigned int param)
 601 {
 602         int idx = sh_pfc_get_pin_index(pfc, _pin);
 603         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
 604
 605         switch (param) {
 606         case PIN_CONFIG_BIAS_DISABLE:
 607                 return pin->configs &
 608                         (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
 609
 610         case PIN_CONFIG_BIAS_PULL_UP:
 611                 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
 612
 613         case PIN_CONFIG_BIAS_PULL_DOWN:
 614                 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
 615
 616         case PIN_CONFIG_DRIVE_STRENGTH:
 617                 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
 618
 619         case PIN_CONFIG_POWER_SOURCE:
 620                 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
 621
 622         default:
 623                 return false;
 624         }
 625 }
 626
 627 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
 628                               unsigned int param, unsigned int arg)
 629 {
 630         struct sh_pfc *pfc = pmx->pfc;
 631         void __iomem *pocctrl;
 632         void __iomem *unlock_reg =
 633                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 634         u32 addr, val;
 635         int bit, ret;
 636
 637         if (!sh_pfc_pinconf_validate(pfc, _pin, param))
 638                 return -ENOTSUPP;
 639
 640         switch (param) {
 641         case PIN_CONFIG_BIAS_PULL_UP:
 642         case PIN_CONFIG_BIAS_PULL_DOWN:
 643         case PIN_CONFIG_BIAS_DISABLE:
 644                 if (!pfc->info->ops || !pfc->info->ops->set_bias)
 645                         return -ENOTSUPP;
 646
 647                 pfc->info->ops->set_bias(pfc, _pin, param);
 648
 649                 break;
 650
 651         case PIN_CONFIG_DRIVE_STRENGTH:
 652                 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
 653                 if (ret < 0)
 654                         return ret;
 655
 656                 break;
 657
 658         case PIN_CONFIG_POWER_SOURCE:
 659                 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
 660                         return -ENOTSUPP;
 661
 662                 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
 663                 if (bit < 0) {
 664                         printf("invalid pin %#x", _pin);
 665                         return bit;
 666                 }
 667
 668                 if (arg != 1800 && arg != 3300)
 669                         return -EINVAL;
 670
 671                 pocctrl = (void __iomem *)(uintptr_t)addr;
 672
 673                 val = sh_pfc_read_raw_reg(pocctrl, 32);
 674                 if (arg == 3300)
 675                         val |= BIT(bit);
 676                 else
 677                         val &= ~BIT(bit);
 678
 679                 if (unlock_reg)
 680                         sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 681
 682                 sh_pfc_write_raw_reg(pocctrl, 32, val);
 683
 684                 break;
 685
 686         default:
 687                 return -ENOTSUPP;
 688         }
 689
 690         return 0;
 691 }
 692
 693 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
 694                                   unsigned int pin_selector,
 695                                   unsigned int param, unsigned int arg)
 696 {
 697         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 698         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 699         struct sh_pfc *pfc = &priv->pfc;
 700         const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
 701
 702         sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
 703
 704         return 0;
 705 }
 706
 707 static int sh_pfc_pinconf_group_set(struct udevice *dev,
 708                                       unsigned int group_selector,
 709                                       unsigned int param, unsigned int arg)
 710 {
 711         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 712         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 713         struct sh_pfc *pfc = &priv->pfc;
 714         const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
 715         unsigned int i;
 716
 717         for (i = 0; i < grp->nr_pins; i++)
 718                 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
 719
 720         return 0;
 721 }
 722 #endif
 723
 724 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
 725         .get_pins_count         = sh_pfc_pinctrl_get_pins_count,
 726         .get_pin_name           = sh_pfc_pinctrl_get_pin_name,
 727         .get_groups_count       = sh_pfc_pinctrl_get_groups_count,
 728         .get_group_name         = sh_pfc_pinctrl_get_group_name,
 729         .get_functions_count    = sh_pfc_pinctrl_get_functions_count,
 730         .get_function_name      = sh_pfc_pinctrl_get_function_name,
 731
 732 #if CONFIG_IS_ENABLED(PINCONF)
 733         .pinconf_num_params     = ARRAY_SIZE(sh_pfc_pinconf_params),
 734         .pinconf_params         = sh_pfc_pinconf_params,
 735         .pinconf_set            = sh_pfc_pinconf_pin_set,
 736         .pinconf_group_set      = sh_pfc_pinconf_group_set,
 737 #endif
 738         .pinmux_set             = sh_pfc_pinctrl_pin_set,
 739         .pinmux_group_set       = sh_pfc_pinctrl_group_set,
 740         .set_state              = pinctrl_generic_set_state,
 741 };
 742
 743 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
 744 {
 745         unsigned int i;
 746
 747         /* Allocate and initialize the pins and configs arrays. */
 748         pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
 749                                     GFP_KERNEL);
 750         if (unlikely(!pmx->configs))
 751                 return -ENOMEM;
 752
 753         for (i = 0; i < pfc->info->nr_pins; ++i) {
 754                 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
 755                 cfg->type = PINMUX_TYPE_NONE;
 756         }
 757
 758         return 0;
 759 }
 760
 761
 762 static int sh_pfc_pinctrl_probe(struct udevice *dev)
 763 {
 764         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 765         enum sh_pfc_model model = dev_get_driver_data(dev);
 766         fdt_addr_t base;
 767
 768         base = devfdt_get_addr(dev);
 769         if (base == FDT_ADDR_T_NONE)
 770                 return -EINVAL;
 771
 772         priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
 773         if (!priv->pfc.regs)
 774                 return -ENOMEM;
 775
 776 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 777         if (model == SH_PFC_R8A7790)
 778                 priv->pfc.info = &r8a7790_pinmux_info;
 779 #endif
 780 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 781         if (model == SH_PFC_R8A7795)
 782                 priv->pfc.info = &r8a7795_pinmux_info;
 783 #endif
 784 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 785         if (model == SH_PFC_R8A7796)
 786                 priv->pfc.info = &r8a7796_pinmux_info;
 787 #endif
 788 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 789         if (model == SH_PFC_R8A77970)
 790                 priv->pfc.info = &r8a77970_pinmux_info;
 791 #endif
 792 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 793         if (model == SH_PFC_R8A77995)
 794                 priv->pfc.info = &r8a77995_pinmux_info;
 795 #endif
 796
 797         priv->pmx.pfc = &priv->pfc;
 798         sh_pfc_init_ranges(&priv->pfc);
 799         sh_pfc_map_pins(&priv->pfc, &priv->pmx);
 800
 801         return 0;
 802 }
 803
 804 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
 805 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 806         {
 807                 .compatible = "renesas,pfc-r8a7790",
 808                 .data = SH_PFC_R8A7790,
 809         },
 810 #endif
 811 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 812         {
 813                 .compatible = "renesas,pfc-r8a7795",
 814                 .data = SH_PFC_R8A7795,
 815         },
 816 #endif
 817 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 818         {
 819                 .compatible = "renesas,pfc-r8a7796",
 820                 .data = SH_PFC_R8A7796,
 821         },
 822 #endif
 823 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 824         {
 825                 .compatible = "renesas,pfc-r8a77970",
 826                 .data = SH_PFC_R8A77970,
 827         },
 828 #endif
 829 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 830         {
 831                 .compatible = "renesas,pfc-r8a77995",
 832                 .data = SH_PFC_R8A77995,
 833         },
 834 #endif
 835         { },
 836 };
 837
 838 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
 839         .name           = "sh_pfc_pinctrl",
 840         .id             = UCLASS_PINCTRL,
 841         .of_match       = sh_pfc_pinctrl_ids,
 842         .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
 843         .ops            = &sh_pfc_pinctrl_ops,
 844         .probe          = sh_pfc_pinctrl_probe,
 845 };