board: cssi: Add CPU board CMPCPRO
[platform/kernel/u-boot.git] / drivers / pinctrl / renesas / pfc.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Pin Control driver for SuperH Pin Function Controller.
4  *
5  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6  *
7  * Copyright (C) 2008 Magnus Damm
8  * Copyright (C) 2009 - 2012 Paul Mundt
9  * Copyright (C) 2017 Marek Vasut
10  */
11
12 #define DRV_NAME "sh-pfc"
13
14 #include <common.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <dm/device_compat.h>
18 #include <dm/devres.h>
19 #include <dm/pinctrl.h>
20 #include <linux/bitops.h>
21 #include <linux/bug.h>
22 #include <linux/io.h>
23 #include <linux/sizes.h>
24
25 #include "sh_pfc.h"
26
27 enum sh_pfc_model {
28         SH_PFC_R8A7790 = 0,
29         SH_PFC_R8A7791,
30         SH_PFC_R8A7792,
31         SH_PFC_R8A7793,
32         SH_PFC_R8A7794,
33         SH_PFC_R8A7795,
34         SH_PFC_R8A77960,
35         SH_PFC_R8A77961,
36         SH_PFC_R8A774A1,
37         SH_PFC_R8A774B1,
38         SH_PFC_R8A774C0,
39         SH_PFC_R8A774E1,
40         SH_PFC_R8A77965,
41         SH_PFC_R8A77970,
42         SH_PFC_R8A77980,
43         SH_PFC_R8A77990,
44         SH_PFC_R8A77995,
45         SH_PFC_R8A779A0,
46 };
47
48 struct sh_pfc_pin_config {
49         u32 type;
50         const char *name;
51 };
52
53 struct sh_pfc_pinctrl {
54         struct sh_pfc *pfc;
55
56         struct sh_pfc_pin_config *configs;
57 };
58
59 struct sh_pfc_pin_range {
60         u16 start;
61         u16 end;
62 };
63
64 struct sh_pfc_pinctrl_priv {
65         struct sh_pfc                   pfc;
66         struct sh_pfc_pinctrl           pmx;
67 };
68
69 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
70 {
71         unsigned int offset;
72         unsigned int i;
73
74         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
75                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
76
77                 if (pin <= range->end)
78                         return pin >= range->start
79                              ? offset + pin - range->start : -1;
80
81                 offset += range->end - range->start + 1;
82         }
83
84         return -EINVAL;
85 }
86
87 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
88 {
89         if (enum_id < r->begin)
90                 return 0;
91
92         if (enum_id > r->end)
93                 return 0;
94
95         return 1;
96 }
97
98 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
99 {
100         switch (reg_width) {
101         case 8:
102                 return readb(mapped_reg);
103         case 16:
104                 return readw(mapped_reg);
105         case 32:
106                 return readl(mapped_reg);
107         }
108
109         BUG();
110         return 0;
111 }
112
113 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
114                           u32 data)
115 {
116         switch (reg_width) {
117         case 8:
118                 writeb(data, mapped_reg);
119                 return;
120         case 16:
121                 writew(data, mapped_reg);
122                 return;
123         case 32:
124                 writel(data, mapped_reg);
125                 return;
126         }
127
128         BUG();
129 }
130
131 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
132 {
133         return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
134 }
135
136 static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
137 {
138         u32 unlock;
139
140         if (!pfc->info->unlock_reg)
141                 return;
142
143         if (pfc->info->unlock_reg >= 0x80000000UL)
144                 unlock = pfc->info->unlock_reg;
145         else
146                 /* unlock_reg is a mask */
147                 unlock = reg & ~pfc->info->unlock_reg;
148
149         sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)unlock, 32, ~data);
150 }
151
152 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
153 {
154         sh_pfc_unlock_reg(pfc, reg, data);
155         sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
156 }
157
158 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
159                                      const struct pinmux_cfg_reg *crp,
160                                      unsigned int in_pos,
161                                      void __iomem **mapped_regp, u32 *maskp,
162                                      unsigned int *posp)
163 {
164         unsigned int k;
165
166         *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
167
168         if (crp->field_width) {
169                 *maskp = (1 << crp->field_width) - 1;
170                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
171         } else {
172                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
173                 *posp = crp->reg_width;
174                 for (k = 0; k <= in_pos; k++)
175                         *posp -= abs(crp->var_field_width[k]);
176         }
177 }
178
179 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
180                                     const struct pinmux_cfg_reg *crp,
181                                     unsigned int field, u32 value)
182 {
183         void __iomem *mapped_reg;
184         unsigned int pos;
185         u32 mask, data;
186
187         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
188
189         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
190                 "r_width = %u, f_width = %u\n",
191                 crp->reg, value, field, crp->reg_width, crp->field_width);
192
193         mask = ~(mask << pos);
194         value = value << pos;
195
196         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
197         data &= mask;
198         data |= value;
199
200         sh_pfc_unlock_reg(pfc, crp->reg, data);
201         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
202 }
203
204 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
205                                  const struct pinmux_cfg_reg **crp,
206                                  unsigned int *fieldp, u32 *valuep)
207 {
208         unsigned int k = 0;
209
210         while (1) {
211                 const struct pinmux_cfg_reg *config_reg =
212                         pfc->info->cfg_regs + k;
213                 unsigned int r_width = config_reg->reg_width;
214                 unsigned int f_width = config_reg->field_width;
215                 unsigned int curr_width;
216                 unsigned int bit_pos;
217                 unsigned int pos = 0;
218                 unsigned int m = 0;
219
220                 if (!r_width)
221                         break;
222
223                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width, m++) {
224                         u32 ncomb;
225                         u32 n;
226
227                         if (f_width) {
228                                 curr_width = f_width;
229                         } else {
230                                 curr_width = abs(config_reg->var_field_width[m]);
231                                 if (config_reg->var_field_width[m] < 0)
232                                         continue;
233                         }
234
235                         ncomb = 1 << curr_width;
236                         for (n = 0; n < ncomb; n++) {
237                                 if (config_reg->enum_ids[pos + n] == enum_id) {
238                                         *crp = config_reg;
239                                         *fieldp = m;
240                                         *valuep = n;
241                                         return 0;
242                                 }
243                         }
244                         pos += ncomb;
245                 }
246                 k++;
247         }
248
249         return -EINVAL;
250 }
251
252 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
253                               u16 *enum_idp)
254 {
255         const u16 *data = pfc->info->pinmux_data;
256         unsigned int k;
257
258         if (pos) {
259                 *enum_idp = data[pos + 1];
260                 return pos + 1;
261         }
262
263         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
264                 if (data[k] == mark) {
265                         *enum_idp = data[k + 1];
266                         return k + 1;
267                 }
268         }
269
270         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
271                 mark);
272         return -EINVAL;
273 }
274
275 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
276 {
277         const struct pinmux_range *range;
278         int pos = 0;
279
280         switch (pinmux_type) {
281         case PINMUX_TYPE_GPIO:
282         case PINMUX_TYPE_FUNCTION:
283                 range = NULL;
284                 break;
285
286         case PINMUX_TYPE_OUTPUT:
287                 range = &pfc->info->output;
288                 break;
289
290         case PINMUX_TYPE_INPUT:
291                 range = &pfc->info->input;
292                 break;
293
294         default:
295                 return -EINVAL;
296         }
297
298         /* Iterate over all the configuration fields we need to update. */
299         while (1) {
300                 const struct pinmux_cfg_reg *cr;
301                 unsigned int field;
302                 u16 enum_id;
303                 u32 value;
304                 int in_range;
305                 int ret;
306
307                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
308                 if (pos < 0)
309                         return pos;
310
311                 if (!enum_id)
312                         break;
313
314                 /* Check if the configuration field selects a function. If it
315                  * doesn't, skip the field if it's not applicable to the
316                  * requested pinmux type.
317                  */
318                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
319                 if (!in_range) {
320                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
321                                 /* Functions are allowed to modify all
322                                  * fields.
323                                  */
324                                 in_range = 1;
325                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
326                                 /* Input/output types can only modify fields
327                                  * that correspond to their respective ranges.
328                                  */
329                                 in_range = sh_pfc_enum_in_range(enum_id, range);
330
331                                 /*
332                                  * special case pass through for fixed
333                                  * input-only or output-only pins without
334                                  * function enum register association.
335                                  */
336                                 if (in_range && enum_id == range->force)
337                                         continue;
338                         }
339                         /* GPIOs are only allowed to modify function fields. */
340                 }
341
342                 if (!in_range)
343                         continue;
344
345                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
346                 if (ret < 0)
347                         return ret;
348
349                 sh_pfc_write_config_reg(pfc, cr, field, value);
350         }
351
352         return 0;
353 }
354
355 const struct pinmux_bias_reg *
356 rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin,
357                      unsigned int *bit)
358 {
359         unsigned int i, j;
360
361         for (i = 0; info->bias_regs[i].puen || info->bias_regs[i].pud; i++) {
362                 for (j = 0; j < ARRAY_SIZE(info->bias_regs[i].pins); j++) {
363                         if (info->bias_regs[i].pins[j] == pin) {
364                                 *bit = j;
365                                 return &info->bias_regs[i];
366                         }
367                 }
368         }
369
370         WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
371
372         return NULL;
373 }
374
375 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
376 {
377         const struct pinmux_bias_reg *reg;
378         unsigned int bit;
379
380         reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
381         if (!reg)
382                 return PIN_CONFIG_BIAS_DISABLE;
383
384         if (reg->puen) {
385                 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
386                         return PIN_CONFIG_BIAS_DISABLE;
387                 else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit)))
388                         return PIN_CONFIG_BIAS_PULL_UP;
389                 else
390                         return PIN_CONFIG_BIAS_PULL_DOWN;
391         } else {
392                 if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
393                         return PIN_CONFIG_BIAS_PULL_DOWN;
394                 else
395                         return PIN_CONFIG_BIAS_DISABLE;
396         }
397 }
398
399 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
400                           unsigned int bias)
401 {
402         const struct pinmux_bias_reg *reg;
403         u32 enable, updown;
404         unsigned int bit;
405
406         reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
407         if (!reg)
408                 return;
409
410         if (reg->puen) {
411                 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
412                 if (bias != PIN_CONFIG_BIAS_DISABLE) {
413                         enable |= BIT(bit);
414
415                         if (reg->pud) {
416                                 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
417                                 if (bias == PIN_CONFIG_BIAS_PULL_UP)
418                                         updown |= BIT(bit);
419
420                                 sh_pfc_write(pfc, reg->pud, updown);
421                         }
422                 }
423                 sh_pfc_write(pfc, reg->puen, enable);
424         } else {
425                 enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
426                 if (bias == PIN_CONFIG_BIAS_PULL_DOWN)
427                         enable |= BIT(bit);
428
429                 sh_pfc_write(pfc, reg->pud, enable);
430         }
431 }
432
433 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
434 {
435         struct sh_pfc_pin_range *range;
436         unsigned int nr_ranges;
437         unsigned int i;
438
439         if (pfc->info->pins[0].pin == (u16)-1) {
440                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
441                  * in its pin arrays yet. Consider the pin numbers range as
442                  * continuous and allocate a single range.
443                  */
444                 pfc->nr_ranges = 1;
445                 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
446                 if (pfc->ranges == NULL)
447                         return -ENOMEM;
448
449                 pfc->ranges->start = 0;
450                 pfc->ranges->end = pfc->info->nr_pins - 1;
451                 pfc->nr_gpio_pins = pfc->info->nr_pins;
452
453                 return 0;
454         }
455
456         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
457          * be sorted by pin numbers, and pins without a GPIO port must come
458          * last.
459          */
460         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
461                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
462                         nr_ranges++;
463         }
464
465         pfc->nr_ranges = nr_ranges;
466         pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
467         if (pfc->ranges == NULL)
468                 return -ENOMEM;
469
470         range = pfc->ranges;
471         range->start = pfc->info->pins[0].pin;
472
473         for (i = 1; i < pfc->info->nr_pins; ++i) {
474                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
475                         continue;
476
477                 range->end = pfc->info->pins[i-1].pin;
478                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
479                         pfc->nr_gpio_pins = range->end + 1;
480
481                 range++;
482                 range->start = pfc->info->pins[i].pin;
483         }
484
485         range->end = pfc->info->pins[i-1].pin;
486         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
487                 pfc->nr_gpio_pins = range->end + 1;
488
489         return 0;
490 }
491
492 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
493 {
494         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
495
496         return priv->pfc.info->nr_pins;
497 }
498
499 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
500                                                   unsigned selector)
501 {
502         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
503
504         return priv->pfc.info->pins[selector].name;
505 }
506
507 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
508 {
509         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
510
511         return priv->pfc.info->nr_groups;
512 }
513
514 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
515                                                   unsigned selector)
516 {
517         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
518
519         return priv->pfc.info->groups[selector].name;
520 }
521
522 static int sh_pfc_pinctrl_get_pin_muxing(struct udevice *dev,
523                                          unsigned int selector,
524                                          char *buf, int size)
525 {
526         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
527         struct sh_pfc_pinctrl *pmx = &priv->pmx;
528         struct sh_pfc *pfc = &priv->pfc;
529         struct sh_pfc_pin_config *cfg;
530         const struct sh_pfc_pin *pin;
531         int idx;
532
533         pin = &priv->pfc.info->pins[selector];
534         if (!pin) {
535                 snprintf(buf, size, "Unknown");
536                 return -EINVAL;
537         }
538
539         idx = sh_pfc_get_pin_index(pfc, pin->pin);
540         cfg = &pmx->configs[idx];
541         snprintf(buf, size, "%s", cfg->name);
542
543         return 0;
544 }
545
546 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
547 {
548         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
549
550         return priv->pfc.info->nr_functions;
551 }
552
553 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
554                                                   unsigned selector)
555 {
556         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
557
558         return priv->pfc.info->functions[selector].name;
559 }
560
561 static int sh_pfc_gpio_request_enable(struct udevice *dev,
562                                       unsigned pin_selector)
563 {
564         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
565         struct sh_pfc_pinctrl *pmx = &priv->pmx;
566         struct sh_pfc *pfc = &priv->pfc;
567         struct sh_pfc_pin_config *cfg;
568         const struct sh_pfc_pin *pin = NULL;
569         int i, ret, idx;
570
571         for (i = 0; i < pfc->info->nr_pins; i++) {
572                 if (priv->pfc.info->pins[i].pin != pin_selector)
573                         continue;
574
575                 pin = &priv->pfc.info->pins[i];
576                 break;
577         }
578
579         if (!pin)
580                 return -EINVAL;
581
582         idx = sh_pfc_get_pin_index(pfc, pin->pin);
583         cfg = &pmx->configs[idx];
584
585         if (cfg->type != PINMUX_TYPE_NONE) {
586                 if (!strcmp(cfg->name, pin->name))
587                         return 0;
588
589                 dev_err(pfc->dev, "Pin already used as %s\n",
590                         cfg->name);
591                 return -EBUSY;
592         }
593
594         ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
595         if (ret)
596                 return ret;
597
598         cfg->type = PINMUX_TYPE_GPIO;
599         cfg->name = "gpio";
600
601         return 0;
602 }
603
604 static int sh_pfc_gpio_disable_free(struct udevice *dev,
605                                     unsigned pin_selector)
606 {
607         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
608         struct sh_pfc_pinctrl *pmx = &priv->pmx;
609         struct sh_pfc *pfc = &priv->pfc;
610         struct sh_pfc_pin_config *cfg;
611         const struct sh_pfc_pin *pin = NULL;
612         int i, idx;
613
614         for (i = 0; i < pfc->info->nr_pins; i++) {
615                 if (priv->pfc.info->pins[i].pin != pin_selector)
616                         continue;
617
618                 pin = &priv->pfc.info->pins[i];
619                 break;
620         }
621
622         if (!pin)
623                 return -EINVAL;
624
625         idx = sh_pfc_get_pin_index(pfc, pin->pin);
626         cfg = &pmx->configs[idx];
627
628         cfg->type = PINMUX_TYPE_NONE;
629         cfg->name = "none";
630
631         return 0;
632 }
633
634 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
635                                   unsigned func_selector)
636 {
637         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
638         struct sh_pfc_pinctrl *pmx = &priv->pmx;
639         struct sh_pfc *pfc = &priv->pfc;
640         const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
641         int idx = sh_pfc_get_pin_index(pfc, pin->pin);
642         struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
643         int ret;
644
645         if (cfg->type != PINMUX_TYPE_NONE) {
646                 if (!strcmp(cfg->name, pin->name))
647                         return 0;
648
649                 dev_err(pfc->dev, "Pin already used as %s\n",
650                         cfg->name);
651                 return -EBUSY;
652         }
653
654         ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
655         if (ret)
656                 return ret;
657
658         cfg->type = PINMUX_TYPE_FUNCTION;
659         cfg->name = "function";
660
661         return 0;
662 }
663
664 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
665                                      unsigned func_selector)
666 {
667         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
668         struct sh_pfc_pinctrl *pmx = &priv->pmx;
669         struct sh_pfc *pfc = &priv->pfc;
670         const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
671         bool grp_pins_configured = true;
672         struct sh_pfc_pin_config *cfg;
673         unsigned int i;
674         int ret = 0;
675         int idx;
676
677         for (i = 0; i < grp->nr_pins; ++i) {
678                 idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
679                 cfg = &pmx->configs[idx];
680
681                 if (cfg->type != PINMUX_TYPE_NONE) {
682                         if (!strcmp(cfg->name, grp->name))
683                                 continue;
684
685                         dev_err(pfc->dev, "Pin already used as %s\n",
686                                 cfg->name);
687                         ret = -EBUSY;
688                         goto done;
689                 } else {
690                         grp_pins_configured = false;
691                 }
692         }
693
694         if (grp_pins_configured)
695                 return 0;
696
697         for (i = 0; i < grp->nr_pins; ++i) {
698                 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
699                 if (ret < 0)
700                         break;
701
702                 idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
703                 cfg = &pmx->configs[idx];
704                 cfg->type = PINMUX_TYPE_FUNCTION;
705                 cfg->name = priv->pfc.info->groups[group_selector].name;
706         }
707
708 done:
709         return ret;
710 }
711 #if CONFIG_IS_ENABLED(PINCONF)
712 static const struct pinconf_param sh_pfc_pinconf_params[] = {
713         { "bias-disable",       PIN_CONFIG_BIAS_DISABLE,        0 },
714         { "bias-pull-up",       PIN_CONFIG_BIAS_PULL_UP,        1 },
715         { "bias-pull-down",     PIN_CONFIG_BIAS_PULL_DOWN,      1 },
716         { "drive-strength",     PIN_CONFIG_DRIVE_STRENGTH,      0 },
717         { "power-source",       PIN_CONFIG_POWER_SOURCE,        3300 },
718 };
719
720 static void __iomem *
721 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
722                                        unsigned int *offset, unsigned int *size)
723 {
724         const struct pinmux_drive_reg_field *field;
725         const struct pinmux_drive_reg *reg;
726         unsigned int i;
727
728         for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
729                 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
730                         field = &reg->fields[i];
731
732                         if (field->size && field->pin == pin) {
733                                 *offset = field->offset;
734                                 *size = field->size;
735
736                                 return (void __iomem *)(uintptr_t)reg->reg;
737                         }
738                 }
739         }
740
741         return NULL;
742 }
743
744 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
745                                              unsigned int pin, u16 strength)
746 {
747         unsigned int offset;
748         unsigned int size;
749         unsigned int step;
750         void __iomem *reg;
751         u32 val;
752
753         reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
754         if (!reg)
755                 return -EINVAL;
756
757         step = size == 2 ? 6 : 3;
758
759         if (strength < step || strength > 24)
760                 return -EINVAL;
761
762         /* Convert the value from mA based on a full drive strength value of
763          * 24mA. We can make the full value configurable later if needed.
764          */
765         strength = strength / step - 1;
766
767         val = sh_pfc_read_raw_reg(reg, 32);
768         val &= ~GENMASK(offset + 4 - 1, offset);
769         val |= strength << offset;
770
771         sh_pfc_unlock_reg(pfc, (uintptr_t)reg, val);
772         sh_pfc_write_raw_reg(reg, 32, val);
773
774         return 0;
775 }
776
777 /* Check whether the requested parameter is supported for a pin. */
778 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
779                                     unsigned int param)
780 {
781         int idx = sh_pfc_get_pin_index(pfc, _pin);
782         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
783
784         switch (param) {
785         case PIN_CONFIG_BIAS_DISABLE:
786                 return pin->configs &
787                         (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
788
789         case PIN_CONFIG_BIAS_PULL_UP:
790                 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
791
792         case PIN_CONFIG_BIAS_PULL_DOWN:
793                 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
794
795         case PIN_CONFIG_DRIVE_STRENGTH:
796                 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
797
798         case PIN_CONFIG_POWER_SOURCE:
799                 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
800
801         default:
802                 return false;
803         }
804 }
805
806 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
807                               unsigned int param, unsigned int arg)
808 {
809         struct sh_pfc *pfc = pmx->pfc;
810         void __iomem *pocctrl;
811         u32 addr, val;
812         int bit, ret;
813
814         if (!sh_pfc_pinconf_validate(pfc, _pin, param))
815                 return -ENOTSUPP;
816
817         switch (param) {
818         case PIN_CONFIG_BIAS_PULL_UP:
819         case PIN_CONFIG_BIAS_PULL_DOWN:
820         case PIN_CONFIG_BIAS_DISABLE:
821                 if (!pfc->info->ops || !pfc->info->ops->set_bias)
822                         return -ENOTSUPP;
823
824                 pfc->info->ops->set_bias(pfc, _pin, param);
825
826                 break;
827
828         case PIN_CONFIG_DRIVE_STRENGTH:
829                 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
830                 if (ret < 0)
831                         return ret;
832
833                 break;
834
835         case PIN_CONFIG_POWER_SOURCE:
836                 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
837                         return -ENOTSUPP;
838
839                 bit = pfc->info->ops->pin_to_pocctrl(_pin, &addr);
840                 if (bit < 0) {
841                         printf("invalid pin %#x", _pin);
842                         return bit;
843                 }
844
845                 if (arg != 1800 && arg != 3300)
846                         return -EINVAL;
847
848                 pocctrl = (void __iomem *)(uintptr_t)addr;
849
850                 val = sh_pfc_read_raw_reg(pocctrl, 32);
851                 if (arg == 3300)
852                         val |= BIT(bit);
853                 else
854                         val &= ~BIT(bit);
855
856                 sh_pfc_unlock_reg(pfc, addr, val);
857                 sh_pfc_write_raw_reg(pocctrl, 32, val);
858
859                 break;
860
861         default:
862                 return -ENOTSUPP;
863         }
864
865         return 0;
866 }
867
868 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
869                                   unsigned int pin_selector,
870                                   unsigned int param, unsigned int arg)
871 {
872         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
873         struct sh_pfc_pinctrl *pmx = &priv->pmx;
874         struct sh_pfc *pfc = &priv->pfc;
875         const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
876
877         sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
878
879         return 0;
880 }
881
882 static int sh_pfc_pinconf_group_set(struct udevice *dev,
883                                       unsigned int group_selector,
884                                       unsigned int param, unsigned int arg)
885 {
886         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
887         struct sh_pfc_pinctrl *pmx = &priv->pmx;
888         struct sh_pfc *pfc = &priv->pfc;
889         const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
890         unsigned int i;
891
892         for (i = 0; i < grp->nr_pins; i++)
893                 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
894
895         return 0;
896 }
897 #endif
898
899 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
900         .get_pins_count         = sh_pfc_pinctrl_get_pins_count,
901         .get_pin_name           = sh_pfc_pinctrl_get_pin_name,
902         .get_groups_count       = sh_pfc_pinctrl_get_groups_count,
903         .get_group_name         = sh_pfc_pinctrl_get_group_name,
904         .get_pin_muxing         = sh_pfc_pinctrl_get_pin_muxing,
905         .get_functions_count    = sh_pfc_pinctrl_get_functions_count,
906         .get_function_name      = sh_pfc_pinctrl_get_function_name,
907
908 #if CONFIG_IS_ENABLED(PINCONF)
909         .pinconf_num_params     = ARRAY_SIZE(sh_pfc_pinconf_params),
910         .pinconf_params         = sh_pfc_pinconf_params,
911         .pinconf_set            = sh_pfc_pinconf_pin_set,
912         .pinconf_group_set      = sh_pfc_pinconf_group_set,
913 #endif
914         .pinmux_set             = sh_pfc_pinctrl_pin_set,
915         .pinmux_group_set       = sh_pfc_pinctrl_group_set,
916         .set_state              = pinctrl_generic_set_state,
917
918         .gpio_request_enable    = sh_pfc_gpio_request_enable,
919         .gpio_disable_free      = sh_pfc_gpio_disable_free,
920 };
921
922 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
923 {
924         unsigned int i;
925
926         /* Allocate and initialize the pins and configs arrays. */
927         pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
928                                     GFP_KERNEL);
929         if (unlikely(!pmx->configs))
930                 return -ENOMEM;
931
932         for (i = 0; i < pfc->info->nr_pins; ++i) {
933                 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
934                 cfg->type = PINMUX_TYPE_NONE;
935                 cfg->name = "none";
936         }
937
938         return 0;
939 }
940
941
942 static int sh_pfc_pinctrl_probe(struct udevice *dev)
943 {
944         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
945         enum sh_pfc_model model = dev_get_driver_data(dev);
946         fdt_addr_t base;
947
948         base = dev_read_addr(dev);
949         if (base == FDT_ADDR_T_NONE)
950                 return -EINVAL;
951
952         priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
953         if (!priv->pfc.regs)
954                 return -ENOMEM;
955
956 #ifdef CONFIG_PINCTRL_PFC_R8A7790
957         if (model == SH_PFC_R8A7790)
958                 priv->pfc.info = &r8a7790_pinmux_info;
959 #endif
960 #ifdef CONFIG_PINCTRL_PFC_R8A7791
961         if (model == SH_PFC_R8A7791)
962                 priv->pfc.info = &r8a7791_pinmux_info;
963 #endif
964 #ifdef CONFIG_PINCTRL_PFC_R8A7792
965         if (model == SH_PFC_R8A7792)
966                 priv->pfc.info = &r8a7792_pinmux_info;
967 #endif
968 #ifdef CONFIG_PINCTRL_PFC_R8A7793
969         if (model == SH_PFC_R8A7793)
970                 priv->pfc.info = &r8a7793_pinmux_info;
971 #endif
972 #ifdef CONFIG_PINCTRL_PFC_R8A7794
973         if (model == SH_PFC_R8A7794)
974                 priv->pfc.info = &r8a7794_pinmux_info;
975 #endif
976 #ifdef CONFIG_PINCTRL_PFC_R8A77951
977         if (model == SH_PFC_R8A7795)
978                 priv->pfc.info = &r8a77951_pinmux_info;
979 #endif
980 #ifdef CONFIG_PINCTRL_PFC_R8A77960
981         if (model == SH_PFC_R8A77960)
982                 priv->pfc.info = &r8a77960_pinmux_info;
983 #endif
984 #ifdef CONFIG_PINCTRL_PFC_R8A77961
985         if (model == SH_PFC_R8A77961)
986                 priv->pfc.info = &r8a77961_pinmux_info;
987 #endif
988 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
989         if (model == SH_PFC_R8A774A1)
990                 priv->pfc.info = &r8a774a1_pinmux_info;
991 #endif
992 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
993         if (model == SH_PFC_R8A774B1)
994                 priv->pfc.info = &r8a774b1_pinmux_info;
995 #endif
996 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
997         if (model == SH_PFC_R8A774C0)
998                 priv->pfc.info = &r8a774c0_pinmux_info;
999 #endif
1000 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
1001         if (model == SH_PFC_R8A774E1)
1002                 priv->pfc.info = &r8a774e1_pinmux_info;
1003 #endif
1004 #ifdef CONFIG_PINCTRL_PFC_R8A77965
1005         if (model == SH_PFC_R8A77965)
1006                 priv->pfc.info = &r8a77965_pinmux_info;
1007 #endif
1008 #ifdef CONFIG_PINCTRL_PFC_R8A77970
1009         if (model == SH_PFC_R8A77970)
1010                 priv->pfc.info = &r8a77970_pinmux_info;
1011 #endif
1012 #ifdef CONFIG_PINCTRL_PFC_R8A77980
1013         if (model == SH_PFC_R8A77980)
1014                 priv->pfc.info = &r8a77980_pinmux_info;
1015 #endif
1016 #ifdef CONFIG_PINCTRL_PFC_R8A77990
1017         if (model == SH_PFC_R8A77990)
1018                 priv->pfc.info = &r8a77990_pinmux_info;
1019 #endif
1020 #ifdef CONFIG_PINCTRL_PFC_R8A77995
1021         if (model == SH_PFC_R8A77995)
1022                 priv->pfc.info = &r8a77995_pinmux_info;
1023 #endif
1024 #ifdef CONFIG_PINCTRL_PFC_R8A779A0
1025         if (model == SH_PFC_R8A779A0)
1026                 priv->pfc.info = &r8a779a0_pinmux_info;
1027 #endif
1028
1029         priv->pmx.pfc = &priv->pfc;
1030         sh_pfc_init_ranges(&priv->pfc);
1031         sh_pfc_map_pins(&priv->pfc, &priv->pmx);
1032
1033         return 0;
1034 }
1035
1036 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
1037 #ifdef CONFIG_PINCTRL_PFC_R8A7790
1038         {
1039                 .compatible = "renesas,pfc-r8a7790",
1040                 .data = SH_PFC_R8A7790,
1041         },
1042 #endif
1043 #ifdef CONFIG_PINCTRL_PFC_R8A7791
1044         {
1045                 .compatible = "renesas,pfc-r8a7791",
1046                 .data = SH_PFC_R8A7791,
1047         },
1048 #endif
1049 #ifdef CONFIG_PINCTRL_PFC_R8A7792
1050         {
1051                 .compatible = "renesas,pfc-r8a7792",
1052                 .data = SH_PFC_R8A7792,
1053         },
1054 #endif
1055 #ifdef CONFIG_PINCTRL_PFC_R8A7793
1056         {
1057                 .compatible = "renesas,pfc-r8a7793",
1058                 .data = SH_PFC_R8A7793,
1059         },
1060 #endif
1061 #ifdef CONFIG_PINCTRL_PFC_R8A7794
1062         {
1063                 .compatible = "renesas,pfc-r8a7794",
1064                 .data = SH_PFC_R8A7794,
1065         },
1066 #endif
1067 #ifdef CONFIG_PINCTRL_PFC_R8A77951
1068         {
1069                 .compatible = "renesas,pfc-r8a7795",
1070                 .data = SH_PFC_R8A7795,
1071         },
1072 #endif
1073 #ifdef CONFIG_PINCTRL_PFC_R8A77960
1074         {
1075                 .compatible = "renesas,pfc-r8a7796",
1076                 .data = SH_PFC_R8A77960,
1077         },
1078 #endif
1079 #ifdef CONFIG_PINCTRL_PFC_R8A77961
1080         {
1081                 .compatible = "renesas,pfc-r8a77961",
1082                 .data = SH_PFC_R8A77961,
1083         },
1084 #endif
1085 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
1086         {
1087                 .compatible = "renesas,pfc-r8a774a1",
1088                 .data = SH_PFC_R8A774A1,
1089         },
1090 #endif
1091 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
1092         {
1093                 .compatible = "renesas,pfc-r8a774b1",
1094                 .data = SH_PFC_R8A774B1,
1095         },
1096 #endif
1097 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
1098         {
1099                 .compatible = "renesas,pfc-r8a774c0",
1100                 .data = SH_PFC_R8A774C0,
1101         },
1102 #endif
1103 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
1104         {
1105                 .compatible = "renesas,pfc-r8a774e1",
1106                 .data = SH_PFC_R8A774E1,
1107         },
1108 #endif
1109 #ifdef CONFIG_PINCTRL_PFC_R8A77965
1110         {
1111                 .compatible = "renesas,pfc-r8a77965",
1112                 .data = SH_PFC_R8A77965,
1113         },
1114 #endif
1115 #ifdef CONFIG_PINCTRL_PFC_R8A77970
1116         {
1117                 .compatible = "renesas,pfc-r8a77970",
1118                 .data = SH_PFC_R8A77970,
1119         },
1120 #endif
1121 #ifdef CONFIG_PINCTRL_PFC_R8A77980
1122         {
1123                 .compatible = "renesas,pfc-r8a77980",
1124                 .data = SH_PFC_R8A77980,
1125         },
1126 #endif
1127 #ifdef CONFIG_PINCTRL_PFC_R8A77990
1128         {
1129                 .compatible = "renesas,pfc-r8a77990",
1130                 .data = SH_PFC_R8A77990,
1131         },
1132 #endif
1133 #ifdef CONFIG_PINCTRL_PFC_R8A77995
1134         {
1135                 .compatible = "renesas,pfc-r8a77995",
1136                 .data = SH_PFC_R8A77995,
1137         },
1138 #endif
1139 #ifdef CONFIG_PINCTRL_PFC_R8A779A0
1140         {
1141                 .compatible = "renesas,pfc-r8a779a0",
1142                 .data = SH_PFC_R8A779A0,
1143         },
1144 #endif
1145
1146         { },
1147 };
1148
1149 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
1150         .name           = "sh_pfc_pinctrl",
1151         .id             = UCLASS_PINCTRL,
1152         .of_match       = sh_pfc_pinctrl_ids,
1153         .priv_auto      = sizeof(struct sh_pfc_pinctrl_priv),
1154         .ops            = &sh_pfc_pinctrl_ops,
1155         .probe          = sh_pfc_pinctrl_probe,
1156 };