drivers/pinctrl/renesas/pfc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pin Control driver for SuperH Pin Function Controller.
   4  *
   5  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   6  *
   7  * Copyright (C) 2008 Magnus Damm
   8  * Copyright (C) 2009 - 2012 Paul Mundt
   9  * Copyright (C) 2017 Marek Vasut
  10  */
  11
  12 #define DRV_NAME "sh-pfc"
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <dm/device_compat.h>
  18 #include <dm/devres.h>
  19 #include <dm/pinctrl.h>
  20 #include <linux/bitops.h>
  21 #include <linux/bug.h>
  22 #include <linux/io.h>
  23 #include <linux/sizes.h>
  24
  25 #include "sh_pfc.h"
  26
  27 enum sh_pfc_model {
  28         SH_PFC_R8A7790 = 0,
  29         SH_PFC_R8A7791,
  30         SH_PFC_R8A7792,
  31         SH_PFC_R8A7793,
  32         SH_PFC_R8A7794,
  33         SH_PFC_R8A7795,
  34         SH_PFC_R8A7796,
  35         SH_PFC_R8A774A1,
  36         SH_PFC_R8A77965,
  37         SH_PFC_R8A77970,
  38         SH_PFC_R8A77980,
  39         SH_PFC_R8A77990,
  40         SH_PFC_R8A77995,
  41 };
  42
  43 struct sh_pfc_pin_config {
  44         u32 type;
  45 };
  46
  47 struct sh_pfc_pinctrl {
  48         struct sh_pfc *pfc;
  49
  50         struct sh_pfc_pin_config *configs;
  51
  52         const char *func_prop_name;
  53         const char *groups_prop_name;
  54         const char *pins_prop_name;
  55 };
  56
  57 struct sh_pfc_pin_range {
  58         u16 start;
  59         u16 end;
  60 };
  61
  62 struct sh_pfc_pinctrl_priv {
  63         struct sh_pfc                   pfc;
  64         struct sh_pfc_pinctrl           pmx;
  65 };
  66
  67 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
  68 {
  69         unsigned int offset;
  70         unsigned int i;
  71
  72         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
  73                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
  74
  75                 if (pin <= range->end)
  76                         return pin >= range->start
  77                              ? offset + pin - range->start : -1;
  78
  79                 offset += range->end - range->start + 1;
  80         }
  81
  82         return -EINVAL;
  83 }
  84
  85 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
  86 {
  87         if (enum_id < r->begin)
  88                 return 0;
  89
  90         if (enum_id > r->end)
  91                 return 0;
  92
  93         return 1;
  94 }
  95
  96 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
  97 {
  98         switch (reg_width) {
  99         case 8:
 100                 return readb(mapped_reg);
 101         case 16:
 102                 return readw(mapped_reg);
 103         case 32:
 104                 return readl(mapped_reg);
 105         }
 106
 107         BUG();
 108         return 0;
 109 }
 110
 111 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 112                           u32 data)
 113 {
 114         switch (reg_width) {
 115         case 8:
 116                 writeb(data, mapped_reg);
 117                 return;
 118         case 16:
 119                 writew(data, mapped_reg);
 120                 return;
 121         case 32:
 122                 writel(data, mapped_reg);
 123                 return;
 124         }
 125
 126         BUG();
 127 }
 128
 129 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
 130 {
 131         return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
 132 }
 133
 134 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
 135 {
 136         void __iomem *unlock_reg =
 137                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 138
 139         if (pfc->info->unlock_reg)
 140                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 141
 142         sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
 143 }
 144
 145 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 146                                      const struct pinmux_cfg_reg *crp,
 147                                      unsigned int in_pos,
 148                                      void __iomem **mapped_regp, u32 *maskp,
 149                                      unsigned int *posp)
 150 {
 151         unsigned int k;
 152
 153         *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
 154
 155         if (crp->field_width) {
 156                 *maskp = (1 << crp->field_width) - 1;
 157                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 158         } else {
 159                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 160                 *posp = crp->reg_width;
 161                 for (k = 0; k <= in_pos; k++)
 162                         *posp -= crp->var_field_width[k];
 163         }
 164 }
 165
 166 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 167                                     const struct pinmux_cfg_reg *crp,
 168                                     unsigned int field, u32 value)
 169 {
 170         void __iomem *mapped_reg;
 171         void __iomem *unlock_reg =
 172                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 173         unsigned int pos;
 174         u32 mask, data;
 175
 176         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 177
 178         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 179                 "r_width = %u, f_width = %u\n",
 180                 crp->reg, value, field, crp->reg_width, crp->field_width);
 181
 182         mask = ~(mask << pos);
 183         value = value << pos;
 184
 185         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 186         data &= mask;
 187         data |= value;
 188
 189         if (pfc->info->unlock_reg)
 190                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 191
 192         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 193 }
 194
 195 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 196                                  const struct pinmux_cfg_reg **crp,
 197                                  unsigned int *fieldp, u32 *valuep)
 198 {
 199         unsigned int k = 0;
 200
 201         while (1) {
 202                 const struct pinmux_cfg_reg *config_reg =
 203                         pfc->info->cfg_regs + k;
 204                 unsigned int r_width = config_reg->reg_width;
 205                 unsigned int f_width = config_reg->field_width;
 206                 unsigned int curr_width;
 207                 unsigned int bit_pos;
 208                 unsigned int pos = 0;
 209                 unsigned int m = 0;
 210
 211                 if (!r_width)
 212                         break;
 213
 214                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 215                         u32 ncomb;
 216                         u32 n;
 217
 218                         if (f_width)
 219                                 curr_width = f_width;
 220                         else
 221                                 curr_width = config_reg->var_field_width[m];
 222
 223                         ncomb = 1 << curr_width;
 224                         for (n = 0; n < ncomb; n++) {
 225                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 226                                         *crp = config_reg;
 227                                         *fieldp = m;
 228                                         *valuep = n;
 229                                         return 0;
 230                                 }
 231                         }
 232                         pos += ncomb;
 233                         m++;
 234                 }
 235                 k++;
 236         }
 237
 238         return -EINVAL;
 239 }
 240
 241 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 242                               u16 *enum_idp)
 243 {
 244         const u16 *data = pfc->info->pinmux_data;
 245         unsigned int k;
 246
 247         if (pos) {
 248                 *enum_idp = data[pos + 1];
 249                 return pos + 1;
 250         }
 251
 252         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 253                 if (data[k] == mark) {
 254                         *enum_idp = data[k + 1];
 255                         return k + 1;
 256                 }
 257         }
 258
 259         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 260                 mark);
 261         return -EINVAL;
 262 }
 263
 264 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 265 {
 266         const struct pinmux_range *range;
 267         int pos = 0;
 268
 269         switch (pinmux_type) {
 270         case PINMUX_TYPE_GPIO:
 271         case PINMUX_TYPE_FUNCTION:
 272                 range = NULL;
 273                 break;
 274
 275         case PINMUX_TYPE_OUTPUT:
 276                 range = &pfc->info->output;
 277                 break;
 278
 279         case PINMUX_TYPE_INPUT:
 280                 range = &pfc->info->input;
 281                 break;
 282
 283         default:
 284                 return -EINVAL;
 285         }
 286
 287         /* Iterate over all the configuration fields we need to update. */
 288         while (1) {
 289                 const struct pinmux_cfg_reg *cr;
 290                 unsigned int field;
 291                 u16 enum_id;
 292                 u32 value;
 293                 int in_range;
 294                 int ret;
 295
 296                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 297                 if (pos < 0)
 298                         return pos;
 299
 300                 if (!enum_id)
 301                         break;
 302
 303                 /* Check if the configuration field selects a function. If it
 304                  * doesn't, skip the field if it's not applicable to the
 305                  * requested pinmux type.
 306                  */
 307                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 308                 if (!in_range) {
 309                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 310                                 /* Functions are allowed to modify all
 311                                  * fields.
 312                                  */
 313                                 in_range = 1;
 314                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 315                                 /* Input/output types can only modify fields
 316                                  * that correspond to their respective ranges.
 317                                  */
 318                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 319
 320                                 /*
 321                                  * special case pass through for fixed
 322                                  * input-only or output-only pins without
 323                                  * function enum register association.
 324                                  */
 325                                 if (in_range && enum_id == range->force)
 326                                         continue;
 327                         }
 328                         /* GPIOs are only allowed to modify function fields. */
 329                 }
 330
 331                 if (!in_range)
 332                         continue;
 333
 334                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 335                 if (ret < 0)
 336                         return ret;
 337
 338                 sh_pfc_write_config_reg(pfc, cr, field, value);
 339         }
 340
 341         return 0;
 342 }
 343
 344 const struct pinmux_bias_reg *
 345 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
 346                        unsigned int *bit)
 347 {
 348         unsigned int i, j;
 349
 350         for (i = 0; pfc->info->bias_regs[i].puen; i++) {
 351                 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
 352                         if (pfc->info->bias_regs[i].pins[j] == pin) {
 353                                 *bit = j;
 354                                 return &pfc->info->bias_regs[i];
 355                         }
 356                 }
 357         }
 358
 359         WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
 360
 361         return NULL;
 362 }
 363
 364 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 365 {
 366         struct sh_pfc_pin_range *range;
 367         unsigned int nr_ranges;
 368         unsigned int i;
 369
 370         if (pfc->info->pins[0].pin == (u16)-1) {
 371                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 372                  * in its pin arrays yet. Consider the pin numbers range as
 373                  * continuous and allocate a single range.
 374                  */
 375                 pfc->nr_ranges = 1;
 376                 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
 377                 if (pfc->ranges == NULL)
 378                         return -ENOMEM;
 379
 380                 pfc->ranges->start = 0;
 381                 pfc->ranges->end = pfc->info->nr_pins - 1;
 382                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 383
 384                 return 0;
 385         }
 386
 387         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 388          * be sorted by pin numbers, and pins without a GPIO port must come
 389          * last.
 390          */
 391         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 392                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 393                         nr_ranges++;
 394         }
 395
 396         pfc->nr_ranges = nr_ranges;
 397         pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
 398         if (pfc->ranges == NULL)
 399                 return -ENOMEM;
 400
 401         range = pfc->ranges;
 402         range->start = pfc->info->pins[0].pin;
 403
 404         for (i = 1; i < pfc->info->nr_pins; ++i) {
 405                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 406                         continue;
 407
 408                 range->end = pfc->info->pins[i-1].pin;
 409                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 410                         pfc->nr_gpio_pins = range->end + 1;
 411
 412                 range++;
 413                 range->start = pfc->info->pins[i].pin;
 414         }
 415
 416         range->end = pfc->info->pins[i-1].pin;
 417         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 418                 pfc->nr_gpio_pins = range->end + 1;
 419
 420         return 0;
 421 }
 422
 423 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
 424 {
 425         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 426
 427         return priv->pfc.info->nr_pins;
 428 }
 429
 430 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
 431                                                   unsigned selector)
 432 {
 433         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 434
 435         return priv->pfc.info->pins[selector].name;
 436 }
 437
 438 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
 439 {
 440         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 441
 442         return priv->pfc.info->nr_groups;
 443 }
 444
 445 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
 446                                                   unsigned selector)
 447 {
 448         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 449
 450         return priv->pfc.info->groups[selector].name;
 451 }
 452
 453 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
 454 {
 455         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 456
 457         return priv->pfc.info->nr_functions;
 458 }
 459
 460 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
 461                                                   unsigned selector)
 462 {
 463         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 464
 465         return priv->pfc.info->functions[selector].name;
 466 }
 467
 468 static int sh_pfc_gpio_request_enable(struct udevice *dev,
 469                                       unsigned pin_selector)
 470 {
 471         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 472         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 473         struct sh_pfc *pfc = &priv->pfc;
 474         struct sh_pfc_pin_config *cfg;
 475         const struct sh_pfc_pin *pin = NULL;
 476         int i, ret, idx;
 477
 478         for (i = 0; i < pfc->info->nr_pins; i++) {
 479                 if (priv->pfc.info->pins[i].pin != pin_selector)
 480                         continue;
 481
 482                 pin = &priv->pfc.info->pins[i];
 483                 break;
 484         }
 485
 486         if (!pin)
 487                 return -EINVAL;
 488
 489         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 490         cfg = &pmx->configs[idx];
 491
 492         if (cfg->type != PINMUX_TYPE_NONE)
 493                 return -EBUSY;
 494
 495         ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
 496         if (ret)
 497                 return ret;
 498
 499         cfg->type = PINMUX_TYPE_GPIO;
 500
 501         return 0;
 502 }
 503
 504 static int sh_pfc_gpio_disable_free(struct udevice *dev,
 505                                     unsigned pin_selector)
 506 {
 507         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 508         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 509         struct sh_pfc *pfc = &priv->pfc;
 510         struct sh_pfc_pin_config *cfg;
 511         const struct sh_pfc_pin *pin = NULL;
 512         int i, idx;
 513
 514         for (i = 0; i < pfc->info->nr_pins; i++) {
 515                 if (priv->pfc.info->pins[i].pin != pin_selector)
 516                         continue;
 517
 518                 pin = &priv->pfc.info->pins[i];
 519                 break;
 520         }
 521
 522         if (!pin)
 523                 return -EINVAL;
 524
 525         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 526         cfg = &pmx->configs[idx];
 527
 528         cfg->type = PINMUX_TYPE_NONE;
 529
 530         return 0;
 531 }
 532
 533 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
 534                                   unsigned func_selector)
 535 {
 536         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 537         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 538         struct sh_pfc *pfc = &priv->pfc;
 539         const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
 540         int idx = sh_pfc_get_pin_index(pfc, pin->pin);
 541         struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 542
 543         if (cfg->type != PINMUX_TYPE_NONE)
 544                 return -EBUSY;
 545
 546         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
 547 }
 548
 549 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
 550                                      unsigned func_selector)
 551 {
 552         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 553         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 554         struct sh_pfc *pfc = &priv->pfc;
 555         const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
 556         unsigned int i;
 557         int ret = 0;
 558
 559         for (i = 0; i < grp->nr_pins; ++i) {
 560                 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
 561                 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 562
 563                 if (cfg->type != PINMUX_TYPE_NONE) {
 564                         ret = -EBUSY;
 565                         goto done;
 566                 }
 567         }
 568
 569         for (i = 0; i < grp->nr_pins; ++i) {
 570                 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
 571                 if (ret < 0)
 572                         break;
 573         }
 574
 575 done:
 576         return ret;
 577 }
 578 #if CONFIG_IS_ENABLED(PINCONF)
 579 static const struct pinconf_param sh_pfc_pinconf_params[] = {
 580         { "bias-disable",       PIN_CONFIG_BIAS_DISABLE,        0 },
 581         { "bias-pull-up",       PIN_CONFIG_BIAS_PULL_UP,        1 },
 582         { "bias-pull-down",     PIN_CONFIG_BIAS_PULL_DOWN,      1 },
 583         { "drive-strength",     PIN_CONFIG_DRIVE_STRENGTH,      0 },
 584         { "power-source",       PIN_CONFIG_POWER_SOURCE,        3300 },
 585 };
 586
 587 static void __iomem *
 588 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
 589                                        unsigned int *offset, unsigned int *size)
 590 {
 591         const struct pinmux_drive_reg_field *field;
 592         const struct pinmux_drive_reg *reg;
 593         unsigned int i;
 594
 595         for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
 596                 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
 597                         field = &reg->fields[i];
 598
 599                         if (field->size && field->pin == pin) {
 600                                 *offset = field->offset;
 601                                 *size = field->size;
 602
 603                                 return (void __iomem *)(uintptr_t)reg->reg;
 604                         }
 605                 }
 606         }
 607
 608         return NULL;
 609 }
 610
 611 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
 612                                              unsigned int pin, u16 strength)
 613 {
 614         unsigned int offset;
 615         unsigned int size;
 616         unsigned int step;
 617         void __iomem *reg;
 618         void __iomem *unlock_reg =
 619                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 620         u32 val;
 621
 622         reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
 623         if (!reg)
 624                 return -EINVAL;
 625
 626         step = size == 2 ? 6 : 3;
 627
 628         if (strength < step || strength > 24)
 629                 return -EINVAL;
 630
 631         /* Convert the value from mA based on a full drive strength value of
 632          * 24mA. We can make the full value configurable later if needed.
 633          */
 634         strength = strength / step - 1;
 635
 636         val = sh_pfc_read_raw_reg(reg, 32);
 637         val &= ~GENMASK(offset + 4 - 1, offset);
 638         val |= strength << offset;
 639
 640         if (unlock_reg)
 641                 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 642
 643         sh_pfc_write_raw_reg(reg, 32, val);
 644
 645         return 0;
 646 }
 647
 648 /* Check whether the requested parameter is supported for a pin. */
 649 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
 650                                     unsigned int param)
 651 {
 652         int idx = sh_pfc_get_pin_index(pfc, _pin);
 653         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
 654
 655         switch (param) {
 656         case PIN_CONFIG_BIAS_DISABLE:
 657                 return pin->configs &
 658                         (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
 659
 660         case PIN_CONFIG_BIAS_PULL_UP:
 661                 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
 662
 663         case PIN_CONFIG_BIAS_PULL_DOWN:
 664                 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
 665
 666         case PIN_CONFIG_DRIVE_STRENGTH:
 667                 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
 668
 669         case PIN_CONFIG_POWER_SOURCE:
 670                 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
 671
 672         default:
 673                 return false;
 674         }
 675 }
 676
 677 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
 678                               unsigned int param, unsigned int arg)
 679 {
 680         struct sh_pfc *pfc = pmx->pfc;
 681         void __iomem *pocctrl;
 682         void __iomem *unlock_reg =
 683                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 684         u32 addr, val;
 685         int bit, ret;
 686
 687         if (!sh_pfc_pinconf_validate(pfc, _pin, param))
 688                 return -ENOTSUPP;
 689
 690         switch (param) {
 691         case PIN_CONFIG_BIAS_PULL_UP:
 692         case PIN_CONFIG_BIAS_PULL_DOWN:
 693         case PIN_CONFIG_BIAS_DISABLE:
 694                 if (!pfc->info->ops || !pfc->info->ops->set_bias)
 695                         return -ENOTSUPP;
 696
 697                 pfc->info->ops->set_bias(pfc, _pin, param);
 698
 699                 break;
 700
 701         case PIN_CONFIG_DRIVE_STRENGTH:
 702                 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
 703                 if (ret < 0)
 704                         return ret;
 705
 706                 break;
 707
 708         case PIN_CONFIG_POWER_SOURCE:
 709                 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
 710                         return -ENOTSUPP;
 711
 712                 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
 713                 if (bit < 0) {
 714                         printf("invalid pin %#x", _pin);
 715                         return bit;
 716                 }
 717
 718                 if (arg != 1800 && arg != 3300)
 719                         return -EINVAL;
 720
 721                 pocctrl = (void __iomem *)(uintptr_t)addr;
 722
 723                 val = sh_pfc_read_raw_reg(pocctrl, 32);
 724                 if (arg == 3300)
 725                         val |= BIT(bit);
 726                 else
 727                         val &= ~BIT(bit);
 728
 729                 if (unlock_reg)
 730                         sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 731
 732                 sh_pfc_write_raw_reg(pocctrl, 32, val);
 733
 734                 break;
 735
 736         default:
 737                 return -ENOTSUPP;
 738         }
 739
 740         return 0;
 741 }
 742
 743 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
 744                                   unsigned int pin_selector,
 745                                   unsigned int param, unsigned int arg)
 746 {
 747         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 748         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 749         struct sh_pfc *pfc = &priv->pfc;
 750         const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
 751
 752         sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
 753
 754         return 0;
 755 }
 756
 757 static int sh_pfc_pinconf_group_set(struct udevice *dev,
 758                                       unsigned int group_selector,
 759                                       unsigned int param, unsigned int arg)
 760 {
 761         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 762         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 763         struct sh_pfc *pfc = &priv->pfc;
 764         const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
 765         unsigned int i;
 766
 767         for (i = 0; i < grp->nr_pins; i++)
 768                 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
 769
 770         return 0;
 771 }
 772 #endif
 773
 774 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
 775         .get_pins_count         = sh_pfc_pinctrl_get_pins_count,
 776         .get_pin_name           = sh_pfc_pinctrl_get_pin_name,
 777         .get_groups_count       = sh_pfc_pinctrl_get_groups_count,
 778         .get_group_name         = sh_pfc_pinctrl_get_group_name,
 779         .get_functions_count    = sh_pfc_pinctrl_get_functions_count,
 780         .get_function_name      = sh_pfc_pinctrl_get_function_name,
 781
 782 #if CONFIG_IS_ENABLED(PINCONF)
 783         .pinconf_num_params     = ARRAY_SIZE(sh_pfc_pinconf_params),
 784         .pinconf_params         = sh_pfc_pinconf_params,
 785         .pinconf_set            = sh_pfc_pinconf_pin_set,
 786         .pinconf_group_set      = sh_pfc_pinconf_group_set,
 787 #endif
 788         .pinmux_set             = sh_pfc_pinctrl_pin_set,
 789         .pinmux_group_set       = sh_pfc_pinctrl_group_set,
 790         .set_state              = pinctrl_generic_set_state,
 791
 792         .gpio_request_enable    = sh_pfc_gpio_request_enable,
 793         .gpio_disable_free      = sh_pfc_gpio_disable_free,
 794 };
 795
 796 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
 797 {
 798         unsigned int i;
 799
 800         /* Allocate and initialize the pins and configs arrays. */
 801         pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
 802                                     GFP_KERNEL);
 803         if (unlikely(!pmx->configs))
 804                 return -ENOMEM;
 805
 806         for (i = 0; i < pfc->info->nr_pins; ++i) {
 807                 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
 808                 cfg->type = PINMUX_TYPE_NONE;
 809         }
 810
 811         return 0;
 812 }
 813
 814
 815 static int sh_pfc_pinctrl_probe(struct udevice *dev)
 816 {
 817         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 818         enum sh_pfc_model model = dev_get_driver_data(dev);
 819         fdt_addr_t base;
 820
 821         base = devfdt_get_addr(dev);
 822         if (base == FDT_ADDR_T_NONE)
 823                 return -EINVAL;
 824
 825         priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
 826         if (!priv->pfc.regs)
 827                 return -ENOMEM;
 828
 829 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 830         if (model == SH_PFC_R8A7790)
 831                 priv->pfc.info = &r8a7790_pinmux_info;
 832 #endif
 833 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 834         if (model == SH_PFC_R8A7791)
 835                 priv->pfc.info = &r8a7791_pinmux_info;
 836 #endif
 837 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 838         if (model == SH_PFC_R8A7792)
 839                 priv->pfc.info = &r8a7792_pinmux_info;
 840 #endif
 841 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 842         if (model == SH_PFC_R8A7793)
 843                 priv->pfc.info = &r8a7793_pinmux_info;
 844 #endif
 845 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 846         if (model == SH_PFC_R8A7794)
 847                 priv->pfc.info = &r8a7794_pinmux_info;
 848 #endif
 849 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 850         if (model == SH_PFC_R8A7795)
 851                 priv->pfc.info = &r8a7795_pinmux_info;
 852 #endif
 853 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 854         if (model == SH_PFC_R8A7796)
 855                 priv->pfc.info = &r8a7796_pinmux_info;
 856 #endif
 857 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
 858         if (model == SH_PFC_R8A774A1)
 859                 priv->pfc.info = &r8a774a1_pinmux_info;
 860 #endif
 861 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 862         if (model == SH_PFC_R8A77965)
 863                 priv->pfc.info = &r8a77965_pinmux_info;
 864 #endif
 865 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 866         if (model == SH_PFC_R8A77970)
 867                 priv->pfc.info = &r8a77970_pinmux_info;
 868 #endif
 869 #ifdef CONFIG_PINCTRL_PFC_R8A77980
 870         if (model == SH_PFC_R8A77980)
 871                 priv->pfc.info = &r8a77980_pinmux_info;
 872 #endif
 873 #ifdef CONFIG_PINCTRL_PFC_R8A77990
 874         if (model == SH_PFC_R8A77990)
 875                 priv->pfc.info = &r8a77990_pinmux_info;
 876 #endif
 877 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 878         if (model == SH_PFC_R8A77995)
 879                 priv->pfc.info = &r8a77995_pinmux_info;
 880 #endif
 881
 882         priv->pmx.pfc = &priv->pfc;
 883         sh_pfc_init_ranges(&priv->pfc);
 884         sh_pfc_map_pins(&priv->pfc, &priv->pmx);
 885
 886         return 0;
 887 }
 888
 889 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
 890 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 891         {
 892                 .compatible = "renesas,pfc-r8a7790",
 893                 .data = SH_PFC_R8A7790,
 894         },
 895 #endif
 896 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 897         {
 898                 .compatible = "renesas,pfc-r8a7791",
 899                 .data = SH_PFC_R8A7791,
 900         },
 901 #endif
 902 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 903         {
 904                 .compatible = "renesas,pfc-r8a7792",
 905                 .data = SH_PFC_R8A7792,
 906         },
 907 #endif
 908 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 909         {
 910                 .compatible = "renesas,pfc-r8a7793",
 911                 .data = SH_PFC_R8A7793,
 912         },
 913 #endif
 914 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 915         {
 916                 .compatible = "renesas,pfc-r8a7794",
 917                 .data = SH_PFC_R8A7794,
 918         },
 919 #endif
 920 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 921         {
 922                 .compatible = "renesas,pfc-r8a7795",
 923                 .data = SH_PFC_R8A7795,
 924         },
 925 #endif
 926 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 927         {
 928                 .compatible = "renesas,pfc-r8a7796",
 929                 .data = SH_PFC_R8A7796,
 930         },
 931 #endif
 932 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
 933         {
 934                 .compatible = "renesas,pfc-r8a774a1",
 935                 .data = SH_PFC_R8A774A1,
 936         },
 937 #endif
 938 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 939         {
 940                 .compatible = "renesas,pfc-r8a77965",
 941                 .data = SH_PFC_R8A77965,
 942         },
 943 #endif
 944 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 945         {
 946                 .compatible = "renesas,pfc-r8a77970",
 947                 .data = SH_PFC_R8A77970,
 948         },
 949 #endif
 950 #ifdef CONFIG_PINCTRL_PFC_R8A77980
 951         {
 952                 .compatible = "renesas,pfc-r8a77980",
 953                 .data = SH_PFC_R8A77980,
 954         },
 955 #endif
 956 #ifdef CONFIG_PINCTRL_PFC_R8A77990
 957         {
 958                 .compatible = "renesas,pfc-r8a77990",
 959                 .data = SH_PFC_R8A77990,
 960         },
 961 #endif
 962 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 963         {
 964                 .compatible = "renesas,pfc-r8a77995",
 965                 .data = SH_PFC_R8A77995,
 966         },
 967 #endif
 968         { },
 969 };
 970
 971 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
 972         .name           = "sh_pfc_pinctrl",
 973         .id             = UCLASS_PINCTRL,
 974         .of_match       = sh_pfc_pinctrl_ids,
 975         .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
 976         .ops            = &sh_pfc_pinctrl_ops,
 977         .probe          = sh_pfc_pinctrl_probe,
 978 };