drivers/pinctrl/renesas/pfc.c

   1 /*
   2  * Pin Control driver for SuperH Pin Function Controller.
   3  *
   4  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   5  *
   6  * Copyright (C) 2008 Magnus Damm
   7  * Copyright (C) 2009 - 2012 Paul Mundt
   8  * Copyright (C) 2017 Marek Vasut
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0
  11  */
  12
  13 #define DRV_NAME "sh-pfc"
  14
  15 #include <common.h>
  16 #include <dm.h>
  17 #include <errno.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/io.h>
  20 #include <linux/sizes.h>
  21
  22 #include "sh_pfc.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 enum sh_pfc_model {
  27         SH_PFC_R8A7795 = 0,
  28         SH_PFC_R8A7796,
  29         SH_PFC_R8A77970,
  30 };
  31
  32 struct sh_pfc_pin_config {
  33         u32 type;
  34 };
  35
  36 struct sh_pfc_pinctrl {
  37         struct sh_pfc *pfc;
  38
  39         struct sh_pfc_pin_config *configs;
  40
  41         const char *func_prop_name;
  42         const char *groups_prop_name;
  43         const char *pins_prop_name;
  44 };
  45
  46 struct sh_pfc_pin_range {
  47         u16 start;
  48         u16 end;
  49 };
  50
  51 struct sh_pfc_pinctrl_priv {
  52         struct sh_pfc                   pfc;
  53         struct sh_pfc_pinctrl           pmx;
  54 };
  55
  56 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
  57 {
  58         unsigned int offset;
  59         unsigned int i;
  60
  61         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
  62                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
  63
  64                 if (pin <= range->end)
  65                         return pin >= range->start
  66                              ? offset + pin - range->start : -1;
  67
  68                 offset += range->end - range->start + 1;
  69         }
  70
  71         return -EINVAL;
  72 }
  73
  74 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
  75 {
  76         if (enum_id < r->begin)
  77                 return 0;
  78
  79         if (enum_id > r->end)
  80                 return 0;
  81
  82         return 1;
  83 }
  84
  85 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
  86 {
  87         switch (reg_width) {
  88         case 8:
  89                 return readb(mapped_reg);
  90         case 16:
  91                 return readw(mapped_reg);
  92         case 32:
  93                 return readl(mapped_reg);
  94         }
  95
  96         BUG();
  97         return 0;
  98 }
  99
 100 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 101                           u32 data)
 102 {
 103         switch (reg_width) {
 104         case 8:
 105                 writeb(data, mapped_reg);
 106                 return;
 107         case 16:
 108                 writew(data, mapped_reg);
 109                 return;
 110         case 32:
 111                 writel(data, mapped_reg);
 112                 return;
 113         }
 114
 115         BUG();
 116 }
 117
 118 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
 119 {
 120         return sh_pfc_read_raw_reg(pfc->regs + reg, width);
 121 }
 122
 123 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
 124 {
 125         void __iomem *unlock_reg =
 126                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 127
 128         if (pfc->info->unlock_reg)
 129                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 130
 131         sh_pfc_write_raw_reg(pfc->regs + reg, width, data);
 132 }
 133
 134 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 135                                      const struct pinmux_cfg_reg *crp,
 136                                      unsigned int in_pos,
 137                                      void __iomem **mapped_regp, u32 *maskp,
 138                                      unsigned int *posp)
 139 {
 140         unsigned int k;
 141
 142         *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
 143
 144         if (crp->field_width) {
 145                 *maskp = (1 << crp->field_width) - 1;
 146                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 147         } else {
 148                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 149                 *posp = crp->reg_width;
 150                 for (k = 0; k <= in_pos; k++)
 151                         *posp -= crp->var_field_width[k];
 152         }
 153 }
 154
 155 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 156                                     const struct pinmux_cfg_reg *crp,
 157                                     unsigned int field, u32 value)
 158 {
 159         void __iomem *mapped_reg;
 160         void __iomem *unlock_reg =
 161                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 162         unsigned int pos;
 163         u32 mask, data;
 164
 165         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 166
 167         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 168                 "r_width = %u, f_width = %u\n",
 169                 crp->reg, value, field, crp->reg_width, crp->field_width);
 170
 171         mask = ~(mask << pos);
 172         value = value << pos;
 173
 174         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 175         data &= mask;
 176         data |= value;
 177
 178         if (pfc->info->unlock_reg)
 179                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 180
 181         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 182 }
 183
 184 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 185                                  const struct pinmux_cfg_reg **crp,
 186                                  unsigned int *fieldp, u32 *valuep)
 187 {
 188         unsigned int k = 0;
 189
 190         while (1) {
 191                 const struct pinmux_cfg_reg *config_reg =
 192                         pfc->info->cfg_regs + k;
 193                 unsigned int r_width = config_reg->reg_width;
 194                 unsigned int f_width = config_reg->field_width;
 195                 unsigned int curr_width;
 196                 unsigned int bit_pos;
 197                 unsigned int pos = 0;
 198                 unsigned int m = 0;
 199
 200                 if (!r_width)
 201                         break;
 202
 203                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 204                         u32 ncomb;
 205                         u32 n;
 206
 207                         if (f_width)
 208                                 curr_width = f_width;
 209                         else
 210                                 curr_width = config_reg->var_field_width[m];
 211
 212                         ncomb = 1 << curr_width;
 213                         for (n = 0; n < ncomb; n++) {
 214                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 215                                         *crp = config_reg;
 216                                         *fieldp = m;
 217                                         *valuep = n;
 218                                         return 0;
 219                                 }
 220                         }
 221                         pos += ncomb;
 222                         m++;
 223                 }
 224                 k++;
 225         }
 226
 227         return -EINVAL;
 228 }
 229
 230 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 231                               u16 *enum_idp)
 232 {
 233         const u16 *data = pfc->info->pinmux_data;
 234         unsigned int k;
 235
 236         if (pos) {
 237                 *enum_idp = data[pos + 1];
 238                 return pos + 1;
 239         }
 240
 241         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 242                 if (data[k] == mark) {
 243                         *enum_idp = data[k + 1];
 244                         return k + 1;
 245                 }
 246         }
 247
 248         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 249                 mark);
 250         return -EINVAL;
 251 }
 252
 253 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 254 {
 255         const struct pinmux_range *range;
 256         int pos = 0;
 257
 258         switch (pinmux_type) {
 259         case PINMUX_TYPE_GPIO:
 260         case PINMUX_TYPE_FUNCTION:
 261                 range = NULL;
 262                 break;
 263
 264         case PINMUX_TYPE_OUTPUT:
 265                 range = &pfc->info->output;
 266                 break;
 267
 268         case PINMUX_TYPE_INPUT:
 269                 range = &pfc->info->input;
 270                 break;
 271
 272         default:
 273                 return -EINVAL;
 274         }
 275
 276         /* Iterate over all the configuration fields we need to update. */
 277         while (1) {
 278                 const struct pinmux_cfg_reg *cr;
 279                 unsigned int field;
 280                 u16 enum_id;
 281                 u32 value;
 282                 int in_range;
 283                 int ret;
 284
 285                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 286                 if (pos < 0)
 287                         return pos;
 288
 289                 if (!enum_id)
 290                         break;
 291
 292                 /* Check if the configuration field selects a function. If it
 293                  * doesn't, skip the field if it's not applicable to the
 294                  * requested pinmux type.
 295                  */
 296                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 297                 if (!in_range) {
 298                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 299                                 /* Functions are allowed to modify all
 300                                  * fields.
 301                                  */
 302                                 in_range = 1;
 303                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 304                                 /* Input/output types can only modify fields
 305                                  * that correspond to their respective ranges.
 306                                  */
 307                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 308
 309                                 /*
 310                                  * special case pass through for fixed
 311                                  * input-only or output-only pins without
 312                                  * function enum register association.
 313                                  */
 314                                 if (in_range && enum_id == range->force)
 315                                         continue;
 316                         }
 317                         /* GPIOs are only allowed to modify function fields. */
 318                 }
 319
 320                 if (!in_range)
 321                         continue;
 322
 323                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 324                 if (ret < 0)
 325                         return ret;
 326
 327                 sh_pfc_write_config_reg(pfc, cr, field, value);
 328         }
 329
 330         return 0;
 331 }
 332
 333 const struct sh_pfc_bias_info *
 334 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
 335                         unsigned int num, unsigned int pin)
 336 {
 337         unsigned int i;
 338
 339         for (i = 0; i < num; i++)
 340                 if (info[i].pin == pin)
 341                         return &info[i];
 342
 343         printf("Pin %u is not in bias info list\n", pin);
 344
 345         return NULL;
 346 }
 347
 348 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 349 {
 350         struct sh_pfc_pin_range *range;
 351         unsigned int nr_ranges;
 352         unsigned int i;
 353
 354         if (pfc->info->pins[0].pin == (u16)-1) {
 355                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 356                  * in its pin arrays yet. Consider the pin numbers range as
 357                  * continuous and allocate a single range.
 358                  */
 359                 pfc->nr_ranges = 1;
 360                 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
 361                 if (pfc->ranges == NULL)
 362                         return -ENOMEM;
 363
 364                 pfc->ranges->start = 0;
 365                 pfc->ranges->end = pfc->info->nr_pins - 1;
 366                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 367
 368                 return 0;
 369         }
 370
 371         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 372          * be sorted by pin numbers, and pins without a GPIO port must come
 373          * last.
 374          */
 375         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 376                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 377                         nr_ranges++;
 378         }
 379
 380         pfc->nr_ranges = nr_ranges;
 381         pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
 382         if (pfc->ranges == NULL)
 383                 return -ENOMEM;
 384
 385         range = pfc->ranges;
 386         range->start = pfc->info->pins[0].pin;
 387
 388         for (i = 1; i < pfc->info->nr_pins; ++i) {
 389                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 390                         continue;
 391
 392                 range->end = pfc->info->pins[i-1].pin;
 393                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 394                         pfc->nr_gpio_pins = range->end + 1;
 395
 396                 range++;
 397                 range->start = pfc->info->pins[i].pin;
 398         }
 399
 400         range->end = pfc->info->pins[i-1].pin;
 401         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 402                 pfc->nr_gpio_pins = range->end + 1;
 403
 404         return 0;
 405 }
 406
 407 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
 408 {
 409         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 410
 411         return priv->pfc.info->nr_pins;
 412 }
 413
 414 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
 415                                                   unsigned selector)
 416 {
 417         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 418
 419         return priv->pfc.info->pins[selector].name;
 420 }
 421
 422 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
 423 {
 424         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 425
 426         return priv->pfc.info->nr_groups;
 427 }
 428
 429 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
 430                                                   unsigned selector)
 431 {
 432         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 433
 434         return priv->pfc.info->groups[selector].name;
 435 }
 436
 437 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
 438 {
 439         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 440
 441         return priv->pfc.info->nr_functions;
 442 }
 443
 444 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
 445                                                   unsigned selector)
 446 {
 447         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 448
 449         return priv->pfc.info->functions[selector].name;
 450 }
 451
 452 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
 453 {
 454         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 455         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 456         struct sh_pfc *pfc = &priv->pfc;
 457         struct sh_pfc_pin_config *cfg;
 458         const struct sh_pfc_pin *pin = NULL;
 459         int i, idx;
 460
 461         for (i = 1; i < pfc->info->nr_pins; i++) {
 462                 if (priv->pfc.info->pins[i].pin != pin_selector)
 463                         continue;
 464
 465                 pin = &priv->pfc.info->pins[i];
 466                 break;
 467         }
 468
 469         if (!pin)
 470                 return -EINVAL;
 471
 472         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 473         cfg = &pmx->configs[idx];
 474
 475         if (cfg->type != PINMUX_TYPE_NONE)
 476                 return -EBUSY;
 477
 478         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
 479 }
 480
 481 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
 482                                   unsigned func_selector)
 483 {
 484         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 485         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 486         struct sh_pfc *pfc = &priv->pfc;
 487         const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
 488         int idx = sh_pfc_get_pin_index(pfc, pin->pin);
 489         struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 490
 491         if (cfg->type != PINMUX_TYPE_NONE)
 492                 return -EBUSY;
 493
 494         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
 495 }
 496
 497 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
 498                                      unsigned func_selector)
 499 {
 500         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 501         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 502         struct sh_pfc *pfc = &priv->pfc;
 503         const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
 504         unsigned int i;
 505         int ret = 0;
 506
 507         for (i = 0; i < grp->nr_pins; ++i) {
 508                 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
 509                 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 510
 511                 if (cfg->type != PINMUX_TYPE_NONE) {
 512                         ret = -EBUSY;
 513                         goto done;
 514                 }
 515         }
 516
 517         for (i = 0; i < grp->nr_pins; ++i) {
 518                 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
 519                 if (ret < 0)
 520                         break;
 521         }
 522
 523 done:
 524         return ret;
 525 }
 526 #if CONFIG_IS_ENABLED(PINCONF)
 527 static const struct pinconf_param sh_pfc_pinconf_params[] = {
 528         { "bias-disable",       PIN_CONFIG_BIAS_DISABLE,        0 },
 529         { "bias-pull-up",       PIN_CONFIG_BIAS_PULL_UP,        1 },
 530         { "bias-pull-down",     PIN_CONFIG_BIAS_PULL_DOWN,      1 },
 531         { "drive-strength",     PIN_CONFIG_DRIVE_STRENGTH,      0 },
 532         { "power-source",       PIN_CONFIG_POWER_SOURCE,        3300 },
 533 };
 534
 535 static void __iomem *
 536 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
 537                                        unsigned int *offset, unsigned int *size)
 538 {
 539         const struct pinmux_drive_reg_field *field;
 540         const struct pinmux_drive_reg *reg;
 541         unsigned int i;
 542
 543         for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
 544                 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
 545                         field = &reg->fields[i];
 546
 547                         if (field->size && field->pin == pin) {
 548                                 *offset = field->offset;
 549                                 *size = field->size;
 550
 551                                 return (void __iomem *)(uintptr_t)reg->reg;
 552                         }
 553                 }
 554         }
 555
 556         return NULL;
 557 }
 558
 559 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
 560                                              unsigned int pin, u16 strength)
 561 {
 562         unsigned int offset;
 563         unsigned int size;
 564         unsigned int step;
 565         void __iomem *reg;
 566         void __iomem *unlock_reg =
 567                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 568         u32 val;
 569
 570         reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
 571         if (!reg)
 572                 return -EINVAL;
 573
 574         step = size == 2 ? 6 : 3;
 575
 576         if (strength < step || strength > 24)
 577                 return -EINVAL;
 578
 579         /* Convert the value from mA based on a full drive strength value of
 580          * 24mA. We can make the full value configurable later if needed.
 581          */
 582         strength = strength / step - 1;
 583
 584         val = sh_pfc_read_raw_reg(reg, 32);
 585         val &= ~GENMASK(offset + size - 1, offset);
 586         val |= strength << offset;
 587
 588         if (unlock_reg)
 589                 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 590
 591         sh_pfc_write_raw_reg(reg, 32, val);
 592
 593         return 0;
 594 }
 595
 596 /* Check whether the requested parameter is supported for a pin. */
 597 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
 598                                     unsigned int param)
 599 {
 600         int idx = sh_pfc_get_pin_index(pfc, _pin);
 601         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
 602
 603         switch (param) {
 604         case PIN_CONFIG_BIAS_DISABLE:
 605                 return pin->configs &
 606                         (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
 607
 608         case PIN_CONFIG_BIAS_PULL_UP:
 609                 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
 610
 611         case PIN_CONFIG_BIAS_PULL_DOWN:
 612                 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
 613
 614         case PIN_CONFIG_DRIVE_STRENGTH:
 615                 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
 616
 617         case PIN_CONFIG_POWER_SOURCE:
 618                 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
 619
 620         default:
 621                 return false;
 622         }
 623 }
 624
 625 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
 626                               unsigned int param, unsigned int arg)
 627 {
 628         struct sh_pfc *pfc = pmx->pfc;
 629         void __iomem *pocctrl;
 630         void __iomem *unlock_reg =
 631                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 632         u32 addr, val;
 633         int bit, ret;
 634
 635         if (!sh_pfc_pinconf_validate(pfc, _pin, param))
 636                 return -ENOTSUPP;
 637
 638         switch (param) {
 639         case PIN_CONFIG_BIAS_PULL_UP:
 640         case PIN_CONFIG_BIAS_PULL_DOWN:
 641         case PIN_CONFIG_BIAS_DISABLE:
 642                 if (!pfc->info->ops || !pfc->info->ops->set_bias)
 643                         return -ENOTSUPP;
 644
 645                 pfc->info->ops->set_bias(pfc, _pin, param);
 646
 647                 break;
 648
 649         case PIN_CONFIG_DRIVE_STRENGTH:
 650                 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
 651                 if (ret < 0)
 652                         return ret;
 653
 654                 break;
 655
 656         case PIN_CONFIG_POWER_SOURCE:
 657                 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
 658                         return -ENOTSUPP;
 659
 660                 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
 661                 if (bit < 0) {
 662                         printf("invalid pin %#x", _pin);
 663                         return bit;
 664                 }
 665
 666                 if (arg != 1800 && arg != 3300)
 667                         return -EINVAL;
 668
 669                 pocctrl = (void __iomem *)(uintptr_t)addr;
 670
 671                 val = sh_pfc_read_raw_reg(pocctrl, 32);
 672                 if (arg == 3300)
 673                         val |= BIT(bit);
 674                 else
 675                         val &= ~BIT(bit);
 676
 677                 if (unlock_reg)
 678                         sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 679
 680                 sh_pfc_write_raw_reg(pocctrl, 32, val);
 681
 682                 break;
 683
 684         default:
 685                 return -ENOTSUPP;
 686         }
 687
 688         return 0;
 689 }
 690
 691 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
 692                                   unsigned int pin_selector,
 693                                   unsigned int param, unsigned int arg)
 694 {
 695         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 696         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 697         struct sh_pfc *pfc = &priv->pfc;
 698         const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
 699
 700         sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
 701
 702         return 0;
 703 }
 704
 705 static int sh_pfc_pinconf_group_set(struct udevice *dev,
 706                                       unsigned int group_selector,
 707                                       unsigned int param, unsigned int arg)
 708 {
 709         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 710         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 711         struct sh_pfc *pfc = &priv->pfc;
 712         const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
 713         unsigned int i;
 714
 715         for (i = 0; i < grp->nr_pins; i++)
 716                 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
 717
 718         return 0;
 719 }
 720 #endif
 721
 722 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
 723         .get_pins_count         = sh_pfc_pinctrl_get_pins_count,
 724         .get_pin_name           = sh_pfc_pinctrl_get_pin_name,
 725         .get_groups_count       = sh_pfc_pinctrl_get_groups_count,
 726         .get_group_name         = sh_pfc_pinctrl_get_group_name,
 727         .get_functions_count    = sh_pfc_pinctrl_get_functions_count,
 728         .get_function_name      = sh_pfc_pinctrl_get_function_name,
 729
 730 #if CONFIG_IS_ENABLED(PINCONF)
 731         .pinconf_num_params     = ARRAY_SIZE(sh_pfc_pinconf_params),
 732         .pinconf_params         = sh_pfc_pinconf_params,
 733         .pinconf_set            = sh_pfc_pinconf_pin_set,
 734         .pinconf_group_set      = sh_pfc_pinconf_group_set,
 735 #endif
 736         .pinmux_set             = sh_pfc_pinctrl_pin_set,
 737         .pinmux_group_set       = sh_pfc_pinctrl_group_set,
 738         .set_state              = pinctrl_generic_set_state,
 739 };
 740
 741 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
 742 {
 743         unsigned int i;
 744
 745         /* Allocate and initialize the pins and configs arrays. */
 746         pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
 747                                     GFP_KERNEL);
 748         if (unlikely(!pmx->configs))
 749                 return -ENOMEM;
 750
 751         for (i = 0; i < pfc->info->nr_pins; ++i) {
 752                 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
 753                 cfg->type = PINMUX_TYPE_NONE;
 754         }
 755
 756         return 0;
 757 }
 758
 759
 760 static int sh_pfc_pinctrl_probe(struct udevice *dev)
 761 {
 762         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 763         enum sh_pfc_model model = dev_get_driver_data(dev);
 764         fdt_addr_t base;
 765
 766         base = devfdt_get_addr(dev);
 767         if (base == FDT_ADDR_T_NONE)
 768                 return -EINVAL;
 769
 770         priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
 771         if (!priv->pfc.regs)
 772                 return -ENOMEM;
 773
 774 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 775         if (model == SH_PFC_R8A7795)
 776                 priv->pfc.info = &r8a7795_pinmux_info;
 777 #endif
 778 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 779         if (model == SH_PFC_R8A7796)
 780                 priv->pfc.info = &r8a7796_pinmux_info;
 781 #endif
 782 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 783         if (model == SH_PFC_R8A77970)
 784                 priv->pfc.info = &r8a77970_pinmux_info;
 785 #endif
 786
 787         priv->pmx.pfc = &priv->pfc;
 788         sh_pfc_init_ranges(&priv->pfc);
 789         sh_pfc_map_pins(&priv->pfc, &priv->pmx);
 790
 791         return 0;
 792 }
 793
 794 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
 795 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 796         {
 797                 .compatible = "renesas,pfc-r8a7795",
 798                 .data = SH_PFC_R8A7795,
 799         },
 800 #endif
 801 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 802         {
 803                 .compatible = "renesas,pfc-r8a7796",
 804                 .data = SH_PFC_R8A7796,
 805         },
 806 #endif
 807 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 808         {
 809                 .compatible = "renesas,pfc-r8a77970",
 810                 .data = SH_PFC_R8A77970,
 811         },
 812 #endif
 813         { },
 814 };
 815
 816 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
 817         .name           = "sh_pfc_pinctrl",
 818         .id             = UCLASS_PINCTRL,
 819         .of_match       = sh_pfc_pinctrl_ids,
 820         .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
 821         .ops            = &sh_pfc_pinctrl_ops,
 822         .probe          = sh_pfc_pinctrl_probe,
 823 };