1 // SPDX-License-Identifier: GPL-2.0
3 * R8A779A0 processor support - PFC hardware block.
5 * Copyright (C) 2021 Renesas Electronics Corp.
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
10 #include <linux/errno.h>
12 #include <linux/kernel.h>
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
18 #define CPU_ALL_GP(fn, sfx) \
19 PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
20 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(1, 23, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_1(1, 24, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(1, 25, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(1, 26, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_1(1, 27, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(1, 28, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_20(2, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
29 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 16, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 17, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 18, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_1(3, 19, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_1(3, 20, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_1(3, 21, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_1(3, 22, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_1(3, 23, fn, sfx, CFG_FLAGS), \
40 PORT_GP_CFG_1(3, 24, fn, sfx, CFG_FLAGS), \
41 PORT_GP_CFG_1(3, 25, fn, sfx, CFG_FLAGS), \
42 PORT_GP_CFG_1(3, 26, fn, sfx, CFG_FLAGS), \
43 PORT_GP_CFG_1(3, 27, fn, sfx, CFG_FLAGS), \
44 PORT_GP_CFG_1(3, 28, fn, sfx, CFG_FLAGS), \
45 PORT_GP_CFG_1(3, 29, fn, sfx, CFG_FLAGS), \
46 PORT_GP_CFG_25(4, fn, sfx, CFG_FLAGS), \
47 PORT_GP_CFG_21(5, fn, sfx, CFG_FLAGS), \
48 PORT_GP_CFG_21(6, fn, sfx, CFG_FLAGS), \
49 PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \
50 PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
53 #define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)
54 #define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)
55 #define GPSR0_16 F_(MSIOF2_TXD, IP2SR0_3_0)
56 #define GPSR0_15 F_(MSIOF2_SYNC, IP1SR0_31_28)
57 #define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24)
58 #define GPSR0_13 F_(MSIOF2_SS2, IP1SR0_23_20)
59 #define GPSR0_12 F_(MSIOF5_RXD, IP1SR0_19_16)
60 #define GPSR0_11 F_(MSIOF5_SCK, IP1SR0_15_12)
61 #define GPSR0_10 F_(MSIOF5_TXD, IP1SR0_11_8)
62 #define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4)
63 #define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0)
64 #define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28)
65 #define GPSR0_6 F_(IRQ0, IP0SR0_27_24)
66 #define GPSR0_5 F_(IRQ1, IP0SR0_23_20)
67 #define GPSR0_4 F_(IRQ2, IP0SR0_19_16)
68 #define GPSR0_3 F_(IRQ3, IP0SR0_15_12)
69 #define GPSR0_2 F_(GP0_02, IP0SR0_11_8)
70 #define GPSR0_1 F_(GP0_01, IP0SR0_7_4)
71 #define GPSR0_0 F_(GP0_00, IP0SR0_3_0)
74 #define GPSR1_28 F_(HTX3, IP3SR1_19_16)
75 #define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12)
76 #define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8)
77 #define GPSR1_25 F_(HSCK3, IP3SR1_7_4)
78 #define GPSR1_24 F_(HRX3, IP3SR1_3_0)
79 #define GPSR1_23 F_(GP1_23, IP2SR1_31_28)
80 #define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24)
81 #define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20)
82 #define GPSR1_20 F_(SSI_SD, IP2SR1_19_16)
83 #define GPSR1_19 F_(SSI_WS, IP2SR1_15_12)
84 #define GPSR1_18 F_(SSI_SCK, IP2SR1_11_8)
85 #define GPSR1_17 F_(SCIF_CLK, IP2SR1_7_4)
86 #define GPSR1_16 F_(HRX0, IP2SR1_3_0)
87 #define GPSR1_15 F_(HSCK0, IP1SR1_31_28)
88 #define GPSR1_14 F_(HRTS0_N, IP1SR1_27_24)
89 #define GPSR1_13 F_(HCTS0_N, IP1SR1_23_20)
90 #define GPSR1_12 F_(HTX0, IP1SR1_19_16)
91 #define GPSR1_11 F_(MSIOF0_RXD, IP1SR1_15_12)
92 #define GPSR1_10 F_(MSIOF0_SCK, IP1SR1_11_8)
93 #define GPSR1_9 F_(MSIOF0_TXD, IP1SR1_7_4)
94 #define GPSR1_8 F_(MSIOF0_SYNC, IP1SR1_3_0)
95 #define GPSR1_7 F_(MSIOF0_SS1, IP0SR1_31_28)
96 #define GPSR1_6 F_(MSIOF0_SS2, IP0SR1_27_24)
97 #define GPSR1_5 F_(MSIOF1_RXD, IP0SR1_23_20)
98 #define GPSR1_4 F_(MSIOF1_TXD, IP0SR1_19_16)
99 #define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12)
100 #define GPSR1_2 F_(MSIOF1_SYNC, IP0SR1_11_8)
101 #define GPSR1_1 F_(MSIOF1_SS1, IP0SR1_7_4)
102 #define GPSR1_0 F_(MSIOF1_SS2, IP0SR1_3_0)
105 #define GPSR2_19 F_(CANFD7_RX, IP2SR2_15_12)
106 #define GPSR2_18 F_(CANFD7_TX, IP2SR2_11_8)
107 #define GPSR2_17 F_(CANFD4_RX, IP2SR2_7_4)
108 #define GPSR2_16 F_(CANFD4_TX, IP2SR2_3_0)
109 #define GPSR2_15 F_(CANFD3_RX, IP1SR2_31_28)
110 #define GPSR2_14 F_(CANFD3_TX, IP1SR2_27_24)
111 #define GPSR2_13 F_(CANFD2_RX, IP1SR2_23_20)
112 #define GPSR2_12 F_(CANFD2_TX, IP1SR2_19_16)
113 #define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12)
114 #define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8)
115 #define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4)
116 #define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0)
117 #define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28)
118 #define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24)
119 #define GPSR2_5 F_(FXR_TXENB_N, IP0SR2_23_20)
120 #define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16)
121 #define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12)
122 #define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8)
123 #define GPSR2_1 F_(FXR_TXENA_N, IP0SR2_7_4)
124 #define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0)
127 #define GPSR3_29 F_(RPC_INT_N, IP3SR3_23_20)
128 #define GPSR3_28 F_(RPC_WP_N, IP3SR3_19_16)
129 #define GPSR3_27 F_(RPC_RESET_N, IP3SR3_15_12)
130 #define GPSR3_26 F_(QSPI1_IO3, IP3SR3_11_8)
131 #define GPSR3_25 F_(QSPI1_SSL, IP3SR3_7_4)
132 #define GPSR3_24 F_(QSPI1_IO2, IP3SR3_3_0)
133 #define GPSR3_23 F_(QSPI1_MISO_IO1, IP2SR3_31_28)
134 #define GPSR3_22 F_(QSPI1_SPCLK, IP2SR3_27_24)
135 #define GPSR3_21 F_(QSPI1_MOSI_IO0, IP2SR3_23_20)
136 #define GPSR3_20 F_(QSPI0_SPCLK, IP2SR3_19_16)
137 #define GPSR3_19 F_(QSPI0_MOSI_IO0, IP2SR3_15_12)
138 #define GPSR3_18 F_(QSPI0_MISO_IO1, IP2SR3_11_8)
139 #define GPSR3_17 F_(QSPI0_IO2, IP2SR3_7_4)
140 #define GPSR3_16 F_(QSPI0_IO3, IP2SR3_3_0)
141 #define GPSR3_15 F_(QSPI0_SSL, IP1SR3_31_28)
142 #define GPSR3_14 F_(IPC_CLKOUT, IP1SR3_27_24)
143 #define GPSR3_13 F_(IPC_CLKIN, IP1SR3_23_20)
144 #define GPSR3_12 F_(SD_WP, IP1SR3_19_16)
145 #define GPSR3_11 F_(SD_CD, IP1SR3_15_12)
146 #define GPSR3_10 F_(MMC_SD_CMD, IP1SR3_11_8)
147 #define GPSR3_9 F_(MMC_D6, IP1SR3_7_4)
148 #define GPSR3_8 F_(MMC_D7, IP1SR3_3_0)
149 #define GPSR3_7 F_(MMC_D4, IP0SR3_31_28)
150 #define GPSR3_6 F_(MMC_D5, IP0SR3_27_24)
151 #define GPSR3_5 F_(MMC_SD_D3, IP0SR3_23_20)
152 #define GPSR3_4 F_(MMC_DS, IP0SR3_19_16)
153 #define GPSR3_3 F_(MMC_SD_CLK, IP0SR3_15_12)
154 #define GPSR3_2 F_(MMC_SD_D2, IP0SR3_11_8)
155 #define GPSR3_1 F_(MMC_SD_D0, IP0SR3_7_4)
156 #define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0)
159 #define GPSR4_24 FM(AVS1)
160 #define GPSR4_23 FM(AVS0)
161 #define GPSR4_22 FM(PCIE1_CLKREQ_N)
162 #define GPSR4_21 FM(PCIE0_CLKREQ_N)
163 #define GPSR4_20 FM(TSN0_TXCREFCLK)
164 #define GPSR4_19 FM(TSN0_TD2)
165 #define GPSR4_18 FM(TSN0_TD3)
166 #define GPSR4_17 FM(TSN0_RD2)
167 #define GPSR4_16 FM(TSN0_RD3)
168 #define GPSR4_15 FM(TSN0_TD0)
169 #define GPSR4_14 FM(TSN0_TD1)
170 #define GPSR4_13 FM(TSN0_RD1)
171 #define GPSR4_12 FM(TSN0_TXC)
172 #define GPSR4_11 FM(TSN0_RXC)
173 #define GPSR4_10 FM(TSN0_RD0)
174 #define GPSR4_9 FM(TSN0_TX_CTL)
175 #define GPSR4_8 FM(TSN0_AVTP_PPS0)
176 #define GPSR4_7 FM(TSN0_RX_CTL)
177 #define GPSR4_6 FM(TSN0_AVTP_CAPTURE)
178 #define GPSR4_5 FM(TSN0_AVTP_MATCH)
179 #define GPSR4_4 FM(TSN0_LINK)
180 #define GPSR4_3 FM(TSN0_PHY_INT)
181 #define GPSR4_2 FM(TSN0_AVTP_PPS1)
182 #define GPSR4_1 FM(TSN0_MDC)
183 #define GPSR4_0 FM(TSN0_MDIO)
186 #define GPSR5_20 FM(AVB2_RX_CTL)
187 #define GPSR5_19 FM(AVB2_TX_CTL)
188 #define GPSR5_18 FM(AVB2_RXC)
189 #define GPSR5_17 FM(AVB2_RD0)
190 #define GPSR5_16 FM(AVB2_TXC)
191 #define GPSR5_15 FM(AVB2_TD0)
192 #define GPSR5_14 FM(AVB2_RD1)
193 #define GPSR5_13 FM(AVB2_RD2)
194 #define GPSR5_12 FM(AVB2_TD1)
195 #define GPSR5_11 FM(AVB2_TD2)
196 #define GPSR5_10 FM(AVB2_MDIO)
197 #define GPSR5_9 FM(AVB2_RD3)
198 #define GPSR5_8 FM(AVB2_TD3)
199 #define GPSR5_7 FM(AVB2_TXCREFCLK)
200 #define GPSR5_6 FM(AVB2_MDC)
201 #define GPSR5_5 FM(AVB2_MAGIC)
202 #define GPSR5_4 FM(AVB2_PHY_INT)
203 #define GPSR5_3 FM(AVB2_LINK)
204 #define GPSR5_2 FM(AVB2_AVTP_MATCH)
205 #define GPSR5_1 FM(AVB2_AVTP_CAPTURE)
206 #define GPSR5_0 FM(AVB2_AVTP_PPS)
209 #define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)
210 #define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12)
211 #define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8)
212 #define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4)
213 #define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0)
214 #define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28)
215 #define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24)
216 #define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20)
217 #define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16)
218 #define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12)
219 #define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8)
220 #define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4)
221 #define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0)
222 #define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28)
223 #define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24)
224 #define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20)
225 #define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16)
226 #define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12)
227 #define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8)
228 #define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4)
229 #define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0)
232 #define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16)
233 #define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12)
234 #define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8)
235 #define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4)
236 #define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0)
237 #define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28)
238 #define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24)
239 #define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20)
240 #define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16)
241 #define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12)
242 #define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8)
243 #define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4)
244 #define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0)
245 #define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28)
246 #define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24)
247 #define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20)
248 #define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16)
249 #define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12)
250 #define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8)
251 #define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
252 #define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
255 #define GPSR8_13 F_(GP8_13, IP1SR8_23_20)
256 #define GPSR8_12 F_(GP8_12, IP1SR8_19_16)
257 #define GPSR8_11 F_(SDA5, IP1SR8_15_12)
258 #define GPSR8_10 F_(SCL5, IP1SR8_11_8)
259 #define GPSR8_9 F_(SDA4, IP1SR8_7_4)
260 #define GPSR8_8 F_(SCL4, IP1SR8_3_0)
261 #define GPSR8_7 F_(SDA3, IP0SR8_31_28)
262 #define GPSR8_6 F_(SCL3, IP0SR8_27_24)
263 #define GPSR8_5 F_(SDA2, IP0SR8_23_20)
264 #define GPSR8_4 F_(SCL2, IP0SR8_19_16)
265 #define GPSR8_3 F_(SDA1, IP0SR8_15_12)
266 #define GPSR8_2 F_(SCL1, IP0SR8_11_8)
267 #define GPSR8_1 F_(SDA0, IP0SR8_7_4)
268 #define GPSR8_0 F_(SCL0, IP0SR8_3_0)
271 /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
272 #define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
282 #define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 /* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
292 #define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
298 #define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP0SR1_27_24 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP0SR1_31_28 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
308 #define IP1SR1_3_0 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP1SR1_7_4 FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP1SR1_11_8 FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 /* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
318 #define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
328 #define IP3SR1_3_0 FM(HRX3) FM(SCK3) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N) FM(MSIOF4_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N) FM(MSIOF4_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP3SR1_15_12 FM(HCTS3_N) FM(RX3) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP3SR1_19_16 FM(HTX3) FM(TX3) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
336 #define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
346 #define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP1SR2_7_4 FM(CAN_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP1SR2_11_8 FM(CANFD0_TX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 /* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
356 #define IP2SR2_3_0 FM(CANFD4_TX) F_(0, 0) FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP2SR2_7_4 FM(CANFD4_RX) F_(0, 0) FM(PWM5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP2SR2_11_8 FM(CANFD7_TX) F_(0, 0) FM(PWM6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP2SR2_15_12 FM(CANFD7_RX) F_(0, 0) FM(PWM7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
363 #define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 /* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
373 #define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 /* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
383 #define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 #define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385 #define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 /* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
393 #define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 /* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
402 #define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 #define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405 #define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
406 #define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
407 #define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
408 #define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
409 #define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
411 /* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
412 #define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
413 #define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
414 #define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
415 #define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
416 #define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
417 #define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
418 #define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
419 #define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
421 /* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
422 #define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
423 #define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
424 #define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
425 #define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
426 #define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
429 /* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
430 #define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
431 #define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
432 #define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
433 #define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
434 #define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
435 #define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
436 #define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
437 #define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
439 /* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
440 #define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
441 #define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
442 #define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
443 #define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
444 #define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
445 #define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
446 #define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
447 #define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
449 /* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
450 #define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
451 #define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
452 #define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
453 #define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
454 #define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
457 /* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
458 #define IP0SR8_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
459 #define IP0SR8_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
460 #define IP0SR8_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
461 #define IP0SR8_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
462 #define IP0SR8_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
463 #define IP0SR8_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
464 #define IP0SR8_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
465 #define IP0SR8_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
467 /* IP1SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
468 #define IP1SR8_3_0 FM(SCL4) FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
469 #define IP1SR8_7_4 FM(SDA4) FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
470 #define IP1SR8_11_8 FM(SCL5) FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
471 #define IP1SR8_15_12 FM(SDA5) FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
472 #define IP1SR8_19_16 F_(0, 0) FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
473 #define IP1SR8_23_20 F_(0, 0) FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define PINMUX_GPSR \
481 GPSR1_24 GPSR3_24 GPSR4_24 \
482 GPSR1_23 GPSR3_23 GPSR4_23 \
483 GPSR1_22 GPSR3_22 GPSR4_22 \
484 GPSR1_21 GPSR3_21 GPSR4_21 \
485 GPSR1_20 GPSR3_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 \
486 GPSR1_19 GPSR2_19 GPSR3_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 \
487 GPSR0_18 GPSR1_18 GPSR2_18 GPSR3_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 \
488 GPSR0_17 GPSR1_17 GPSR2_17 GPSR3_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 \
489 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 \
490 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 \
491 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 \
492 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 \
493 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 \
494 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 \
495 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 \
496 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 \
497 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 \
498 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 \
499 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 \
500 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 \
501 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 \
502 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 \
503 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 \
504 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 \
505 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0
507 #define PINMUX_IPSR \
509 FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \
510 FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \
511 FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \
512 FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 \
513 FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 \
514 FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \
515 FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \
516 FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \
518 FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \
519 FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \
520 FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \
521 FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
522 FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
523 FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 \
524 FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 \
525 FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \
527 FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
528 FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
529 FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \
530 FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \
531 FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 \
532 FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 \
533 FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 \
534 FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \
536 FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 FM(IP2SR3_3_0) IP2SR3_3_0 FM(IP3SR3_3_0) IP3SR3_3_0 \
537 FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 FM(IP2SR3_7_4) IP2SR3_7_4 FM(IP3SR3_7_4) IP3SR3_7_4 \
538 FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 FM(IP2SR3_11_8) IP2SR3_11_8 FM(IP3SR3_11_8) IP3SR3_11_8 \
539 FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 FM(IP2SR3_15_12) IP2SR3_15_12 FM(IP3SR3_15_12) IP3SR3_15_12 \
540 FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 FM(IP2SR3_19_16) IP2SR3_19_16 FM(IP3SR3_19_16) IP3SR3_19_16 \
541 FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2SR3_23_20 FM(IP3SR3_23_20) IP3SR3_23_20 \
542 FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 \
543 FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 \
545 FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \
546 FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \
547 FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \
548 FM(IP0SR6_15_12) IP0SR6_15_12 FM(IP1SR6_15_12) IP1SR6_15_12 FM(IP2SR6_15_12) IP2SR6_15_12 \
549 FM(IP0SR6_19_16) IP0SR6_19_16 FM(IP1SR6_19_16) IP1SR6_19_16 FM(IP2SR6_19_16) IP2SR6_19_16 \
550 FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 \
551 FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 \
552 FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 \
554 FM(IP0SR7_3_0) IP0SR7_3_0 FM(IP1SR7_3_0) IP1SR7_3_0 FM(IP2SR7_3_0) IP2SR7_3_0 \
555 FM(IP0SR7_7_4) IP0SR7_7_4 FM(IP1SR7_7_4) IP1SR7_7_4 FM(IP2SR7_7_4) IP2SR7_7_4 \
556 FM(IP0SR7_11_8) IP0SR7_11_8 FM(IP1SR7_11_8) IP1SR7_11_8 FM(IP2SR7_11_8) IP2SR7_11_8 \
557 FM(IP0SR7_15_12) IP0SR7_15_12 FM(IP1SR7_15_12) IP1SR7_15_12 FM(IP2SR7_15_12) IP2SR7_15_12 \
558 FM(IP0SR7_19_16) IP0SR7_19_16 FM(IP1SR7_19_16) IP1SR7_19_16 FM(IP2SR7_19_16) IP2SR7_19_16 \
559 FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 \
560 FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 \
561 FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 \
563 FM(IP0SR8_3_0) IP0SR8_3_0 FM(IP1SR8_3_0) IP1SR8_3_0 \
564 FM(IP0SR8_7_4) IP0SR8_7_4 FM(IP1SR8_7_4) IP1SR8_7_4 \
565 FM(IP0SR8_11_8) IP0SR8_11_8 FM(IP1SR8_11_8) IP1SR8_11_8 \
566 FM(IP0SR8_15_12) IP0SR8_15_12 FM(IP1SR8_15_12) IP1SR8_15_12 \
567 FM(IP0SR8_19_16) IP0SR8_19_16 FM(IP1SR8_19_16) IP1SR8_19_16 \
568 FM(IP0SR8_23_20) IP0SR8_23_20 FM(IP1SR8_23_20) IP1SR8_23_20 \
569 FM(IP0SR8_27_24) IP0SR8_27_24 \
570 FM(IP0SR8_31_28) IP0SR8_31_28
572 /* MOD_SEL4 */ /* 0 */ /* 1 */
573 #define MOD_SEL4_19 FM(SEL_TSN0_TD2_0) FM(SEL_TSN0_TD2_1)
574 #define MOD_SEL4_18 FM(SEL_TSN0_TD3_0) FM(SEL_TSN0_TD3_1)
575 #define MOD_SEL4_15 FM(SEL_TSN0_TD0_0) FM(SEL_TSN0_TD0_1)
576 #define MOD_SEL4_14 FM(SEL_TSN0_TD1_0) FM(SEL_TSN0_TD1_1)
577 #define MOD_SEL4_12 FM(SEL_TSN0_TXC_0) FM(SEL_TSN0_TXC_1)
578 #define MOD_SEL4_9 FM(SEL_TSN0_TX_CTL_0) FM(SEL_TSN0_TX_CTL_1)
579 #define MOD_SEL4_8 FM(SEL_TSN0_AVTP_PPS0_0) FM(SEL_TSN0_AVTP_PPS0_1)
580 #define MOD_SEL4_5 FM(SEL_TSN0_AVTP_MATCH_0) FM(SEL_TSN0_AVTP_MATCH_1)
581 #define MOD_SEL4_2 FM(SEL_TSN0_AVTP_PPS1_0) FM(SEL_TSN0_AVTP_PPS1_1)
582 #define MOD_SEL4_1 FM(SEL_TSN0_MDC_0) FM(SEL_TSN0_MDC_1)
584 /* MOD_SEL5 */ /* 0 */ /* 1 */
585 #define MOD_SEL5_19 FM(SEL_AVB2_TX_CTL_0) FM(SEL_AVB2_TX_CTL_1)
586 #define MOD_SEL5_16 FM(SEL_AVB2_TXC_0) FM(SEL_AVB2_TXC_1)
587 #define MOD_SEL5_15 FM(SEL_AVB2_TD0_0) FM(SEL_AVB2_TD0_1)
588 #define MOD_SEL5_12 FM(SEL_AVB2_TD1_0) FM(SEL_AVB2_TD1_1)
589 #define MOD_SEL5_11 FM(SEL_AVB2_TD2_0) FM(SEL_AVB2_TD2_1)
590 #define MOD_SEL5_8 FM(SEL_AVB2_TD3_0) FM(SEL_AVB2_TD3_1)
591 #define MOD_SEL5_6 FM(SEL_AVB2_MDC_0) FM(SEL_AVB2_MDC_1)
592 #define MOD_SEL5_5 FM(SEL_AVB2_MAGIC_0) FM(SEL_AVB2_MAGIC_1)
593 #define MOD_SEL5_2 FM(SEL_AVB2_AVTP_MATCH_0) FM(SEL_AVB2_AVTP_MATCH_1)
594 #define MOD_SEL5_0 FM(SEL_AVB2_AVTP_PPS_0) FM(SEL_AVB2_AVTP_PPS_1)
596 /* MOD_SEL6 */ /* 0 */ /* 1 */
597 #define MOD_SEL6_18 FM(SEL_AVB1_TD3_0) FM(SEL_AVB1_TD3_1)
598 #define MOD_SEL6_16 FM(SEL_AVB1_TD2_0) FM(SEL_AVB1_TD2_1)
599 #define MOD_SEL6_13 FM(SEL_AVB1_TD0_0) FM(SEL_AVB1_TD0_1)
600 #define MOD_SEL6_12 FM(SEL_AVB1_TD1_0) FM(SEL_AVB1_TD1_1)
601 #define MOD_SEL6_10 FM(SEL_AVB1_AVTP_PPS_0) FM(SEL_AVB1_AVTP_PPS_1)
602 #define MOD_SEL6_7 FM(SEL_AVB1_TX_CTL_0) FM(SEL_AVB1_TX_CTL_1)
603 #define MOD_SEL6_6 FM(SEL_AVB1_TXC_0) FM(SEL_AVB1_TXC_1)
604 #define MOD_SEL6_5 FM(SEL_AVB1_AVTP_MATCH_0) FM(SEL_AVB1_AVTP_MATCH_1)
605 #define MOD_SEL6_2 FM(SEL_AVB1_MDC_0) FM(SEL_AVB1_MDC_1)
606 #define MOD_SEL6_1 FM(SEL_AVB1_MAGIC_0) FM(SEL_AVB1_MAGIC_1)
608 /* MOD_SEL7 */ /* 0 */ /* 1 */
609 #define MOD_SEL7_16 FM(SEL_AVB0_TX_CTL_0) FM(SEL_AVB0_TX_CTL_1)
610 #define MOD_SEL7_15 FM(SEL_AVB0_TXC_0) FM(SEL_AVB0_TXC_1)
611 #define MOD_SEL7_13 FM(SEL_AVB0_MDC_0) FM(SEL_AVB0_MDC_1)
612 #define MOD_SEL7_11 FM(SEL_AVB0_TD0_0) FM(SEL_AVB0_TD0_1)
613 #define MOD_SEL7_10 FM(SEL_AVB0_MAGIC_0) FM(SEL_AVB0_MAGIC_1)
614 #define MOD_SEL7_7 FM(SEL_AVB0_TD1_0) FM(SEL_AVB0_TD1_1)
615 #define MOD_SEL7_6 FM(SEL_AVB0_TD2_0) FM(SEL_AVB0_TD2_1)
616 #define MOD_SEL7_3 FM(SEL_AVB0_TD3_0) FM(SEL_AVB0_TD3_1)
617 #define MOD_SEL7_2 FM(SEL_AVB0_AVTP_MATCH_0) FM(SEL_AVB0_AVTP_MATCH_1)
618 #define MOD_SEL7_0 FM(SEL_AVB0_AVTP_PPS_0) FM(SEL_AVB0_AVTP_PPS_1)
620 /* MOD_SEL8 */ /* 0 */ /* 1 */
621 #define MOD_SEL8_11 FM(SEL_SDA5_0) FM(SEL_SDA5_1)
622 #define MOD_SEL8_10 FM(SEL_SCL5_0) FM(SEL_SCL5_1)
623 #define MOD_SEL8_9 FM(SEL_SDA4_0) FM(SEL_SDA4_1)
624 #define MOD_SEL8_8 FM(SEL_SCL4_0) FM(SEL_SCL4_1)
625 #define MOD_SEL8_7 FM(SEL_SDA3_0) FM(SEL_SDA3_1)
626 #define MOD_SEL8_6 FM(SEL_SCL3_0) FM(SEL_SCL3_1)
627 #define MOD_SEL8_5 FM(SEL_SDA2_0) FM(SEL_SDA2_1)
628 #define MOD_SEL8_4 FM(SEL_SCL2_0) FM(SEL_SCL2_1)
629 #define MOD_SEL8_3 FM(SEL_SDA1_0) FM(SEL_SDA1_1)
630 #define MOD_SEL8_2 FM(SEL_SCL1_0) FM(SEL_SCL1_1)
631 #define MOD_SEL8_1 FM(SEL_SDA0_0) FM(SEL_SDA0_1)
632 #define MOD_SEL8_0 FM(SEL_SCL0_0) FM(SEL_SCL0_1)
634 #define PINMUX_MOD_SELS \
636 MOD_SEL4_19 MOD_SEL5_19 \
637 MOD_SEL4_18 MOD_SEL6_18 \
639 MOD_SEL5_16 MOD_SEL6_16 MOD_SEL7_16 \
640 MOD_SEL4_15 MOD_SEL5_15 MOD_SEL7_15 \
642 MOD_SEL6_13 MOD_SEL7_13 \
643 MOD_SEL4_12 MOD_SEL5_12 MOD_SEL6_12 \
644 MOD_SEL5_11 MOD_SEL7_11 MOD_SEL8_11 \
645 MOD_SEL6_10 MOD_SEL7_10 MOD_SEL8_10 \
646 MOD_SEL4_9 MOD_SEL8_9 \
647 MOD_SEL4_8 MOD_SEL5_8 MOD_SEL8_8 \
648 MOD_SEL6_7 MOD_SEL7_7 MOD_SEL8_7 \
649 MOD_SEL5_6 MOD_SEL6_6 MOD_SEL7_6 MOD_SEL8_6 \
650 MOD_SEL4_5 MOD_SEL5_5 MOD_SEL6_5 MOD_SEL8_5 \
652 MOD_SEL7_3 MOD_SEL8_3 \
653 MOD_SEL4_2 MOD_SEL5_2 MOD_SEL6_2 MOD_SEL7_2 MOD_SEL8_2 \
654 MOD_SEL4_1 MOD_SEL6_1 MOD_SEL8_1 \
655 MOD_SEL5_0 MOD_SEL7_0 MOD_SEL8_0
665 #define FM(x) FN_##x,
666 PINMUX_FUNCTION_BEGIN,
676 #define FM(x) x##_MARK,
686 static const u16 pinmux_data[] = {
687 PINMUX_DATA_GP_ALL(),
691 PINMUX_SINGLE(PCIE1_CLKREQ_N),
692 PINMUX_SINGLE(PCIE0_CLKREQ_N),
693 PINMUX_SINGLE(TSN0_TXCREFCLK),
694 PINMUX_SINGLE(TSN0_TD2),
695 PINMUX_SINGLE(TSN0_TD3),
696 PINMUX_SINGLE(TSN0_RD2),
697 PINMUX_SINGLE(TSN0_RD3),
698 PINMUX_SINGLE(TSN0_TD0),
699 PINMUX_SINGLE(TSN0_TD1),
700 PINMUX_SINGLE(TSN0_RD1),
701 PINMUX_SINGLE(TSN0_TXC),
702 PINMUX_SINGLE(TSN0_RXC),
703 PINMUX_SINGLE(TSN0_RD0),
704 PINMUX_SINGLE(TSN0_TX_CTL),
705 PINMUX_SINGLE(TSN0_AVTP_PPS0),
706 PINMUX_SINGLE(TSN0_RX_CTL),
707 PINMUX_SINGLE(TSN0_AVTP_CAPTURE),
708 PINMUX_SINGLE(TSN0_AVTP_MATCH),
709 PINMUX_SINGLE(TSN0_LINK),
710 PINMUX_SINGLE(TSN0_PHY_INT),
711 PINMUX_SINGLE(TSN0_AVTP_PPS1),
712 PINMUX_SINGLE(TSN0_MDC),
713 PINMUX_SINGLE(TSN0_MDIO),
715 PINMUX_SINGLE(AVB2_RX_CTL),
716 PINMUX_SINGLE(AVB2_TX_CTL),
717 PINMUX_SINGLE(AVB2_RXC),
718 PINMUX_SINGLE(AVB2_RD0),
719 PINMUX_SINGLE(AVB2_TXC),
720 PINMUX_SINGLE(AVB2_TD0),
721 PINMUX_SINGLE(AVB2_RD1),
722 PINMUX_SINGLE(AVB2_RD2),
723 PINMUX_SINGLE(AVB2_TD1),
724 PINMUX_SINGLE(AVB2_TD2),
725 PINMUX_SINGLE(AVB2_MDIO),
726 PINMUX_SINGLE(AVB2_RD3),
727 PINMUX_SINGLE(AVB2_TD3),
728 PINMUX_SINGLE(AVB2_TXCREFCLK),
729 PINMUX_SINGLE(AVB2_MDC),
730 PINMUX_SINGLE(AVB2_MAGIC),
731 PINMUX_SINGLE(AVB2_PHY_INT),
732 PINMUX_SINGLE(AVB2_LINK),
733 PINMUX_SINGLE(AVB2_AVTP_MATCH),
734 PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
735 PINMUX_SINGLE(AVB2_AVTP_PPS),
738 PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC),
739 PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_A),
741 PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1),
743 PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2),
745 PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3),
746 PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK),
748 PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2),
749 PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD),
751 PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1),
752 PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD),
754 PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0),
755 PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC),
757 PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2),
760 PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF5_SS1),
762 PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF5_SYNC),
764 PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF5_TXD),
766 PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF5_SCK),
768 PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD),
770 PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2),
771 PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1),
772 PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_A),
774 PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),
775 PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1),
776 PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1),
778 PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC),
779 PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1),
780 PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1),
783 PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD),
784 PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N),
785 PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N),
787 PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK),
788 PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N),
789 PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N),
791 PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD),
792 PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1),
793 PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1),
796 PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
797 PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A),
799 PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
800 PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_A),
802 PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
803 PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_A),
805 PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
806 PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A),
808 PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
809 PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A),
811 PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
812 PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
813 PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
816 PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),
818 PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),
820 PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),
822 PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),
824 PINMUX_IPSR_GPSR(IP1SR1_19_16, HTX0),
825 PINMUX_IPSR_GPSR(IP1SR1_19_16, TX0),
827 PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),
828 PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),
829 PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8),
831 PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),
832 PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),
833 PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9),
835 PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
836 PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
837 PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0),
840 PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),
841 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0),
843 PINMUX_IPSR_GPSR(IP2SR1_7_4, SCIF_CLK),
844 PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A),
846 PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK),
847 PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3),
849 PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS),
850 PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4),
852 PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD),
853 PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_A),
855 PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT),
856 PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_A),
858 PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN),
859 PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3),
861 PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2),
862 PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1),
863 PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B),
866 PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3),
867 PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3),
868 PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
870 PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3),
871 PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N),
872 PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
874 PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N),
875 PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N),
876 PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
878 PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N),
879 PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3),
880 PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
882 PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3),
883 PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3),
884 PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
887 PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA),
888 PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX),
890 PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N),
891 PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX),
893 PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR),
894 PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX),
895 PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5),
897 PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR),
898 PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX),
899 PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B),
901 PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR),
903 PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N),
905 PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB),
907 PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1),
908 PINMUX_IPSR_GPSR(IP0SR2_31_28, CANFD6_TX),
909 PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_B),
912 PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0),
913 PINMUX_IPSR_GPSR(IP1SR2_3_0, CANFD6_RX),
914 PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_A),
916 PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK),
918 PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX),
920 PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),
921 PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),
923 PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),
924 PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2),
925 PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_A),
927 PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),
928 PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3),
929 PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1),
930 PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_A),
932 PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),
933 PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2),
935 PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),
938 PINMUX_IPSR_GPSR(IP2SR2_3_0, CANFD4_TX),
939 PINMUX_IPSR_GPSR(IP2SR2_3_0, PWM4),
941 PINMUX_IPSR_GPSR(IP2SR2_7_4, CANFD4_RX),
942 PINMUX_IPSR_GPSR(IP2SR2_7_4, PWM5),
944 PINMUX_IPSR_GPSR(IP2SR2_11_8, CANFD7_TX),
945 PINMUX_IPSR_GPSR(IP2SR2_11_8, PWM6),
947 PINMUX_IPSR_GPSR(IP2SR2_15_12, CANFD7_RX),
948 PINMUX_IPSR_GPSR(IP2SR2_15_12, PWM7),
951 PINMUX_IPSR_GPSR(IP0SR3_3_0, MMC_SD_D1),
952 PINMUX_IPSR_GPSR(IP0SR3_7_4, MMC_SD_D0),
953 PINMUX_IPSR_GPSR(IP0SR3_11_8, MMC_SD_D2),
954 PINMUX_IPSR_GPSR(IP0SR3_15_12, MMC_SD_CLK),
955 PINMUX_IPSR_GPSR(IP0SR3_19_16, MMC_DS),
956 PINMUX_IPSR_GPSR(IP0SR3_23_20, MMC_SD_D3),
957 PINMUX_IPSR_GPSR(IP0SR3_27_24, MMC_D5),
958 PINMUX_IPSR_GPSR(IP0SR3_31_28, MMC_D4),
961 PINMUX_IPSR_GPSR(IP1SR3_3_0, MMC_D7),
963 PINMUX_IPSR_GPSR(IP1SR3_7_4, MMC_D6),
965 PINMUX_IPSR_GPSR(IP1SR3_11_8, MMC_SD_CMD),
967 PINMUX_IPSR_GPSR(IP1SR3_15_12, SD_CD),
969 PINMUX_IPSR_GPSR(IP1SR3_19_16, SD_WP),
971 PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKIN),
972 PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKEN_IN),
973 PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_X),
975 PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT),
976 PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT),
977 PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_X),
979 PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL),
982 PINMUX_IPSR_GPSR(IP2SR3_3_0, QSPI0_IO3),
983 PINMUX_IPSR_GPSR(IP2SR3_7_4, QSPI0_IO2),
984 PINMUX_IPSR_GPSR(IP2SR3_11_8, QSPI0_MISO_IO1),
985 PINMUX_IPSR_GPSR(IP2SR3_15_12, QSPI0_MOSI_IO0),
986 PINMUX_IPSR_GPSR(IP2SR3_19_16, QSPI0_SPCLK),
987 PINMUX_IPSR_GPSR(IP2SR3_23_20, QSPI1_MOSI_IO0),
988 PINMUX_IPSR_GPSR(IP2SR3_27_24, QSPI1_SPCLK),
989 PINMUX_IPSR_GPSR(IP2SR3_31_28, QSPI1_MISO_IO1),
992 PINMUX_IPSR_GPSR(IP3SR3_3_0, QSPI1_IO2),
993 PINMUX_IPSR_GPSR(IP3SR3_7_4, QSPI1_SSL),
994 PINMUX_IPSR_GPSR(IP3SR3_11_8, QSPI1_IO3),
995 PINMUX_IPSR_GPSR(IP3SR3_15_12, RPC_RESET_N),
996 PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N),
997 PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N),
1000 PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),
1002 PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),
1004 PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),
1006 PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),
1008 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),
1009 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),
1011 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),
1012 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),
1014 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),
1015 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),
1017 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),
1018 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),
1021 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),
1022 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC),
1024 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),
1025 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),
1027 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),
1028 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),
1030 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),
1031 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),
1033 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),
1034 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),
1036 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),
1037 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),
1039 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),
1040 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),
1042 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0),
1043 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),
1046 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),
1047 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),
1049 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),
1050 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),
1052 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),
1053 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),
1055 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),
1056 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),
1058 PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK),
1061 PINMUX_IPSR_MSEL(IP0SR7_3_0, AVB0_AVTP_PPS, SEL_AVB0_AVTP_PPS_1),
1062 PINMUX_IPSR_MSEL(IP0SR7_3_0, AVB0_MII_COL, SEL_AVB0_AVTP_PPS_0),
1064 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE),
1065 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS),
1067 PINMUX_IPSR_MSEL(IP0SR7_11_8, AVB0_AVTP_MATCH, SEL_AVB0_AVTP_MATCH_1),
1068 PINMUX_IPSR_MSEL(IP0SR7_11_8, AVB0_MII_RX_ER, SEL_AVB0_AVTP_MATCH_0),
1069 PINMUX_IPSR_MSEL(IP0SR7_11_8, CC5_OSCOUT, SEL_AVB0_AVTP_MATCH_0),
1071 PINMUX_IPSR_MSEL(IP0SR7_15_12, AVB0_TD3, SEL_AVB0_TD3_1),
1072 PINMUX_IPSR_MSEL(IP0SR7_15_12, AVB0_MII_TD3, SEL_AVB0_TD3_0),
1074 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK),
1075 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER),
1077 PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT),
1079 PINMUX_IPSR_MSEL(IP0SR7_27_24, AVB0_TD2, SEL_AVB0_TD2_1),
1080 PINMUX_IPSR_MSEL(IP0SR7_27_24, AVB0_MII_TD2, SEL_AVB0_TD2_0),
1082 PINMUX_IPSR_MSEL(IP0SR7_31_28, AVB0_TD1, SEL_AVB0_TD1_1),
1083 PINMUX_IPSR_MSEL(IP0SR7_31_28, AVB0_MII_TD1, SEL_AVB0_TD1_0),
1086 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3),
1087 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3),
1089 PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK),
1091 PINMUX_IPSR_MSEL(IP1SR7_11_8, AVB0_MAGIC, SEL_AVB0_MAGIC_1),
1093 PINMUX_IPSR_MSEL(IP1SR7_15_12, AVB0_TD0, SEL_AVB0_TD0_1),
1094 PINMUX_IPSR_MSEL(IP1SR7_15_12, AVB0_MII_TD0, SEL_AVB0_TD0_0),
1096 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2),
1097 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2),
1099 PINMUX_IPSR_MSEL(IP1SR7_23_20, AVB0_MDC, SEL_AVB0_MDC_1),
1101 PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO),
1103 PINMUX_IPSR_MSEL(IP1SR7_31_28, AVB0_TXC, SEL_AVB0_TXC_1),
1104 PINMUX_IPSR_MSEL(IP1SR7_31_28, AVB0_MII_TXC, SEL_AVB0_TXC_0),
1107 PINMUX_IPSR_MSEL(IP2SR7_3_0, AVB0_TX_CTL, SEL_AVB0_TX_CTL_1),
1108 PINMUX_IPSR_MSEL(IP2SR7_3_0, AVB0_MII_TX_EN, SEL_AVB0_TX_CTL_0),
1110 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1),
1111 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1),
1113 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0),
1114 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0),
1116 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC),
1117 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC),
1119 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL),
1120 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV),
1123 PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0),
1124 PINMUX_IPSR_MSEL(IP0SR8_7_4, SDA0, SEL_SDA0_0),
1125 PINMUX_IPSR_MSEL(IP0SR8_11_8, SCL1, SEL_SCL1_0),
1126 PINMUX_IPSR_MSEL(IP0SR8_15_12, SDA1, SEL_SDA1_0),
1127 PINMUX_IPSR_MSEL(IP0SR8_19_16, SCL2, SEL_SCL2_0),
1128 PINMUX_IPSR_MSEL(IP0SR8_23_20, SDA2, SEL_SDA2_0),
1129 PINMUX_IPSR_MSEL(IP0SR8_27_24, SCL3, SEL_SCL3_0),
1130 PINMUX_IPSR_MSEL(IP0SR8_31_28, SDA3, SEL_SDA3_0),
1133 PINMUX_IPSR_MSEL(IP1SR8_3_0, SCL4, SEL_SCL4_0),
1134 PINMUX_IPSR_MSEL(IP1SR8_3_0, HRX2, SEL_SCL4_0),
1135 PINMUX_IPSR_MSEL(IP1SR8_3_0, SCK4, SEL_SCL4_0),
1137 PINMUX_IPSR_MSEL(IP1SR8_7_4, SDA4, SEL_SDA4_0),
1138 PINMUX_IPSR_MSEL(IP1SR8_7_4, HTX2, SEL_SDA4_0),
1139 PINMUX_IPSR_MSEL(IP1SR8_7_4, CTS4_N, SEL_SDA4_0),
1141 PINMUX_IPSR_MSEL(IP1SR8_11_8, SCL5, SEL_SCL5_0),
1142 PINMUX_IPSR_MSEL(IP1SR8_11_8, HRTS2_N, SEL_SCL5_0),
1143 PINMUX_IPSR_MSEL(IP1SR8_11_8, RTS4_N, SEL_SCL5_0),
1145 PINMUX_IPSR_MSEL(IP1SR8_15_12, SDA5, SEL_SDA5_0),
1146 PINMUX_IPSR_MSEL(IP1SR8_15_12, SCIF_CLK2, SEL_SDA5_0),
1148 PINMUX_IPSR_GPSR(IP1SR8_19_16, HCTS2_N),
1149 PINMUX_IPSR_GPSR(IP1SR8_19_16, TX4),
1151 PINMUX_IPSR_GPSR(IP1SR8_23_20, HSCK2),
1152 PINMUX_IPSR_GPSR(IP1SR8_23_20, RX4),
1156 * Pins not associated with a GPIO port.
1162 static const struct sh_pfc_pin pinmux_pins[] = {
1163 PINMUX_GPIO_GP_ALL(),
1166 /* - AVB0 ------------------------------------------------ */
1167 static const unsigned int avb0_link_pins[] = {
1171 static const unsigned int avb0_link_mux[] = {
1174 static const unsigned int avb0_magic_pins[] = {
1178 static const unsigned int avb0_magic_mux[] = {
1181 static const unsigned int avb0_phy_int_pins[] = {
1185 static const unsigned int avb0_phy_int_mux[] = {
1188 static const unsigned int avb0_mdio_pins[] = {
1189 /* AVB0_MDC, AVB0_MDIO */
1190 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1192 static const unsigned int avb0_mdio_mux[] = {
1193 AVB0_MDC_MARK, AVB0_MDIO_MARK,
1195 static const unsigned int avb0_rgmii_pins[] = {
1197 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
1198 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
1200 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
1201 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7),
1202 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3),
1203 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
1204 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
1205 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8),
1207 static const unsigned int avb0_rgmii_mux[] = {
1208 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
1209 AVB0_TD0_MARK, AVB0_TD1_MARK,
1210 AVB0_TD2_MARK, AVB0_TD3_MARK,
1211 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
1212 AVB0_RD0_MARK, AVB0_RD1_MARK,
1213 AVB0_RD2_MARK, AVB0_RD3_MARK,
1215 static const unsigned int avb0_txcrefclk_pins[] = {
1216 /* AVB0_TXCREFCLK */
1219 static const unsigned int avb0_txcrefclk_mux[] = {
1220 AVB0_TXCREFCLK_MARK,
1222 static const unsigned int avb0_avtp_pps_pins[] = {
1226 static const unsigned int avb0_avtp_pps_mux[] = {
1229 static const unsigned int avb0_avtp_capture_pins[] = {
1230 /* AVB0_AVTP_CAPTURE */
1233 static const unsigned int avb0_avtp_capture_mux[] = {
1234 AVB0_AVTP_CAPTURE_MARK,
1236 static const unsigned int avb0_avtp_match_pins[] = {
1237 /* AVB0_AVTP_MATCH */
1240 static const unsigned int avb0_avtp_match_mux[] = {
1241 AVB0_AVTP_MATCH_MARK,
1244 /* - AVB1 ------------------------------------------------ */
1245 static const unsigned int avb1_link_pins[] = {
1249 static const unsigned int avb1_link_mux[] = {
1252 static const unsigned int avb1_magic_pins[] = {
1256 static const unsigned int avb1_magic_mux[] = {
1259 static const unsigned int avb1_phy_int_pins[] = {
1263 static const unsigned int avb1_phy_int_mux[] = {
1266 static const unsigned int avb1_mdio_pins[] = {
1267 /* AVB1_MDC, AVB1_MDIO */
1268 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
1270 static const unsigned int avb1_mdio_mux[] = {
1271 AVB1_MDC_MARK, AVB1_MDIO_MARK,
1273 static const unsigned int avb1_rgmii_pins[] = {
1275 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
1276 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
1278 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1279 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
1280 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
1281 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8),
1282 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1283 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
1285 static const unsigned int avb1_rgmii_mux[] = {
1286 AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
1287 AVB1_TD0_MARK, AVB1_TD1_MARK,
1288 AVB1_TD2_MARK, AVB1_TD3_MARK,
1289 AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
1290 AVB1_RD0_MARK, AVB1_RD1_MARK,
1291 AVB1_RD2_MARK, AVB1_RD3_MARK,
1293 static const unsigned int avb1_txcrefclk_pins[] = {
1294 /* AVB1_TXCREFCLK */
1297 static const unsigned int avb1_txcrefclk_mux[] = {
1298 AVB1_TXCREFCLK_MARK,
1300 static const unsigned int avb1_avtp_pps_pins[] = {
1304 static const unsigned int avb1_avtp_pps_mux[] = {
1307 static const unsigned int avb1_avtp_capture_pins[] = {
1308 /* AVB1_AVTP_CAPTURE */
1311 static const unsigned int avb1_avtp_capture_mux[] = {
1312 AVB1_AVTP_CAPTURE_MARK,
1314 static const unsigned int avb1_avtp_match_pins[] = {
1315 /* AVB1_AVTP_MATCH */
1318 static const unsigned int avb1_avtp_match_mux[] = {
1319 AVB1_AVTP_MATCH_MARK,
1322 /* - AVB2 ------------------------------------------------ */
1323 static const unsigned int avb2_link_pins[] = {
1327 static const unsigned int avb2_link_mux[] = {
1330 static const unsigned int avb2_magic_pins[] = {
1334 static const unsigned int avb2_magic_mux[] = {
1337 static const unsigned int avb2_phy_int_pins[] = {
1341 static const unsigned int avb2_phy_int_mux[] = {
1344 static const unsigned int avb2_mdio_pins[] = {
1345 /* AVB2_MDC, AVB2_MDIO */
1346 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
1348 static const unsigned int avb2_mdio_mux[] = {
1349 AVB2_MDC_MARK, AVB2_MDIO_MARK,
1351 static const unsigned int avb2_rgmii_pins[] = {
1353 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
1354 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
1356 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
1357 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
1358 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8),
1359 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
1360 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
1361 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9),
1363 static const unsigned int avb2_rgmii_mux[] = {
1364 AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
1365 AVB2_TD0_MARK, AVB2_TD1_MARK,
1366 AVB2_TD2_MARK, AVB2_TD3_MARK,
1367 AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
1368 AVB2_RD0_MARK, AVB2_RD1_MARK,
1369 AVB2_RD2_MARK, AVB2_RD3_MARK,
1371 static const unsigned int avb2_txcrefclk_pins[] = {
1372 /* AVB2_TXCREFCLK */
1375 static const unsigned int avb2_txcrefclk_mux[] = {
1376 AVB2_TXCREFCLK_MARK,
1378 static const unsigned int avb2_avtp_pps_pins[] = {
1382 static const unsigned int avb2_avtp_pps_mux[] = {
1385 static const unsigned int avb2_avtp_capture_pins[] = {
1386 /* AVB2_AVTP_CAPTURE */
1389 static const unsigned int avb2_avtp_capture_mux[] = {
1390 AVB2_AVTP_CAPTURE_MARK,
1392 static const unsigned int avb2_avtp_match_pins[] = {
1393 /* AVB2_AVTP_MATCH */
1396 static const unsigned int avb2_avtp_match_mux[] = {
1397 AVB2_AVTP_MATCH_MARK,
1400 /* - CANFD0 ----------------------------------------------------------------- */
1401 static const unsigned int canfd0_data_pins[] = {
1402 /* CANFD0_TX, CANFD0_RX */
1403 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1405 static const unsigned int canfd0_data_mux[] = {
1406 CANFD0_TX_MARK, CANFD0_RX_MARK,
1409 /* - CANFD1 ----------------------------------------------------------------- */
1410 static const unsigned int canfd1_data_pins[] = {
1411 /* CANFD1_TX, CANFD1_RX */
1412 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1414 static const unsigned int canfd1_data_mux[] = {
1415 CANFD1_TX_MARK, CANFD1_RX_MARK,
1418 /* - CANFD2 ----------------------------------------------------------------- */
1419 static const unsigned int canfd2_data_pins[] = {
1420 /* CANFD2_TX, CANFD2_RX */
1421 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1423 static const unsigned int canfd2_data_mux[] = {
1424 CANFD2_TX_MARK, CANFD2_RX_MARK,
1427 /* - CANFD3 ----------------------------------------------------------------- */
1428 static const unsigned int canfd3_data_pins[] = {
1429 /* CANFD3_TX, CANFD3_RX */
1430 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1432 static const unsigned int canfd3_data_mux[] = {
1433 CANFD3_TX_MARK, CANFD3_RX_MARK,
1436 /* - CANFD4 ----------------------------------------------------------------- */
1437 static const unsigned int canfd4_data_pins[] = {
1438 /* CANFD4_TX, CANFD4_RX */
1439 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1441 static const unsigned int canfd4_data_mux[] = {
1442 CANFD4_TX_MARK, CANFD4_RX_MARK,
1445 /* - CANFD5 ----------------------------------------------------------------- */
1446 static const unsigned int canfd5_data_pins[] = {
1447 /* CANFD5_TX, CANFD5_RX */
1448 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1450 static const unsigned int canfd5_data_mux[] = {
1451 CANFD5_TX_MARK, CANFD5_RX_MARK,
1454 /* - CANFD6 ----------------------------------------------------------------- */
1455 static const unsigned int canfd6_data_pins[] = {
1456 /* CANFD6_TX, CANFD6_RX */
1457 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1459 static const unsigned int canfd6_data_mux[] = {
1460 CANFD6_TX_MARK, CANFD6_RX_MARK,
1463 /* - CANFD7 ----------------------------------------------------------------- */
1464 static const unsigned int canfd7_data_pins[] = {
1465 /* CANFD7_TX, CANFD7_RX */
1466 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1468 static const unsigned int canfd7_data_mux[] = {
1469 CANFD7_TX_MARK, CANFD7_RX_MARK,
1472 /* - CANFD Clock ------------------------------------------------------------ */
1473 static const unsigned int can_clk_pins[] = {
1477 static const unsigned int can_clk_mux[] = {
1481 /* - HSCIF0 ----------------------------------------------------------------- */
1482 static const unsigned int hscif0_data_pins[] = {
1484 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
1486 static const unsigned int hscif0_data_mux[] = {
1487 HRX0_MARK, HTX0_MARK,
1489 static const unsigned int hscif0_clk_pins[] = {
1493 static const unsigned int hscif0_clk_mux[] = {
1496 static const unsigned int hscif0_ctrl_pins[] = {
1497 /* HRTS0_N, HCTS0_N */
1498 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1500 static const unsigned int hscif0_ctrl_mux[] = {
1501 HRTS0_N_MARK, HCTS0_N_MARK,
1504 /* - HSCIF1 ----------------------------------------------------------------- */
1505 static const unsigned int hscif1_data_pins[] = {
1507 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1509 static const unsigned int hscif1_data_mux[] = {
1510 HRX1_MARK, HTX1_MARK,
1512 static const unsigned int hscif1_clk_pins[] = {
1516 static const unsigned int hscif1_clk_mux[] = {
1519 static const unsigned int hscif1_ctrl_pins[] = {
1520 /* HRTS1_N, HCTS1_N */
1521 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
1523 static const unsigned int hscif1_ctrl_mux[] = {
1524 HRTS1_N_MARK, HCTS1_N_MARK,
1527 /* - HSCIF2 ----------------------------------------------------------------- */
1528 static const unsigned int hscif2_data_pins[] = {
1530 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1532 static const unsigned int hscif2_data_mux[] = {
1533 HRX2_MARK, HTX2_MARK,
1535 static const unsigned int hscif2_clk_pins[] = {
1539 static const unsigned int hscif2_clk_mux[] = {
1542 static const unsigned int hscif2_ctrl_pins[] = {
1543 /* HRTS2_N, HCTS2_N */
1544 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),
1546 static const unsigned int hscif2_ctrl_mux[] = {
1547 HRTS2_N_MARK, HCTS2_N_MARK,
1550 /* - HSCIF3 ----------------------------------------------------------------- */
1551 static const unsigned int hscif3_data_pins[] = {
1553 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
1555 static const unsigned int hscif3_data_mux[] = {
1556 HRX3_MARK, HTX3_MARK,
1558 static const unsigned int hscif3_clk_pins[] = {
1562 static const unsigned int hscif3_clk_mux[] = {
1565 static const unsigned int hscif3_ctrl_pins[] = {
1566 /* HRTS3_N, HCTS3_N */
1567 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1569 static const unsigned int hscif3_ctrl_mux[] = {
1570 HRTS3_N_MARK, HCTS3_N_MARK,
1573 /* - HSCIF3_A ----------------------------------------------------------------- */
1574 static const unsigned int hscif3_data_a_pins[] = {
1575 /* HRX3_A, HTX3_A */
1576 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1578 static const unsigned int hscif3_data_a_mux[] = {
1579 HRX3_A_MARK, HTX3_A_MARK,
1581 static const unsigned int hscif3_clk_a_pins[] = {
1585 static const unsigned int hscif3_clk_a_mux[] = {
1588 static const unsigned int hscif3_ctrl_a_pins[] = {
1589 /* HRTS3_N_A, HCTS3_N_A */
1590 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1592 static const unsigned int hscif3_ctrl_a_mux[] = {
1593 HRTS3_N_A_MARK, HCTS3_N_A_MARK,
1596 /* - I2C0 ------------------------------------------------------------------- */
1597 static const unsigned int i2c0_pins[] = {
1599 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),
1601 static const unsigned int i2c0_mux[] = {
1602 SDA0_MARK, SCL0_MARK,
1605 /* - I2C1 ------------------------------------------------------------------- */
1606 static const unsigned int i2c1_pins[] = {
1608 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),
1610 static const unsigned int i2c1_mux[] = {
1611 SDA1_MARK, SCL1_MARK,
1614 /* - I2C2 ------------------------------------------------------------------- */
1615 static const unsigned int i2c2_pins[] = {
1617 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),
1619 static const unsigned int i2c2_mux[] = {
1620 SDA2_MARK, SCL2_MARK,
1623 /* - I2C3 ------------------------------------------------------------------- */
1624 static const unsigned int i2c3_pins[] = {
1626 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),
1628 static const unsigned int i2c3_mux[] = {
1629 SDA3_MARK, SCL3_MARK,
1632 /* - I2C4 ------------------------------------------------------------------- */
1633 static const unsigned int i2c4_pins[] = {
1635 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),
1637 static const unsigned int i2c4_mux[] = {
1638 SDA4_MARK, SCL4_MARK,
1641 /* - I2C5 ------------------------------------------------------------------- */
1642 static const unsigned int i2c5_pins[] = {
1644 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),
1646 static const unsigned int i2c5_mux[] = {
1647 SDA5_MARK, SCL5_MARK,
1650 /* - MMC -------------------------------------------------------------------- */
1651 static const unsigned int mmc_data_pins[] = {
1652 /* MMC_SD_D[0:3], MMC_D[4:7] */
1653 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1654 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
1655 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
1656 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1658 static const unsigned int mmc_data_mux[] = {
1659 MMC_SD_D0_MARK, MMC_SD_D1_MARK,
1660 MMC_SD_D2_MARK, MMC_SD_D3_MARK,
1661 MMC_D4_MARK, MMC_D5_MARK,
1662 MMC_D6_MARK, MMC_D7_MARK,
1664 static const unsigned int mmc_ctrl_pins[] = {
1665 /* MMC_SD_CLK, MMC_SD_CMD */
1666 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
1668 static const unsigned int mmc_ctrl_mux[] = {
1669 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
1671 static const unsigned int mmc_cd_pins[] = {
1675 static const unsigned int mmc_cd_mux[] = {
1678 static const unsigned int mmc_wp_pins[] = {
1682 static const unsigned int mmc_wp_mux[] = {
1685 static const unsigned int mmc_ds_pins[] = {
1689 static const unsigned int mmc_ds_mux[] = {
1693 /* - MSIOF0 ----------------------------------------------------------------- */
1694 static const unsigned int msiof0_clk_pins[] = {
1698 static const unsigned int msiof0_clk_mux[] = {
1701 static const unsigned int msiof0_sync_pins[] = {
1705 static const unsigned int msiof0_sync_mux[] = {
1708 static const unsigned int msiof0_ss1_pins[] = {
1712 static const unsigned int msiof0_ss1_mux[] = {
1715 static const unsigned int msiof0_ss2_pins[] = {
1719 static const unsigned int msiof0_ss2_mux[] = {
1722 static const unsigned int msiof0_txd_pins[] = {
1726 static const unsigned int msiof0_txd_mux[] = {
1729 static const unsigned int msiof0_rxd_pins[] = {
1733 static const unsigned int msiof0_rxd_mux[] = {
1737 /* - MSIOF1 ----------------------------------------------------------------- */
1738 static const unsigned int msiof1_clk_pins[] = {
1742 static const unsigned int msiof1_clk_mux[] = {
1745 static const unsigned int msiof1_sync_pins[] = {
1749 static const unsigned int msiof1_sync_mux[] = {
1752 static const unsigned int msiof1_ss1_pins[] = {
1756 static const unsigned int msiof1_ss1_mux[] = {
1759 static const unsigned int msiof1_ss2_pins[] = {
1763 static const unsigned int msiof1_ss2_mux[] = {
1766 static const unsigned int msiof1_txd_pins[] = {
1770 static const unsigned int msiof1_txd_mux[] = {
1773 static const unsigned int msiof1_rxd_pins[] = {
1777 static const unsigned int msiof1_rxd_mux[] = {
1781 /* - MSIOF2 ----------------------------------------------------------------- */
1782 static const unsigned int msiof2_clk_pins[] = {
1786 static const unsigned int msiof2_clk_mux[] = {
1789 static const unsigned int msiof2_sync_pins[] = {
1793 static const unsigned int msiof2_sync_mux[] = {
1796 static const unsigned int msiof2_ss1_pins[] = {
1800 static const unsigned int msiof2_ss1_mux[] = {
1803 static const unsigned int msiof2_ss2_pins[] = {
1807 static const unsigned int msiof2_ss2_mux[] = {
1810 static const unsigned int msiof2_txd_pins[] = {
1814 static const unsigned int msiof2_txd_mux[] = {
1817 static const unsigned int msiof2_rxd_pins[] = {
1821 static const unsigned int msiof2_rxd_mux[] = {
1825 /* - MSIOF3 ----------------------------------------------------------------- */
1826 static const unsigned int msiof3_clk_pins[] = {
1830 static const unsigned int msiof3_clk_mux[] = {
1833 static const unsigned int msiof3_sync_pins[] = {
1837 static const unsigned int msiof3_sync_mux[] = {
1840 static const unsigned int msiof3_ss1_pins[] = {
1844 static const unsigned int msiof3_ss1_mux[] = {
1847 static const unsigned int msiof3_ss2_pins[] = {
1851 static const unsigned int msiof3_ss2_mux[] = {
1854 static const unsigned int msiof3_txd_pins[] = {
1858 static const unsigned int msiof3_txd_mux[] = {
1861 static const unsigned int msiof3_rxd_pins[] = {
1865 static const unsigned int msiof3_rxd_mux[] = {
1869 /* - MSIOF4 ----------------------------------------------------------------- */
1870 static const unsigned int msiof4_clk_pins[] = {
1874 static const unsigned int msiof4_clk_mux[] = {
1877 static const unsigned int msiof4_sync_pins[] = {
1881 static const unsigned int msiof4_sync_mux[] = {
1884 static const unsigned int msiof4_ss1_pins[] = {
1888 static const unsigned int msiof4_ss1_mux[] = {
1891 static const unsigned int msiof4_ss2_pins[] = {
1895 static const unsigned int msiof4_ss2_mux[] = {
1898 static const unsigned int msiof4_txd_pins[] = {
1902 static const unsigned int msiof4_txd_mux[] = {
1905 static const unsigned int msiof4_rxd_pins[] = {
1909 static const unsigned int msiof4_rxd_mux[] = {
1913 /* - MSIOF5 ----------------------------------------------------------------- */
1914 static const unsigned int msiof5_clk_pins[] = {
1918 static const unsigned int msiof5_clk_mux[] = {
1921 static const unsigned int msiof5_sync_pins[] = {
1925 static const unsigned int msiof5_sync_mux[] = {
1928 static const unsigned int msiof5_ss1_pins[] = {
1932 static const unsigned int msiof5_ss1_mux[] = {
1935 static const unsigned int msiof5_ss2_pins[] = {
1939 static const unsigned int msiof5_ss2_mux[] = {
1942 static const unsigned int msiof5_txd_pins[] = {
1946 static const unsigned int msiof5_txd_mux[] = {
1949 static const unsigned int msiof5_rxd_pins[] = {
1953 static const unsigned int msiof5_rxd_mux[] = {
1957 /* - PCIE ------------------------------------------------------------------- */
1958 static const unsigned int pcie0_clkreq_n_pins[] = {
1959 /* PCIE0_CLKREQ_N */
1963 static const unsigned int pcie0_clkreq_n_mux[] = {
1964 PCIE0_CLKREQ_N_MARK,
1967 static const unsigned int pcie1_clkreq_n_pins[] = {
1968 /* PCIE1_CLKREQ_N */
1972 static const unsigned int pcie1_clkreq_n_mux[] = {
1973 PCIE1_CLKREQ_N_MARK,
1976 /* - PWM0 ------------------------------------------------------------------- */
1977 static const unsigned int pwm0_pins[] = {
1981 static const unsigned int pwm0_mux[] = {
1985 /* - PWM1 ------------------------------------------------------------------- */
1986 static const unsigned int pwm1_pins[] = {
1990 static const unsigned int pwm1_mux[] = {
1994 /* - PWM2 ------------------------------------------------------------------- */
1995 static const unsigned int pwm2_pins[] = {
1999 static const unsigned int pwm2_mux[] = {
2003 /* - PWM3 ------------------------------------------------------------------- */
2004 static const unsigned int pwm3_pins[] = {
2008 static const unsigned int pwm3_mux[] = {
2012 /* - PWM4 ------------------------------------------------------------------- */
2013 static const unsigned int pwm4_pins[] = {
2017 static const unsigned int pwm4_mux[] = {
2021 /* - PWM5 ------------------------------------------------------------------- */
2022 static const unsigned int pwm5_pins[] = {
2026 static const unsigned int pwm5_mux[] = {
2030 /* - PWM6 ------------------------------------------------------------------- */
2031 static const unsigned int pwm6_pins[] = {
2035 static const unsigned int pwm6_mux[] = {
2039 /* - PWM7 ------------------------------------------------------------------- */
2040 static const unsigned int pwm7_pins[] = {
2044 static const unsigned int pwm7_mux[] = {
2048 /* - PWM8 ------------------------------------------------------------------- */
2049 static const unsigned int pwm8_pins[] = {
2053 static const unsigned int pwm8_mux[] = {
2057 /* - PWM9 ------------------------------------------------------------------- */
2058 static const unsigned int pwm9_pins[] = {
2062 static const unsigned int pwm9_mux[] = {
2066 /* - QSPI0 ------------------------------------------------------------------ */
2067 static const unsigned int qspi0_ctrl_pins[] = {
2069 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
2071 static const unsigned int qspi0_ctrl_mux[] = {
2072 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2074 static const unsigned int qspi0_data_pins[] = {
2075 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2076 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2077 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2079 static const unsigned int qspi0_data_mux[] = {
2080 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2081 QSPI0_IO2_MARK, QSPI0_IO3_MARK
2084 /* - QSPI1 ------------------------------------------------------------------ */
2085 static const unsigned int qspi1_ctrl_pins[] = {
2087 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
2089 static const unsigned int qspi1_ctrl_mux[] = {
2090 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2092 static const unsigned int qspi1_data_pins[] = {
2093 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2094 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
2095 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
2097 static const unsigned int qspi1_data_mux[] = {
2098 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2099 QSPI1_IO2_MARK, QSPI1_IO3_MARK
2102 /* - SCIF0 ------------------------------------------------------------------ */
2103 static const unsigned int scif0_data_pins[] = {
2105 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
2107 static const unsigned int scif0_data_mux[] = {
2110 static const unsigned int scif0_clk_pins[] = {
2114 static const unsigned int scif0_clk_mux[] = {
2117 static const unsigned int scif0_ctrl_pins[] = {
2118 /* RTS0_N, CTS0_N */
2119 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2121 static const unsigned int scif0_ctrl_mux[] = {
2122 RTS0_N_MARK, CTS0_N_MARK,
2125 /* - SCIF1 ------------------------------------------------------------------ */
2126 static const unsigned int scif1_data_pins[] = {
2128 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2130 static const unsigned int scif1_data_mux[] = {
2133 static const unsigned int scif1_clk_pins[] = {
2137 static const unsigned int scif1_clk_mux[] = {
2140 static const unsigned int scif1_ctrl_pins[] = {
2141 /* RTS1_N, CTS1_N */
2142 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
2144 static const unsigned int scif1_ctrl_mux[] = {
2145 RTS1_N_MARK, CTS1_N_MARK,
2148 /* - SCIF3 ------------------------------------------------------------------ */
2149 static const unsigned int scif3_data_pins[] = {
2151 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2153 static const unsigned int scif3_data_mux[] = {
2156 static const unsigned int scif3_clk_pins[] = {
2160 static const unsigned int scif3_clk_mux[] = {
2163 static const unsigned int scif3_ctrl_pins[] = {
2164 /* RTS3_N, CTS3_N */
2165 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2167 static const unsigned int scif3_ctrl_mux[] = {
2168 RTS3_N_MARK, CTS3_N_MARK,
2171 /* - SCIF4 ------------------------------------------------------------------ */
2172 static const unsigned int scif4_data_pins[] = {
2174 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
2176 static const unsigned int scif4_data_mux[] = {
2179 static const unsigned int scif4_clk_pins[] = {
2183 static const unsigned int scif4_clk_mux[] = {
2186 static const unsigned int scif4_ctrl_pins[] = {
2187 /* RTS4_N, CTS4_N */
2188 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
2190 static const unsigned int scif4_ctrl_mux[] = {
2191 RTS4_N_MARK, CTS4_N_MARK,
2194 /* - SCIF Clock ------------------------------------------------------------- */
2195 static const unsigned int scif_clk_pins[] = {
2199 static const unsigned int scif_clk_mux[] = {
2203 /* - TPU ------------------------------------------------------------------- */
2204 static const unsigned int tpu_to0_pins[] = {
2208 static const unsigned int tpu_to0_mux[] = {
2211 static const unsigned int tpu_to1_pins[] = {
2215 static const unsigned int tpu_to1_mux[] = {
2218 static const unsigned int tpu_to2_pins[] = {
2222 static const unsigned int tpu_to2_mux[] = {
2225 static const unsigned int tpu_to3_pins[] = {
2229 static const unsigned int tpu_to3_mux[] = {
2233 /* - TSN0 ------------------------------------------------ */
2234 static const unsigned int tsn0_link_pins[] = {
2238 static const unsigned int tsn0_link_mux[] = {
2241 static const unsigned int tsn0_phy_int_pins[] = {
2245 static const unsigned int tsn0_phy_int_mux[] = {
2248 static const unsigned int tsn0_mdio_pins[] = {
2249 /* TSN0_MDC, TSN0_MDIO */
2250 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
2252 static const unsigned int tsn0_mdio_mux[] = {
2253 TSN0_MDC_MARK, TSN0_MDIO_MARK,
2255 static const unsigned int tsn0_rgmii_pins[] = {
2257 * TSN0_TX_CTL, TSN0_TXC, TSN0_TD0, TSN0_TD1, TSN0_TD2, TSN0_TD3,
2258 * TSN0_RX_CTL, TSN0_RXC, TSN0_RD0, TSN0_RD1, TSN0_RD2, TSN0_RD3,
2260 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 12),
2261 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),
2262 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2263 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 11),
2264 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),
2265 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
2267 static const unsigned int tsn0_rgmii_mux[] = {
2268 TSN0_TX_CTL_MARK, TSN0_TXC_MARK,
2269 TSN0_TD0_MARK, TSN0_TD1_MARK,
2270 TSN0_TD2_MARK, TSN0_TD3_MARK,
2271 TSN0_RX_CTL_MARK, TSN0_RXC_MARK,
2272 TSN0_RD0_MARK, TSN0_RD1_MARK,
2273 TSN0_RD2_MARK, TSN0_RD3_MARK,
2275 static const unsigned int tsn0_txcrefclk_pins[] = {
2276 /* TSN0_TXCREFCLK */
2279 static const unsigned int tsn0_txcrefclk_mux[] = {
2280 TSN0_TXCREFCLK_MARK,
2282 static const unsigned int tsn0_avtp_pps_pins[] = {
2283 /* TSN0_AVTP_PPS0, TSN0_AVTP_PPS1 */
2284 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),
2286 static const unsigned int tsn0_avtp_pps_mux[] = {
2287 TSN0_AVTP_PPS0_MARK, TSN0_AVTP_PPS1_MARK,
2289 static const unsigned int tsn0_avtp_capture_pins[] = {
2290 /* TSN0_AVTP_CAPTURE */
2293 static const unsigned int tsn0_avtp_capture_mux[] = {
2294 TSN0_AVTP_CAPTURE_MARK,
2296 static const unsigned int tsn0_avtp_match_pins[] = {
2297 /* TSN0_AVTP_MATCH */
2300 static const unsigned int tsn0_avtp_match_mux[] = {
2301 TSN0_AVTP_MATCH_MARK,
2304 static const struct sh_pfc_pin_group pinmux_groups[] = {
2305 SH_PFC_PIN_GROUP(avb0_link),
2306 SH_PFC_PIN_GROUP(avb0_magic),
2307 SH_PFC_PIN_GROUP(avb0_phy_int),
2308 SH_PFC_PIN_GROUP(avb0_mdio),
2309 SH_PFC_PIN_GROUP(avb0_rgmii),
2310 SH_PFC_PIN_GROUP(avb0_txcrefclk),
2311 SH_PFC_PIN_GROUP(avb0_avtp_pps),
2312 SH_PFC_PIN_GROUP(avb0_avtp_capture),
2313 SH_PFC_PIN_GROUP(avb0_avtp_match),
2315 SH_PFC_PIN_GROUP(avb1_link),
2316 SH_PFC_PIN_GROUP(avb1_magic),
2317 SH_PFC_PIN_GROUP(avb1_phy_int),
2318 SH_PFC_PIN_GROUP(avb1_mdio),
2319 SH_PFC_PIN_GROUP(avb1_rgmii),
2320 SH_PFC_PIN_GROUP(avb1_txcrefclk),
2321 SH_PFC_PIN_GROUP(avb1_avtp_pps),
2322 SH_PFC_PIN_GROUP(avb1_avtp_capture),
2323 SH_PFC_PIN_GROUP(avb1_avtp_match),
2325 SH_PFC_PIN_GROUP(avb2_link),
2326 SH_PFC_PIN_GROUP(avb2_magic),
2327 SH_PFC_PIN_GROUP(avb2_phy_int),
2328 SH_PFC_PIN_GROUP(avb2_mdio),
2329 SH_PFC_PIN_GROUP(avb2_rgmii),
2330 SH_PFC_PIN_GROUP(avb2_txcrefclk),
2331 SH_PFC_PIN_GROUP(avb2_avtp_pps),
2332 SH_PFC_PIN_GROUP(avb2_avtp_capture),
2333 SH_PFC_PIN_GROUP(avb2_avtp_match),
2335 SH_PFC_PIN_GROUP(canfd0_data),
2336 SH_PFC_PIN_GROUP(canfd1_data),
2337 SH_PFC_PIN_GROUP(canfd2_data),
2338 SH_PFC_PIN_GROUP(canfd3_data),
2339 SH_PFC_PIN_GROUP(canfd4_data),
2340 SH_PFC_PIN_GROUP(canfd5_data),
2341 SH_PFC_PIN_GROUP(canfd6_data),
2342 SH_PFC_PIN_GROUP(canfd7_data),
2343 SH_PFC_PIN_GROUP(can_clk),
2345 SH_PFC_PIN_GROUP(hscif0_data),
2346 SH_PFC_PIN_GROUP(hscif0_clk),
2347 SH_PFC_PIN_GROUP(hscif0_ctrl),
2348 SH_PFC_PIN_GROUP(hscif1_data),
2349 SH_PFC_PIN_GROUP(hscif1_clk),
2350 SH_PFC_PIN_GROUP(hscif1_ctrl),
2351 SH_PFC_PIN_GROUP(hscif2_data),
2352 SH_PFC_PIN_GROUP(hscif2_clk),
2353 SH_PFC_PIN_GROUP(hscif2_ctrl),
2354 SH_PFC_PIN_GROUP(hscif3_data), /* suffix might be updated */
2355 SH_PFC_PIN_GROUP(hscif3_clk), /* suffix might be updated */
2356 SH_PFC_PIN_GROUP(hscif3_ctrl), /* suffix might be updated */
2357 SH_PFC_PIN_GROUP(hscif3_data_a), /* suffix might be updated */
2358 SH_PFC_PIN_GROUP(hscif3_clk_a), /* suffix might be updated */
2359 SH_PFC_PIN_GROUP(hscif3_ctrl_a), /* suffix might be updated */
2361 SH_PFC_PIN_GROUP(i2c0),
2362 SH_PFC_PIN_GROUP(i2c1),
2363 SH_PFC_PIN_GROUP(i2c2),
2364 SH_PFC_PIN_GROUP(i2c3),
2365 SH_PFC_PIN_GROUP(i2c4),
2366 SH_PFC_PIN_GROUP(i2c5),
2368 BUS_DATA_PIN_GROUP(mmc_data, 1),
2369 BUS_DATA_PIN_GROUP(mmc_data, 4),
2370 BUS_DATA_PIN_GROUP(mmc_data, 8),
2371 SH_PFC_PIN_GROUP(mmc_ctrl),
2372 SH_PFC_PIN_GROUP(mmc_cd),
2373 SH_PFC_PIN_GROUP(mmc_wp),
2374 SH_PFC_PIN_GROUP(mmc_ds),
2376 SH_PFC_PIN_GROUP(msiof0_clk),
2377 SH_PFC_PIN_GROUP(msiof0_sync),
2378 SH_PFC_PIN_GROUP(msiof0_ss1),
2379 SH_PFC_PIN_GROUP(msiof0_ss2),
2380 SH_PFC_PIN_GROUP(msiof0_txd),
2381 SH_PFC_PIN_GROUP(msiof0_rxd),
2383 SH_PFC_PIN_GROUP(msiof1_clk),
2384 SH_PFC_PIN_GROUP(msiof1_sync),
2385 SH_PFC_PIN_GROUP(msiof1_ss1),
2386 SH_PFC_PIN_GROUP(msiof1_ss2),
2387 SH_PFC_PIN_GROUP(msiof1_txd),
2388 SH_PFC_PIN_GROUP(msiof1_rxd),
2390 SH_PFC_PIN_GROUP(msiof2_clk),
2391 SH_PFC_PIN_GROUP(msiof2_sync),
2392 SH_PFC_PIN_GROUP(msiof2_ss1),
2393 SH_PFC_PIN_GROUP(msiof2_ss2),
2394 SH_PFC_PIN_GROUP(msiof2_txd),
2395 SH_PFC_PIN_GROUP(msiof2_rxd),
2397 SH_PFC_PIN_GROUP(msiof3_clk),
2398 SH_PFC_PIN_GROUP(msiof3_sync),
2399 SH_PFC_PIN_GROUP(msiof3_ss1),
2400 SH_PFC_PIN_GROUP(msiof3_ss2),
2401 SH_PFC_PIN_GROUP(msiof3_txd),
2402 SH_PFC_PIN_GROUP(msiof3_rxd),
2404 SH_PFC_PIN_GROUP(msiof4_clk),
2405 SH_PFC_PIN_GROUP(msiof4_sync),
2406 SH_PFC_PIN_GROUP(msiof4_ss1),
2407 SH_PFC_PIN_GROUP(msiof4_ss2),
2408 SH_PFC_PIN_GROUP(msiof4_txd),
2409 SH_PFC_PIN_GROUP(msiof4_rxd),
2411 SH_PFC_PIN_GROUP(msiof5_clk),
2412 SH_PFC_PIN_GROUP(msiof5_sync),
2413 SH_PFC_PIN_GROUP(msiof5_ss1),
2414 SH_PFC_PIN_GROUP(msiof5_ss2),
2415 SH_PFC_PIN_GROUP(msiof5_txd),
2416 SH_PFC_PIN_GROUP(msiof5_rxd),
2418 SH_PFC_PIN_GROUP(pcie0_clkreq_n),
2419 SH_PFC_PIN_GROUP(pcie1_clkreq_n),
2421 SH_PFC_PIN_GROUP(pwm0),
2422 SH_PFC_PIN_GROUP(pwm1),
2423 SH_PFC_PIN_GROUP(pwm2),
2424 SH_PFC_PIN_GROUP(pwm3),
2425 SH_PFC_PIN_GROUP(pwm4),
2426 SH_PFC_PIN_GROUP(pwm5),
2427 SH_PFC_PIN_GROUP(pwm6),
2428 SH_PFC_PIN_GROUP(pwm7),
2429 SH_PFC_PIN_GROUP(pwm8),
2430 SH_PFC_PIN_GROUP(pwm9),
2432 SH_PFC_PIN_GROUP(qspi0_ctrl),
2433 BUS_DATA_PIN_GROUP(qspi0_data, 2),
2434 BUS_DATA_PIN_GROUP(qspi0_data, 4),
2435 SH_PFC_PIN_GROUP(qspi1_ctrl),
2436 BUS_DATA_PIN_GROUP(qspi1_data, 2),
2437 BUS_DATA_PIN_GROUP(qspi1_data, 4),
2439 SH_PFC_PIN_GROUP(scif0_data),
2440 SH_PFC_PIN_GROUP(scif0_clk),
2441 SH_PFC_PIN_GROUP(scif0_ctrl),
2442 SH_PFC_PIN_GROUP(scif1_data),
2443 SH_PFC_PIN_GROUP(scif1_clk),
2444 SH_PFC_PIN_GROUP(scif1_ctrl),
2445 SH_PFC_PIN_GROUP(scif3_data),
2446 SH_PFC_PIN_GROUP(scif3_clk),
2447 SH_PFC_PIN_GROUP(scif3_ctrl),
2448 SH_PFC_PIN_GROUP(scif4_data),
2449 SH_PFC_PIN_GROUP(scif4_clk),
2450 SH_PFC_PIN_GROUP(scif4_ctrl),
2451 SH_PFC_PIN_GROUP(scif_clk),
2453 SH_PFC_PIN_GROUP(tpu_to0),
2454 SH_PFC_PIN_GROUP(tpu_to1),
2455 SH_PFC_PIN_GROUP(tpu_to2),
2456 SH_PFC_PIN_GROUP(tpu_to3),
2458 SH_PFC_PIN_GROUP(tsn0_link),
2459 SH_PFC_PIN_GROUP(tsn0_phy_int),
2460 SH_PFC_PIN_GROUP(tsn0_mdio),
2461 SH_PFC_PIN_GROUP(tsn0_rgmii),
2462 SH_PFC_PIN_GROUP(tsn0_txcrefclk),
2463 SH_PFC_PIN_GROUP(tsn0_avtp_pps),
2464 SH_PFC_PIN_GROUP(tsn0_avtp_capture),
2465 SH_PFC_PIN_GROUP(tsn0_avtp_match),
2468 static const char * const avb0_groups[] = {
2476 "avb0_avtp_capture",
2480 static const char * const avb1_groups[] = {
2488 "avb1_avtp_capture",
2492 static const char * const avb2_groups[] = {
2500 "avb2_avtp_capture",
2504 static const char * const canfd0_groups[] = {
2508 static const char * const canfd1_groups[] = {
2512 static const char * const canfd2_groups[] = {
2516 static const char * const canfd3_groups[] = {
2520 static const char * const canfd4_groups[] = {
2524 static const char * const canfd5_groups[] = {
2528 static const char * const canfd6_groups[] = {
2532 static const char * const canfd7_groups[] = {
2536 static const char * const can_clk_groups[] = {
2540 static const char * const hscif0_groups[] = {
2546 static const char * const hscif1_groups[] = {
2552 static const char * const hscif2_groups[] = {
2558 static const char * const hscif3_groups[] = {
2559 /* suffix might be updated */
2568 static const char * const i2c0_groups[] = {
2572 static const char * const i2c1_groups[] = {
2576 static const char * const i2c2_groups[] = {
2580 static const char * const i2c3_groups[] = {
2584 static const char * const i2c4_groups[] = {
2588 static const char * const i2c5_groups[] = {
2592 static const char * const mmc_groups[] = {
2602 static const char * const msiof0_groups[] = {
2611 static const char * const msiof1_groups[] = {
2620 static const char * const msiof2_groups[] = {
2629 static const char * const msiof3_groups[] = {
2638 static const char * const msiof4_groups[] = {
2647 static const char * const msiof5_groups[] = {
2656 static const char * const pcie_groups[] = {
2661 static const char * const pwm0_groups[] = {
2665 static const char * const pwm1_groups[] = {
2669 static const char * const pwm2_groups[] = {
2673 static const char * const pwm3_groups[] = {
2677 static const char * const pwm4_groups[] = {
2681 static const char * const pwm5_groups[] = {
2685 static const char * const pwm6_groups[] = {
2689 static const char * const pwm7_groups[] = {
2693 static const char * const pwm8_groups[] = {
2697 static const char * const pwm9_groups[] = {
2701 static const char * const qspi0_groups[] = {
2707 static const char * const qspi1_groups[] = {
2713 static const char * const scif0_groups[] = {
2719 static const char * const scif1_groups[] = {
2725 static const char * const scif3_groups[] = {
2731 static const char * const scif4_groups[] = {
2737 static const char * const scif_clk_groups[] = {
2741 static const char * const tpu_groups[] = {
2748 static const char * const tsn0_groups[] = {
2755 "tsn0_avtp_capture",
2759 static const struct sh_pfc_function pinmux_functions[] = {
2760 SH_PFC_FUNCTION(avb0),
2761 SH_PFC_FUNCTION(avb1),
2762 SH_PFC_FUNCTION(avb2),
2764 SH_PFC_FUNCTION(canfd0),
2765 SH_PFC_FUNCTION(canfd1),
2766 SH_PFC_FUNCTION(canfd2),
2767 SH_PFC_FUNCTION(canfd3),
2768 SH_PFC_FUNCTION(canfd4),
2769 SH_PFC_FUNCTION(canfd5),
2770 SH_PFC_FUNCTION(canfd6),
2771 SH_PFC_FUNCTION(canfd7),
2772 SH_PFC_FUNCTION(can_clk),
2774 SH_PFC_FUNCTION(hscif0),
2775 SH_PFC_FUNCTION(hscif1),
2776 SH_PFC_FUNCTION(hscif2),
2777 SH_PFC_FUNCTION(hscif3),
2779 SH_PFC_FUNCTION(i2c0),
2780 SH_PFC_FUNCTION(i2c1),
2781 SH_PFC_FUNCTION(i2c2),
2782 SH_PFC_FUNCTION(i2c3),
2783 SH_PFC_FUNCTION(i2c4),
2784 SH_PFC_FUNCTION(i2c5),
2786 SH_PFC_FUNCTION(mmc),
2788 SH_PFC_FUNCTION(msiof0),
2789 SH_PFC_FUNCTION(msiof1),
2790 SH_PFC_FUNCTION(msiof2),
2791 SH_PFC_FUNCTION(msiof3),
2792 SH_PFC_FUNCTION(msiof4),
2793 SH_PFC_FUNCTION(msiof5),
2795 SH_PFC_FUNCTION(pcie),
2797 SH_PFC_FUNCTION(pwm0),
2798 SH_PFC_FUNCTION(pwm1),
2799 SH_PFC_FUNCTION(pwm2),
2800 SH_PFC_FUNCTION(pwm3),
2801 SH_PFC_FUNCTION(pwm4),
2802 SH_PFC_FUNCTION(pwm5),
2803 SH_PFC_FUNCTION(pwm6),
2804 SH_PFC_FUNCTION(pwm7),
2805 SH_PFC_FUNCTION(pwm8),
2806 SH_PFC_FUNCTION(pwm9),
2808 SH_PFC_FUNCTION(qspi0),
2809 SH_PFC_FUNCTION(qspi1),
2811 SH_PFC_FUNCTION(scif0),
2812 SH_PFC_FUNCTION(scif1),
2813 SH_PFC_FUNCTION(scif3),
2814 SH_PFC_FUNCTION(scif4),
2815 SH_PFC_FUNCTION(scif_clk),
2817 SH_PFC_FUNCTION(tpu),
2819 SH_PFC_FUNCTION(tsn0),
2822 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2823 #define F_(x, y) FN_##y
2824 #define FM(x) FN_##x
2825 { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,
2826 GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2827 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2829 /* GP0_31_19 RESERVED */
2830 GP_0_18_FN, GPSR0_18,
2831 GP_0_17_FN, GPSR0_17,
2832 GP_0_16_FN, GPSR0_16,
2833 GP_0_15_FN, GPSR0_15,
2834 GP_0_14_FN, GPSR0_14,
2835 GP_0_13_FN, GPSR0_13,
2836 GP_0_12_FN, GPSR0_12,
2837 GP_0_11_FN, GPSR0_11,
2838 GP_0_10_FN, GPSR0_10,
2848 GP_0_0_FN, GPSR0_0, ))
2850 { PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP(
2854 GP_1_28_FN, GPSR1_28,
2855 GP_1_27_FN, GPSR1_27,
2856 GP_1_26_FN, GPSR1_26,
2857 GP_1_25_FN, GPSR1_25,
2858 GP_1_24_FN, GPSR1_24,
2859 GP_1_23_FN, GPSR1_23,
2860 GP_1_22_FN, GPSR1_22,
2861 GP_1_21_FN, GPSR1_21,
2862 GP_1_20_FN, GPSR1_20,
2863 GP_1_19_FN, GPSR1_19,
2864 GP_1_18_FN, GPSR1_18,
2865 GP_1_17_FN, GPSR1_17,
2866 GP_1_16_FN, GPSR1_16,
2867 GP_1_15_FN, GPSR1_15,
2868 GP_1_14_FN, GPSR1_14,
2869 GP_1_13_FN, GPSR1_13,
2870 GP_1_12_FN, GPSR1_12,
2871 GP_1_11_FN, GPSR1_11,
2872 GP_1_10_FN, GPSR1_10,
2882 GP_1_0_FN, GPSR1_0, ))
2884 { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,
2885 GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2886 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2888 /* GP2_31_20 RESERVED */
2889 GP_2_19_FN, GPSR2_19,
2890 GP_2_18_FN, GPSR2_18,
2891 GP_2_17_FN, GPSR2_17,
2892 GP_2_16_FN, GPSR2_16,
2893 GP_2_15_FN, GPSR2_15,
2894 GP_2_14_FN, GPSR2_14,
2895 GP_2_13_FN, GPSR2_13,
2896 GP_2_12_FN, GPSR2_12,
2897 GP_2_11_FN, GPSR2_11,
2898 GP_2_10_FN, GPSR2_10,
2908 GP_2_0_FN, GPSR2_0, ))
2910 { PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP(
2913 GP_3_29_FN, GPSR3_29,
2914 GP_3_28_FN, GPSR3_28,
2915 GP_3_27_FN, GPSR3_27,
2916 GP_3_26_FN, GPSR3_26,
2917 GP_3_25_FN, GPSR3_25,
2918 GP_3_24_FN, GPSR3_24,
2919 GP_3_23_FN, GPSR3_23,
2920 GP_3_22_FN, GPSR3_22,
2921 GP_3_21_FN, GPSR3_21,
2922 GP_3_20_FN, GPSR3_20,
2923 GP_3_19_FN, GPSR3_19,
2924 GP_3_18_FN, GPSR3_18,
2925 GP_3_17_FN, GPSR3_17,
2926 GP_3_16_FN, GPSR3_16,
2927 GP_3_15_FN, GPSR3_15,
2928 GP_3_14_FN, GPSR3_14,
2929 GP_3_13_FN, GPSR3_13,
2930 GP_3_12_FN, GPSR3_12,
2931 GP_3_11_FN, GPSR3_11,
2932 GP_3_10_FN, GPSR3_10,
2942 GP_3_0_FN, GPSR3_0, ))
2944 { PINMUX_CFG_REG("GPSR4", 0xE6060040, 32, 1, GROUP(
2952 GP_4_24_FN, GPSR4_24,
2953 GP_4_23_FN, GPSR4_23,
2954 GP_4_22_FN, GPSR4_22,
2955 GP_4_21_FN, GPSR4_21,
2956 GP_4_20_FN, GPSR4_20,
2957 GP_4_19_FN, GPSR4_19,
2958 GP_4_18_FN, GPSR4_18,
2959 GP_4_17_FN, GPSR4_17,
2960 GP_4_16_FN, GPSR4_16,
2961 GP_4_15_FN, GPSR4_15,
2962 GP_4_14_FN, GPSR4_14,
2963 GP_4_13_FN, GPSR4_13,
2964 GP_4_12_FN, GPSR4_12,
2965 GP_4_11_FN, GPSR4_11,
2966 GP_4_10_FN, GPSR4_10,
2976 GP_4_0_FN, GPSR4_0, ))
2978 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,
2979 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2980 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2982 /* GP5_31_21 RESERVED */
2983 GP_5_20_FN, GPSR5_20,
2984 GP_5_19_FN, GPSR5_19,
2985 GP_5_18_FN, GPSR5_18,
2986 GP_5_17_FN, GPSR5_17,
2987 GP_5_16_FN, GPSR5_16,
2988 GP_5_15_FN, GPSR5_15,
2989 GP_5_14_FN, GPSR5_14,
2990 GP_5_13_FN, GPSR5_13,
2991 GP_5_12_FN, GPSR5_12,
2992 GP_5_11_FN, GPSR5_11,
2993 GP_5_10_FN, GPSR5_10,
3003 GP_5_0_FN, GPSR5_0, ))
3005 { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,
3006 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3007 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3009 /* GP6_31_21 RESERVED */
3010 GP_6_20_FN, GPSR6_20,
3011 GP_6_19_FN, GPSR6_19,
3012 GP_6_18_FN, GPSR6_18,
3013 GP_6_17_FN, GPSR6_17,
3014 GP_6_16_FN, GPSR6_16,
3015 GP_6_15_FN, GPSR6_15,
3016 GP_6_14_FN, GPSR6_14,
3017 GP_6_13_FN, GPSR6_13,
3018 GP_6_12_FN, GPSR6_12,
3019 GP_6_11_FN, GPSR6_11,
3020 GP_6_10_FN, GPSR6_10,
3030 GP_6_0_FN, GPSR6_0, ))
3032 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,
3033 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3034 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3036 /* GP7_31_21 RESERVED */
3037 GP_7_20_FN, GPSR7_20,
3038 GP_7_19_FN, GPSR7_19,
3039 GP_7_18_FN, GPSR7_18,
3040 GP_7_17_FN, GPSR7_17,
3041 GP_7_16_FN, GPSR7_16,
3042 GP_7_15_FN, GPSR7_15,
3043 GP_7_14_FN, GPSR7_14,
3044 GP_7_13_FN, GPSR7_13,
3045 GP_7_12_FN, GPSR7_12,
3046 GP_7_11_FN, GPSR7_11,
3047 GP_7_10_FN, GPSR7_10,
3057 GP_7_0_FN, GPSR7_0, ))
3059 { PINMUX_CFG_REG_VAR("GPSR8", 0xE6068040, 32,
3060 GROUP(-18, 1, 1, 1, 1,
3061 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3063 /* GP8_31_14 RESERVED */
3064 GP_8_13_FN, GPSR8_13,
3065 GP_8_12_FN, GPSR8_12,
3066 GP_8_11_FN, GPSR8_11,
3067 GP_8_10_FN, GPSR8_10,
3077 GP_8_0_FN, GPSR8_0, ))
3083 #define FM(x) FN_##x,
3084 { PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP(
3094 { PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP(
3104 { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,
3105 GROUP(-20, 4, 4, 4),
3107 /* IP2SR0_31_12 RESERVED */
3112 { PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP(
3122 { PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP(
3132 { PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP(
3142 { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,
3143 GROUP(-12, 4, 4, 4, 4, 4),
3145 /* IP3SR1_31_20 RESERVED */
3152 { PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP(
3162 { PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP(
3172 { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,
3173 GROUP(-16, 4, 4, 4, 4),
3175 /* IP2SR2_31_16 RESERVED */
3181 { PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP(
3191 { PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP(
3201 { PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP(
3211 { PINMUX_CFG_REG_VAR("IP3SR3", 0xE605886C, 32,
3212 GROUP(-8, 4, 4, 4, 4, 4, 4),
3214 /* IP3SR3_31_24 RESERVED */
3222 { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(
3232 { PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP(
3242 { PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32,
3243 GROUP(-12, 4, 4, 4, 4, 4),
3245 /* IP2SR6_31_20 RESERVED */
3252 { PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP(
3262 { PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP(
3272 { PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32,
3273 GROUP(-12, 4, 4, 4, 4, 4),
3275 /* IP2SR7_31_20 RESERVED */
3282 { PINMUX_CFG_REG("IP0SR8", 0xE6068060, 32, 4, GROUP(
3292 { PINMUX_CFG_REG_VAR("IP1SR8", 0xE6068064, 32,
3293 GROUP(-8, 4, 4, 4, 4, 4, 4),
3295 /* IP1SR8_31_24 RESERVED */
3307 #define FM(x) FN_##x,
3308 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE6060100, 32,
3309 GROUP(-12, 1, 1, -2, 1, 1, -1, 1, -2, 1, 1, -2, 1,
3312 /* RESERVED 31-20 */
3315 /* RESERVED 17-16 */
3320 /* RESERVED 11-10 */
3331 { PINMUX_CFG_REG_VAR("MOD_SEL5", 0xE6060900, 32,
3332 GROUP(-12, 1, -2, 1, 1, -2, 1, 1, -2, 1, -1,
3333 1, 1, -2, 1, -1, 1),
3335 /* RESERVED 31-20 */
3337 /* RESERVED 18-17 */
3340 /* RESERVED 14-13 */
3353 { PINMUX_CFG_REG_VAR("MOD_SEL6", 0xE6061100, 32,
3354 GROUP(-13, 1, -1, 1, -2, 1, 1,
3355 -1, 1, -2, 1, 1, 1, -2, 1, 1, -1),
3357 /* RESERVED 31-19 */
3361 /* RESERVED 15-14 */
3376 { PINMUX_CFG_REG_VAR("MOD_SEL7", 0xE6061900, 32,
3377 GROUP(-15, 1, 1, -1, 1, -1, 1, 1, -2, 1, 1,
3380 /* RESERVED 31-17 */
3397 { PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,
3398 GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3400 /* RESERVED 31-12 */
3417 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3418 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) {
3419 { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */
3420 { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */
3421 { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */
3422 { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */
3423 { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */
3424 { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */
3425 { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */
3426 { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */
3428 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) {
3429 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */
3430 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */
3431 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */
3432 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */
3433 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */
3434 { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */
3435 { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */
3436 { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */
3438 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) {
3439 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */
3440 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */
3441 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */
3443 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) {
3444 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */
3445 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */
3446 { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */
3447 { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */
3448 { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */
3449 { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */
3450 { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */
3451 { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */
3453 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) {
3454 { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */
3455 { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */
3456 { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */
3457 { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */
3458 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */
3459 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */
3460 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */
3461 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */
3463 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) {
3464 { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */
3465 { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */
3466 { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */
3467 { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */
3468 { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */
3469 { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */
3470 { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */
3471 { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */
3473 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) {
3474 { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */
3475 { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */
3476 { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */
3477 { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */
3478 { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */
3480 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) {
3481 { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */
3482 { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */
3483 { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */
3484 { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */
3485 { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */
3486 { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */
3487 { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */
3488 { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */
3490 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) {
3491 { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */
3492 { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */
3493 { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */
3494 { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */
3495 { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */
3496 { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */
3497 { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */
3498 { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */
3500 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) {
3501 { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD7_RX */
3502 { RCAR_GP_PIN(2, 18), 8, 3 }, /* CANFD7_TX */
3503 { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD4_RX */
3504 { RCAR_GP_PIN(2, 16), 0, 3 }, /* CANFD4_TX */
3506 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) {
3507 { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */
3508 { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */
3509 { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */
3510 { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */
3511 { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */
3512 { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */
3513 { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */
3514 { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */
3516 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) {
3517 { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */
3518 { RCAR_GP_PIN(3, 14), 24, 2 }, /* IPC_CLKOUT */
3519 { RCAR_GP_PIN(3, 13), 20, 2 }, /* IPC_CLKIN */
3520 { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */
3521 { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */
3522 { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */
3523 { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/
3524 { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */
3526 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) {
3527 { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */
3528 { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */
3529 { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */
3530 { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */
3531 { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */
3532 { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */
3533 { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */
3534 { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */
3536 { PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) {
3537 { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */
3538 { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */
3539 { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */
3540 { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */
3541 { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */
3542 { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */
3544 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) {
3545 { RCAR_GP_PIN(4, 7), 28, 3 }, /* TSN0_RX_CTL */
3546 { RCAR_GP_PIN(4, 6), 24, 3 }, /* TSN0_AVTP_CAPTURE */
3547 { RCAR_GP_PIN(4, 5), 20, 3 }, /* TSN0_AVTP_MATCH */
3548 { RCAR_GP_PIN(4, 4), 16, 3 }, /* TSN0_LINK */
3549 { RCAR_GP_PIN(4, 3), 12, 3 }, /* TSN0_PHY_INT */
3550 { RCAR_GP_PIN(4, 2), 8, 3 }, /* TSN0_AVTP_PPS1 */
3551 { RCAR_GP_PIN(4, 1), 4, 3 }, /* TSN0_MDC */
3552 { RCAR_GP_PIN(4, 0), 0, 3 }, /* TSN0_MDIO */
3554 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) {
3555 { RCAR_GP_PIN(4, 15), 28, 3 }, /* TSN0_TD0 */
3556 { RCAR_GP_PIN(4, 14), 24, 3 }, /* TSN0_TD1 */
3557 { RCAR_GP_PIN(4, 13), 20, 3 }, /* TSN0_RD1 */
3558 { RCAR_GP_PIN(4, 12), 16, 3 }, /* TSN0_TXC */
3559 { RCAR_GP_PIN(4, 11), 12, 3 }, /* TSN0_RXC */
3560 { RCAR_GP_PIN(4, 10), 8, 3 }, /* TSN0_RD0 */
3561 { RCAR_GP_PIN(4, 9), 4, 3 }, /* TSN0_TX_CTL */
3562 { RCAR_GP_PIN(4, 8), 0, 3 }, /* TSN0_AVTP_PPS0 */
3564 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) {
3565 { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */
3566 { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */
3567 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
3568 { RCAR_GP_PIN(4, 20), 16, 3 }, /* TSN0_TXCREFCLK */
3569 { RCAR_GP_PIN(4, 19), 12, 3 }, /* TSN0_TD2 */
3570 { RCAR_GP_PIN(4, 18), 8, 3 }, /* TSN0_TD3 */
3571 { RCAR_GP_PIN(4, 17), 4, 3 }, /* TSN0_RD2 */
3572 { RCAR_GP_PIN(4, 16), 0, 3 }, /* TSN0_RD3 */
3574 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) {
3575 { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */
3577 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) {
3578 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */
3579 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */
3580 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */
3581 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */
3582 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */
3583 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */
3584 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */
3585 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */
3587 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) {
3588 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */
3589 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */
3590 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */
3591 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */
3592 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */
3593 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */
3594 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */
3595 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */
3597 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) {
3598 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */
3599 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */
3600 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */
3601 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */
3602 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */
3604 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) {
3605 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */
3606 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */
3607 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */
3608 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */
3609 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */
3610 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */
3611 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */
3612 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */
3614 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) {
3615 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */
3616 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */
3617 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */
3618 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */
3619 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */
3620 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */
3621 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */
3622 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */
3624 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) {
3625 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */
3626 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */
3627 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */
3628 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */
3629 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */
3631 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) {
3632 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */
3633 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */
3634 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */
3635 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */
3636 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */
3637 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */
3638 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */
3639 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */
3641 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) {
3642 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */
3643 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */
3644 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */
3645 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */
3646 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */
3647 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */
3648 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */
3649 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */
3651 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) {
3652 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */
3653 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */
3654 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */
3655 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */
3656 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */
3658 { PINMUX_DRIVE_REG("DRV0CTRL8", 0xE6068080) {
3659 { RCAR_GP_PIN(8, 7), 28, 3 }, /* SDA3 */
3660 { RCAR_GP_PIN(8, 6), 24, 3 }, /* SCL3 */
3661 { RCAR_GP_PIN(8, 5), 20, 3 }, /* SDA2 */
3662 { RCAR_GP_PIN(8, 4), 16, 3 }, /* SCL2 */
3663 { RCAR_GP_PIN(8, 3), 12, 3 }, /* SDA1 */
3664 { RCAR_GP_PIN(8, 2), 8, 3 }, /* SCL1 */
3665 { RCAR_GP_PIN(8, 1), 4, 3 }, /* SDA0 */
3666 { RCAR_GP_PIN(8, 0), 0, 3 }, /* SCL0 */
3668 { PINMUX_DRIVE_REG("DRV1CTRL8", 0xE6068084) {
3669 { RCAR_GP_PIN(8, 13), 20, 3 }, /* GP8_13 */
3670 { RCAR_GP_PIN(8, 12), 16, 3 }, /* GP8_12 */
3671 { RCAR_GP_PIN(8, 11), 12, 3 }, /* SDA5 */
3672 { RCAR_GP_PIN(8, 10), 8, 3 }, /* SCL5 */
3673 { RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */
3674 { RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */
3690 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
3691 [POC0] = { 0xE60500A0, },
3692 [POC1] = { 0xE60508A0, },
3693 [POC3] = { 0xE60588A0, },
3694 [POC4] = { 0xE60600A0, },
3695 [POC5] = { 0xE60608A0, },
3696 [POC6] = { 0xE60610A0, },
3697 [POC7] = { 0xE60618A0, },
3698 [POC8] = { 0xE60680A0, },
3702 static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
3704 int bit = pin & 0x1f;
3706 *pocctrl = pinmux_ioctrl_regs[POC0].reg;
3707 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 18))
3710 *pocctrl = pinmux_ioctrl_regs[POC1].reg;
3711 if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 22))
3714 *pocctrl = pinmux_ioctrl_regs[POC3].reg;
3715 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 12))
3718 *pocctrl = pinmux_ioctrl_regs[POC8].reg;
3719 if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 13))
3725 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
3726 { PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) {
3727 [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */
3728 [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */
3729 [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */
3730 [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */
3731 [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */
3732 [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */
3733 [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */
3734 [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */
3735 [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */
3736 [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */
3737 [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */
3738 [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */
3739 [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */
3740 [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */
3741 [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */
3742 [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */
3743 [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */
3744 [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */
3745 [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */
3746 [19] = SH_PFC_PIN_NONE,
3747 [20] = SH_PFC_PIN_NONE,
3748 [21] = SH_PFC_PIN_NONE,
3749 [22] = SH_PFC_PIN_NONE,
3750 [23] = SH_PFC_PIN_NONE,
3751 [24] = SH_PFC_PIN_NONE,
3752 [25] = SH_PFC_PIN_NONE,
3753 [26] = SH_PFC_PIN_NONE,
3754 [27] = SH_PFC_PIN_NONE,
3755 [28] = SH_PFC_PIN_NONE,
3756 [29] = SH_PFC_PIN_NONE,
3757 [30] = SH_PFC_PIN_NONE,
3758 [31] = SH_PFC_PIN_NONE,
3760 { PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) {
3761 [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */
3762 [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */
3763 [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */
3764 [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */
3765 [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */
3766 [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */
3767 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */
3768 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */
3769 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */
3770 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */
3771 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */
3772 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */
3773 [12] = RCAR_GP_PIN(1, 12), /* HTX0 */
3774 [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */
3775 [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */
3776 [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */
3777 [16] = RCAR_GP_PIN(1, 16), /* HRX0 */
3778 [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */
3779 [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */
3780 [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */
3781 [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */
3782 [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */
3783 [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */
3784 [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */
3785 [24] = RCAR_GP_PIN(1, 24), /* HRX3 */
3786 [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */
3787 [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */
3788 [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */
3789 [28] = RCAR_GP_PIN(1, 28), /* HTX3 */
3790 [29] = SH_PFC_PIN_NONE,
3791 [30] = SH_PFC_PIN_NONE,
3792 [31] = SH_PFC_PIN_NONE,
3794 { PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) {
3795 [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */
3796 [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */
3797 [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */
3798 [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */
3799 [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */
3800 [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */
3801 [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */
3802 [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */
3803 [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */
3804 [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */
3805 [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */
3806 [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */
3807 [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */
3808 [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */
3809 [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */
3810 [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */
3811 [16] = RCAR_GP_PIN(2, 16), /* CANFD4_TX */
3812 [17] = RCAR_GP_PIN(2, 17), /* CANFD4_RX */
3813 [18] = RCAR_GP_PIN(2, 18), /* CANFD7_TX */
3814 [19] = RCAR_GP_PIN(2, 19), /* CANFD7_RX */
3815 [20] = SH_PFC_PIN_NONE,
3816 [21] = SH_PFC_PIN_NONE,
3817 [22] = SH_PFC_PIN_NONE,
3818 [23] = SH_PFC_PIN_NONE,
3819 [24] = SH_PFC_PIN_NONE,
3820 [25] = SH_PFC_PIN_NONE,
3821 [26] = SH_PFC_PIN_NONE,
3822 [27] = SH_PFC_PIN_NONE,
3823 [28] = SH_PFC_PIN_NONE,
3824 [29] = SH_PFC_PIN_NONE,
3825 [30] = SH_PFC_PIN_NONE,
3826 [31] = SH_PFC_PIN_NONE,
3828 { PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) {
3829 [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */
3830 [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */
3831 [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */
3832 [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */
3833 [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */
3834 [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */
3835 [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */
3836 [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */
3837 [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */
3838 [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */
3839 [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */
3840 [11] = RCAR_GP_PIN(3, 11), /* SD_CD */
3841 [12] = RCAR_GP_PIN(3, 12), /* SD_WP */
3842 [13] = RCAR_GP_PIN(3, 13), /* IPC_CLKIN */
3843 [14] = RCAR_GP_PIN(3, 14), /* IPC_CLKOUT */
3844 [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */
3845 [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */
3846 [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */
3847 [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */
3848 [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */
3849 [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */
3850 [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */
3851 [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */
3852 [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */
3853 [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */
3854 [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */
3855 [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */
3856 [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */
3857 [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */
3858 [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */
3859 [30] = SH_PFC_PIN_NONE,
3860 [31] = SH_PFC_PIN_NONE,
3862 { PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) {
3863 [ 0] = RCAR_GP_PIN(4, 0), /* TSN0_MDIO */
3864 [ 1] = RCAR_GP_PIN(4, 1), /* TSN0_MDC */
3865 [ 2] = RCAR_GP_PIN(4, 2), /* TSN0_AVTP_PPS1 */
3866 [ 3] = RCAR_GP_PIN(4, 3), /* TSN0_PHY_INT */
3867 [ 4] = RCAR_GP_PIN(4, 4), /* TSN0_LINK */
3868 [ 5] = RCAR_GP_PIN(4, 5), /* TSN0_AVTP_MATCH */
3869 [ 6] = RCAR_GP_PIN(4, 6), /* TSN0_AVTP_CAPTURE */
3870 [ 7] = RCAR_GP_PIN(4, 7), /* TSN0_RX_CTL */
3871 [ 8] = RCAR_GP_PIN(4, 8), /* TSN0_AVTP_PPS0 */
3872 [ 9] = RCAR_GP_PIN(4, 9), /* TSN0_TX_CTL */
3873 [10] = RCAR_GP_PIN(4, 10), /* TSN0_RD0 */
3874 [11] = RCAR_GP_PIN(4, 11), /* TSN0_RXC */
3875 [12] = RCAR_GP_PIN(4, 12), /* TSN0_TXC */
3876 [13] = RCAR_GP_PIN(4, 13), /* TSN0_RD1 */
3877 [14] = RCAR_GP_PIN(4, 14), /* TSN0_TD1 */
3878 [15] = RCAR_GP_PIN(4, 15), /* TSN0_TD0 */
3879 [16] = RCAR_GP_PIN(4, 16), /* TSN0_RD3 */
3880 [17] = RCAR_GP_PIN(4, 17), /* TSN0_RD2 */
3881 [18] = RCAR_GP_PIN(4, 18), /* TSN0_TD3 */
3882 [19] = RCAR_GP_PIN(4, 19), /* TSN0_TD2 */
3883 [20] = RCAR_GP_PIN(4, 20), /* TSN0_TXCREFCLK */
3884 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
3885 [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */
3886 [23] = RCAR_GP_PIN(4, 23), /* AVS0 */
3887 [24] = RCAR_GP_PIN(4, 24), /* AVS1 */
3888 [25] = SH_PFC_PIN_NONE,
3889 [26] = SH_PFC_PIN_NONE,
3890 [27] = SH_PFC_PIN_NONE,
3891 [28] = SH_PFC_PIN_NONE,
3892 [29] = SH_PFC_PIN_NONE,
3893 [30] = SH_PFC_PIN_NONE,
3894 [31] = SH_PFC_PIN_NONE,
3896 { PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) {
3897 [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */
3898 [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */
3899 [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */
3900 [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */
3901 [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */
3902 [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */
3903 [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */
3904 [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */
3905 [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */
3906 [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */
3907 [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */
3908 [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */
3909 [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */
3910 [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */
3911 [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */
3912 [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */
3913 [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */
3914 [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */
3915 [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */
3916 [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */
3917 [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */
3918 [21] = SH_PFC_PIN_NONE,
3919 [22] = SH_PFC_PIN_NONE,
3920 [23] = SH_PFC_PIN_NONE,
3921 [24] = SH_PFC_PIN_NONE,
3922 [25] = SH_PFC_PIN_NONE,
3923 [26] = SH_PFC_PIN_NONE,
3924 [27] = SH_PFC_PIN_NONE,
3925 [28] = SH_PFC_PIN_NONE,
3926 [29] = SH_PFC_PIN_NONE,
3927 [30] = SH_PFC_PIN_NONE,
3928 [31] = SH_PFC_PIN_NONE,
3930 { PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) {
3931 [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */
3932 [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */
3933 [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */
3934 [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */
3935 [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */
3936 [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */
3937 [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */
3938 [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */
3939 [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */
3940 [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */
3941 [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */
3942 [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */
3943 [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */
3944 [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */
3945 [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/
3946 [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */
3947 [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */
3948 [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */
3949 [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */
3950 [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */
3951 [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */
3952 [21] = SH_PFC_PIN_NONE,
3953 [22] = SH_PFC_PIN_NONE,
3954 [23] = SH_PFC_PIN_NONE,
3955 [24] = SH_PFC_PIN_NONE,
3956 [25] = SH_PFC_PIN_NONE,
3957 [26] = SH_PFC_PIN_NONE,
3958 [27] = SH_PFC_PIN_NONE,
3959 [28] = SH_PFC_PIN_NONE,
3960 [29] = SH_PFC_PIN_NONE,
3961 [30] = SH_PFC_PIN_NONE,
3962 [31] = SH_PFC_PIN_NONE,
3964 { PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) {
3965 [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */
3966 [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */
3967 [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */
3968 [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */
3969 [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */
3970 [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */
3971 [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */
3972 [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */
3973 [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */
3974 [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */
3975 [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */
3976 [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */
3977 [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */
3978 [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */
3979 [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */
3980 [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */
3981 [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */
3982 [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */
3983 [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */
3984 [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */
3985 [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */
3986 [21] = SH_PFC_PIN_NONE,
3987 [22] = SH_PFC_PIN_NONE,
3988 [23] = SH_PFC_PIN_NONE,
3989 [24] = SH_PFC_PIN_NONE,
3990 [25] = SH_PFC_PIN_NONE,
3991 [26] = SH_PFC_PIN_NONE,
3992 [27] = SH_PFC_PIN_NONE,
3993 [28] = SH_PFC_PIN_NONE,
3994 [29] = SH_PFC_PIN_NONE,
3995 [30] = SH_PFC_PIN_NONE,
3996 [31] = SH_PFC_PIN_NONE,
3998 { PINMUX_BIAS_REG("PUEN8", 0xE60680C0, "PUD8", 0xE60680E0) {
3999 [ 0] = RCAR_GP_PIN(8, 0), /* SCL0 */
4000 [ 1] = RCAR_GP_PIN(8, 1), /* SDA0 */
4001 [ 2] = RCAR_GP_PIN(8, 2), /* SCL1 */
4002 [ 3] = RCAR_GP_PIN(8, 3), /* SDA1 */
4003 [ 4] = RCAR_GP_PIN(8, 4), /* SCL2 */
4004 [ 5] = RCAR_GP_PIN(8, 5), /* SDA2 */
4005 [ 6] = RCAR_GP_PIN(8, 6), /* SCL3 */
4006 [ 7] = RCAR_GP_PIN(8, 7), /* SDA3 */
4007 [ 8] = RCAR_GP_PIN(8, 8), /* SCL4 */
4008 [ 9] = RCAR_GP_PIN(8, 9), /* SDA4 */
4009 [10] = RCAR_GP_PIN(8, 10), /* SCL5 */
4010 [11] = RCAR_GP_PIN(8, 11), /* SDA5 */
4011 [12] = RCAR_GP_PIN(8, 12), /* GP8_12 */
4012 [13] = RCAR_GP_PIN(8, 13), /* GP8_13 */
4013 [14] = SH_PFC_PIN_NONE,
4014 [15] = SH_PFC_PIN_NONE,
4015 [16] = SH_PFC_PIN_NONE,
4016 [17] = SH_PFC_PIN_NONE,
4017 [18] = SH_PFC_PIN_NONE,
4018 [19] = SH_PFC_PIN_NONE,
4019 [20] = SH_PFC_PIN_NONE,
4020 [21] = SH_PFC_PIN_NONE,
4021 [22] = SH_PFC_PIN_NONE,
4022 [23] = SH_PFC_PIN_NONE,
4023 [24] = SH_PFC_PIN_NONE,
4024 [25] = SH_PFC_PIN_NONE,
4025 [26] = SH_PFC_PIN_NONE,
4026 [27] = SH_PFC_PIN_NONE,
4027 [28] = SH_PFC_PIN_NONE,
4028 [29] = SH_PFC_PIN_NONE,
4029 [30] = SH_PFC_PIN_NONE,
4030 [31] = SH_PFC_PIN_NONE,
4035 static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {
4036 .pin_to_pocctrl = r8a779g0_pin_to_pocctrl,
4037 .get_bias = rcar_pinmux_get_bias,
4038 .set_bias = rcar_pinmux_set_bias,
4041 const struct sh_pfc_soc_info r8a779g0_pinmux_info = {
4042 .name = "r8a779g0_pfc",
4043 .ops = &r8a779g0_pin_ops,
4044 .unlock_reg = 0x1ff, /* PMMRn mask */
4046 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4048 .pins = pinmux_pins,
4049 .nr_pins = ARRAY_SIZE(pinmux_pins),
4050 .groups = pinmux_groups,
4051 .nr_groups = ARRAY_SIZE(pinmux_groups),
4052 .functions = pinmux_functions,
4053 .nr_functions = ARRAY_SIZE(pinmux_functions),
4055 .cfg_regs = pinmux_config_regs,
4056 .drive_regs = pinmux_drive_regs,
4057 .bias_regs = pinmux_bias_regs,
4058 .ioctrl_regs = pinmux_ioctrl_regs,
4060 .pinmux_data = pinmux_data,
4061 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
projects / platform / kernel / linux-starfive.git / blob