1 // SPDX-License-Identifier: GPL-2.0
3 * R8A779A0 processor support - PFC hardware block.
5 * Copyright (C) 2021 Renesas Electronics Corp.
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
10 #include <linux/errno.h>
12 #include <linux/kernel.h>
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
18 #define CPU_ALL_GP(fn, sfx) \
19 PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
20 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_20(2, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
23 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(3, 16, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 17, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 18, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 19, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 20, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 21, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 22, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 23, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 24, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_1(3, 25, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_1(3, 26, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_1(3, 27, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_1(3, 28, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_1(3, 29, fn, sfx, CFG_FLAGS), \
40 PORT_GP_CFG_25(4, fn, sfx, CFG_FLAGS), \
41 PORT_GP_CFG_21(5, fn, sfx, CFG_FLAGS), \
42 PORT_GP_CFG_21(6, fn, sfx, CFG_FLAGS), \
43 PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \
44 PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
46 #define CPU_ALL_NOGP(fn) \
47 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
48 PIN_NOGP_CFG(PRESETOUT0_N, "PRESETOUT0#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
49 PIN_NOGP_CFG(PRESETOUT1_N, "PRESETOUT1#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
50 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
51 PIN_NOGP_CFG(DCUTRST0_N, "DCUTRST0#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
52 PIN_NOGP_CFG(DCUTCK0, "DCUTCK0", fn, SH_PFC_PIN_CFG_PULL_UP), \
53 PIN_NOGP_CFG(DCUTMS0, "DCUTMS0", fn, SH_PFC_PIN_CFG_PULL_UP), \
54 PIN_NOGP_CFG(DCUTDI0, "DCUTDI0", fn, SH_PFC_PIN_CFG_PULL_UP), \
55 PIN_NOGP_CFG(DCUTRST1_N, "DCUTRST1#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
56 PIN_NOGP_CFG(DCUTCK1, "DCUTCK1", fn, SH_PFC_PIN_CFG_PULL_UP), \
57 PIN_NOGP_CFG(DCUTMS1, "DCUTMS1", fn, SH_PFC_PIN_CFG_PULL_UP), \
58 PIN_NOGP_CFG(DCUTDI1, "DCUTDI1", fn, SH_PFC_PIN_CFG_PULL_UP), \
59 PIN_NOGP_CFG(EVTI_N, "EVTI#", fn, SH_PFC_PIN_CFG_PULL_UP), \
60 PIN_NOGP_CFG(MSYN_N, "MSYN#", fn, SH_PFC_PIN_CFG_PULL_UP)
63 #define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)
64 #define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)
65 #define GPSR0_16 F_(MSIOF2_TXD, IP2SR0_3_0)
66 #define GPSR0_15 F_(MSIOF2_SYNC, IP1SR0_31_28)
67 #define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24)
68 #define GPSR0_13 F_(MSIOF2_SS2, IP1SR0_23_20)
69 #define GPSR0_12 F_(MSIOF5_RXD, IP1SR0_19_16)
70 #define GPSR0_11 F_(MSIOF5_SCK, IP1SR0_15_12)
71 #define GPSR0_10 F_(MSIOF5_TXD, IP1SR0_11_8)
72 #define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4)
73 #define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0)
74 #define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28)
75 #define GPSR0_6 F_(IRQ0, IP0SR0_27_24)
76 #define GPSR0_5 F_(IRQ1, IP0SR0_23_20)
77 #define GPSR0_4 F_(IRQ2, IP0SR0_19_16)
78 #define GPSR0_3 F_(IRQ3, IP0SR0_15_12)
79 #define GPSR0_2 F_(GP0_02, IP0SR0_11_8)
80 #define GPSR0_1 F_(GP0_01, IP0SR0_7_4)
81 #define GPSR0_0 F_(GP0_00, IP0SR0_3_0)
84 #define GPSR1_28 F_(HTX3, IP3SR1_19_16)
85 #define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12)
86 #define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8)
87 #define GPSR1_25 F_(HSCK3, IP3SR1_7_4)
88 #define GPSR1_24 F_(HRX3, IP3SR1_3_0)
89 #define GPSR1_23 F_(GP1_23, IP2SR1_31_28)
90 #define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24)
91 #define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20)
92 #define GPSR1_20 F_(SSI_SD, IP2SR1_19_16)
93 #define GPSR1_19 F_(SSI_WS, IP2SR1_15_12)
94 #define GPSR1_18 F_(SSI_SCK, IP2SR1_11_8)
95 #define GPSR1_17 F_(SCIF_CLK, IP2SR1_7_4)
96 #define GPSR1_16 F_(HRX0, IP2SR1_3_0)
97 #define GPSR1_15 F_(HSCK0, IP1SR1_31_28)
98 #define GPSR1_14 F_(HRTS0_N, IP1SR1_27_24)
99 #define GPSR1_13 F_(HCTS0_N, IP1SR1_23_20)
100 #define GPSR1_12 F_(HTX0, IP1SR1_19_16)
101 #define GPSR1_11 F_(MSIOF0_RXD, IP1SR1_15_12)
102 #define GPSR1_10 F_(MSIOF0_SCK, IP1SR1_11_8)
103 #define GPSR1_9 F_(MSIOF0_TXD, IP1SR1_7_4)
104 #define GPSR1_8 F_(MSIOF0_SYNC, IP1SR1_3_0)
105 #define GPSR1_7 F_(MSIOF0_SS1, IP0SR1_31_28)
106 #define GPSR1_6 F_(MSIOF0_SS2, IP0SR1_27_24)
107 #define GPSR1_5 F_(MSIOF1_RXD, IP0SR1_23_20)
108 #define GPSR1_4 F_(MSIOF1_TXD, IP0SR1_19_16)
109 #define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12)
110 #define GPSR1_2 F_(MSIOF1_SYNC, IP0SR1_11_8)
111 #define GPSR1_1 F_(MSIOF1_SS1, IP0SR1_7_4)
112 #define GPSR1_0 F_(MSIOF1_SS2, IP0SR1_3_0)
115 #define GPSR2_19 F_(CANFD7_RX, IP2SR2_15_12)
116 #define GPSR2_18 F_(CANFD7_TX, IP2SR2_11_8)
117 #define GPSR2_17 F_(CANFD4_RX, IP2SR2_7_4)
118 #define GPSR2_16 F_(CANFD4_TX, IP2SR2_3_0)
119 #define GPSR2_15 F_(CANFD3_RX, IP1SR2_31_28)
120 #define GPSR2_14 F_(CANFD3_TX, IP1SR2_27_24)
121 #define GPSR2_13 F_(CANFD2_RX, IP1SR2_23_20)
122 #define GPSR2_12 F_(CANFD2_TX, IP1SR2_19_16)
123 #define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12)
124 #define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8)
125 #define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4)
126 #define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0)
127 #define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28)
128 #define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24)
129 #define GPSR2_5 F_(FXR_TXENB_N, IP0SR2_23_20)
130 #define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16)
131 #define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12)
132 #define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8)
133 #define GPSR2_1 F_(FXR_TXENA_N, IP0SR2_7_4)
134 #define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0)
137 #define GPSR3_29 F_(RPC_INT_N, IP3SR3_23_20)
138 #define GPSR3_28 F_(RPC_WP_N, IP3SR3_19_16)
139 #define GPSR3_27 F_(RPC_RESET_N, IP3SR3_15_12)
140 #define GPSR3_26 F_(QSPI1_IO3, IP3SR3_11_8)
141 #define GPSR3_25 F_(QSPI1_SSL, IP3SR3_7_4)
142 #define GPSR3_24 F_(QSPI1_IO2, IP3SR3_3_0)
143 #define GPSR3_23 F_(QSPI1_MISO_IO1, IP2SR3_31_28)
144 #define GPSR3_22 F_(QSPI1_SPCLK, IP2SR3_27_24)
145 #define GPSR3_21 F_(QSPI1_MOSI_IO0, IP2SR3_23_20)
146 #define GPSR3_20 F_(QSPI0_SPCLK, IP2SR3_19_16)
147 #define GPSR3_19 F_(QSPI0_MOSI_IO0, IP2SR3_15_12)
148 #define GPSR3_18 F_(QSPI0_MISO_IO1, IP2SR3_11_8)
149 #define GPSR3_17 F_(QSPI0_IO2, IP2SR3_7_4)
150 #define GPSR3_16 F_(QSPI0_IO3, IP2SR3_3_0)
151 #define GPSR3_15 F_(QSPI0_SSL, IP1SR3_31_28)
152 #define GPSR3_14 F_(IPC_CLKOUT, IP1SR3_27_24)
153 #define GPSR3_13 F_(IPC_CLKIN, IP1SR3_23_20)
154 #define GPSR3_12 F_(SD_WP, IP1SR3_19_16)
155 #define GPSR3_11 F_(SD_CD, IP1SR3_15_12)
156 #define GPSR3_10 F_(MMC_SD_CMD, IP1SR3_11_8)
157 #define GPSR3_9 F_(MMC_D6, IP1SR3_7_4)
158 #define GPSR3_8 F_(MMC_D7, IP1SR3_3_0)
159 #define GPSR3_7 F_(MMC_D4, IP0SR3_31_28)
160 #define GPSR3_6 F_(MMC_D5, IP0SR3_27_24)
161 #define GPSR3_5 F_(MMC_SD_D3, IP0SR3_23_20)
162 #define GPSR3_4 F_(MMC_DS, IP0SR3_19_16)
163 #define GPSR3_3 F_(MMC_SD_CLK, IP0SR3_15_12)
164 #define GPSR3_2 F_(MMC_SD_D2, IP0SR3_11_8)
165 #define GPSR3_1 F_(MMC_SD_D0, IP0SR3_7_4)
166 #define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0)
169 #define GPSR4_24 FM(AVS1)
170 #define GPSR4_23 FM(AVS0)
171 #define GPSR4_22 FM(PCIE1_CLKREQ_N)
172 #define GPSR4_21 FM(PCIE0_CLKREQ_N)
173 #define GPSR4_20 FM(TSN0_TXCREFCLK)
174 #define GPSR4_19 FM(TSN0_TD2)
175 #define GPSR4_18 FM(TSN0_TD3)
176 #define GPSR4_17 FM(TSN0_RD2)
177 #define GPSR4_16 FM(TSN0_RD3)
178 #define GPSR4_15 FM(TSN0_TD0)
179 #define GPSR4_14 FM(TSN0_TD1)
180 #define GPSR4_13 FM(TSN0_RD1)
181 #define GPSR4_12 FM(TSN0_TXC)
182 #define GPSR4_11 FM(TSN0_RXC)
183 #define GPSR4_10 FM(TSN0_RD0)
184 #define GPSR4_9 FM(TSN0_TX_CTL)
185 #define GPSR4_8 FM(TSN0_AVTP_PPS0)
186 #define GPSR4_7 FM(TSN0_RX_CTL)
187 #define GPSR4_6 FM(TSN0_AVTP_CAPTURE)
188 #define GPSR4_5 FM(TSN0_AVTP_MATCH)
189 #define GPSR4_4 FM(TSN0_LINK)
190 #define GPSR4_3 FM(TSN0_PHY_INT)
191 #define GPSR4_2 FM(TSN0_AVTP_PPS1)
192 #define GPSR4_1 FM(TSN0_MDC)
193 #define GPSR4_0 FM(TSN0_MDIO)
196 #define GPSR5_20 FM(AVB2_RX_CTL)
197 #define GPSR5_19 FM(AVB2_TX_CTL)
198 #define GPSR5_18 FM(AVB2_RXC)
199 #define GPSR5_17 FM(AVB2_RD0)
200 #define GPSR5_16 FM(AVB2_TXC)
201 #define GPSR5_15 FM(AVB2_TD0)
202 #define GPSR5_14 FM(AVB2_RD1)
203 #define GPSR5_13 FM(AVB2_RD2)
204 #define GPSR5_12 FM(AVB2_TD1)
205 #define GPSR5_11 FM(AVB2_TD2)
206 #define GPSR5_10 FM(AVB2_MDIO)
207 #define GPSR5_9 FM(AVB2_RD3)
208 #define GPSR5_8 FM(AVB2_TD3)
209 #define GPSR5_7 FM(AVB2_TXCREFCLK)
210 #define GPSR5_6 FM(AVB2_MDC)
211 #define GPSR5_5 FM(AVB2_MAGIC)
212 #define GPSR5_4 FM(AVB2_PHY_INT)
213 #define GPSR5_3 FM(AVB2_LINK)
214 #define GPSR5_2 FM(AVB2_AVTP_MATCH)
215 #define GPSR5_1 FM(AVB2_AVTP_CAPTURE)
216 #define GPSR5_0 FM(AVB2_AVTP_PPS)
219 #define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)
220 #define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12)
221 #define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8)
222 #define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4)
223 #define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0)
224 #define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28)
225 #define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24)
226 #define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20)
227 #define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16)
228 #define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12)
229 #define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8)
230 #define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4)
231 #define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0)
232 #define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28)
233 #define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24)
234 #define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20)
235 #define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16)
236 #define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12)
237 #define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8)
238 #define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4)
239 #define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0)
242 #define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16)
243 #define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12)
244 #define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8)
245 #define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4)
246 #define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0)
247 #define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28)
248 #define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24)
249 #define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20)
250 #define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16)
251 #define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12)
252 #define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8)
253 #define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4)
254 #define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0)
255 #define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28)
256 #define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24)
257 #define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20)
258 #define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16)
259 #define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12)
260 #define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8)
261 #define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
262 #define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
265 #define GPSR8_13 F_(GP8_13, IP1SR8_23_20)
266 #define GPSR8_12 F_(GP8_12, IP1SR8_19_16)
267 #define GPSR8_11 F_(SDA5, IP1SR8_15_12)
268 #define GPSR8_10 F_(SCL5, IP1SR8_11_8)
269 #define GPSR8_9 F_(SDA4, IP1SR8_7_4)
270 #define GPSR8_8 F_(SCL4, IP1SR8_3_0)
271 #define GPSR8_7 F_(SDA3, IP0SR8_31_28)
272 #define GPSR8_6 F_(SCL3, IP0SR8_27_24)
273 #define GPSR8_5 F_(SDA2, IP0SR8_23_20)
274 #define GPSR8_4 F_(SCL2, IP0SR8_19_16)
275 #define GPSR8_3 F_(SDA1, IP0SR8_15_12)
276 #define GPSR8_2 F_(SCL1, IP0SR8_11_8)
277 #define GPSR8_1 F_(SDA0, IP0SR8_7_4)
278 #define GPSR8_0 F_(SCL0, IP0SR8_3_0)
281 /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
282 #define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
292 #define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 /* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
302 #define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP2SR0_15_12 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP2SR0_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP2SR0_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP2SR0_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP2SR0_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
313 #define IP0SR1_3_0 FM(MSIOF1_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP0SR1_7_4 FM(MSIOF1_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP0SR1_11_8 FM(MSIOF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP0SR1_15_12 FM(MSIOF1_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP0SR1_19_16 FM(MSIOF1_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP0SR1_27_24 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP0SR1_31_28 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
323 #define IP1SR1_3_0 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP1SR1_7_4 FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP1SR1_11_8 FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 /* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
333 #define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP2SR1_19_16 FM(SSI_SD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP2SR1_23_20 FM(AUDIO_CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
343 #define IP3SR1_3_0 FM(HRX3) FM(SCK3) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N) FM(MSIOF4_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N) FM(MSIOF4_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP3SR1_15_12 FM(HCTS3_N) FM(RX3) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP3SR1_19_16 FM(HTX3) FM(TX3) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP3SR1_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP3SR1_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP3SR1_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
354 #define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
364 #define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP1SR2_7_4 FM(CAN_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP1SR2_11_8 FM(CANFD0_TX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 /* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
374 #define IP2SR2_3_0 FM(CANFD4_TX) F_(0, 0) FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP2SR2_7_4 FM(CANFD4_RX) F_(0, 0) FM(PWM5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP2SR2_11_8 FM(CANFD7_TX) F_(0, 0) FM(PWM6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP2SR2_15_12 FM(CANFD7_RX) F_(0, 0) FM(PWM7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP2SR2_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP2SR2_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP2SR2_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP2SR2_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
385 #define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 /* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
395 #define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399 #define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 #define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402 #define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 /* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
405 #define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
406 #define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
407 #define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
408 #define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
409 #define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410 #define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
411 #define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
412 #define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
414 /* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
415 #define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
416 #define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
417 #define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
418 #define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
419 #define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
420 #define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
421 #define IP3SR3_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
422 #define IP3SR3_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
425 /* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
426 #define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
427 #define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
428 #define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
429 #define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
430 #define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
431 #define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
432 #define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
433 #define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
435 /* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
436 #define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
437 #define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
438 #define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
439 #define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
440 #define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
441 #define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
442 #define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
443 #define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
445 /* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
446 #define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
447 #define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
448 #define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
449 #define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
450 #define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
451 #define IP2SR6_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
452 #define IP2SR6_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
453 #define IP2SR6_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
456 /* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
457 #define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
458 #define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
459 #define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
460 #define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
461 #define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
462 #define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
463 #define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
464 #define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
466 /* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
467 #define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
468 #define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
469 #define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
470 #define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
471 #define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
472 #define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
473 #define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
474 #define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
476 /* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
477 #define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
478 #define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
479 #define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
480 #define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
481 #define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
482 #define IP2SR7_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
483 #define IP2SR7_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
484 #define IP2SR7_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
487 /* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
488 #define IP0SR8_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
489 #define IP0SR8_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
490 #define IP0SR8_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
491 #define IP0SR8_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
492 #define IP0SR8_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
493 #define IP0SR8_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
494 #define IP0SR8_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
495 #define IP0SR8_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
497 /* IP1SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
498 #define IP1SR8_3_0 FM(SCL4) FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
499 #define IP1SR8_7_4 FM(SDA4) FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
500 #define IP1SR8_11_8 FM(SCL5) FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
501 #define IP1SR8_15_12 FM(SDA5) FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
502 #define IP1SR8_19_16 F_(0, 0) FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
503 #define IP1SR8_23_20 F_(0, 0) FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
504 #define IP1SR8_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
505 #define IP1SR8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
508 #define PINMUX_GPSR \
514 GPSR1_24 GPSR3_24 GPSR4_24 \
515 GPSR1_23 GPSR3_23 GPSR4_23 \
516 GPSR1_22 GPSR3_22 GPSR4_22 \
517 GPSR1_21 GPSR3_21 GPSR4_21 \
518 GPSR1_20 GPSR3_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 \
519 GPSR1_19 GPSR2_19 GPSR3_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 \
520 GPSR0_18 GPSR1_18 GPSR2_18 GPSR3_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 \
521 GPSR0_17 GPSR1_17 GPSR2_17 GPSR3_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 \
522 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 \
523 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 \
524 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 \
525 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 \
526 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 \
527 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 \
528 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 \
529 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 \
530 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 \
531 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 \
532 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 \
533 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 \
534 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 \
535 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 \
536 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 \
537 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 \
538 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0
540 #define PINMUX_IPSR \
542 FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \
543 FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \
544 FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \
545 FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 FM(IP2SR0_15_12) IP2SR0_15_12 \
546 FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 FM(IP2SR0_19_16) IP2SR0_19_16 \
547 FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 FM(IP2SR0_23_20) IP2SR0_23_20 \
548 FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 FM(IP2SR0_27_24) IP2SR0_27_24 \
549 FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 FM(IP2SR0_31_28) IP2SR0_31_28 \
551 FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \
552 FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \
553 FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \
554 FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
555 FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
556 FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \
557 FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \
558 FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 FM(IP3SR1_31_28) IP3SR1_31_28 \
560 FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
561 FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
562 FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \
563 FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \
564 FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 FM(IP2SR2_19_16) IP2SR2_19_16 \
565 FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2SR2_23_20 \
566 FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \
567 FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \
569 FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 FM(IP2SR3_3_0) IP2SR3_3_0 FM(IP3SR3_3_0) IP3SR3_3_0 \
570 FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 FM(IP2SR3_7_4) IP2SR3_7_4 FM(IP3SR3_7_4) IP3SR3_7_4 \
571 FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 FM(IP2SR3_11_8) IP2SR3_11_8 FM(IP3SR3_11_8) IP3SR3_11_8 \
572 FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 FM(IP2SR3_15_12) IP2SR3_15_12 FM(IP3SR3_15_12) IP3SR3_15_12 \
573 FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 FM(IP2SR3_19_16) IP2SR3_19_16 FM(IP3SR3_19_16) IP3SR3_19_16 \
574 FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2SR3_23_20 FM(IP3SR3_23_20) IP3SR3_23_20 \
575 FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 FM(IP3SR3_27_24) IP3SR3_27_24 \
576 FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 FM(IP3SR3_31_28) IP3SR3_31_28 \
578 FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \
579 FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \
580 FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \
581 FM(IP0SR6_15_12) IP0SR6_15_12 FM(IP1SR6_15_12) IP1SR6_15_12 FM(IP2SR6_15_12) IP2SR6_15_12 \
582 FM(IP0SR6_19_16) IP0SR6_19_16 FM(IP1SR6_19_16) IP1SR6_19_16 FM(IP2SR6_19_16) IP2SR6_19_16 \
583 FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 FM(IP2SR6_23_20) IP2SR6_23_20 \
584 FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 FM(IP2SR6_27_24) IP2SR6_27_24 \
585 FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 FM(IP2SR6_31_28) IP2SR6_31_28 \
587 FM(IP0SR7_3_0) IP0SR7_3_0 FM(IP1SR7_3_0) IP1SR7_3_0 FM(IP2SR7_3_0) IP2SR7_3_0 \
588 FM(IP0SR7_7_4) IP0SR7_7_4 FM(IP1SR7_7_4) IP1SR7_7_4 FM(IP2SR7_7_4) IP2SR7_7_4 \
589 FM(IP0SR7_11_8) IP0SR7_11_8 FM(IP1SR7_11_8) IP1SR7_11_8 FM(IP2SR7_11_8) IP2SR7_11_8 \
590 FM(IP0SR7_15_12) IP0SR7_15_12 FM(IP1SR7_15_12) IP1SR7_15_12 FM(IP2SR7_15_12) IP2SR7_15_12 \
591 FM(IP0SR7_19_16) IP0SR7_19_16 FM(IP1SR7_19_16) IP1SR7_19_16 FM(IP2SR7_19_16) IP2SR7_19_16 \
592 FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 FM(IP2SR7_23_20) IP2SR7_23_20 \
593 FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 FM(IP2SR7_27_24) IP2SR7_27_24 \
594 FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 FM(IP2SR7_31_28) IP2SR7_31_28 \
596 FM(IP0SR8_3_0) IP0SR8_3_0 FM(IP1SR8_3_0) IP1SR8_3_0 \
597 FM(IP0SR8_7_4) IP0SR8_7_4 FM(IP1SR8_7_4) IP1SR8_7_4 \
598 FM(IP0SR8_11_8) IP0SR8_11_8 FM(IP1SR8_11_8) IP1SR8_11_8 \
599 FM(IP0SR8_15_12) IP0SR8_15_12 FM(IP1SR8_15_12) IP1SR8_15_12 \
600 FM(IP0SR8_19_16) IP0SR8_19_16 FM(IP1SR8_19_16) IP1SR8_19_16 \
601 FM(IP0SR8_23_20) IP0SR8_23_20 FM(IP1SR8_23_20) IP1SR8_23_20 \
602 FM(IP0SR8_27_24) IP0SR8_27_24 FM(IP1SR8_27_24) IP1SR8_27_24 \
603 FM(IP0SR8_31_28) IP0SR8_31_28 FM(IP1SR8_31_28) IP1SR8_31_28
605 /* MOD_SEL4 */ /* 0 */ /* 1 */
606 #define MOD_SEL4_19 FM(SEL_TSN0_TD2_0) FM(SEL_TSN0_TD2_1)
607 #define MOD_SEL4_18 FM(SEL_TSN0_TD3_0) FM(SEL_TSN0_TD3_1)
608 #define MOD_SEL4_17 F_(0, 0) F_(0, 0)
609 #define MOD_SEL4_16 F_(0, 0) F_(0, 0)
610 #define MOD_SEL4_15 FM(SEL_TSN0_TD0_0) FM(SEL_TSN0_TD0_1)
611 #define MOD_SEL4_14 FM(SEL_TSN0_TD1_0) FM(SEL_TSN0_TD1_1)
612 #define MOD_SEL4_13 F_(0, 0) F_(0, 0)
613 #define MOD_SEL4_12 FM(SEL_TSN0_TXC_0) FM(SEL_TSN0_TXC_1)
614 #define MOD_SEL4_11 F_(0, 0) F_(0, 0)
615 #define MOD_SEL4_10 F_(0, 0) F_(0, 0)
616 #define MOD_SEL4_9 FM(SEL_TSN0_TX_CTL_0) FM(SEL_TSN0_TX_CTL_1)
617 #define MOD_SEL4_8 FM(SEL_TSN0_AVTP_PPS0_0) FM(SEL_TSN0_AVTP_PPS0_1)
618 #define MOD_SEL4_7 F_(0, 0) F_(0, 0)
619 #define MOD_SEL4_6 F_(0, 0) F_(0, 0)
620 #define MOD_SEL4_5 FM(SEL_TSN0_AVTP_MATCH_0) FM(SEL_TSN0_AVTP_MATCH_1)
621 #define MOD_SEL4_4 F_(0, 0) F_(0, 0)
622 #define MOD_SEL4_3 F_(0, 0) F_(0, 0)
623 #define MOD_SEL4_2 FM(SEL_TSN0_AVTP_PPS1_0) FM(SEL_TSN0_AVTP_PPS1_1)
624 #define MOD_SEL4_1 FM(SEL_TSN0_MDC_0) FM(SEL_TSN0_MDC_1)
625 #define MOD_SEL4_0 F_(0, 0) F_(0, 0)
627 /* MOD_SEL5 */ /* 0 */ /* 1 */
628 #define MOD_SEL5_19 FM(SEL_AVB2_TX_CTL_0) FM(SEL_AVB2_TX_CTL_1)
629 #define MOD_SEL5_18 F_(0, 0) F_(0, 0)
630 #define MOD_SEL5_17 F_(0, 0) F_(0, 0)
631 #define MOD_SEL5_16 FM(SEL_AVB2_TXC_0) FM(SEL_AVB2_TXC_1)
632 #define MOD_SEL5_15 FM(SEL_AVB2_TD0_0) FM(SEL_AVB2_TD0_1)
633 #define MOD_SEL5_14 F_(0, 0) F_(0, 0)
634 #define MOD_SEL5_13 F_(0, 0) F_(0, 0)
635 #define MOD_SEL5_12 FM(SEL_AVB2_TD1_0) FM(SEL_AVB2_TD1_1)
636 #define MOD_SEL5_11 FM(SEL_AVB2_TD2_0) FM(SEL_AVB2_TD2_1)
637 #define MOD_SEL5_10 F_(0, 0) F_(0, 0)
638 #define MOD_SEL5_9 F_(0, 0) F_(0, 0)
639 #define MOD_SEL5_8 FM(SEL_AVB2_TD3_0) FM(SEL_AVB2_TD3_1)
640 #define MOD_SEL5_7 F_(0, 0) F_(0, 0)
641 #define MOD_SEL5_6 FM(SEL_AVB2_MDC_0) FM(SEL_AVB2_MDC_1)
642 #define MOD_SEL5_5 FM(SEL_AVB2_MAGIC_0) FM(SEL_AVB2_MAGIC_1)
643 #define MOD_SEL5_4 F_(0, 0) F_(0, 0)
644 #define MOD_SEL5_3 F_(0, 0) F_(0, 0)
645 #define MOD_SEL5_2 FM(SEL_AVB2_AVTP_MATCH_0) FM(SEL_AVB2_AVTP_MATCH_1)
646 #define MOD_SEL5_1 F_(0, 0) F_(0, 0)
647 #define MOD_SEL5_0 FM(SEL_AVB2_AVTP_PPS_0) FM(SEL_AVB2_AVTP_PPS_1)
649 /* MOD_SEL6 */ /* 0 */ /* 1 */
650 #define MOD_SEL6_18 FM(SEL_AVB1_TD3_0) FM(SEL_AVB1_TD3_1)
651 #define MOD_SEL6_17 F_(0, 0) F_(0, 0)
652 #define MOD_SEL6_16 FM(SEL_AVB1_TD2_0) FM(SEL_AVB1_TD2_1)
653 #define MOD_SEL6_15 F_(0, 0) F_(0, 0)
654 #define MOD_SEL6_14 F_(0, 0) F_(0, 0)
655 #define MOD_SEL6_13 FM(SEL_AVB1_TD0_0) FM(SEL_AVB1_TD0_1)
656 #define MOD_SEL6_12 FM(SEL_AVB1_TD1_0) FM(SEL_AVB1_TD1_1)
657 #define MOD_SEL6_11 F_(0, 0) F_(0, 0)
658 #define MOD_SEL6_10 FM(SEL_AVB1_AVTP_PPS_0) FM(SEL_AVB1_AVTP_PPS_1)
659 #define MOD_SEL6_9 F_(0, 0) F_(0, 0)
660 #define MOD_SEL6_8 F_(0, 0) F_(0, 0)
661 #define MOD_SEL6_7 FM(SEL_AVB1_TX_CTL_0) FM(SEL_AVB1_TX_CTL_1)
662 #define MOD_SEL6_6 FM(SEL_AVB1_TXC_0) FM(SEL_AVB1_TXC_1)
663 #define MOD_SEL6_5 FM(SEL_AVB1_AVTP_MATCH_0) FM(SEL_AVB1_AVTP_MATCH_1)
664 #define MOD_SEL6_4 F_(0, 0) F_(0, 0)
665 #define MOD_SEL6_3 F_(0, 0) F_(0, 0)
666 #define MOD_SEL6_2 FM(SEL_AVB1_MDC_0) FM(SEL_AVB1_MDC_1)
667 #define MOD_SEL6_1 FM(SEL_AVB1_MAGIC_0) FM(SEL_AVB1_MAGIC_1)
668 #define MOD_SEL6_0 F_(0, 0) F_(0, 0)
670 /* MOD_SEL7 */ /* 0 */ /* 1 */
671 #define MOD_SEL7_16 FM(SEL_AVB0_TX_CTL_0) FM(SEL_AVB0_TX_CTL_1)
672 #define MOD_SEL7_15 FM(SEL_AVB0_TXC_0) FM(SEL_AVB0_TXC_1)
673 #define MOD_SEL7_14 F_(0, 0) F_(0, 0)
674 #define MOD_SEL7_13 FM(SEL_AVB0_MDC_0) FM(SEL_AVB0_MDC_1)
675 #define MOD_SEL7_12 F_(0, 0) F_(0, 0)
676 #define MOD_SEL7_11 FM(SEL_AVB0_TD0_0) FM(SEL_AVB0_TD0_1)
677 #define MOD_SEL7_10 FM(SEL_AVB0_MAGIC_0) FM(SEL_AVB0_MAGIC_1)
678 #define MOD_SEL7_9 F_(0, 0) F_(0, 0)
679 #define MOD_SEL7_8 F_(0, 0) F_(0, 0)
680 #define MOD_SEL7_7 FM(SEL_AVB0_TD1_0) FM(SEL_AVB0_TD1_1)
681 #define MOD_SEL7_6 FM(SEL_AVB0_TD2_0) FM(SEL_AVB0_TD2_1)
682 #define MOD_SEL7_5 F_(0, 0) F_(0, 0)
683 #define MOD_SEL7_4 F_(0, 0) F_(0, 0)
684 #define MOD_SEL7_3 FM(SEL_AVB0_TD3_0) FM(SEL_AVB0_TD3_1)
685 #define MOD_SEL7_2 FM(SEL_AVB0_AVTP_MATCH_0) FM(SEL_AVB0_AVTP_MATCH_1)
686 #define MOD_SEL7_1 F_(0, 0) F_(0, 0)
687 #define MOD_SEL7_0 FM(SEL_AVB0_AVTP_PPS_0) FM(SEL_AVB0_AVTP_PPS_1)
689 /* MOD_SEL8 */ /* 0 */ /* 1 */
690 #define MOD_SEL8_11 FM(SEL_SDA5_0) FM(SEL_SDA5_1)
691 #define MOD_SEL8_10 FM(SEL_SCL5_0) FM(SEL_SCL5_1)
692 #define MOD_SEL8_9 FM(SEL_SDA4_0) FM(SEL_SDA4_1)
693 #define MOD_SEL8_8 FM(SEL_SCL4_0) FM(SEL_SCL4_1)
694 #define MOD_SEL8_7 FM(SEL_SDA3_0) FM(SEL_SDA3_1)
695 #define MOD_SEL8_6 FM(SEL_SCL3_0) FM(SEL_SCL3_1)
696 #define MOD_SEL8_5 FM(SEL_SDA2_0) FM(SEL_SDA2_1)
697 #define MOD_SEL8_4 FM(SEL_SCL2_0) FM(SEL_SCL2_1)
698 #define MOD_SEL8_3 FM(SEL_SDA1_0) FM(SEL_SDA1_1)
699 #define MOD_SEL8_2 FM(SEL_SCL1_0) FM(SEL_SCL1_1)
700 #define MOD_SEL8_1 FM(SEL_SDA0_0) FM(SEL_SDA0_1)
701 #define MOD_SEL8_0 FM(SEL_SCL0_0) FM(SEL_SCL0_1)
703 #define PINMUX_MOD_SELS \
705 MOD_SEL4_19 MOD_SEL5_19 \
706 MOD_SEL4_18 MOD_SEL5_18 MOD_SEL6_18 \
707 MOD_SEL4_17 MOD_SEL5_17 MOD_SEL6_17 \
708 MOD_SEL4_16 MOD_SEL5_16 MOD_SEL6_16 MOD_SEL7_16 \
709 MOD_SEL4_15 MOD_SEL5_15 MOD_SEL6_15 MOD_SEL7_15 \
710 MOD_SEL4_14 MOD_SEL5_14 MOD_SEL6_14 MOD_SEL7_14 \
711 MOD_SEL4_13 MOD_SEL5_13 MOD_SEL6_13 MOD_SEL7_13 \
712 MOD_SEL4_12 MOD_SEL5_12 MOD_SEL6_12 MOD_SEL7_12 \
713 MOD_SEL4_11 MOD_SEL5_11 MOD_SEL6_11 MOD_SEL7_11 MOD_SEL8_11 \
714 MOD_SEL4_10 MOD_SEL5_10 MOD_SEL6_10 MOD_SEL7_10 MOD_SEL8_10 \
715 MOD_SEL4_9 MOD_SEL5_9 MOD_SEL6_9 MOD_SEL7_9 MOD_SEL8_9 \
716 MOD_SEL4_8 MOD_SEL5_8 MOD_SEL6_8 MOD_SEL7_8 MOD_SEL8_8 \
717 MOD_SEL4_7 MOD_SEL5_7 MOD_SEL6_7 MOD_SEL7_7 MOD_SEL8_7 \
718 MOD_SEL4_6 MOD_SEL5_6 MOD_SEL6_6 MOD_SEL7_6 MOD_SEL8_6 \
719 MOD_SEL4_5 MOD_SEL5_5 MOD_SEL6_5 MOD_SEL7_5 MOD_SEL8_5 \
720 MOD_SEL4_4 MOD_SEL5_4 MOD_SEL6_4 MOD_SEL7_4 MOD_SEL8_4 \
721 MOD_SEL4_3 MOD_SEL5_3 MOD_SEL6_3 MOD_SEL7_3 MOD_SEL8_3 \
722 MOD_SEL4_2 MOD_SEL5_2 MOD_SEL6_2 MOD_SEL7_2 MOD_SEL8_2 \
723 MOD_SEL4_1 MOD_SEL5_1 MOD_SEL6_1 MOD_SEL7_1 MOD_SEL8_1 \
724 MOD_SEL4_0 MOD_SEL5_0 MOD_SEL6_0 MOD_SEL7_0 MOD_SEL8_0
734 #define FM(x) FN_##x,
735 PINMUX_FUNCTION_BEGIN,
745 #define FM(x) x##_MARK,
755 static const u16 pinmux_data[] = {
756 PINMUX_DATA_GP_ALL(),
760 PINMUX_SINGLE(PCIE1_CLKREQ_N),
761 PINMUX_SINGLE(PCIE0_CLKREQ_N),
762 PINMUX_SINGLE(TSN0_TXCREFCLK),
763 PINMUX_SINGLE(TSN0_TD2),
764 PINMUX_SINGLE(TSN0_TD3),
765 PINMUX_SINGLE(TSN0_RD2),
766 PINMUX_SINGLE(TSN0_RD3),
767 PINMUX_SINGLE(TSN0_TD0),
768 PINMUX_SINGLE(TSN0_TD1),
769 PINMUX_SINGLE(TSN0_RD1),
770 PINMUX_SINGLE(TSN0_TXC),
771 PINMUX_SINGLE(TSN0_RXC),
772 PINMUX_SINGLE(TSN0_RD0),
773 PINMUX_SINGLE(TSN0_TX_CTL),
774 PINMUX_SINGLE(TSN0_AVTP_PPS0),
775 PINMUX_SINGLE(TSN0_RX_CTL),
776 PINMUX_SINGLE(TSN0_AVTP_CAPTURE),
777 PINMUX_SINGLE(TSN0_AVTP_MATCH),
778 PINMUX_SINGLE(TSN0_LINK),
779 PINMUX_SINGLE(TSN0_PHY_INT),
780 PINMUX_SINGLE(TSN0_AVTP_PPS1),
781 PINMUX_SINGLE(TSN0_MDC),
782 PINMUX_SINGLE(TSN0_MDIO),
784 PINMUX_SINGLE(AVB2_RX_CTL),
785 PINMUX_SINGLE(AVB2_TX_CTL),
786 PINMUX_SINGLE(AVB2_RXC),
787 PINMUX_SINGLE(AVB2_RD0),
788 PINMUX_SINGLE(AVB2_TXC),
789 PINMUX_SINGLE(AVB2_TD0),
790 PINMUX_SINGLE(AVB2_RD1),
791 PINMUX_SINGLE(AVB2_RD2),
792 PINMUX_SINGLE(AVB2_TD1),
793 PINMUX_SINGLE(AVB2_TD2),
794 PINMUX_SINGLE(AVB2_MDIO),
795 PINMUX_SINGLE(AVB2_RD3),
796 PINMUX_SINGLE(AVB2_TD3),
797 PINMUX_SINGLE(AVB2_TXCREFCLK),
798 PINMUX_SINGLE(AVB2_MDC),
799 PINMUX_SINGLE(AVB2_MAGIC),
800 PINMUX_SINGLE(AVB2_PHY_INT),
801 PINMUX_SINGLE(AVB2_LINK),
802 PINMUX_SINGLE(AVB2_AVTP_MATCH),
803 PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
804 PINMUX_SINGLE(AVB2_AVTP_PPS),
807 PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC),
809 PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1),
811 PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2),
813 PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3),
814 PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK),
816 PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2),
817 PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD),
819 PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1),
820 PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD),
822 PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0),
823 PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC),
825 PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2),
828 PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF5_SS1),
830 PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF5_SYNC),
832 PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF5_TXD),
834 PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF5_SCK),
836 PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD),
838 PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2),
839 PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1),
841 PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),
842 PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1),
843 PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1),
845 PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC),
846 PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1),
847 PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1),
850 PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD),
851 PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N),
852 PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N),
854 PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK),
855 PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N),
856 PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N),
858 PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD),
859 PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1),
860 PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1),
863 PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
864 PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
865 PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
866 PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
867 PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
868 PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
869 PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
870 PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
873 PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),
875 PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),
877 PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),
879 PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),
881 PINMUX_IPSR_GPSR(IP1SR1_19_16, HTX0),
882 PINMUX_IPSR_GPSR(IP1SR1_19_16, TX0),
884 PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),
885 PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),
886 PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8),
888 PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),
889 PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),
890 PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9),
892 PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
893 PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
894 PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0),
897 PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),
898 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0),
900 PINMUX_IPSR_GPSR(IP2SR1_7_4, SCIF_CLK),
901 PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A),
903 PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK),
904 PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3),
906 PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS),
907 PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4),
909 PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD),
911 PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT),
913 PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN),
914 PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3),
916 PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2),
917 PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1),
920 PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3),
921 PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3),
922 PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
924 PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3),
925 PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N),
926 PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
928 PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N),
929 PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N),
930 PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
932 PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N),
933 PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3),
934 PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
936 PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3),
937 PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3),
938 PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
941 PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA),
942 PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX),
944 PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N),
945 PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX),
947 PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR),
948 PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX),
949 PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5),
951 PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR),
952 PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX),
954 PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR),
956 PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N),
958 PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB),
960 PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1),
961 PINMUX_IPSR_GPSR(IP0SR2_31_28, CANFD6_TX),
964 PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0),
965 PINMUX_IPSR_GPSR(IP1SR2_3_0, CANFD6_RX),
967 PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK),
969 PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX),
971 PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),
972 PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),
974 PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),
975 PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2),
977 PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),
978 PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3),
979 PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1),
981 PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),
982 PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2),
984 PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),
987 PINMUX_IPSR_GPSR(IP2SR2_3_0, CANFD4_TX),
988 PINMUX_IPSR_GPSR(IP2SR2_3_0, PWM4),
990 PINMUX_IPSR_GPSR(IP2SR2_7_4, CANFD4_RX),
991 PINMUX_IPSR_GPSR(IP2SR2_7_4, PWM5),
993 PINMUX_IPSR_GPSR(IP2SR2_11_8, CANFD7_TX),
994 PINMUX_IPSR_GPSR(IP2SR2_11_8, PWM6),
996 PINMUX_IPSR_GPSR(IP2SR2_15_12, CANFD7_RX),
997 PINMUX_IPSR_GPSR(IP2SR2_15_12, PWM7),
1000 PINMUX_IPSR_GPSR(IP0SR3_3_0, MMC_SD_D1),
1001 PINMUX_IPSR_GPSR(IP0SR3_7_4, MMC_SD_D0),
1002 PINMUX_IPSR_GPSR(IP0SR3_11_8, MMC_SD_D2),
1003 PINMUX_IPSR_GPSR(IP0SR3_15_12, MMC_SD_CLK),
1004 PINMUX_IPSR_GPSR(IP0SR3_19_16, MMC_DS),
1005 PINMUX_IPSR_GPSR(IP0SR3_23_20, MMC_SD_D3),
1006 PINMUX_IPSR_GPSR(IP0SR3_27_24, MMC_D5),
1007 PINMUX_IPSR_GPSR(IP0SR3_31_28, MMC_D4),
1010 PINMUX_IPSR_GPSR(IP1SR3_3_0, MMC_D7),
1012 PINMUX_IPSR_GPSR(IP1SR3_7_4, MMC_D6),
1014 PINMUX_IPSR_GPSR(IP1SR3_11_8, MMC_SD_CMD),
1016 PINMUX_IPSR_GPSR(IP1SR3_15_12, SD_CD),
1018 PINMUX_IPSR_GPSR(IP1SR3_19_16, SD_WP),
1020 PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKIN),
1021 PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKEN_IN),
1023 PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT),
1024 PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT),
1026 PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL),
1029 PINMUX_IPSR_GPSR(IP2SR3_3_0, QSPI0_IO3),
1030 PINMUX_IPSR_GPSR(IP2SR3_7_4, QSPI0_IO2),
1031 PINMUX_IPSR_GPSR(IP2SR3_11_8, QSPI0_MISO_IO1),
1032 PINMUX_IPSR_GPSR(IP2SR3_15_12, QSPI0_MOSI_IO0),
1033 PINMUX_IPSR_GPSR(IP2SR3_19_16, QSPI0_SPCLK),
1034 PINMUX_IPSR_GPSR(IP2SR3_23_20, QSPI1_MOSI_IO0),
1035 PINMUX_IPSR_GPSR(IP2SR3_27_24, QSPI1_SPCLK),
1036 PINMUX_IPSR_GPSR(IP2SR3_31_28, QSPI1_MISO_IO1),
1039 PINMUX_IPSR_GPSR(IP3SR3_3_0, QSPI1_IO2),
1040 PINMUX_IPSR_GPSR(IP3SR3_7_4, QSPI1_SSL),
1041 PINMUX_IPSR_GPSR(IP3SR3_11_8, QSPI1_IO3),
1042 PINMUX_IPSR_GPSR(IP3SR3_15_12, RPC_RESET_N),
1043 PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N),
1044 PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N),
1047 PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),
1049 PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),
1051 PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),
1053 PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),
1055 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),
1056 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),
1058 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),
1059 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),
1061 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),
1062 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),
1064 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),
1065 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),
1068 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),
1069 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC),
1071 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),
1072 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),
1074 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),
1075 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),
1077 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),
1078 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),
1080 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),
1081 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),
1083 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),
1084 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),
1086 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),
1087 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),
1089 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0),
1090 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),
1093 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),
1094 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),
1096 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),
1097 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),
1099 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),
1100 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),
1102 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),
1103 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),
1105 PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK),
1108 PINMUX_IPSR_MSEL(IP0SR7_3_0, AVB0_AVTP_PPS, SEL_AVB0_AVTP_PPS_1),
1109 PINMUX_IPSR_MSEL(IP0SR7_3_0, AVB0_MII_COL, SEL_AVB0_AVTP_PPS_0),
1111 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE),
1112 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS),
1114 PINMUX_IPSR_MSEL(IP0SR7_11_8, AVB0_AVTP_MATCH, SEL_AVB0_AVTP_MATCH_1),
1115 PINMUX_IPSR_MSEL(IP0SR7_11_8, AVB0_MII_RX_ER, SEL_AVB0_AVTP_MATCH_0),
1116 PINMUX_IPSR_MSEL(IP0SR7_11_8, CC5_OSCOUT, SEL_AVB0_AVTP_MATCH_0),
1118 PINMUX_IPSR_MSEL(IP0SR7_15_12, AVB0_TD3, SEL_AVB0_TD3_1),
1119 PINMUX_IPSR_MSEL(IP0SR7_15_12, AVB0_MII_TD3, SEL_AVB0_TD3_0),
1121 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK),
1122 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER),
1124 PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT),
1126 PINMUX_IPSR_MSEL(IP0SR7_27_24, AVB0_TD2, SEL_AVB0_TD2_1),
1127 PINMUX_IPSR_MSEL(IP0SR7_27_24, AVB0_MII_TD2, SEL_AVB0_TD2_0),
1129 PINMUX_IPSR_MSEL(IP0SR7_31_28, AVB0_TD1, SEL_AVB0_TD1_1),
1130 PINMUX_IPSR_MSEL(IP0SR7_31_28, AVB0_MII_TD1, SEL_AVB0_TD1_0),
1133 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3),
1134 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3),
1136 PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK),
1138 PINMUX_IPSR_MSEL(IP1SR7_11_8, AVB0_MAGIC, SEL_AVB0_MAGIC_1),
1140 PINMUX_IPSR_MSEL(IP1SR7_15_12, AVB0_TD0, SEL_AVB0_TD0_1),
1141 PINMUX_IPSR_MSEL(IP1SR7_15_12, AVB0_MII_TD0, SEL_AVB0_TD0_0),
1143 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2),
1144 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2),
1146 PINMUX_IPSR_MSEL(IP1SR7_23_20, AVB0_MDC, SEL_AVB0_MDC_1),
1148 PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO),
1150 PINMUX_IPSR_MSEL(IP1SR7_31_28, AVB0_TXC, SEL_AVB0_TXC_1),
1151 PINMUX_IPSR_MSEL(IP1SR7_31_28, AVB0_MII_TXC, SEL_AVB0_TXC_0),
1154 PINMUX_IPSR_MSEL(IP2SR7_3_0, AVB0_TX_CTL, SEL_AVB0_TX_CTL_1),
1155 PINMUX_IPSR_MSEL(IP2SR7_3_0, AVB0_MII_TX_EN, SEL_AVB0_TX_CTL_0),
1157 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1),
1158 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1),
1160 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0),
1161 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0),
1163 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC),
1164 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC),
1166 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL),
1167 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV),
1170 PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_1),
1171 PINMUX_IPSR_MSEL(IP0SR8_7_4, SDA0, SEL_SDA0_1),
1172 PINMUX_IPSR_MSEL(IP0SR8_11_8, SCL1, SEL_SCL1_1),
1173 PINMUX_IPSR_MSEL(IP0SR8_15_12, SDA1, SEL_SDA1_1),
1174 PINMUX_IPSR_MSEL(IP0SR8_19_16, SCL2, SEL_SCL2_1),
1175 PINMUX_IPSR_MSEL(IP0SR8_23_20, SDA2, SEL_SDA2_1),
1176 PINMUX_IPSR_MSEL(IP0SR8_27_24, SCL3, SEL_SCL3_1),
1177 PINMUX_IPSR_MSEL(IP0SR8_31_28, SDA3, SEL_SDA3_1),
1180 PINMUX_IPSR_MSEL(IP1SR8_3_0, SCL4, SEL_SCL4_1),
1181 PINMUX_IPSR_MSEL(IP1SR8_3_0, HRX2, SEL_SCL4_0),
1182 PINMUX_IPSR_MSEL(IP1SR8_3_0, SCK4, SEL_SCL4_0),
1184 PINMUX_IPSR_MSEL(IP1SR8_7_4, SDA4, SEL_SDA4_1),
1185 PINMUX_IPSR_MSEL(IP1SR8_7_4, HTX2, SEL_SDA4_0),
1186 PINMUX_IPSR_MSEL(IP1SR8_7_4, CTS4_N, SEL_SDA4_0),
1188 PINMUX_IPSR_MSEL(IP1SR8_11_8, SCL5, SEL_SCL5_1),
1189 PINMUX_IPSR_MSEL(IP1SR8_11_8, HRTS2_N, SEL_SCL5_0),
1190 PINMUX_IPSR_MSEL(IP1SR8_11_8, RTS4_N, SEL_SCL5_0),
1192 PINMUX_IPSR_MSEL(IP1SR8_15_12, SDA5, SEL_SDA5_1),
1193 PINMUX_IPSR_MSEL(IP1SR8_15_12, SCIF_CLK2, SEL_SDA5_0),
1195 PINMUX_IPSR_GPSR(IP1SR8_19_16, HCTS2_N),
1196 PINMUX_IPSR_GPSR(IP1SR8_19_16, TX4),
1198 PINMUX_IPSR_GPSR(IP1SR8_23_20, HSCK2),
1199 PINMUX_IPSR_GPSR(IP1SR8_23_20, RX4),
1203 * Pins not associated with a GPIO port.
1210 static const struct sh_pfc_pin pinmux_pins[] = {
1211 PINMUX_GPIO_GP_ALL(),
1214 /* - AVB0 ------------------------------------------------ */
1215 static const unsigned int avb0_link_pins[] = {
1219 static const unsigned int avb0_link_mux[] = {
1222 static const unsigned int avb0_magic_pins[] = {
1226 static const unsigned int avb0_magic_mux[] = {
1229 static const unsigned int avb0_phy_int_pins[] = {
1233 static const unsigned int avb0_phy_int_mux[] = {
1236 static const unsigned int avb0_mdio_pins[] = {
1237 /* AVB0_MDC, AVB0_MDIO */
1238 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1240 static const unsigned int avb0_mdio_mux[] = {
1241 AVB0_MDC_MARK, AVB0_MDIO_MARK,
1243 static const unsigned int avb0_rgmii_pins[] = {
1245 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
1246 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
1248 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
1249 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7),
1250 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3),
1251 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
1252 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
1253 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8),
1255 static const unsigned int avb0_rgmii_mux[] = {
1256 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
1257 AVB0_TD0_MARK, AVB0_TD1_MARK,
1258 AVB0_TD2_MARK, AVB0_TD3_MARK,
1259 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
1260 AVB0_RD0_MARK, AVB0_RD1_MARK,
1261 AVB0_RD2_MARK, AVB0_RD3_MARK,
1263 static const unsigned int avb0_txcrefclk_pins[] = {
1264 /* AVB0_TXCREFCLK */
1267 static const unsigned int avb0_txcrefclk_mux[] = {
1268 AVB0_TXCREFCLK_MARK,
1270 static const unsigned int avb0_avtp_pps_pins[] = {
1274 static const unsigned int avb0_avtp_pps_mux[] = {
1277 static const unsigned int avb0_avtp_capture_pins[] = {
1278 /* AVB0_AVTP_CAPTURE */
1281 static const unsigned int avb0_avtp_capture_mux[] = {
1282 AVB0_AVTP_CAPTURE_MARK,
1284 static const unsigned int avb0_avtp_match_pins[] = {
1285 /* AVB0_AVTP_MATCH */
1288 static const unsigned int avb0_avtp_match_mux[] = {
1289 AVB0_AVTP_MATCH_MARK,
1292 /* - AVB1 ------------------------------------------------ */
1293 static const unsigned int avb1_link_pins[] = {
1297 static const unsigned int avb1_link_mux[] = {
1300 static const unsigned int avb1_magic_pins[] = {
1304 static const unsigned int avb1_magic_mux[] = {
1307 static const unsigned int avb1_phy_int_pins[] = {
1311 static const unsigned int avb1_phy_int_mux[] = {
1314 static const unsigned int avb1_mdio_pins[] = {
1315 /* AVB1_MDC, AVB1_MDIO */
1316 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
1318 static const unsigned int avb1_mdio_mux[] = {
1319 AVB1_MDC_MARK, AVB1_MDIO_MARK,
1321 static const unsigned int avb1_rgmii_pins[] = {
1323 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
1324 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
1326 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1327 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
1328 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
1329 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8),
1330 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1331 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
1333 static const unsigned int avb1_rgmii_mux[] = {
1334 AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
1335 AVB1_TD0_MARK, AVB1_TD1_MARK,
1336 AVB1_TD2_MARK, AVB1_TD3_MARK,
1337 AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
1338 AVB1_RD0_MARK, AVB1_RD1_MARK,
1339 AVB1_RD2_MARK, AVB1_RD3_MARK,
1341 static const unsigned int avb1_txcrefclk_pins[] = {
1342 /* AVB1_TXCREFCLK */
1345 static const unsigned int avb1_txcrefclk_mux[] = {
1346 AVB1_TXCREFCLK_MARK,
1348 static const unsigned int avb1_avtp_pps_pins[] = {
1352 static const unsigned int avb1_avtp_pps_mux[] = {
1355 static const unsigned int avb1_avtp_capture_pins[] = {
1356 /* AVB1_AVTP_CAPTURE */
1359 static const unsigned int avb1_avtp_capture_mux[] = {
1360 AVB1_AVTP_CAPTURE_MARK,
1362 static const unsigned int avb1_avtp_match_pins[] = {
1363 /* AVB1_AVTP_MATCH */
1366 static const unsigned int avb1_avtp_match_mux[] = {
1367 AVB1_AVTP_MATCH_MARK,
1370 /* - AVB2 ------------------------------------------------ */
1371 static const unsigned int avb2_link_pins[] = {
1375 static const unsigned int avb2_link_mux[] = {
1378 static const unsigned int avb2_magic_pins[] = {
1382 static const unsigned int avb2_magic_mux[] = {
1385 static const unsigned int avb2_phy_int_pins[] = {
1389 static const unsigned int avb2_phy_int_mux[] = {
1392 static const unsigned int avb2_mdio_pins[] = {
1393 /* AVB2_MDC, AVB2_MDIO */
1394 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
1396 static const unsigned int avb2_mdio_mux[] = {
1397 AVB2_MDC_MARK, AVB2_MDIO_MARK,
1399 static const unsigned int avb2_rgmii_pins[] = {
1401 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
1402 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
1404 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
1405 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
1406 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8),
1407 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
1408 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
1409 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9),
1411 static const unsigned int avb2_rgmii_mux[] = {
1412 AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
1413 AVB2_TD0_MARK, AVB2_TD1_MARK,
1414 AVB2_TD2_MARK, AVB2_TD3_MARK,
1415 AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
1416 AVB2_RD0_MARK, AVB2_RD1_MARK,
1417 AVB2_RD2_MARK, AVB2_RD3_MARK,
1419 static const unsigned int avb2_txcrefclk_pins[] = {
1420 /* AVB2_TXCREFCLK */
1423 static const unsigned int avb2_txcrefclk_mux[] = {
1424 AVB2_TXCREFCLK_MARK,
1426 static const unsigned int avb2_avtp_pps_pins[] = {
1430 static const unsigned int avb2_avtp_pps_mux[] = {
1433 static const unsigned int avb2_avtp_capture_pins[] = {
1434 /* AVB2_AVTP_CAPTURE */
1437 static const unsigned int avb2_avtp_capture_mux[] = {
1438 AVB2_AVTP_CAPTURE_MARK,
1440 static const unsigned int avb2_avtp_match_pins[] = {
1441 /* AVB2_AVTP_MATCH */
1444 static const unsigned int avb2_avtp_match_mux[] = {
1445 AVB2_AVTP_MATCH_MARK,
1448 /* - CANFD0 ----------------------------------------------------------------- */
1449 static const unsigned int canfd0_data_pins[] = {
1450 /* CANFD0_TX, CANFD0_RX */
1451 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1453 static const unsigned int canfd0_data_mux[] = {
1454 CANFD0_TX_MARK, CANFD0_RX_MARK,
1457 /* - CANFD1 ----------------------------------------------------------------- */
1458 static const unsigned int canfd1_data_pins[] = {
1459 /* CANFD1_TX, CANFD1_RX */
1460 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1462 static const unsigned int canfd1_data_mux[] = {
1463 CANFD1_TX_MARK, CANFD1_RX_MARK,
1466 /* - CANFD2 ----------------------------------------------------------------- */
1467 static const unsigned int canfd2_data_pins[] = {
1468 /* CANFD2_TX, CANFD2_RX */
1469 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1471 static const unsigned int canfd2_data_mux[] = {
1472 CANFD2_TX_MARK, CANFD2_RX_MARK,
1475 /* - CANFD3 ----------------------------------------------------------------- */
1476 static const unsigned int canfd3_data_pins[] = {
1477 /* CANFD3_TX, CANFD3_RX */
1478 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1480 static const unsigned int canfd3_data_mux[] = {
1481 CANFD3_TX_MARK, CANFD3_RX_MARK,
1484 /* - CANFD4 ----------------------------------------------------------------- */
1485 static const unsigned int canfd4_data_pins[] = {
1486 /* CANFD4_TX, CANFD4_RX */
1487 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1489 static const unsigned int canfd4_data_mux[] = {
1490 CANFD4_TX_MARK, CANFD4_RX_MARK,
1493 /* - CANFD5 ----------------------------------------------------------------- */
1494 static const unsigned int canfd5_data_pins[] = {
1495 /* CANFD5_TX, CANFD5_RX */
1496 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1498 static const unsigned int canfd5_data_mux[] = {
1499 CANFD5_TX_MARK, CANFD5_RX_MARK,
1502 /* - CANFD6 ----------------------------------------------------------------- */
1503 static const unsigned int canfd6_data_pins[] = {
1504 /* CANFD6_TX, CANFD6_RX */
1505 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1507 static const unsigned int canfd6_data_mux[] = {
1508 CANFD6_TX_MARK, CANFD6_RX_MARK,
1511 /* - CANFD7 ----------------------------------------------------------------- */
1512 static const unsigned int canfd7_data_pins[] = {
1513 /* CANFD7_TX, CANFD7_RX */
1514 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1516 static const unsigned int canfd7_data_mux[] = {
1517 CANFD7_TX_MARK, CANFD7_RX_MARK,
1520 /* - CANFD Clock ------------------------------------------------------------ */
1521 static const unsigned int can_clk_pins[] = {
1525 static const unsigned int can_clk_mux[] = {
1529 /* - HSCIF0 ----------------------------------------------------------------- */
1530 static const unsigned int hscif0_data_pins[] = {
1532 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
1534 static const unsigned int hscif0_data_mux[] = {
1535 HRX0_MARK, HTX0_MARK,
1537 static const unsigned int hscif0_clk_pins[] = {
1541 static const unsigned int hscif0_clk_mux[] = {
1544 static const unsigned int hscif0_ctrl_pins[] = {
1545 /* HRTS0_N, HCTS0_N */
1546 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1548 static const unsigned int hscif0_ctrl_mux[] = {
1549 HRTS0_N_MARK, HCTS0_N_MARK,
1552 /* - HSCIF1 ----------------------------------------------------------------- */
1553 static const unsigned int hscif1_data_pins[] = {
1555 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1557 static const unsigned int hscif1_data_mux[] = {
1558 HRX1_MARK, HTX1_MARK,
1560 static const unsigned int hscif1_clk_pins[] = {
1564 static const unsigned int hscif1_clk_mux[] = {
1567 static const unsigned int hscif1_ctrl_pins[] = {
1568 /* HRTS1_N, HCTS1_N */
1569 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
1571 static const unsigned int hscif1_ctrl_mux[] = {
1572 HRTS1_N_MARK, HCTS1_N_MARK,
1575 /* - HSCIF2 ----------------------------------------------------------------- */
1576 static const unsigned int hscif2_data_pins[] = {
1578 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1580 static const unsigned int hscif2_data_mux[] = {
1581 HRX2_MARK, HTX2_MARK,
1583 static const unsigned int hscif2_clk_pins[] = {
1587 static const unsigned int hscif2_clk_mux[] = {
1590 static const unsigned int hscif2_ctrl_pins[] = {
1591 /* HRTS2_N, HCTS2_N */
1592 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),
1594 static const unsigned int hscif2_ctrl_mux[] = {
1595 HRTS2_N_MARK, HCTS2_N_MARK,
1598 /* - HSCIF3 ----------------------------------------------------------------- */
1599 static const unsigned int hscif3_data_pins[] = {
1601 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
1603 static const unsigned int hscif3_data_mux[] = {
1604 HRX3_MARK, HTX3_MARK,
1606 static const unsigned int hscif3_clk_pins[] = {
1610 static const unsigned int hscif3_clk_mux[] = {
1613 static const unsigned int hscif3_ctrl_pins[] = {
1614 /* HRTS3_N, HCTS3_N */
1615 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1617 static const unsigned int hscif3_ctrl_mux[] = {
1618 HRTS3_N_MARK, HCTS3_N_MARK,
1621 /* - I2C0 ------------------------------------------------------------------- */
1622 static const unsigned int i2c0_pins[] = {
1624 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),
1626 static const unsigned int i2c0_mux[] = {
1627 SDA0_MARK, SCL0_MARK,
1630 /* - I2C1 ------------------------------------------------------------------- */
1631 static const unsigned int i2c1_pins[] = {
1633 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),
1635 static const unsigned int i2c1_mux[] = {
1636 SDA1_MARK, SCL1_MARK,
1639 /* - I2C2 ------------------------------------------------------------------- */
1640 static const unsigned int i2c2_pins[] = {
1642 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),
1644 static const unsigned int i2c2_mux[] = {
1645 SDA2_MARK, SCL2_MARK,
1648 /* - I2C3 ------------------------------------------------------------------- */
1649 static const unsigned int i2c3_pins[] = {
1651 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),
1653 static const unsigned int i2c3_mux[] = {
1654 SDA3_MARK, SCL3_MARK,
1657 /* - I2C4 ------------------------------------------------------------------- */
1658 static const unsigned int i2c4_pins[] = {
1660 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),
1662 static const unsigned int i2c4_mux[] = {
1663 SDA4_MARK, SCL4_MARK,
1666 /* - I2C5 ------------------------------------------------------------------- */
1667 static const unsigned int i2c5_pins[] = {
1669 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),
1671 static const unsigned int i2c5_mux[] = {
1672 SDA5_MARK, SCL5_MARK,
1675 /* - MMC -------------------------------------------------------------------- */
1676 static const unsigned int mmc_data_pins[] = {
1677 /* MMC_SD_D[0:3], MMC_D[4:7] */
1678 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1679 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
1680 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
1681 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1683 static const unsigned int mmc_data_mux[] = {
1684 MMC_SD_D0_MARK, MMC_SD_D1_MARK,
1685 MMC_SD_D2_MARK, MMC_SD_D3_MARK,
1686 MMC_D4_MARK, MMC_D5_MARK,
1687 MMC_D6_MARK, MMC_D7_MARK,
1689 static const unsigned int mmc_ctrl_pins[] = {
1690 /* MMC_SD_CLK, MMC_SD_CMD */
1691 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
1693 static const unsigned int mmc_ctrl_mux[] = {
1694 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
1696 static const unsigned int mmc_cd_pins[] = {
1700 static const unsigned int mmc_cd_mux[] = {
1703 static const unsigned int mmc_wp_pins[] = {
1707 static const unsigned int mmc_wp_mux[] = {
1710 static const unsigned int mmc_ds_pins[] = {
1714 static const unsigned int mmc_ds_mux[] = {
1718 /* - MSIOF0 ----------------------------------------------------------------- */
1719 static const unsigned int msiof0_clk_pins[] = {
1723 static const unsigned int msiof0_clk_mux[] = {
1726 static const unsigned int msiof0_sync_pins[] = {
1730 static const unsigned int msiof0_sync_mux[] = {
1733 static const unsigned int msiof0_ss1_pins[] = {
1737 static const unsigned int msiof0_ss1_mux[] = {
1740 static const unsigned int msiof0_ss2_pins[] = {
1744 static const unsigned int msiof0_ss2_mux[] = {
1747 static const unsigned int msiof0_txd_pins[] = {
1751 static const unsigned int msiof0_txd_mux[] = {
1754 static const unsigned int msiof0_rxd_pins[] = {
1758 static const unsigned int msiof0_rxd_mux[] = {
1762 /* - MSIOF1 ----------------------------------------------------------------- */
1763 static const unsigned int msiof1_clk_pins[] = {
1767 static const unsigned int msiof1_clk_mux[] = {
1770 static const unsigned int msiof1_sync_pins[] = {
1774 static const unsigned int msiof1_sync_mux[] = {
1777 static const unsigned int msiof1_ss1_pins[] = {
1781 static const unsigned int msiof1_ss1_mux[] = {
1784 static const unsigned int msiof1_ss2_pins[] = {
1788 static const unsigned int msiof1_ss2_mux[] = {
1791 static const unsigned int msiof1_txd_pins[] = {
1795 static const unsigned int msiof1_txd_mux[] = {
1798 static const unsigned int msiof1_rxd_pins[] = {
1802 static const unsigned int msiof1_rxd_mux[] = {
1806 /* - MSIOF2 ----------------------------------------------------------------- */
1807 static const unsigned int msiof2_clk_pins[] = {
1811 static const unsigned int msiof2_clk_mux[] = {
1814 static const unsigned int msiof2_sync_pins[] = {
1818 static const unsigned int msiof2_sync_mux[] = {
1821 static const unsigned int msiof2_ss1_pins[] = {
1825 static const unsigned int msiof2_ss1_mux[] = {
1828 static const unsigned int msiof2_ss2_pins[] = {
1832 static const unsigned int msiof2_ss2_mux[] = {
1835 static const unsigned int msiof2_txd_pins[] = {
1839 static const unsigned int msiof2_txd_mux[] = {
1842 static const unsigned int msiof2_rxd_pins[] = {
1846 static const unsigned int msiof2_rxd_mux[] = {
1850 /* - MSIOF3 ----------------------------------------------------------------- */
1851 static const unsigned int msiof3_clk_pins[] = {
1855 static const unsigned int msiof3_clk_mux[] = {
1858 static const unsigned int msiof3_sync_pins[] = {
1862 static const unsigned int msiof3_sync_mux[] = {
1865 static const unsigned int msiof3_ss1_pins[] = {
1869 static const unsigned int msiof3_ss1_mux[] = {
1872 static const unsigned int msiof3_ss2_pins[] = {
1876 static const unsigned int msiof3_ss2_mux[] = {
1879 static const unsigned int msiof3_txd_pins[] = {
1883 static const unsigned int msiof3_txd_mux[] = {
1886 static const unsigned int msiof3_rxd_pins[] = {
1890 static const unsigned int msiof3_rxd_mux[] = {
1894 /* - MSIOF4 ----------------------------------------------------------------- */
1895 static const unsigned int msiof4_clk_pins[] = {
1899 static const unsigned int msiof4_clk_mux[] = {
1902 static const unsigned int msiof4_sync_pins[] = {
1906 static const unsigned int msiof4_sync_mux[] = {
1909 static const unsigned int msiof4_ss1_pins[] = {
1913 static const unsigned int msiof4_ss1_mux[] = {
1916 static const unsigned int msiof4_ss2_pins[] = {
1920 static const unsigned int msiof4_ss2_mux[] = {
1923 static const unsigned int msiof4_txd_pins[] = {
1927 static const unsigned int msiof4_txd_mux[] = {
1930 static const unsigned int msiof4_rxd_pins[] = {
1934 static const unsigned int msiof4_rxd_mux[] = {
1938 /* - MSIOF5 ----------------------------------------------------------------- */
1939 static const unsigned int msiof5_clk_pins[] = {
1943 static const unsigned int msiof5_clk_mux[] = {
1946 static const unsigned int msiof5_sync_pins[] = {
1950 static const unsigned int msiof5_sync_mux[] = {
1953 static const unsigned int msiof5_ss1_pins[] = {
1957 static const unsigned int msiof5_ss1_mux[] = {
1960 static const unsigned int msiof5_ss2_pins[] = {
1964 static const unsigned int msiof5_ss2_mux[] = {
1967 static const unsigned int msiof5_txd_pins[] = {
1971 static const unsigned int msiof5_txd_mux[] = {
1974 static const unsigned int msiof5_rxd_pins[] = {
1978 static const unsigned int msiof5_rxd_mux[] = {
1982 /* - PCIE ------------------------------------------------------------------- */
1983 static const unsigned int pcie0_clkreq_n_pins[] = {
1984 /* PCIE0_CLKREQ_N */
1988 static const unsigned int pcie0_clkreq_n_mux[] = {
1989 PCIE0_CLKREQ_N_MARK,
1992 static const unsigned int pcie1_clkreq_n_pins[] = {
1993 /* PCIE1_CLKREQ_N */
1997 static const unsigned int pcie1_clkreq_n_mux[] = {
1998 PCIE1_CLKREQ_N_MARK,
2001 /* - PWM0 ------------------------------------------------------------------- */
2002 static const unsigned int pwm0_pins[] = {
2006 static const unsigned int pwm0_mux[] = {
2010 /* - PWM1 ------------------------------------------------------------------- */
2011 static const unsigned int pwm1_pins[] = {
2015 static const unsigned int pwm1_mux[] = {
2019 /* - PWM2 ------------------------------------------------------------------- */
2020 static const unsigned int pwm2_pins[] = {
2024 static const unsigned int pwm2_mux[] = {
2028 /* - PWM3 ------------------------------------------------------------------- */
2029 static const unsigned int pwm3_pins[] = {
2033 static const unsigned int pwm3_mux[] = {
2037 /* - PWM4 ------------------------------------------------------------------- */
2038 static const unsigned int pwm4_pins[] = {
2042 static const unsigned int pwm4_mux[] = {
2046 /* - PWM5 ------------------------------------------------------------------- */
2047 static const unsigned int pwm5_pins[] = {
2051 static const unsigned int pwm5_mux[] = {
2055 /* - PWM6 ------------------------------------------------------------------- */
2056 static const unsigned int pwm6_pins[] = {
2060 static const unsigned int pwm6_mux[] = {
2064 /* - PWM7 ------------------------------------------------------------------- */
2065 static const unsigned int pwm7_pins[] = {
2069 static const unsigned int pwm7_mux[] = {
2073 /* - PWM8 ------------------------------------------------------------------- */
2074 static const unsigned int pwm8_pins[] = {
2078 static const unsigned int pwm8_mux[] = {
2082 /* - PWM9 ------------------------------------------------------------------- */
2083 static const unsigned int pwm9_pins[] = {
2087 static const unsigned int pwm9_mux[] = {
2091 /* - QSPI0 ------------------------------------------------------------------ */
2092 static const unsigned int qspi0_ctrl_pins[] = {
2094 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
2096 static const unsigned int qspi0_ctrl_mux[] = {
2097 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2099 static const unsigned int qspi0_data_pins[] = {
2100 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2101 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2102 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2104 static const unsigned int qspi0_data_mux[] = {
2105 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2106 QSPI0_IO2_MARK, QSPI0_IO3_MARK
2109 /* - QSPI1 ------------------------------------------------------------------ */
2110 static const unsigned int qspi1_ctrl_pins[] = {
2112 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
2114 static const unsigned int qspi1_ctrl_mux[] = {
2115 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2117 static const unsigned int qspi1_data_pins[] = {
2118 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2119 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
2120 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
2122 static const unsigned int qspi1_data_mux[] = {
2123 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2124 QSPI1_IO2_MARK, QSPI1_IO3_MARK
2127 /* - SCIF0 ------------------------------------------------------------------ */
2128 static const unsigned int scif0_data_pins[] = {
2130 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
2132 static const unsigned int scif0_data_mux[] = {
2135 static const unsigned int scif0_clk_pins[] = {
2139 static const unsigned int scif0_clk_mux[] = {
2142 static const unsigned int scif0_ctrl_pins[] = {
2143 /* RTS0_N, CTS0_N */
2144 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2146 static const unsigned int scif0_ctrl_mux[] = {
2147 RTS0_N_MARK, CTS0_N_MARK,
2150 /* - SCIF1 ------------------------------------------------------------------ */
2151 static const unsigned int scif1_data_pins[] = {
2153 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2155 static const unsigned int scif1_data_mux[] = {
2158 static const unsigned int scif1_clk_pins[] = {
2162 static const unsigned int scif1_clk_mux[] = {
2165 static const unsigned int scif1_ctrl_pins[] = {
2166 /* RTS1_N, CTS1_N */
2167 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
2169 static const unsigned int scif1_ctrl_mux[] = {
2170 RTS1_N_MARK, CTS1_N_MARK,
2173 /* - SCIF3 ------------------------------------------------------------------ */
2174 static const unsigned int scif3_data_pins[] = {
2176 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2178 static const unsigned int scif3_data_mux[] = {
2181 static const unsigned int scif3_clk_pins[] = {
2185 static const unsigned int scif3_clk_mux[] = {
2188 static const unsigned int scif3_ctrl_pins[] = {
2189 /* RTS3_N, CTS3_N */
2190 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2192 static const unsigned int scif3_ctrl_mux[] = {
2193 RTS3_N_MARK, CTS3_N_MARK,
2196 /* - SCIF4 ------------------------------------------------------------------ */
2197 static const unsigned int scif4_data_pins[] = {
2199 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
2201 static const unsigned int scif4_data_mux[] = {
2204 static const unsigned int scif4_clk_pins[] = {
2208 static const unsigned int scif4_clk_mux[] = {
2211 static const unsigned int scif4_ctrl_pins[] = {
2212 /* RTS4_N, CTS4_N */
2213 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
2215 static const unsigned int scif4_ctrl_mux[] = {
2216 RTS4_N_MARK, CTS4_N_MARK,
2219 /* - SCIF Clock ------------------------------------------------------------- */
2220 static const unsigned int scif_clk_pins[] = {
2224 static const unsigned int scif_clk_mux[] = {
2228 /* - TPU ------------------------------------------------------------------- */
2229 static const unsigned int tpu_to0_pins[] = {
2233 static const unsigned int tpu_to0_mux[] = {
2236 static const unsigned int tpu_to1_pins[] = {
2240 static const unsigned int tpu_to1_mux[] = {
2243 static const unsigned int tpu_to2_pins[] = {
2247 static const unsigned int tpu_to2_mux[] = {
2250 static const unsigned int tpu_to3_pins[] = {
2254 static const unsigned int tpu_to3_mux[] = {
2258 /* - TSN0 ------------------------------------------------ */
2259 static const unsigned int tsn0_link_pins[] = {
2263 static const unsigned int tsn0_link_mux[] = {
2266 static const unsigned int tsn0_phy_int_pins[] = {
2270 static const unsigned int tsn0_phy_int_mux[] = {
2273 static const unsigned int tsn0_mdio_pins[] = {
2274 /* TSN0_MDC, TSN0_MDIO */
2275 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
2277 static const unsigned int tsn0_mdio_mux[] = {
2278 TSN0_MDC_MARK, TSN0_MDIO_MARK,
2280 static const unsigned int tsn0_rgmii_pins[] = {
2282 * TSN0_TX_CTL, TSN0_TXC, TSN0_TD0, TSN0_TD1, TSN0_TD2, TSN0_TD3,
2283 * TSN0_RX_CTL, TSN0_RXC, TSN0_RD0, TSN0_RD1, TSN0_RD2, TSN0_RD3,
2285 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 12),
2286 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),
2287 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2288 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 11),
2289 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),
2290 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
2292 static const unsigned int tsn0_rgmii_mux[] = {
2293 TSN0_TX_CTL_MARK, TSN0_TXC_MARK,
2294 TSN0_TD0_MARK, TSN0_TD1_MARK,
2295 TSN0_TD2_MARK, TSN0_TD3_MARK,
2296 TSN0_RX_CTL_MARK, TSN0_RXC_MARK,
2297 TSN0_RD0_MARK, TSN0_RD1_MARK,
2298 TSN0_RD2_MARK, TSN0_RD3_MARK,
2300 static const unsigned int tsn0_txcrefclk_pins[] = {
2301 /* TSN0_TXCREFCLK */
2304 static const unsigned int tsn0_txcrefclk_mux[] = {
2305 TSN0_TXCREFCLK_MARK,
2307 static const unsigned int tsn0_avtp_pps_pins[] = {
2308 /* TSN0_AVTP_PPS0, TSN0_AVTP_PPS1 */
2309 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),
2311 static const unsigned int tsn0_avtp_pps_mux[] = {
2312 TSN0_AVTP_PPS0_MARK, TSN0_AVTP_PPS1_MARK,
2314 static const unsigned int tsn0_avtp_capture_pins[] = {
2315 /* TSN0_AVTP_CAPTURE */
2318 static const unsigned int tsn0_avtp_capture_mux[] = {
2319 TSN0_AVTP_CAPTURE_MARK,
2321 static const unsigned int tsn0_avtp_match_pins[] = {
2322 /* TSN0_AVTP_MATCH */
2325 static const unsigned int tsn0_avtp_match_mux[] = {
2326 TSN0_AVTP_MATCH_MARK,
2329 static const struct sh_pfc_pin_group pinmux_groups[] = {
2330 SH_PFC_PIN_GROUP(avb0_link),
2331 SH_PFC_PIN_GROUP(avb0_magic),
2332 SH_PFC_PIN_GROUP(avb0_phy_int),
2333 SH_PFC_PIN_GROUP(avb0_mdio),
2334 SH_PFC_PIN_GROUP(avb0_rgmii),
2335 SH_PFC_PIN_GROUP(avb0_txcrefclk),
2336 SH_PFC_PIN_GROUP(avb0_avtp_pps),
2337 SH_PFC_PIN_GROUP(avb0_avtp_capture),
2338 SH_PFC_PIN_GROUP(avb0_avtp_match),
2340 SH_PFC_PIN_GROUP(avb1_link),
2341 SH_PFC_PIN_GROUP(avb1_magic),
2342 SH_PFC_PIN_GROUP(avb1_phy_int),
2343 SH_PFC_PIN_GROUP(avb1_mdio),
2344 SH_PFC_PIN_GROUP(avb1_rgmii),
2345 SH_PFC_PIN_GROUP(avb1_txcrefclk),
2346 SH_PFC_PIN_GROUP(avb1_avtp_pps),
2347 SH_PFC_PIN_GROUP(avb1_avtp_capture),
2348 SH_PFC_PIN_GROUP(avb1_avtp_match),
2350 SH_PFC_PIN_GROUP(avb2_link),
2351 SH_PFC_PIN_GROUP(avb2_magic),
2352 SH_PFC_PIN_GROUP(avb2_phy_int),
2353 SH_PFC_PIN_GROUP(avb2_mdio),
2354 SH_PFC_PIN_GROUP(avb2_rgmii),
2355 SH_PFC_PIN_GROUP(avb2_txcrefclk),
2356 SH_PFC_PIN_GROUP(avb2_avtp_pps),
2357 SH_PFC_PIN_GROUP(avb2_avtp_capture),
2358 SH_PFC_PIN_GROUP(avb2_avtp_match),
2360 SH_PFC_PIN_GROUP(canfd0_data),
2361 SH_PFC_PIN_GROUP(canfd1_data),
2362 SH_PFC_PIN_GROUP(canfd2_data),
2363 SH_PFC_PIN_GROUP(canfd3_data),
2364 SH_PFC_PIN_GROUP(canfd4_data),
2365 SH_PFC_PIN_GROUP(canfd5_data),
2366 SH_PFC_PIN_GROUP(canfd6_data),
2367 SH_PFC_PIN_GROUP(canfd7_data),
2368 SH_PFC_PIN_GROUP(can_clk),
2370 SH_PFC_PIN_GROUP(hscif0_data),
2371 SH_PFC_PIN_GROUP(hscif0_clk),
2372 SH_PFC_PIN_GROUP(hscif0_ctrl),
2373 SH_PFC_PIN_GROUP(hscif1_data),
2374 SH_PFC_PIN_GROUP(hscif1_clk),
2375 SH_PFC_PIN_GROUP(hscif1_ctrl),
2376 SH_PFC_PIN_GROUP(hscif2_data),
2377 SH_PFC_PIN_GROUP(hscif2_clk),
2378 SH_PFC_PIN_GROUP(hscif2_ctrl),
2379 SH_PFC_PIN_GROUP(hscif3_data),
2380 SH_PFC_PIN_GROUP(hscif3_clk),
2381 SH_PFC_PIN_GROUP(hscif3_ctrl),
2383 SH_PFC_PIN_GROUP(i2c0),
2384 SH_PFC_PIN_GROUP(i2c1),
2385 SH_PFC_PIN_GROUP(i2c2),
2386 SH_PFC_PIN_GROUP(i2c3),
2387 SH_PFC_PIN_GROUP(i2c4),
2388 SH_PFC_PIN_GROUP(i2c5),
2390 BUS_DATA_PIN_GROUP(mmc_data, 1),
2391 BUS_DATA_PIN_GROUP(mmc_data, 4),
2392 BUS_DATA_PIN_GROUP(mmc_data, 8),
2393 SH_PFC_PIN_GROUP(mmc_ctrl),
2394 SH_PFC_PIN_GROUP(mmc_cd),
2395 SH_PFC_PIN_GROUP(mmc_wp),
2396 SH_PFC_PIN_GROUP(mmc_ds),
2398 SH_PFC_PIN_GROUP(msiof0_clk),
2399 SH_PFC_PIN_GROUP(msiof0_sync),
2400 SH_PFC_PIN_GROUP(msiof0_ss1),
2401 SH_PFC_PIN_GROUP(msiof0_ss2),
2402 SH_PFC_PIN_GROUP(msiof0_txd),
2403 SH_PFC_PIN_GROUP(msiof0_rxd),
2405 SH_PFC_PIN_GROUP(msiof1_clk),
2406 SH_PFC_PIN_GROUP(msiof1_sync),
2407 SH_PFC_PIN_GROUP(msiof1_ss1),
2408 SH_PFC_PIN_GROUP(msiof1_ss2),
2409 SH_PFC_PIN_GROUP(msiof1_txd),
2410 SH_PFC_PIN_GROUP(msiof1_rxd),
2412 SH_PFC_PIN_GROUP(msiof2_clk),
2413 SH_PFC_PIN_GROUP(msiof2_sync),
2414 SH_PFC_PIN_GROUP(msiof2_ss1),
2415 SH_PFC_PIN_GROUP(msiof2_ss2),
2416 SH_PFC_PIN_GROUP(msiof2_txd),
2417 SH_PFC_PIN_GROUP(msiof2_rxd),
2419 SH_PFC_PIN_GROUP(msiof3_clk),
2420 SH_PFC_PIN_GROUP(msiof3_sync),
2421 SH_PFC_PIN_GROUP(msiof3_ss1),
2422 SH_PFC_PIN_GROUP(msiof3_ss2),
2423 SH_PFC_PIN_GROUP(msiof3_txd),
2424 SH_PFC_PIN_GROUP(msiof3_rxd),
2426 SH_PFC_PIN_GROUP(msiof4_clk),
2427 SH_PFC_PIN_GROUP(msiof4_sync),
2428 SH_PFC_PIN_GROUP(msiof4_ss1),
2429 SH_PFC_PIN_GROUP(msiof4_ss2),
2430 SH_PFC_PIN_GROUP(msiof4_txd),
2431 SH_PFC_PIN_GROUP(msiof4_rxd),
2433 SH_PFC_PIN_GROUP(msiof5_clk),
2434 SH_PFC_PIN_GROUP(msiof5_sync),
2435 SH_PFC_PIN_GROUP(msiof5_ss1),
2436 SH_PFC_PIN_GROUP(msiof5_ss2),
2437 SH_PFC_PIN_GROUP(msiof5_txd),
2438 SH_PFC_PIN_GROUP(msiof5_rxd),
2440 SH_PFC_PIN_GROUP(pcie0_clkreq_n),
2441 SH_PFC_PIN_GROUP(pcie1_clkreq_n),
2443 SH_PFC_PIN_GROUP(pwm0),
2444 SH_PFC_PIN_GROUP(pwm1),
2445 SH_PFC_PIN_GROUP(pwm2),
2446 SH_PFC_PIN_GROUP(pwm3),
2447 SH_PFC_PIN_GROUP(pwm4),
2448 SH_PFC_PIN_GROUP(pwm5),
2449 SH_PFC_PIN_GROUP(pwm6),
2450 SH_PFC_PIN_GROUP(pwm7),
2451 SH_PFC_PIN_GROUP(pwm8),
2452 SH_PFC_PIN_GROUP(pwm9),
2454 SH_PFC_PIN_GROUP(qspi0_ctrl),
2455 BUS_DATA_PIN_GROUP(qspi0_data, 2),
2456 BUS_DATA_PIN_GROUP(qspi0_data, 4),
2457 SH_PFC_PIN_GROUP(qspi1_ctrl),
2458 BUS_DATA_PIN_GROUP(qspi1_data, 2),
2459 BUS_DATA_PIN_GROUP(qspi1_data, 4),
2461 SH_PFC_PIN_GROUP(scif0_data),
2462 SH_PFC_PIN_GROUP(scif0_clk),
2463 SH_PFC_PIN_GROUP(scif0_ctrl),
2464 SH_PFC_PIN_GROUP(scif1_data),
2465 SH_PFC_PIN_GROUP(scif1_clk),
2466 SH_PFC_PIN_GROUP(scif1_ctrl),
2467 SH_PFC_PIN_GROUP(scif3_data),
2468 SH_PFC_PIN_GROUP(scif3_clk),
2469 SH_PFC_PIN_GROUP(scif3_ctrl),
2470 SH_PFC_PIN_GROUP(scif4_data),
2471 SH_PFC_PIN_GROUP(scif4_clk),
2472 SH_PFC_PIN_GROUP(scif4_ctrl),
2473 SH_PFC_PIN_GROUP(scif_clk),
2475 SH_PFC_PIN_GROUP(tpu_to0),
2476 SH_PFC_PIN_GROUP(tpu_to1),
2477 SH_PFC_PIN_GROUP(tpu_to2),
2478 SH_PFC_PIN_GROUP(tpu_to3),
2480 SH_PFC_PIN_GROUP(tsn0_link),
2481 SH_PFC_PIN_GROUP(tsn0_phy_int),
2482 SH_PFC_PIN_GROUP(tsn0_mdio),
2483 SH_PFC_PIN_GROUP(tsn0_rgmii),
2484 SH_PFC_PIN_GROUP(tsn0_txcrefclk),
2485 SH_PFC_PIN_GROUP(tsn0_avtp_pps),
2486 SH_PFC_PIN_GROUP(tsn0_avtp_capture),
2487 SH_PFC_PIN_GROUP(tsn0_avtp_match),
2490 static const char * const avb0_groups[] = {
2498 "avb0_avtp_capture",
2502 static const char * const avb1_groups[] = {
2510 "avb1_avtp_capture",
2514 static const char * const avb2_groups[] = {
2522 "avb2_avtp_capture",
2526 static const char * const canfd0_groups[] = {
2530 static const char * const canfd1_groups[] = {
2534 static const char * const canfd2_groups[] = {
2538 static const char * const canfd3_groups[] = {
2542 static const char * const canfd4_groups[] = {
2546 static const char * const canfd5_groups[] = {
2550 static const char * const canfd6_groups[] = {
2554 static const char * const canfd7_groups[] = {
2558 static const char * const can_clk_groups[] = {
2562 static const char * const hscif0_groups[] = {
2568 static const char * const hscif1_groups[] = {
2574 static const char * const hscif2_groups[] = {
2580 static const char * const hscif3_groups[] = {
2586 static const char * const i2c0_groups[] = {
2590 static const char * const i2c1_groups[] = {
2594 static const char * const i2c2_groups[] = {
2598 static const char * const i2c3_groups[] = {
2602 static const char * const i2c4_groups[] = {
2606 static const char * const i2c5_groups[] = {
2610 static const char * const mmc_groups[] = {
2620 static const char * const msiof0_groups[] = {
2629 static const char * const msiof1_groups[] = {
2638 static const char * const msiof2_groups[] = {
2647 static const char * const msiof3_groups[] = {
2656 static const char * const msiof4_groups[] = {
2665 static const char * const msiof5_groups[] = {
2674 static const char * const pcie_groups[] = {
2679 static const char * const pwm0_groups[] = {
2683 static const char * const pwm1_groups[] = {
2687 static const char * const pwm2_groups[] = {
2691 static const char * const pwm3_groups[] = {
2695 static const char * const pwm4_groups[] = {
2699 static const char * const pwm5_groups[] = {
2703 static const char * const pwm6_groups[] = {
2707 static const char * const pwm7_groups[] = {
2711 static const char * const pwm8_groups[] = {
2715 static const char * const pwm9_groups[] = {
2719 static const char * const qspi0_groups[] = {
2725 static const char * const qspi1_groups[] = {
2731 static const char * const scif0_groups[] = {
2737 static const char * const scif1_groups[] = {
2743 static const char * const scif3_groups[] = {
2749 static const char * const scif4_groups[] = {
2755 static const char * const scif_clk_groups[] = {
2759 static const char * const tpu_groups[] = {
2766 static const char * const tsn0_groups[] = {
2773 "tsn0_avtp_capture",
2777 static const struct sh_pfc_function pinmux_functions[] = {
2778 SH_PFC_FUNCTION(avb0),
2779 SH_PFC_FUNCTION(avb1),
2780 SH_PFC_FUNCTION(avb2),
2782 SH_PFC_FUNCTION(canfd0),
2783 SH_PFC_FUNCTION(canfd1),
2784 SH_PFC_FUNCTION(canfd2),
2785 SH_PFC_FUNCTION(canfd3),
2786 SH_PFC_FUNCTION(canfd4),
2787 SH_PFC_FUNCTION(canfd5),
2788 SH_PFC_FUNCTION(canfd6),
2789 SH_PFC_FUNCTION(canfd7),
2790 SH_PFC_FUNCTION(can_clk),
2792 SH_PFC_FUNCTION(hscif0),
2793 SH_PFC_FUNCTION(hscif1),
2794 SH_PFC_FUNCTION(hscif2),
2795 SH_PFC_FUNCTION(hscif3),
2797 SH_PFC_FUNCTION(i2c0),
2798 SH_PFC_FUNCTION(i2c1),
2799 SH_PFC_FUNCTION(i2c2),
2800 SH_PFC_FUNCTION(i2c3),
2801 SH_PFC_FUNCTION(i2c4),
2802 SH_PFC_FUNCTION(i2c5),
2804 SH_PFC_FUNCTION(mmc),
2806 SH_PFC_FUNCTION(msiof0),
2807 SH_PFC_FUNCTION(msiof1),
2808 SH_PFC_FUNCTION(msiof2),
2809 SH_PFC_FUNCTION(msiof3),
2810 SH_PFC_FUNCTION(msiof4),
2811 SH_PFC_FUNCTION(msiof5),
2813 SH_PFC_FUNCTION(pcie),
2815 SH_PFC_FUNCTION(pwm0),
2816 SH_PFC_FUNCTION(pwm1),
2817 SH_PFC_FUNCTION(pwm2),
2818 SH_PFC_FUNCTION(pwm3),
2819 SH_PFC_FUNCTION(pwm4),
2820 SH_PFC_FUNCTION(pwm5),
2821 SH_PFC_FUNCTION(pwm6),
2822 SH_PFC_FUNCTION(pwm7),
2823 SH_PFC_FUNCTION(pwm8),
2824 SH_PFC_FUNCTION(pwm9),
2826 SH_PFC_FUNCTION(qspi0),
2827 SH_PFC_FUNCTION(qspi1),
2829 SH_PFC_FUNCTION(scif0),
2830 SH_PFC_FUNCTION(scif1),
2831 SH_PFC_FUNCTION(scif3),
2832 SH_PFC_FUNCTION(scif4),
2833 SH_PFC_FUNCTION(scif_clk),
2835 SH_PFC_FUNCTION(tpu),
2837 SH_PFC_FUNCTION(tsn0),
2840 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2841 #define F_(x, y) FN_##y
2842 #define FM(x) FN_##x
2843 { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,
2844 GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2845 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2847 /* GP0_31_19 RESERVED */
2848 GP_0_18_FN, GPSR0_18,
2849 GP_0_17_FN, GPSR0_17,
2850 GP_0_16_FN, GPSR0_16,
2851 GP_0_15_FN, GPSR0_15,
2852 GP_0_14_FN, GPSR0_14,
2853 GP_0_13_FN, GPSR0_13,
2854 GP_0_12_FN, GPSR0_12,
2855 GP_0_11_FN, GPSR0_11,
2856 GP_0_10_FN, GPSR0_10,
2866 GP_0_0_FN, GPSR0_0, ))
2868 { PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP(
2872 GP_1_28_FN, GPSR1_28,
2873 GP_1_27_FN, GPSR1_27,
2874 GP_1_26_FN, GPSR1_26,
2875 GP_1_25_FN, GPSR1_25,
2876 GP_1_24_FN, GPSR1_24,
2877 GP_1_23_FN, GPSR1_23,
2878 GP_1_22_FN, GPSR1_22,
2879 GP_1_21_FN, GPSR1_21,
2880 GP_1_20_FN, GPSR1_20,
2881 GP_1_19_FN, GPSR1_19,
2882 GP_1_18_FN, GPSR1_18,
2883 GP_1_17_FN, GPSR1_17,
2884 GP_1_16_FN, GPSR1_16,
2885 GP_1_15_FN, GPSR1_15,
2886 GP_1_14_FN, GPSR1_14,
2887 GP_1_13_FN, GPSR1_13,
2888 GP_1_12_FN, GPSR1_12,
2889 GP_1_11_FN, GPSR1_11,
2890 GP_1_10_FN, GPSR1_10,
2900 GP_1_0_FN, GPSR1_0, ))
2902 { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,
2903 GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2904 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2906 /* GP2_31_20 RESERVED */
2907 GP_2_19_FN, GPSR2_19,
2908 GP_2_18_FN, GPSR2_18,
2909 GP_2_17_FN, GPSR2_17,
2910 GP_2_16_FN, GPSR2_16,
2911 GP_2_15_FN, GPSR2_15,
2912 GP_2_14_FN, GPSR2_14,
2913 GP_2_13_FN, GPSR2_13,
2914 GP_2_12_FN, GPSR2_12,
2915 GP_2_11_FN, GPSR2_11,
2916 GP_2_10_FN, GPSR2_10,
2926 GP_2_0_FN, GPSR2_0, ))
2928 { PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP(
2931 GP_3_29_FN, GPSR3_29,
2932 GP_3_28_FN, GPSR3_28,
2933 GP_3_27_FN, GPSR3_27,
2934 GP_3_26_FN, GPSR3_26,
2935 GP_3_25_FN, GPSR3_25,
2936 GP_3_24_FN, GPSR3_24,
2937 GP_3_23_FN, GPSR3_23,
2938 GP_3_22_FN, GPSR3_22,
2939 GP_3_21_FN, GPSR3_21,
2940 GP_3_20_FN, GPSR3_20,
2941 GP_3_19_FN, GPSR3_19,
2942 GP_3_18_FN, GPSR3_18,
2943 GP_3_17_FN, GPSR3_17,
2944 GP_3_16_FN, GPSR3_16,
2945 GP_3_15_FN, GPSR3_15,
2946 GP_3_14_FN, GPSR3_14,
2947 GP_3_13_FN, GPSR3_13,
2948 GP_3_12_FN, GPSR3_12,
2949 GP_3_11_FN, GPSR3_11,
2950 GP_3_10_FN, GPSR3_10,
2960 GP_3_0_FN, GPSR3_0, ))
2962 { PINMUX_CFG_REG("GPSR4", 0xE6060040, 32, 1, GROUP(
2970 GP_4_24_FN, GPSR4_24,
2971 GP_4_23_FN, GPSR4_23,
2972 GP_4_22_FN, GPSR4_22,
2973 GP_4_21_FN, GPSR4_21,
2974 GP_4_20_FN, GPSR4_20,
2975 GP_4_19_FN, GPSR4_19,
2976 GP_4_18_FN, GPSR4_18,
2977 GP_4_17_FN, GPSR4_17,
2978 GP_4_16_FN, GPSR4_16,
2979 GP_4_15_FN, GPSR4_15,
2980 GP_4_14_FN, GPSR4_14,
2981 GP_4_13_FN, GPSR4_13,
2982 GP_4_12_FN, GPSR4_12,
2983 GP_4_11_FN, GPSR4_11,
2984 GP_4_10_FN, GPSR4_10,
2994 GP_4_0_FN, GPSR4_0, ))
2996 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,
2997 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2998 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3000 /* GP5_31_21 RESERVED */
3001 GP_5_20_FN, GPSR5_20,
3002 GP_5_19_FN, GPSR5_19,
3003 GP_5_18_FN, GPSR5_18,
3004 GP_5_17_FN, GPSR5_17,
3005 GP_5_16_FN, GPSR5_16,
3006 GP_5_15_FN, GPSR5_15,
3007 GP_5_14_FN, GPSR5_14,
3008 GP_5_13_FN, GPSR5_13,
3009 GP_5_12_FN, GPSR5_12,
3010 GP_5_11_FN, GPSR5_11,
3011 GP_5_10_FN, GPSR5_10,
3021 GP_5_0_FN, GPSR5_0, ))
3023 { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,
3024 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3025 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3027 /* GP6_31_21 RESERVED */
3028 GP_6_20_FN, GPSR6_20,
3029 GP_6_19_FN, GPSR6_19,
3030 GP_6_18_FN, GPSR6_18,
3031 GP_6_17_FN, GPSR6_17,
3032 GP_6_16_FN, GPSR6_16,
3033 GP_6_15_FN, GPSR6_15,
3034 GP_6_14_FN, GPSR6_14,
3035 GP_6_13_FN, GPSR6_13,
3036 GP_6_12_FN, GPSR6_12,
3037 GP_6_11_FN, GPSR6_11,
3038 GP_6_10_FN, GPSR6_10,
3048 GP_6_0_FN, GPSR6_0, ))
3050 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,
3051 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3052 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3054 /* GP7_31_21 RESERVED */
3055 GP_7_20_FN, GPSR7_20,
3056 GP_7_19_FN, GPSR7_19,
3057 GP_7_18_FN, GPSR7_18,
3058 GP_7_17_FN, GPSR7_17,
3059 GP_7_16_FN, GPSR7_16,
3060 GP_7_15_FN, GPSR7_15,
3061 GP_7_14_FN, GPSR7_14,
3062 GP_7_13_FN, GPSR7_13,
3063 GP_7_12_FN, GPSR7_12,
3064 GP_7_11_FN, GPSR7_11,
3065 GP_7_10_FN, GPSR7_10,
3075 GP_7_0_FN, GPSR7_0, ))
3077 { PINMUX_CFG_REG_VAR("GPSR8", 0xE6068040, 32,
3078 GROUP(-18, 1, 1, 1, 1,
3079 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3081 /* GP8_31_14 RESERVED */
3082 GP_8_13_FN, GPSR8_13,
3083 GP_8_12_FN, GPSR8_12,
3084 GP_8_11_FN, GPSR8_11,
3085 GP_8_10_FN, GPSR8_10,
3095 GP_8_0_FN, GPSR8_0, ))
3101 #define FM(x) FN_##x,
3102 { PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP(
3112 { PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP(
3122 { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,
3123 GROUP(-20, 4, 4, 4),
3125 /* IP2SR0_31_12 RESERVED */
3130 { PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP(
3140 { PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP(
3150 { PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP(
3160 { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,
3161 GROUP(-12, 4, 4, 4, 4, 4),
3163 /* IP3SR1_31_20 RESERVED */
3170 { PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP(
3180 { PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP(
3190 { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,
3191 GROUP(-16, 4, 4, 4, 4),
3193 /* IP2SR2_31_16 RESERVED */
3199 { PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP(
3209 { PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP(
3219 { PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP(
3229 { PINMUX_CFG_REG_VAR("IP3SR3", 0xE605886C, 32,
3230 GROUP(-8, 4, 4, 4, 4, 4, 4),
3232 /* IP3SR3_31_24 RESERVED */
3240 { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(
3250 { PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP(
3260 { PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32,
3261 GROUP(-12, 4, 4, 4, 4, 4),
3263 /* IP2SR6_31_20 RESERVED */
3270 { PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP(
3280 { PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP(
3290 { PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32,
3291 GROUP(-12, 4, 4, 4, 4, 4),
3293 /* IP2SR7_31_20 RESERVED */
3300 { PINMUX_CFG_REG("IP0SR8", 0xE6068060, 32, 4, GROUP(
3310 { PINMUX_CFG_REG_VAR("IP1SR8", 0xE6068064, 32,
3311 GROUP(-8, 4, 4, 4, 4, 4, 4),
3313 /* IP1SR8_31_24 RESERVED */
3325 #define FM(x) FN_##x,
3326 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE6060100, 32,
3327 GROUP(-12, 1, 1, -2, 1, 1, -1, 1, -2, 1, 1, -2, 1,
3330 /* RESERVED 31-20 */
3333 /* RESERVED 17-16 */
3338 /* RESERVED 11-10 */
3349 { PINMUX_CFG_REG_VAR("MOD_SEL5", 0xE6060900, 32,
3350 GROUP(-12, 1, -2, 1, 1, -2, 1, 1, -2, 1, -1,
3351 1, 1, -2, 1, -1, 1),
3353 /* RESERVED 31-20 */
3355 /* RESERVED 18-17 */
3358 /* RESERVED 14-13 */
3371 { PINMUX_CFG_REG_VAR("MOD_SEL6", 0xE6061100, 32,
3372 GROUP(-13, 1, -1, 1, -2, 1, 1,
3373 -1, 1, -2, 1, 1, 1, -2, 1, 1, -1),
3375 /* RESERVED 31-19 */
3379 /* RESERVED 15-14 */
3394 { PINMUX_CFG_REG_VAR("MOD_SEL7", 0xE6061900, 32,
3395 GROUP(-15, 1, 1, -1, 1, -1, 1, 1, -2, 1, 1,
3398 /* RESERVED 31-17 */
3415 { PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,
3416 GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3418 /* RESERVED 31-12 */
3435 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3436 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) {
3437 { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */
3438 { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */
3439 { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */
3440 { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */
3441 { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */
3442 { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */
3443 { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */
3444 { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */
3446 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) {
3447 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */
3448 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */
3449 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */
3450 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */
3451 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */
3452 { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */
3453 { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */
3454 { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */
3456 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) {
3457 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */
3458 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */
3459 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */
3461 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) {
3462 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */
3463 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */
3464 { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */
3465 { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */
3466 { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */
3467 { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */
3468 { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */
3469 { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */
3471 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) {
3472 { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */
3473 { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */
3474 { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */
3475 { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */
3476 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */
3477 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */
3478 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */
3479 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */
3481 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) {
3482 { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */
3483 { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */
3484 { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */
3485 { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */
3486 { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */
3487 { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */
3488 { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */
3489 { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */
3491 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) {
3492 { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */
3493 { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */
3494 { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */
3495 { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */
3496 { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */
3498 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) {
3499 { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */
3500 { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */
3501 { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */
3502 { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */
3503 { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */
3504 { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */
3505 { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */
3506 { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */
3508 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) {
3509 { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */
3510 { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */
3511 { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */
3512 { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */
3513 { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */
3514 { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */
3515 { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */
3516 { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */
3518 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) {
3519 { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD7_RX */
3520 { RCAR_GP_PIN(2, 18), 8, 3 }, /* CANFD7_TX */
3521 { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD4_RX */
3522 { RCAR_GP_PIN(2, 16), 0, 3 }, /* CANFD4_TX */
3524 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) {
3525 { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */
3526 { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */
3527 { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */
3528 { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */
3529 { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */
3530 { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */
3531 { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */
3532 { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */
3534 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) {
3535 { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */
3536 { RCAR_GP_PIN(3, 14), 24, 2 }, /* IPC_CLKOUT */
3537 { RCAR_GP_PIN(3, 13), 20, 2 }, /* IPC_CLKIN */
3538 { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */
3539 { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */
3540 { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */
3541 { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/
3542 { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */
3544 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) {
3545 { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */
3546 { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */
3547 { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */
3548 { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */
3549 { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */
3550 { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */
3551 { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */
3552 { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */
3554 { PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) {
3555 { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */
3556 { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */
3557 { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */
3558 { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */
3559 { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */
3560 { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */
3562 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) {
3563 { RCAR_GP_PIN(4, 7), 28, 3 }, /* TSN0_RX_CTL */
3564 { RCAR_GP_PIN(4, 6), 24, 3 }, /* TSN0_AVTP_CAPTURE */
3565 { RCAR_GP_PIN(4, 5), 20, 3 }, /* TSN0_AVTP_MATCH */
3566 { RCAR_GP_PIN(4, 4), 16, 3 }, /* TSN0_LINK */
3567 { RCAR_GP_PIN(4, 3), 12, 3 }, /* TSN0_PHY_INT */
3568 { RCAR_GP_PIN(4, 2), 8, 3 }, /* TSN0_AVTP_PPS1 */
3569 { RCAR_GP_PIN(4, 1), 4, 3 }, /* TSN0_MDC */
3570 { RCAR_GP_PIN(4, 0), 0, 3 }, /* TSN0_MDIO */
3572 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) {
3573 { RCAR_GP_PIN(4, 15), 28, 3 }, /* TSN0_TD0 */
3574 { RCAR_GP_PIN(4, 14), 24, 3 }, /* TSN0_TD1 */
3575 { RCAR_GP_PIN(4, 13), 20, 3 }, /* TSN0_RD1 */
3576 { RCAR_GP_PIN(4, 12), 16, 3 }, /* TSN0_TXC */
3577 { RCAR_GP_PIN(4, 11), 12, 3 }, /* TSN0_RXC */
3578 { RCAR_GP_PIN(4, 10), 8, 3 }, /* TSN0_RD0 */
3579 { RCAR_GP_PIN(4, 9), 4, 3 }, /* TSN0_TX_CTL */
3580 { RCAR_GP_PIN(4, 8), 0, 3 }, /* TSN0_AVTP_PPS0 */
3582 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) {
3583 { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */
3584 { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */
3585 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
3586 { RCAR_GP_PIN(4, 20), 16, 3 }, /* TSN0_TXCREFCLK */
3587 { RCAR_GP_PIN(4, 19), 12, 3 }, /* TSN0_TD2 */
3588 { RCAR_GP_PIN(4, 18), 8, 3 }, /* TSN0_TD3 */
3589 { RCAR_GP_PIN(4, 17), 4, 3 }, /* TSN0_RD2 */
3590 { RCAR_GP_PIN(4, 16), 0, 3 }, /* TSN0_RD3 */
3592 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) {
3593 { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */
3595 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) {
3596 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */
3597 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */
3598 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */
3599 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */
3600 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */
3601 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */
3602 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */
3603 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */
3605 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) {
3606 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */
3607 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */
3608 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */
3609 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */
3610 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */
3611 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */
3612 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */
3613 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */
3615 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) {
3616 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */
3617 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */
3618 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */
3619 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */
3620 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */
3622 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) {
3623 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */
3624 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */
3625 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */
3626 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */
3627 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */
3628 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */
3629 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */
3630 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */
3632 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) {
3633 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */
3634 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */
3635 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */
3636 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */
3637 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */
3638 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */
3639 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */
3640 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */
3642 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) {
3643 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */
3644 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */
3645 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */
3646 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */
3647 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */
3649 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) {
3650 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */
3651 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */
3652 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */
3653 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */
3654 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */
3655 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */
3656 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */
3657 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */
3659 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) {
3660 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */
3661 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */
3662 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */
3663 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */
3664 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */
3665 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */
3666 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */
3667 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */
3669 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) {
3670 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */
3671 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */
3672 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */
3673 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */
3674 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */
3676 { PINMUX_DRIVE_REG("DRV0CTRL8", 0xE6068080) {
3677 { RCAR_GP_PIN(8, 7), 28, 3 }, /* SDA3 */
3678 { RCAR_GP_PIN(8, 6), 24, 3 }, /* SCL3 */
3679 { RCAR_GP_PIN(8, 5), 20, 3 }, /* SDA2 */
3680 { RCAR_GP_PIN(8, 4), 16, 3 }, /* SCL2 */
3681 { RCAR_GP_PIN(8, 3), 12, 3 }, /* SDA1 */
3682 { RCAR_GP_PIN(8, 2), 8, 3 }, /* SCL1 */
3683 { RCAR_GP_PIN(8, 1), 4, 3 }, /* SDA0 */
3684 { RCAR_GP_PIN(8, 0), 0, 3 }, /* SCL0 */
3686 { PINMUX_DRIVE_REG("DRV1CTRL8", 0xE6068084) {
3687 { RCAR_GP_PIN(8, 13), 20, 3 }, /* GP8_13 */
3688 { RCAR_GP_PIN(8, 12), 16, 3 }, /* GP8_12 */
3689 { RCAR_GP_PIN(8, 11), 12, 3 }, /* SDA5 */
3690 { RCAR_GP_PIN(8, 10), 8, 3 }, /* SCL5 */
3691 { RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */
3692 { RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */
3710 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
3711 [POC0] = { 0xE60500A0, },
3712 [POC1] = { 0xE60508A0, },
3713 [POC2] = { 0xE60580A0, },
3714 [POC3] = { 0xE60588A0, },
3715 [POC4] = { 0xE60600A0, },
3716 [POC5] = { 0xE60608A0, },
3717 [POC6] = { 0xE60610A0, },
3718 [POC7] = { 0xE60618A0, },
3719 [POC8] = { 0xE60680A0, },
3720 [TD0SEL3] = { 0xE60589C0, },
3724 static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
3726 int bit = pin & 0x1f;
3728 *pocctrl = pinmux_ioctrl_regs[POC0].reg;
3729 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 18))
3732 *pocctrl = pinmux_ioctrl_regs[POC1].reg;
3733 if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 28))
3736 *pocctrl = pinmux_ioctrl_regs[POC3].reg;
3737 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 12))
3740 *pocctrl = pinmux_ioctrl_regs[POC8].reg;
3741 if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 13))
3747 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
3748 { PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) {
3749 [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */
3750 [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */
3751 [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */
3752 [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */
3753 [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */
3754 [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */
3755 [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */
3756 [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */
3757 [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */
3758 [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */
3759 [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */
3760 [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */
3761 [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */
3762 [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */
3763 [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */
3764 [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */
3765 [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */
3766 [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */
3767 [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */
3768 [19] = SH_PFC_PIN_NONE,
3769 [20] = SH_PFC_PIN_NONE,
3770 [21] = SH_PFC_PIN_NONE,
3771 [22] = SH_PFC_PIN_NONE,
3772 [23] = SH_PFC_PIN_NONE,
3773 [24] = SH_PFC_PIN_NONE,
3774 [25] = SH_PFC_PIN_NONE,
3775 [26] = SH_PFC_PIN_NONE,
3776 [27] = SH_PFC_PIN_NONE,
3777 [28] = SH_PFC_PIN_NONE,
3778 [29] = SH_PFC_PIN_NONE,
3779 [30] = SH_PFC_PIN_NONE,
3780 [31] = SH_PFC_PIN_NONE,
3782 { PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) {
3783 [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */
3784 [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */
3785 [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */
3786 [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */
3787 [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */
3788 [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */
3789 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */
3790 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */
3791 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */
3792 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */
3793 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */
3794 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */
3795 [12] = RCAR_GP_PIN(1, 12), /* HTX0 */
3796 [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */
3797 [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */
3798 [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */
3799 [16] = RCAR_GP_PIN(1, 16), /* HRX0 */
3800 [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */
3801 [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */
3802 [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */
3803 [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */
3804 [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */
3805 [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */
3806 [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */
3807 [24] = RCAR_GP_PIN(1, 24), /* HRX3 */
3808 [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */
3809 [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */
3810 [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */
3811 [28] = RCAR_GP_PIN(1, 28), /* HTX3 */
3812 [29] = SH_PFC_PIN_NONE,
3813 [30] = SH_PFC_PIN_NONE,
3814 [31] = SH_PFC_PIN_NONE,
3816 { PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) {
3817 [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */
3818 [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */
3819 [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */
3820 [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */
3821 [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */
3822 [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */
3823 [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */
3824 [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */
3825 [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */
3826 [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */
3827 [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */
3828 [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */
3829 [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */
3830 [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */
3831 [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */
3832 [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */
3833 [16] = RCAR_GP_PIN(2, 16), /* CANFD4_TX */
3834 [17] = RCAR_GP_PIN(2, 17), /* CANFD4_RX */
3835 [18] = RCAR_GP_PIN(2, 18), /* CANFD7_TX */
3836 [19] = RCAR_GP_PIN(2, 19), /* CANFD7_RX */
3837 [20] = SH_PFC_PIN_NONE,
3838 [21] = SH_PFC_PIN_NONE,
3839 [22] = SH_PFC_PIN_NONE,
3840 [23] = SH_PFC_PIN_NONE,
3841 [24] = SH_PFC_PIN_NONE,
3842 [25] = SH_PFC_PIN_NONE,
3843 [26] = SH_PFC_PIN_NONE,
3844 [27] = SH_PFC_PIN_NONE,
3845 [28] = SH_PFC_PIN_NONE,
3846 [29] = SH_PFC_PIN_NONE,
3847 [30] = SH_PFC_PIN_NONE,
3848 [31] = SH_PFC_PIN_NONE,
3850 { PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) {
3851 [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */
3852 [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */
3853 [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */
3854 [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */
3855 [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */
3856 [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */
3857 [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */
3858 [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */
3859 [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */
3860 [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */
3861 [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */
3862 [11] = RCAR_GP_PIN(3, 11), /* SD_CD */
3863 [12] = RCAR_GP_PIN(3, 12), /* SD_WP */
3864 [13] = RCAR_GP_PIN(3, 13), /* IPC_CLKIN */
3865 [14] = RCAR_GP_PIN(3, 14), /* IPC_CLKOUT */
3866 [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */
3867 [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */
3868 [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */
3869 [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */
3870 [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */
3871 [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */
3872 [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */
3873 [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */
3874 [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */
3875 [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */
3876 [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */
3877 [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */
3878 [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */
3879 [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */
3880 [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */
3881 [30] = SH_PFC_PIN_NONE,
3882 [31] = SH_PFC_PIN_NONE,
3884 { PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) {
3885 [ 0] = RCAR_GP_PIN(4, 0), /* TSN0_MDIO */
3886 [ 1] = RCAR_GP_PIN(4, 1), /* TSN0_MDC */
3887 [ 2] = RCAR_GP_PIN(4, 2), /* TSN0_AVTP_PPS1 */
3888 [ 3] = RCAR_GP_PIN(4, 3), /* TSN0_PHY_INT */
3889 [ 4] = RCAR_GP_PIN(4, 4), /* TSN0_LINK */
3890 [ 5] = RCAR_GP_PIN(4, 5), /* TSN0_AVTP_MATCH */
3891 [ 6] = RCAR_GP_PIN(4, 6), /* TSN0_AVTP_CAPTURE */
3892 [ 7] = RCAR_GP_PIN(4, 7), /* TSN0_RX_CTL */
3893 [ 8] = RCAR_GP_PIN(4, 8), /* TSN0_AVTP_PPS0 */
3894 [ 9] = RCAR_GP_PIN(4, 9), /* TSN0_TX_CTL */
3895 [10] = RCAR_GP_PIN(4, 10), /* TSN0_RD0 */
3896 [11] = RCAR_GP_PIN(4, 11), /* TSN0_RXC */
3897 [12] = RCAR_GP_PIN(4, 12), /* TSN0_TXC */
3898 [13] = RCAR_GP_PIN(4, 13), /* TSN0_RD1 */
3899 [14] = RCAR_GP_PIN(4, 14), /* TSN0_TD1 */
3900 [15] = RCAR_GP_PIN(4, 15), /* TSN0_TD0 */
3901 [16] = RCAR_GP_PIN(4, 16), /* TSN0_RD3 */
3902 [17] = RCAR_GP_PIN(4, 17), /* TSN0_RD2 */
3903 [18] = RCAR_GP_PIN(4, 18), /* TSN0_TD3 */
3904 [19] = RCAR_GP_PIN(4, 19), /* TSN0_TD2 */
3905 [20] = RCAR_GP_PIN(4, 20), /* TSN0_TXCREFCLK */
3906 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
3907 [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */
3908 [23] = RCAR_GP_PIN(4, 23), /* AVS0 */
3909 [24] = RCAR_GP_PIN(4, 24), /* AVS1 */
3910 [25] = SH_PFC_PIN_NONE,
3911 [26] = SH_PFC_PIN_NONE,
3912 [27] = SH_PFC_PIN_NONE,
3913 [28] = SH_PFC_PIN_NONE,
3914 [29] = SH_PFC_PIN_NONE,
3915 [30] = SH_PFC_PIN_NONE,
3916 [31] = SH_PFC_PIN_NONE,
3918 { PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) {
3919 [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */
3920 [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */
3921 [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */
3922 [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */
3923 [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */
3924 [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */
3925 [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */
3926 [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */
3927 [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */
3928 [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */
3929 [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */
3930 [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */
3931 [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */
3932 [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */
3933 [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */
3934 [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */
3935 [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */
3936 [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */
3937 [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */
3938 [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */
3939 [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */
3940 [21] = SH_PFC_PIN_NONE,
3941 [22] = SH_PFC_PIN_NONE,
3942 [23] = SH_PFC_PIN_NONE,
3943 [24] = SH_PFC_PIN_NONE,
3944 [25] = SH_PFC_PIN_NONE,
3945 [26] = SH_PFC_PIN_NONE,
3946 [27] = SH_PFC_PIN_NONE,
3947 [28] = SH_PFC_PIN_NONE,
3948 [29] = SH_PFC_PIN_NONE,
3949 [30] = SH_PFC_PIN_NONE,
3950 [31] = SH_PFC_PIN_NONE,
3952 { PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) {
3953 [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */
3954 [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */
3955 [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */
3956 [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */
3957 [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */
3958 [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */
3959 [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */
3960 [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */
3961 [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */
3962 [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */
3963 [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */
3964 [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */
3965 [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */
3966 [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */
3967 [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/
3968 [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */
3969 [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */
3970 [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */
3971 [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */
3972 [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */
3973 [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */
3974 [21] = SH_PFC_PIN_NONE,
3975 [22] = SH_PFC_PIN_NONE,
3976 [23] = SH_PFC_PIN_NONE,
3977 [24] = SH_PFC_PIN_NONE,
3978 [25] = SH_PFC_PIN_NONE,
3979 [26] = SH_PFC_PIN_NONE,
3980 [27] = SH_PFC_PIN_NONE,
3981 [28] = SH_PFC_PIN_NONE,
3982 [29] = SH_PFC_PIN_NONE,
3983 [30] = SH_PFC_PIN_NONE,
3984 [31] = SH_PFC_PIN_NONE,
3986 { PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) {
3987 [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */
3988 [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */
3989 [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */
3990 [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */
3991 [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */
3992 [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */
3993 [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */
3994 [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */
3995 [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */
3996 [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */
3997 [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */
3998 [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */
3999 [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */
4000 [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */
4001 [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */
4002 [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */
4003 [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */
4004 [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */
4005 [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */
4006 [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */
4007 [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */
4008 [21] = SH_PFC_PIN_NONE,
4009 [22] = SH_PFC_PIN_NONE,
4010 [23] = SH_PFC_PIN_NONE,
4011 [24] = SH_PFC_PIN_NONE,
4012 [25] = SH_PFC_PIN_NONE,
4013 [26] = SH_PFC_PIN_NONE,
4014 [27] = SH_PFC_PIN_NONE,
4015 [28] = SH_PFC_PIN_NONE,
4016 [29] = SH_PFC_PIN_NONE,
4017 [30] = SH_PFC_PIN_NONE,
4018 [31] = SH_PFC_PIN_NONE,
4020 { PINMUX_BIAS_REG("PUEN8", 0xE60680C0, "PUD8", 0xE60680E0) {
4021 [ 0] = RCAR_GP_PIN(8, 0), /* SCL0 */
4022 [ 1] = RCAR_GP_PIN(8, 1), /* SDA0 */
4023 [ 2] = RCAR_GP_PIN(8, 2), /* SCL1 */
4024 [ 3] = RCAR_GP_PIN(8, 3), /* SDA1 */
4025 [ 4] = RCAR_GP_PIN(8, 4), /* SCL2 */
4026 [ 5] = RCAR_GP_PIN(8, 5), /* SDA2 */
4027 [ 6] = RCAR_GP_PIN(8, 6), /* SCL3 */
4028 [ 7] = RCAR_GP_PIN(8, 7), /* SDA3 */
4029 [ 8] = RCAR_GP_PIN(8, 8), /* SCL4 */
4030 [ 9] = RCAR_GP_PIN(8, 9), /* SDA4 */
4031 [10] = RCAR_GP_PIN(8, 10), /* SCL5 */
4032 [11] = RCAR_GP_PIN(8, 11), /* SDA5 */
4033 [12] = RCAR_GP_PIN(8, 12), /* GP8_12 */
4034 [13] = RCAR_GP_PIN(8, 13), /* GP8_13 */
4035 [14] = SH_PFC_PIN_NONE,
4036 [15] = SH_PFC_PIN_NONE,
4037 [16] = SH_PFC_PIN_NONE,
4038 [17] = SH_PFC_PIN_NONE,
4039 [18] = SH_PFC_PIN_NONE,
4040 [19] = SH_PFC_PIN_NONE,
4041 [20] = SH_PFC_PIN_NONE,
4042 [21] = SH_PFC_PIN_NONE,
4043 [22] = SH_PFC_PIN_NONE,
4044 [23] = SH_PFC_PIN_NONE,
4045 [24] = SH_PFC_PIN_NONE,
4046 [25] = SH_PFC_PIN_NONE,
4047 [26] = SH_PFC_PIN_NONE,
4048 [27] = SH_PFC_PIN_NONE,
4049 [28] = SH_PFC_PIN_NONE,
4050 [29] = SH_PFC_PIN_NONE,
4051 [30] = SH_PFC_PIN_NONE,
4052 [31] = SH_PFC_PIN_NONE,
4057 static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {
4058 .pin_to_pocctrl = r8a779g0_pin_to_pocctrl,
4059 .get_bias = rcar_pinmux_get_bias,
4060 .set_bias = rcar_pinmux_set_bias,
4063 const struct sh_pfc_soc_info r8a779g0_pinmux_info = {
4064 .name = "r8a779g0_pfc",
4065 .ops = &r8a779g0_pin_ops,
4066 .unlock_reg = 0x1ff, /* PMMRn mask */
4068 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4070 .pins = pinmux_pins,
4071 .nr_pins = ARRAY_SIZE(pinmux_pins),
4072 .groups = pinmux_groups,
4073 .nr_groups = ARRAY_SIZE(pinmux_groups),
4074 .functions = pinmux_functions,
4075 .nr_functions = ARRAY_SIZE(pinmux_functions),
4077 .cfg_regs = pinmux_config_regs,
4078 .drive_regs = pinmux_drive_regs,
4079 .bias_regs = pinmux_bias_regs,
4080 .ioctrl_regs = pinmux_ioctrl_regs,
4082 .pinmux_data = pinmux_data,
4083 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
projects / platform / kernel / linux-starfive.git / blob