drivers/pinctrl/renesas/pfc-r8a779f0.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A779F0 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  *
   7  * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
   8  */
   9
  10 #include <linux/errno.h>
  11 #include <linux/io.h>
  12 #include <linux/kernel.h>
  13
  14 #include "sh_pfc.h"
  15
  16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
  17
  18 #define CPU_ALL_GP(fn, sfx)     \
  19         PORT_GP_CFG_21(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),        \
  20         PORT_GP_CFG_25(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),        \
  21         PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS),  \
  22         PORT_GP_CFG_19(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
  23
  24 #define CPU_ALL_NOGP(fn)                                                                \
  25         PIN_NOGP_CFG(PRESETOUT0_N, "PRESETOUT0#", fn, SH_PFC_PIN_CFG_PULL_DOWN),        \
  26         PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
  27
  28 /*
  29  * F_() : just information
  30  * FM() : macro for FN_xxx / xxx_MARK
  31  */
  32
  33 /* GPSR0 */
  34 #define GPSR0_20        F_(IRQ3,        IP2SR0_19_16)
  35 #define GPSR0_19        F_(IRQ2,        IP2SR0_15_12)
  36 #define GPSR0_18        F_(IRQ1,        IP2SR0_11_8)
  37 #define GPSR0_17        F_(IRQ0,        IP2SR0_7_4)
  38 #define GPSR0_16        F_(MSIOF0_SS2,  IP2SR0_3_0)
  39 #define GPSR0_15        F_(MSIOF0_SS1,  IP1SR0_31_28)
  40 #define GPSR0_14        F_(MSIOF0_SCK,  IP1SR0_27_24)
  41 #define GPSR0_13        F_(MSIOF0_TXD,  IP1SR0_23_20)
  42 #define GPSR0_12        F_(MSIOF0_RXD,  IP1SR0_19_16)
  43 #define GPSR0_11        F_(MSIOF0_SYNC, IP1SR0_15_12)
  44 #define GPSR0_10        F_(CTS0_N,      IP1SR0_11_8)
  45 #define GPSR0_9         F_(RTS0_N,      IP1SR0_7_4)
  46 #define GPSR0_8         F_(SCK0,        IP1SR0_3_0)
  47 #define GPSR0_7         F_(TX0,         IP0SR0_31_28)
  48 #define GPSR0_6         F_(RX0,         IP0SR0_27_24)
  49 #define GPSR0_5         F_(HRTS0_N,     IP0SR0_23_20)
  50 #define GPSR0_4         F_(HCTS0_N,     IP0SR0_19_16)
  51 #define GPSR0_3         F_(HTX0,        IP0SR0_15_12)
  52 #define GPSR0_2         F_(HRX0,        IP0SR0_11_8)
  53 #define GPSR0_1         F_(HSCK0,       IP0SR0_7_4)
  54 #define GPSR0_0         F_(SCIF_CLK,    IP0SR0_3_0)
  55
  56 /* GPSR1 */
  57 #define GPSR1_24        FM(SD_WP)
  58 #define GPSR1_23        FM(SD_CD)
  59 #define GPSR1_22        FM(MMC_SD_CMD)
  60 #define GPSR1_21        FM(MMC_D7)
  61 #define GPSR1_20        FM(MMC_DS)
  62 #define GPSR1_19        FM(MMC_D6)
  63 #define GPSR1_18        FM(MMC_D4)
  64 #define GPSR1_17        FM(MMC_D5)
  65 #define GPSR1_16        FM(MMC_SD_D3)
  66 #define GPSR1_15        FM(MMC_SD_D2)
  67 #define GPSR1_14        FM(MMC_SD_D1)
  68 #define GPSR1_13        FM(MMC_SD_D0)
  69 #define GPSR1_12        FM(MMC_SD_CLK)
  70 #define GPSR1_11        FM(GP1_11)
  71 #define GPSR1_10        FM(GP1_10)
  72 #define GPSR1_9         FM(GP1_09)
  73 #define GPSR1_8         FM(GP1_08)
  74 #define GPSR1_7         F_(GP1_07,      IP0SR1_31_28)
  75 #define GPSR1_6         F_(GP1_06,      IP0SR1_27_24)
  76 #define GPSR1_5         F_(GP1_05,      IP0SR1_23_20)
  77 #define GPSR1_4         F_(GP1_04,      IP0SR1_19_16)
  78 #define GPSR1_3         F_(GP1_03,      IP0SR1_15_12)
  79 #define GPSR1_2         F_(GP1_02,      IP0SR1_11_8)
  80 #define GPSR1_1         F_(GP1_01,      IP0SR1_7_4)
  81 #define GPSR1_0         F_(GP1_00,      IP0SR1_3_0)
  82
  83 /* GPSR2 */
  84 #define GPSR2_16        FM(PCIE1_CLKREQ_N)
  85 #define GPSR2_15        FM(PCIE0_CLKREQ_N)
  86 #define GPSR2_14        FM(QSPI0_IO3)
  87 #define GPSR2_13        FM(QSPI0_SSL)
  88 #define GPSR2_12        FM(QSPI0_MISO_IO1)
  89 #define GPSR2_11        FM(QSPI0_IO2)
  90 #define GPSR2_10        FM(QSPI0_SPCLK)
  91 #define GPSR2_9         FM(QSPI0_MOSI_IO0)
  92 #define GPSR2_8         FM(QSPI1_SPCLK)
  93 #define GPSR2_7         FM(QSPI1_MOSI_IO0)
  94 #define GPSR2_6         FM(QSPI1_IO2)
  95 #define GPSR2_5         FM(QSPI1_MISO_IO1)
  96 #define GPSR2_4         FM(QSPI1_IO3)
  97 #define GPSR2_3         FM(QSPI1_SSL)
  98 #define GPSR2_2         FM(RPC_RESET_N)
  99 #define GPSR2_1         FM(RPC_WP_N)
 100 #define GPSR2_0         FM(RPC_INT_N)
 101
 102 /* GPSR3 */
 103 #define GPSR3_18        FM(TSN0_AVTP_CAPTURE_B)
 104 #define GPSR3_17        FM(TSN0_AVTP_MATCH_B)
 105 #define GPSR3_16        FM(TSN0_AVTP_PPS)
 106 #define GPSR3_15        FM(TSN1_AVTP_CAPTURE_B)
 107 #define GPSR3_14        FM(TSN1_AVTP_MATCH_B)
 108 #define GPSR3_13        FM(TSN1_AVTP_PPS)
 109 #define GPSR3_12        FM(TSN0_MAGIC_B)
 110 #define GPSR3_11        FM(TSN1_PHY_INT_B)
 111 #define GPSR3_10        FM(TSN0_PHY_INT_B)
 112 #define GPSR3_9         FM(TSN2_PHY_INT_B)
 113 #define GPSR3_8         FM(TSN0_LINK_B)
 114 #define GPSR3_7         FM(TSN2_LINK_B)
 115 #define GPSR3_6         FM(TSN1_LINK_B)
 116 #define GPSR3_5         FM(TSN1_MDC_B)
 117 #define GPSR3_4         FM(TSN0_MDC_B)
 118 #define GPSR3_3         FM(TSN2_MDC_B)
 119 #define GPSR3_2         FM(TSN0_MDIO_B)
 120 #define GPSR3_1         FM(TSN2_MDIO_B)
 121 #define GPSR3_0         FM(TSN1_MDIO_B)
 122
 123 /* IP0SR0 */            /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */         /* 5 */                 /* 6 */                 /* 7 - F */
 124 #define IP0SR0_3_0      FM(SCIF_CLK)            F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 125 #define IP0SR0_7_4      FM(HSCK0)               FM(SCK3)                FM(MSIOF3_SCK)          F_(0, 0)                F_(0, 0)        FM(TSN0_AVTP_CAPTURE_A) F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 126 #define IP0SR0_11_8     FM(HRX0)                FM(RX3)                 FM(MSIOF3_RXD)          F_(0, 0)                F_(0, 0)        FM(TSN0_AVTP_MATCH_A)   F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 127 #define IP0SR0_15_12    FM(HTX0)                FM(TX3)                 FM(MSIOF3_TXD)          F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 128 #define IP0SR0_19_16    FM(HCTS0_N)             FM(CTS3_N)              FM(MSIOF3_SS1)          F_(0, 0)                F_(0, 0)        FM(TSN0_MDC_A)          F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 129 #define IP0SR0_23_20    FM(HRTS0_N)             FM(RTS3_N)              FM(MSIOF3_SS2)          F_(0, 0)                F_(0, 0)        FM(TSN0_MDIO_A)         F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 130 #define IP0SR0_27_24    FM(RX0)                 FM(HRX1)                F_(0, 0)                FM(MSIOF1_RXD)          F_(0, 0)        FM(TSN1_AVTP_MATCH_A)   F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 131 #define IP0SR0_31_28    FM(TX0)                 FM(HTX1)                F_(0, 0)                FM(MSIOF1_TXD)          F_(0, 0)        FM(TSN1_AVTP_CAPTURE_A) F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 132 /* IP1SR0 */            /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */         /* 5 */                 /* 6 */                 /* 7 - F */
 133 #define IP1SR0_3_0      FM(SCK0)                FM(HSCK1)               F_(0, 0)                FM(MSIOF1_SCK)          F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 134 #define IP1SR0_7_4      FM(RTS0_N)              FM(HRTS1_N)             FM(MSIOF3_SYNC)         F_(0, 0)                F_(0, 0)        FM(TSN1_MDIO_A)         F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 135 #define IP1SR0_11_8     FM(CTS0_N)              FM(HCTS1_N)             F_(0, 0)                FM(MSIOF1_SYNC)         F_(0, 0)        FM(TSN1_MDC_A)          F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 136 #define IP1SR0_15_12    FM(MSIOF0_SYNC)         FM(HCTS3_N)             FM(CTS1_N)              FM(IRQ4)                F_(0, 0)        FM(TSN0_LINK_A)         F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 137 #define IP1SR0_19_16    FM(MSIOF0_RXD)          FM(HRX3)                FM(RX1)                 F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 138 #define IP1SR0_23_20    FM(MSIOF0_TXD)          FM(HTX3)                FM(TX1)                 F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 139 #define IP1SR0_27_24    FM(MSIOF0_SCK)          FM(HSCK3)               FM(SCK1)                F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 140 #define IP1SR0_31_28    FM(MSIOF0_SS1)          FM(HRTS3_N)             FM(RTS1_N)              FM(IRQ5)                F_(0, 0)        FM(TSN1_LINK_A)         F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 141 /* IP2SR0 */            /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */         /* 5 */                 /* 6 */                 /* 7 - F */
 142 #define IP2SR0_3_0      FM(MSIOF0_SS2)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(TSN2_LINK_A)         F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 143 #define IP2SR0_7_4      FM(IRQ0)                F_(0, 0)                F_(0, 0)                FM(MSIOF1_SS1)          F_(0, 0)        FM(TSN0_MAGIC_A)        F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 144 #define IP2SR0_11_8     FM(IRQ1)                F_(0, 0)                F_(0, 0)                FM(MSIOF1_SS2)          F_(0, 0)        FM(TSN0_PHY_INT_A)      F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 145 #define IP2SR0_15_12    FM(IRQ2)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(TSN1_PHY_INT_A)      F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 146 #define IP2SR0_19_16    FM(IRQ3)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(TSN2_PHY_INT_A)      F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 147 #define IP2SR0_23_20    F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 148 #define IP2SR0_27_24    F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 149 #define IP2SR0_31_28    F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 150
 151 /* IP0SR1 */            /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */         /* 5 */                 /* 6 */                 /* 7 - F */
 152 #define IP0SR1_3_0      FM(GP1_00)              FM(TCLK1)               FM(HSCK2)               F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 153 #define IP0SR1_7_4      FM(GP1_01)              FM(TCLK4)               FM(HRX2)                F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 154 #define IP0SR1_11_8     FM(GP1_02)              F_(0, 0)                FM(HTX2)                FM(MSIOF2_SS1)          F_(0, 0)        FM(TSN2_MDC_A)          F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 155 #define IP0SR1_15_12    FM(GP1_03)              FM(TCLK2)               FM(HCTS2_N)             FM(MSIOF2_SS2)          FM(CTS4_N)      FM(TSN2_MDIO_A)         F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 156 #define IP0SR1_19_16    FM(GP1_04)              FM(TCLK3)               FM(HRTS2_N)             FM(MSIOF2_SYNC)         FM(RTS4_N)      F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 157 #define IP0SR1_23_20    FM(GP1_05)              FM(MSIOF2_SCK)          FM(SCK4)                F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 158 #define IP0SR1_27_24    FM(GP1_06)              FM(MSIOF2_RXD)          FM(RX4)                 F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 159 #define IP0SR1_31_28    FM(GP1_07)              FM(MSIOF2_TXD)          FM(TX4)                 F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)                F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 160
 161 #define PINMUX_GPSR     \
 162                 GPSR1_24                                        \
 163                 GPSR1_23                                        \
 164                 GPSR1_22                                        \
 165                 GPSR1_21                                        \
 166 GPSR0_20        GPSR1_20                                        \
 167 GPSR0_19        GPSR1_19                                        \
 168 GPSR0_18        GPSR1_18                        GPSR3_18        \
 169 GPSR0_17        GPSR1_17                        GPSR3_17        \
 170 GPSR0_16        GPSR1_16        GPSR2_16        GPSR3_16        \
 171 GPSR0_15        GPSR1_15        GPSR2_15        GPSR3_15        \
 172 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        \
 173 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        \
 174 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        \
 175 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        \
 176 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        \
 177 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         \
 178 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         \
 179 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         \
 180 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         \
 181 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         \
 182 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         \
 183 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         \
 184 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         \
 185 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         \
 186 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0
 187
 188 #define PINMUX_IPSR     \
 189 \
 190 FM(IP0SR0_3_0)          IP0SR0_3_0      FM(IP1SR0_3_0)          IP1SR0_3_0      FM(IP2SR0_3_0)          IP2SR0_3_0      \
 191 FM(IP0SR0_7_4)          IP0SR0_7_4      FM(IP1SR0_7_4)          IP1SR0_7_4      FM(IP2SR0_7_4)          IP2SR0_7_4      \
 192 FM(IP0SR0_11_8)         IP0SR0_11_8     FM(IP1SR0_11_8)         IP1SR0_11_8     FM(IP2SR0_11_8)         IP2SR0_11_8     \
 193 FM(IP0SR0_15_12)        IP0SR0_15_12    FM(IP1SR0_15_12)        IP1SR0_15_12    FM(IP2SR0_15_12)        IP2SR0_15_12    \
 194 FM(IP0SR0_19_16)        IP0SR0_19_16    FM(IP1SR0_19_16)        IP1SR0_19_16    FM(IP2SR0_19_16)        IP2SR0_19_16    \
 195 FM(IP0SR0_23_20)        IP0SR0_23_20    FM(IP1SR0_23_20)        IP1SR0_23_20    FM(IP2SR0_23_20)        IP2SR0_23_20    \
 196 FM(IP0SR0_27_24)        IP0SR0_27_24    FM(IP1SR0_27_24)        IP1SR0_27_24    FM(IP2SR0_27_24)        IP2SR0_27_24    \
 197 FM(IP0SR0_31_28)        IP0SR0_31_28    FM(IP1SR0_31_28)        IP1SR0_31_28    FM(IP2SR0_31_28)        IP2SR0_31_28    \
 198 \
 199 FM(IP0SR1_3_0)          IP0SR1_3_0      \
 200 FM(IP0SR1_7_4)          IP0SR1_7_4      \
 201 FM(IP0SR1_11_8)         IP0SR1_11_8     \
 202 FM(IP0SR1_15_12)        IP0SR1_15_12    \
 203 FM(IP0SR1_19_16)        IP0SR1_19_16    \
 204 FM(IP0SR1_23_20)        IP0SR1_23_20    \
 205 FM(IP0SR1_27_24)        IP0SR1_27_24    \
 206 FM(IP0SR1_31_28)        IP0SR1_31_28
 207
 208 /* MOD_SEL1 */                  /* 0 */         /* 1 */         /* 2 */         /* 3 */
 209 #define MOD_SEL1_11_10          FM(SEL_I2C5_0)  F_(0, 0)        F_(0, 0)        FM(SEL_I2C5_3)
 210 #define MOD_SEL1_9_8            FM(SEL_I2C4_0)  F_(0, 0)        F_(0, 0)        FM(SEL_I2C4_3)
 211 #define MOD_SEL1_7_6            FM(SEL_I2C3_0)  F_(0, 0)        F_(0, 0)        FM(SEL_I2C3_3)
 212 #define MOD_SEL1_5_4            FM(SEL_I2C2_0)  F_(0, 0)        F_(0, 0)        FM(SEL_I2C2_3)
 213 #define MOD_SEL1_3_2            FM(SEL_I2C1_0)  F_(0, 0)        F_(0, 0)        FM(SEL_I2C1_3)
 214 #define MOD_SEL1_1_0            FM(SEL_I2C0_0)  F_(0, 0)        F_(0, 0)        FM(SEL_I2C0_3)
 215
 216 #define PINMUX_MOD_SELS \
 217 \
 218 MOD_SEL1_11_10 \
 219 MOD_SEL1_9_8 \
 220 MOD_SEL1_7_6 \
 221 MOD_SEL1_5_4 \
 222 MOD_SEL1_3_2 \
 223 MOD_SEL1_1_0
 224
 225 #define PINMUX_PHYS \
 226         FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \
 227         FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5)
 228
 229 enum {
 230         PINMUX_RESERVED = 0,
 231
 232         PINMUX_DATA_BEGIN,
 233         GP_ALL(DATA),
 234         PINMUX_DATA_END,
 235
 236 #define F_(x, y)
 237 #define FM(x)   FN_##x,
 238         PINMUX_FUNCTION_BEGIN,
 239         GP_ALL(FN),
 240         PINMUX_GPSR
 241         PINMUX_IPSR
 242         PINMUX_MOD_SELS
 243         PINMUX_FUNCTION_END,
 244 #undef F_
 245 #undef FM
 246
 247 #define F_(x, y)
 248 #define FM(x)   x##_MARK,
 249         PINMUX_MARK_BEGIN,
 250         PINMUX_GPSR
 251         PINMUX_IPSR
 252         PINMUX_MOD_SELS
 253         PINMUX_PHYS
 254         PINMUX_MARK_END,
 255 #undef F_
 256 #undef FM
 257 };
 258
 259 static const u16 pinmux_data[] = {
 260 /* Using GP_1_[0-9] requires disabling I2C in MOD_SEL1 */
 261 #define GP_1_0_FN       GP_1_0_FN,      FN_SEL_I2C0_0
 262 #define GP_1_1_FN       GP_1_1_FN,      FN_SEL_I2C0_0
 263 #define GP_1_2_FN       GP_1_2_FN,      FN_SEL_I2C1_0
 264 #define GP_1_3_FN       GP_1_3_FN,      FN_SEL_I2C1_0
 265 #define GP_1_4_FN       GP_1_4_FN,      FN_SEL_I2C2_0
 266 #define GP_1_5_FN       GP_1_5_FN,      FN_SEL_I2C2_0
 267 #define GP_1_6_FN       GP_1_6_FN,      FN_SEL_I2C3_0
 268 #define GP_1_7_FN       GP_1_7_FN,      FN_SEL_I2C3_0
 269 #define GP_1_8_FN       GP_1_8_FN,      FN_SEL_I2C4_0
 270 #define GP_1_9_FN       GP_1_9_FN,      FN_SEL_I2C4_0
 271         PINMUX_DATA_GP_ALL(),
 272 #undef GP_1_0_FN
 273 #undef GP_1_1_FN
 274 #undef GP_1_2_FN
 275 #undef GP_1_3_FN
 276 #undef GP_1_4_FN
 277 #undef GP_1_5_FN
 278 #undef GP_1_6_FN
 279 #undef GP_1_7_FN
 280 #undef GP_1_8_FN
 281 #undef GP_1_9_FN
 282
 283         PINMUX_SINGLE(SD_WP),
 284         PINMUX_SINGLE(SD_CD),
 285         PINMUX_SINGLE(MMC_SD_CMD),
 286         PINMUX_SINGLE(MMC_D7),
 287         PINMUX_SINGLE(MMC_DS),
 288         PINMUX_SINGLE(MMC_D6),
 289         PINMUX_SINGLE(MMC_D4),
 290         PINMUX_SINGLE(MMC_D5),
 291         PINMUX_SINGLE(MMC_SD_D3),
 292         PINMUX_SINGLE(MMC_SD_D2),
 293         PINMUX_SINGLE(MMC_SD_D1),
 294         PINMUX_SINGLE(MMC_SD_D0),
 295         PINMUX_SINGLE(MMC_SD_CLK),
 296         PINMUX_SINGLE(PCIE1_CLKREQ_N),
 297         PINMUX_SINGLE(PCIE0_CLKREQ_N),
 298         PINMUX_SINGLE(QSPI0_IO3),
 299         PINMUX_SINGLE(QSPI0_SSL),
 300         PINMUX_SINGLE(QSPI0_MISO_IO1),
 301         PINMUX_SINGLE(QSPI0_IO2),
 302         PINMUX_SINGLE(QSPI0_SPCLK),
 303         PINMUX_SINGLE(QSPI0_MOSI_IO0),
 304         PINMUX_SINGLE(QSPI1_SPCLK),
 305         PINMUX_SINGLE(QSPI1_MOSI_IO0),
 306         PINMUX_SINGLE(QSPI1_IO2),
 307         PINMUX_SINGLE(QSPI1_MISO_IO1),
 308         PINMUX_SINGLE(QSPI1_IO3),
 309         PINMUX_SINGLE(QSPI1_SSL),
 310         PINMUX_SINGLE(RPC_RESET_N),
 311         PINMUX_SINGLE(RPC_WP_N),
 312         PINMUX_SINGLE(RPC_INT_N),
 313
 314         PINMUX_SINGLE(TSN0_AVTP_CAPTURE_B),
 315         PINMUX_SINGLE(TSN0_AVTP_MATCH_B),
 316         PINMUX_SINGLE(TSN0_AVTP_PPS),
 317         PINMUX_SINGLE(TSN1_AVTP_CAPTURE_B),
 318         PINMUX_SINGLE(TSN1_AVTP_MATCH_B),
 319         PINMUX_SINGLE(TSN1_AVTP_PPS),
 320         PINMUX_SINGLE(TSN0_MAGIC_B),
 321         PINMUX_SINGLE(TSN1_PHY_INT_B),
 322         PINMUX_SINGLE(TSN0_PHY_INT_B),
 323         PINMUX_SINGLE(TSN2_PHY_INT_B),
 324         PINMUX_SINGLE(TSN0_LINK_B),
 325         PINMUX_SINGLE(TSN2_LINK_B),
 326         PINMUX_SINGLE(TSN1_LINK_B),
 327         PINMUX_SINGLE(TSN1_MDC_B),
 328         PINMUX_SINGLE(TSN0_MDC_B),
 329         PINMUX_SINGLE(TSN2_MDC_B),
 330         PINMUX_SINGLE(TSN0_MDIO_B),
 331         PINMUX_SINGLE(TSN2_MDIO_B),
 332         PINMUX_SINGLE(TSN1_MDIO_B),
 333
 334         /* IP0SR0 */
 335         PINMUX_IPSR_GPSR(IP0SR0_3_0,    SCIF_CLK),
 336
 337         PINMUX_IPSR_GPSR(IP0SR0_7_4,    HSCK0),
 338         PINMUX_IPSR_GPSR(IP0SR0_7_4,    SCK3),
 339         PINMUX_IPSR_GPSR(IP0SR0_7_4,    MSIOF3_SCK),
 340         PINMUX_IPSR_GPSR(IP0SR0_7_4,    TSN0_AVTP_CAPTURE_A),
 341
 342         PINMUX_IPSR_GPSR(IP0SR0_11_8,   HRX0),
 343         PINMUX_IPSR_GPSR(IP0SR0_11_8,   RX3),
 344         PINMUX_IPSR_GPSR(IP0SR0_11_8,   MSIOF3_RXD),
 345         PINMUX_IPSR_GPSR(IP0SR0_11_8,   TSN0_AVTP_MATCH_A),
 346
 347         PINMUX_IPSR_GPSR(IP0SR0_15_12,  HTX0),
 348         PINMUX_IPSR_GPSR(IP0SR0_15_12,  TX3),
 349         PINMUX_IPSR_GPSR(IP0SR0_15_12,  MSIOF3_TXD),
 350
 351         PINMUX_IPSR_GPSR(IP0SR0_19_16,  HCTS0_N),
 352         PINMUX_IPSR_GPSR(IP0SR0_19_16,  CTS3_N),
 353         PINMUX_IPSR_GPSR(IP0SR0_19_16,  MSIOF3_SS1),
 354         PINMUX_IPSR_GPSR(IP0SR0_19_16,  TSN0_MDC_A),
 355
 356         PINMUX_IPSR_GPSR(IP0SR0_23_20,  HRTS0_N),
 357         PINMUX_IPSR_GPSR(IP0SR0_23_20,  RTS3_N),
 358         PINMUX_IPSR_GPSR(IP0SR0_23_20,  MSIOF3_SS2),
 359         PINMUX_IPSR_GPSR(IP0SR0_23_20,  TSN0_MDIO_A),
 360
 361         PINMUX_IPSR_GPSR(IP0SR0_27_24,  RX0),
 362         PINMUX_IPSR_GPSR(IP0SR0_27_24,  HRX1),
 363         PINMUX_IPSR_GPSR(IP0SR0_27_24,  MSIOF1_RXD),
 364         PINMUX_IPSR_GPSR(IP0SR0_27_24,  TSN1_AVTP_MATCH_A),
 365
 366         PINMUX_IPSR_GPSR(IP0SR0_31_28,  TX0),
 367         PINMUX_IPSR_GPSR(IP0SR0_31_28,  HTX1),
 368         PINMUX_IPSR_GPSR(IP0SR0_31_28,  MSIOF1_TXD),
 369         PINMUX_IPSR_GPSR(IP0SR0_31_28,  TSN1_AVTP_CAPTURE_A),
 370
 371         /* IP1SR0 */
 372         PINMUX_IPSR_GPSR(IP1SR0_3_0,    SCK0),
 373         PINMUX_IPSR_GPSR(IP1SR0_3_0,    HSCK1),
 374         PINMUX_IPSR_GPSR(IP1SR0_3_0,    MSIOF1_SCK),
 375
 376         PINMUX_IPSR_GPSR(IP1SR0_7_4,    RTS0_N),
 377         PINMUX_IPSR_GPSR(IP1SR0_7_4,    HRTS1_N),
 378         PINMUX_IPSR_GPSR(IP1SR0_7_4,    MSIOF3_SYNC),
 379         PINMUX_IPSR_GPSR(IP1SR0_7_4,    TSN1_MDIO_A),
 380
 381         PINMUX_IPSR_GPSR(IP1SR0_11_8,   CTS0_N),
 382         PINMUX_IPSR_GPSR(IP1SR0_11_8,   HCTS1_N),
 383         PINMUX_IPSR_GPSR(IP1SR0_11_8,   MSIOF1_SYNC),
 384         PINMUX_IPSR_GPSR(IP1SR0_11_8,   TSN1_MDC_A),
 385
 386         PINMUX_IPSR_GPSR(IP1SR0_15_12,  MSIOF0_SYNC),
 387         PINMUX_IPSR_GPSR(IP1SR0_15_12,  HCTS3_N),
 388         PINMUX_IPSR_GPSR(IP1SR0_15_12,  CTS1_N),
 389         PINMUX_IPSR_GPSR(IP1SR0_15_12,  IRQ4),
 390         PINMUX_IPSR_GPSR(IP1SR0_15_12,  TSN0_LINK_A),
 391
 392         PINMUX_IPSR_GPSR(IP1SR0_19_16,  MSIOF0_RXD),
 393         PINMUX_IPSR_GPSR(IP1SR0_19_16,  HRX3),
 394         PINMUX_IPSR_GPSR(IP1SR0_19_16,  RX1),
 395
 396         PINMUX_IPSR_GPSR(IP1SR0_23_20,  MSIOF0_TXD),
 397         PINMUX_IPSR_GPSR(IP1SR0_23_20,  HTX3),
 398         PINMUX_IPSR_GPSR(IP1SR0_23_20,  TX1),
 399
 400         PINMUX_IPSR_GPSR(IP1SR0_27_24,  MSIOF0_SCK),
 401         PINMUX_IPSR_GPSR(IP1SR0_27_24,  HSCK3),
 402         PINMUX_IPSR_GPSR(IP1SR0_27_24,  SCK1),
 403
 404         PINMUX_IPSR_GPSR(IP1SR0_31_28,  MSIOF0_SS1),
 405         PINMUX_IPSR_GPSR(IP1SR0_31_28,  HRTS3_N),
 406         PINMUX_IPSR_GPSR(IP1SR0_31_28,  RTS1_N),
 407         PINMUX_IPSR_GPSR(IP1SR0_31_28,  IRQ5),
 408         PINMUX_IPSR_GPSR(IP1SR0_31_28,  TSN1_LINK_A),
 409
 410         /* IP2SR0 */
 411         PINMUX_IPSR_GPSR(IP2SR0_3_0,    MSIOF0_SS2),
 412         PINMUX_IPSR_GPSR(IP2SR0_3_0,    TSN2_LINK_A),
 413
 414         PINMUX_IPSR_GPSR(IP2SR0_7_4,    IRQ0),
 415         PINMUX_IPSR_GPSR(IP2SR0_7_4,    MSIOF1_SS1),
 416         PINMUX_IPSR_GPSR(IP2SR0_7_4,    TSN0_MAGIC_A),
 417
 418         PINMUX_IPSR_GPSR(IP2SR0_11_8,   IRQ1),
 419         PINMUX_IPSR_GPSR(IP2SR0_11_8,   MSIOF1_SS2),
 420         PINMUX_IPSR_GPSR(IP2SR0_11_8,   TSN0_PHY_INT_A),
 421
 422         PINMUX_IPSR_GPSR(IP2SR0_15_12,  IRQ2),
 423         PINMUX_IPSR_GPSR(IP2SR0_15_12,  TSN1_PHY_INT_A),
 424
 425         PINMUX_IPSR_GPSR(IP2SR0_19_16,  IRQ3),
 426         PINMUX_IPSR_GPSR(IP2SR0_19_16,  TSN2_PHY_INT_A),
 427
 428         /* IP0SR1 */
 429         /* GP1_00 = SCL0 */
 430         PINMUX_IPSR_MSEL(IP0SR1_3_0,    GP1_00,         SEL_I2C0_0),
 431         PINMUX_IPSR_MSEL(IP0SR1_3_0,    TCLK1,          SEL_I2C0_0),
 432         PINMUX_IPSR_MSEL(IP0SR1_3_0,    HSCK2,          SEL_I2C0_0),
 433         PINMUX_IPSR_PHYS(IP0SR1_3_0,    SCL0,           SEL_I2C0_3),
 434
 435         /* GP1_01 = SDA0 */
 436         PINMUX_IPSR_MSEL(IP0SR1_7_4,    GP1_01,         SEL_I2C0_0),
 437         PINMUX_IPSR_MSEL(IP0SR1_7_4,    TCLK4,          SEL_I2C0_0),
 438         PINMUX_IPSR_MSEL(IP0SR1_7_4,    HRX2,           SEL_I2C0_0),
 439         PINMUX_IPSR_PHYS(IP0SR1_7_4,    SDA0,           SEL_I2C0_3),
 440
 441         /* GP1_02 = SCL1 */
 442         PINMUX_IPSR_MSEL(IP0SR1_11_8,   GP1_02,         SEL_I2C1_0),
 443         PINMUX_IPSR_MSEL(IP0SR1_11_8,   HTX2,           SEL_I2C1_0),
 444         PINMUX_IPSR_MSEL(IP0SR1_11_8,   MSIOF2_SS1,     SEL_I2C1_0),
 445         PINMUX_IPSR_MSEL(IP0SR1_11_8,   TSN2_MDC_A,     SEL_I2C1_0),
 446         PINMUX_IPSR_PHYS(IP0SR1_11_8,   SCL1,           SEL_I2C1_3),
 447
 448         /* GP1_03 = SDA1 */
 449         PINMUX_IPSR_MSEL(IP0SR1_15_12,  GP1_03,         SEL_I2C1_0),
 450         PINMUX_IPSR_MSEL(IP0SR1_15_12,  TCLK2,          SEL_I2C1_0),
 451         PINMUX_IPSR_MSEL(IP0SR1_15_12,  HCTS2_N,        SEL_I2C1_0),
 452         PINMUX_IPSR_MSEL(IP0SR1_15_12,  MSIOF2_SS2,     SEL_I2C1_0),
 453         PINMUX_IPSR_MSEL(IP0SR1_15_12,  CTS4_N,         SEL_I2C1_0),
 454         PINMUX_IPSR_MSEL(IP0SR1_15_12,  TSN2_MDIO_A,    SEL_I2C1_0),
 455         PINMUX_IPSR_PHYS(IP0SR1_15_12,  SDA1,           SEL_I2C1_3),
 456
 457         /* GP1_04 = SCL2 */
 458         PINMUX_IPSR_MSEL(IP0SR1_19_16,  GP1_04,         SEL_I2C2_0),
 459         PINMUX_IPSR_MSEL(IP0SR1_19_16,  TCLK3,          SEL_I2C2_0),
 460         PINMUX_IPSR_MSEL(IP0SR1_19_16,  HRTS2_N,        SEL_I2C2_0),
 461         PINMUX_IPSR_MSEL(IP0SR1_19_16,  MSIOF2_SYNC,    SEL_I2C2_0),
 462         PINMUX_IPSR_MSEL(IP0SR1_19_16,  RTS4_N,         SEL_I2C2_0),
 463         PINMUX_IPSR_PHYS(IP0SR1_19_16,  SCL2,           SEL_I2C2_3),
 464
 465         /* GP1_05 = SDA2 */
 466         PINMUX_IPSR_MSEL(IP0SR1_23_20,  GP1_05,         SEL_I2C2_0),
 467         PINMUX_IPSR_MSEL(IP0SR1_23_20,  MSIOF2_SCK,     SEL_I2C2_0),
 468         PINMUX_IPSR_MSEL(IP0SR1_23_20,  SCK4,           SEL_I2C2_0),
 469         PINMUX_IPSR_PHYS(IP0SR1_23_20,  SDA2,           SEL_I2C2_3),
 470
 471         /* GP1_06 = SCL3 */
 472         PINMUX_IPSR_MSEL(IP0SR1_27_24,  GP1_06,         SEL_I2C3_0),
 473         PINMUX_IPSR_MSEL(IP0SR1_27_24,  MSIOF2_RXD,     SEL_I2C3_0),
 474         PINMUX_IPSR_MSEL(IP0SR1_27_24,  RX4,            SEL_I2C3_0),
 475         PINMUX_IPSR_PHYS(IP0SR1_27_24,  SCL3,           SEL_I2C3_3),
 476
 477         /* GP1_07 = SDA3 */
 478         PINMUX_IPSR_MSEL(IP0SR1_31_28,  GP1_07,         SEL_I2C3_0),
 479         PINMUX_IPSR_MSEL(IP0SR1_31_28,  MSIOF2_TXD,     SEL_I2C3_0),
 480         PINMUX_IPSR_MSEL(IP0SR1_31_28,  TX4,            SEL_I2C3_0),
 481         PINMUX_IPSR_PHYS(IP0SR1_31_28,  SDA3,           SEL_I2C3_3),
 482
 483         /* GP1_08 = SCL4 */
 484         PINMUX_IPSR_NOGM(0,             GP1_08,         SEL_I2C4_0),
 485         PINMUX_IPSR_NOFN(GP1_08,        SCL4,           SEL_I2C4_3),
 486
 487         /* GP1_09 = SDA4 */
 488         PINMUX_IPSR_NOGM(0,             GP1_09,         SEL_I2C4_0),
 489         PINMUX_IPSR_NOFN(GP1_09,        SDA4,           SEL_I2C4_3),
 490
 491         /* GP1_10 = SCL5 */
 492         PINMUX_IPSR_NOGM(0,             GP1_10,         SEL_I2C5_0),
 493         PINMUX_IPSR_NOFN(GP1_10,        SCL5,           SEL_I2C5_3),
 494
 495         /* GP1_11 = SDA5 */
 496         PINMUX_IPSR_NOGM(0,             GP1_11,         SEL_I2C5_0),
 497         PINMUX_IPSR_NOFN(GP1_11,        SDA5,           SEL_I2C5_3),
 498 };
 499
 500 /*
 501  * Pins not associated with a GPIO port.
 502  */
 503 enum {
 504         GP_ASSIGN_LAST(),
 505         NOGP_ALL(),
 506 };
 507
 508 static const struct sh_pfc_pin pinmux_pins[] = {
 509         PINMUX_GPIO_GP_ALL(),
 510 };
 511
 512 /* - HSCIF0 ----------------------------------------------------------------- */
 513 static const unsigned int hscif0_data_pins[] = {
 514         /* HRX0, HTX0 */
 515         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
 516 };
 517 static const unsigned int hscif0_data_mux[] = {
 518         HRX0_MARK, HTX0_MARK,
 519 };
 520 static const unsigned int hscif0_clk_pins[] = {
 521         /* HSCK0 */
 522         RCAR_GP_PIN(0, 1),
 523 };
 524 static const unsigned int hscif0_clk_mux[] = {
 525         HSCK0_MARK,
 526 };
 527 static const unsigned int hscif0_ctrl_pins[] = {
 528         /* HRTS0#, HCTS0# */
 529         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
 530 };
 531 static const unsigned int hscif0_ctrl_mux[] = {
 532         HRTS0_N_MARK, HCTS0_N_MARK,
 533 };
 534
 535 /* - HSCIF1 ----------------------------------------------------------------- */
 536 static const unsigned int hscif1_data_pins[] = {
 537         /* HRX1, HTX1 */
 538         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 539 };
 540 static const unsigned int hscif1_data_mux[] = {
 541         HRX1_MARK, HTX1_MARK,
 542 };
 543 static const unsigned int hscif1_clk_pins[] = {
 544         /* HSCK1 */
 545         RCAR_GP_PIN(0, 8),
 546 };
 547 static const unsigned int hscif1_clk_mux[] = {
 548         HSCK1_MARK,
 549 };
 550 static const unsigned int hscif1_ctrl_pins[] = {
 551         /* HRTS1#, HCTS1# */
 552         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
 553 };
 554 static const unsigned int hscif1_ctrl_mux[] = {
 555         HRTS1_N_MARK, HCTS1_N_MARK,
 556 };
 557
 558 /* - HSCIF2 ----------------------------------------------------------------- */
 559 static const unsigned int hscif2_data_pins[] = {
 560         /* HRX2, HTX2 */
 561         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
 562 };
 563 static const unsigned int hscif2_data_mux[] = {
 564         HRX2_MARK, HTX2_MARK,
 565 };
 566 static const unsigned int hscif2_clk_pins[] = {
 567         /* HSCK2 */
 568         RCAR_GP_PIN(1, 0),
 569 };
 570 static const unsigned int hscif2_clk_mux[] = {
 571         HSCK2_MARK,
 572 };
 573 static const unsigned int hscif2_ctrl_pins[] = {
 574         /* HRTS2#, HCTS2# */
 575         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
 576 };
 577 static const unsigned int hscif2_ctrl_mux[] = {
 578         HRTS2_N_MARK, HCTS2_N_MARK,
 579 };
 580
 581 /* - HSCIF3 ----------------------------------------------------------------- */
 582 static const unsigned int hscif3_data_pins[] = {
 583         /* HRX3, HTX3 */
 584         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
 585 };
 586 static const unsigned int hscif3_data_mux[] = {
 587         HRX3_MARK, HTX3_MARK,
 588 };
 589 static const unsigned int hscif3_clk_pins[] = {
 590         /* HSCK3 */
 591         RCAR_GP_PIN(0, 14),
 592 };
 593 static const unsigned int hscif3_clk_mux[] = {
 594         HSCK3_MARK,
 595 };
 596 static const unsigned int hscif3_ctrl_pins[] = {
 597         /* HRTS3#, HCTS3# */
 598         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
 599 };
 600 static const unsigned int hscif3_ctrl_mux[] = {
 601         HRTS3_N_MARK, HCTS3_N_MARK,
 602 };
 603
 604 /* - I2C0 ------------------------------------------------------------------- */
 605 static const unsigned int i2c0_pins[] = {
 606         /* SDA0, SCL0 */
 607         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
 608 };
 609 static const unsigned int i2c0_mux[] = {
 610         SDA0_MARK, SCL0_MARK,
 611 };
 612
 613 /* - I2C1 ------------------------------------------------------------------- */
 614 static const unsigned int i2c1_pins[] = {
 615         /* SDA1, SCL1 */
 616         RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
 617 };
 618 static const unsigned int i2c1_mux[] = {
 619         SDA1_MARK, SCL1_MARK,
 620 };
 621
 622 /* - I2C2 ------------------------------------------------------------------- */
 623 static const unsigned int i2c2_pins[] = {
 624         /* SDA2, SCL2 */
 625         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4),
 626 };
 627 static const unsigned int i2c2_mux[] = {
 628         SDA2_MARK, SCL2_MARK,
 629 };
 630
 631 /* - I2C3 ------------------------------------------------------------------- */
 632 static const unsigned int i2c3_pins[] = {
 633         /* SDA3, SCL3 */
 634         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
 635 };
 636 static const unsigned int i2c3_mux[] = {
 637         SDA3_MARK, SCL3_MARK,
 638 };
 639
 640 /* - I2C4 ------------------------------------------------------------------- */
 641 static const unsigned int i2c4_pins[] = {
 642         /* SDA4, SCL4 */
 643         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
 644 };
 645 static const unsigned int i2c4_mux[] = {
 646         SDA4_MARK, SCL4_MARK,
 647 };
 648
 649 /* - I2C5 ------------------------------------------------------------------- */
 650 static const unsigned int i2c5_pins[] = {
 651         /* SDA5, SCL5 */
 652         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
 653 };
 654 static const unsigned int i2c5_mux[] = {
 655         SDA5_MARK, SCL5_MARK,
 656 };
 657
 658
 659 /* - INTC-EX ---------------------------------------------------------------- */
 660 static const unsigned int intc_ex_irq0_pins[] = {
 661         /* IRQ0 */
 662         RCAR_GP_PIN(0, 17),
 663 };
 664 static const unsigned int intc_ex_irq0_mux[] = {
 665         IRQ0_MARK,
 666 };
 667 static const unsigned int intc_ex_irq1_pins[] = {
 668         /* IRQ1 */
 669         RCAR_GP_PIN(0, 18),
 670 };
 671 static const unsigned int intc_ex_irq1_mux[] = {
 672         IRQ1_MARK,
 673 };
 674 static const unsigned int intc_ex_irq2_pins[] = {
 675         /* IRQ2 */
 676         RCAR_GP_PIN(0, 19),
 677 };
 678 static const unsigned int intc_ex_irq2_mux[] = {
 679         IRQ2_MARK,
 680 };
 681 static const unsigned int intc_ex_irq3_pins[] = {
 682         /* IRQ3 */
 683         RCAR_GP_PIN(0, 20),
 684 };
 685 static const unsigned int intc_ex_irq3_mux[] = {
 686         IRQ3_MARK,
 687 };
 688 static const unsigned int intc_ex_irq4_pins[] = {
 689         /* IRQ4 */
 690         RCAR_GP_PIN(0, 11),
 691 };
 692 static const unsigned int intc_ex_irq4_mux[] = {
 693         IRQ4_MARK,
 694 };
 695 static const unsigned int intc_ex_irq5_pins[] = {
 696         /* IRQ5 */
 697         RCAR_GP_PIN(0, 15),
 698 };
 699 static const unsigned int intc_ex_irq5_mux[] = {
 700         IRQ5_MARK,
 701 };
 702
 703 /* - MMC -------------------------------------------------------------------- */
 704 static const unsigned int mmc_data_pins[] = {
 705         /* MMC_SD_D[0:3], MMC_D[4:7] */
 706         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
 707         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
 708         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
 709         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 21),
 710 };
 711 static const unsigned int mmc_data_mux[] = {
 712         MMC_SD_D0_MARK, MMC_SD_D1_MARK,
 713         MMC_SD_D2_MARK, MMC_SD_D3_MARK,
 714         MMC_D4_MARK, MMC_D5_MARK,
 715         MMC_D6_MARK, MMC_D7_MARK,
 716 };
 717 static const unsigned int mmc_ctrl_pins[] = {
 718         /* MMC_SD_CLK, MMC_SD_CMD */
 719         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 22),
 720 };
 721 static const unsigned int mmc_ctrl_mux[] = {
 722         MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
 723 };
 724 static const unsigned int mmc_cd_pins[] = {
 725         /* SD_CD */
 726         RCAR_GP_PIN(1, 23),
 727 };
 728 static const unsigned int mmc_cd_mux[] = {
 729         SD_CD_MARK,
 730 };
 731 static const unsigned int mmc_wp_pins[] = {
 732         /* SD_WP */
 733         RCAR_GP_PIN(1, 24),
 734 };
 735 static const unsigned int mmc_wp_mux[] = {
 736         SD_WP_MARK,
 737 };
 738 static const unsigned int mmc_ds_pins[] = {
 739         /* MMC_DS */
 740         RCAR_GP_PIN(1, 20),
 741 };
 742 static const unsigned int mmc_ds_mux[] = {
 743         MMC_DS_MARK,
 744 };
 745
 746 /* - MSIOF0 ----------------------------------------------------------------- */
 747 static const unsigned int msiof0_clk_pins[] = {
 748         /* MSIOF0_SCK */
 749         RCAR_GP_PIN(0, 14),
 750 };
 751 static const unsigned int msiof0_clk_mux[] = {
 752         MSIOF0_SCK_MARK,
 753 };
 754 static const unsigned int msiof0_sync_pins[] = {
 755         /* MSIOF0_SYNC */
 756         RCAR_GP_PIN(0, 11),
 757 };
 758 static const unsigned int msiof0_sync_mux[] = {
 759         MSIOF0_SYNC_MARK,
 760 };
 761 static const unsigned int msiof0_ss1_pins[] = {
 762         /* MSIOF0_SS1 */
 763         RCAR_GP_PIN(0, 15),
 764 };
 765 static const unsigned int msiof0_ss1_mux[] = {
 766         MSIOF0_SS1_MARK,
 767 };
 768 static const unsigned int msiof0_ss2_pins[] = {
 769         /* MSIOF0_SS2 */
 770         RCAR_GP_PIN(0, 16),
 771 };
 772 static const unsigned int msiof0_ss2_mux[] = {
 773         MSIOF0_SS2_MARK,
 774 };
 775 static const unsigned int msiof0_txd_pins[] = {
 776         /* MSIOF0_TXD */
 777         RCAR_GP_PIN(0, 13),
 778 };
 779 static const unsigned int msiof0_txd_mux[] = {
 780         MSIOF0_TXD_MARK,
 781 };
 782 static const unsigned int msiof0_rxd_pins[] = {
 783         /* MSIOF0_RXD */
 784         RCAR_GP_PIN(0, 12),
 785 };
 786 static const unsigned int msiof0_rxd_mux[] = {
 787         MSIOF0_RXD_MARK,
 788 };
 789
 790 /* - MSIOF1 ----------------------------------------------------------------- */
 791 static const unsigned int msiof1_clk_pins[] = {
 792         /* MSIOF1_SCK */
 793         RCAR_GP_PIN(0, 8),
 794 };
 795 static const unsigned int msiof1_clk_mux[] = {
 796         MSIOF1_SCK_MARK,
 797 };
 798 static const unsigned int msiof1_sync_pins[] = {
 799         /* MSIOF1_SYNC */
 800         RCAR_GP_PIN(0, 10),
 801 };
 802 static const unsigned int msiof1_sync_mux[] = {
 803         MSIOF1_SYNC_MARK,
 804 };
 805 static const unsigned int msiof1_ss1_pins[] = {
 806         /* MSIOF1_SS1 */
 807         RCAR_GP_PIN(0, 17),
 808 };
 809 static const unsigned int msiof1_ss1_mux[] = {
 810         MSIOF1_SS1_MARK,
 811 };
 812 static const unsigned int msiof1_ss2_pins[] = {
 813         /* MSIOF1_SS2 */
 814         RCAR_GP_PIN(0, 18),
 815 };
 816 static const unsigned int msiof1_ss2_mux[] = {
 817         MSIOF1_SS2_MARK,
 818 };
 819 static const unsigned int msiof1_txd_pins[] = {
 820         /* MSIOF1_TXD */
 821         RCAR_GP_PIN(0, 7),
 822 };
 823 static const unsigned int msiof1_txd_mux[] = {
 824         MSIOF1_TXD_MARK,
 825 };
 826 static const unsigned int msiof1_rxd_pins[] = {
 827         /* MSIOF1_RXD */
 828         RCAR_GP_PIN(0, 6),
 829 };
 830 static const unsigned int msiof1_rxd_mux[] = {
 831         MSIOF1_RXD_MARK,
 832 };
 833
 834 /* - MSIOF2 ----------------------------------------------------------------- */
 835 static const unsigned int msiof2_clk_pins[] = {
 836         /* MSIOF2_SCK */
 837         RCAR_GP_PIN(1, 5),
 838 };
 839 static const unsigned int msiof2_clk_mux[] = {
 840         MSIOF2_SCK_MARK,
 841 };
 842 static const unsigned int msiof2_sync_pins[] = {
 843         /* MSIOF2_SYNC */
 844         RCAR_GP_PIN(1, 4),
 845 };
 846 static const unsigned int msiof2_sync_mux[] = {
 847         MSIOF2_SYNC_MARK,
 848 };
 849 static const unsigned int msiof2_ss1_pins[] = {
 850         /* MSIOF2_SS1 */
 851         RCAR_GP_PIN(1, 2),
 852 };
 853 static const unsigned int msiof2_ss1_mux[] = {
 854         MSIOF2_SS1_MARK,
 855 };
 856 static const unsigned int msiof2_ss2_pins[] = {
 857         /* MSIOF2_SS2 */
 858         RCAR_GP_PIN(1, 3),
 859 };
 860 static const unsigned int msiof2_ss2_mux[] = {
 861         MSIOF2_SS2_MARK,
 862 };
 863 static const unsigned int msiof2_txd_pins[] = {
 864         /* MSIOF2_TXD */
 865         RCAR_GP_PIN(1, 7),
 866 };
 867 static const unsigned int msiof2_txd_mux[] = {
 868         MSIOF2_TXD_MARK,
 869 };
 870 static const unsigned int msiof2_rxd_pins[] = {
 871         /* MSIOF2_RXD */
 872         RCAR_GP_PIN(1, 6),
 873 };
 874 static const unsigned int msiof2_rxd_mux[] = {
 875         MSIOF2_RXD_MARK,
 876 };
 877
 878 /* - MSIOF3 ----------------------------------------------------------------- */
 879 static const unsigned int msiof3_clk_pins[] = {
 880         /* MSIOF3_SCK */
 881         RCAR_GP_PIN(0, 1),
 882 };
 883 static const unsigned int msiof3_clk_mux[] = {
 884         MSIOF3_SCK_MARK,
 885 };
 886 static const unsigned int msiof3_sync_pins[] = {
 887         /* MSIOF3_SYNC */
 888         RCAR_GP_PIN(0, 9),
 889 };
 890 static const unsigned int msiof3_sync_mux[] = {
 891         MSIOF3_SYNC_MARK,
 892 };
 893 static const unsigned int msiof3_ss1_pins[] = {
 894         /* MSIOF3_SS1 */
 895         RCAR_GP_PIN(0, 4),
 896 };
 897 static const unsigned int msiof3_ss1_mux[] = {
 898         MSIOF3_SS1_MARK,
 899 };
 900 static const unsigned int msiof3_ss2_pins[] = {
 901         /* MSIOF3_SS2 */
 902         RCAR_GP_PIN(0, 5),
 903 };
 904 static const unsigned int msiof3_ss2_mux[] = {
 905         MSIOF3_SS2_MARK,
 906 };
 907 static const unsigned int msiof3_txd_pins[] = {
 908         /* MSIOF3_TXD */
 909         RCAR_GP_PIN(0, 3),
 910 };
 911 static const unsigned int msiof3_txd_mux[] = {
 912         MSIOF3_TXD_MARK,
 913 };
 914 static const unsigned int msiof3_rxd_pins[] = {
 915         /* MSIOF3_RXD */
 916         RCAR_GP_PIN(0, 2),
 917 };
 918 static const unsigned int msiof3_rxd_mux[] = {
 919         MSIOF3_RXD_MARK,
 920 };
 921
 922 /* - PCIE ------------------------------------------------------------------- */
 923 static const unsigned int pcie0_clkreq_n_pins[] = {
 924         /* PCIE0_CLKREQ# */
 925         RCAR_GP_PIN(2, 15),
 926 };
 927
 928 static const unsigned int pcie0_clkreq_n_mux[] = {
 929         PCIE0_CLKREQ_N_MARK,
 930 };
 931
 932 static const unsigned int pcie1_clkreq_n_pins[] = {
 933         /* PCIE1_CLKREQ# */
 934         RCAR_GP_PIN(2, 16),
 935 };
 936
 937 static const unsigned int pcie1_clkreq_n_mux[] = {
 938         PCIE1_CLKREQ_N_MARK,
 939 };
 940
 941 /* - QSPI0 ------------------------------------------------------------------ */
 942 static const unsigned int qspi0_ctrl_pins[] = {
 943         /* SPCLK, SSL */
 944         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13),
 945 };
 946 static const unsigned int qspi0_ctrl_mux[] = {
 947         QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
 948 };
 949 static const unsigned int qspi0_data_pins[] = {
 950         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
 951         RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 12),
 952         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 14),
 953 };
 954 static const unsigned int qspi0_data_mux[] = {
 955         QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
 956         QSPI0_IO2_MARK, QSPI0_IO3_MARK
 957 };
 958
 959 /* - QSPI1 ------------------------------------------------------------------ */
 960 static const unsigned int qspi1_ctrl_pins[] = {
 961         /* SPCLK, SSL */
 962         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 3),
 963 };
 964 static const unsigned int qspi1_ctrl_mux[] = {
 965         QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
 966 };
 967 static const unsigned int qspi1_data_pins[] = {
 968         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
 969         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 5),
 970         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 4),
 971 };
 972 static const unsigned int qspi1_data_mux[] = {
 973         QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
 974         QSPI1_IO2_MARK, QSPI1_IO3_MARK
 975 };
 976
 977 /* - SCIF0 ------------------------------------------------------------------ */
 978 static const unsigned int scif0_data_pins[] = {
 979         /* RX0, TX0 */
 980         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 981 };
 982 static const unsigned int scif0_data_mux[] = {
 983         RX0_MARK, TX0_MARK,
 984 };
 985 static const unsigned int scif0_clk_pins[] = {
 986         /* SCK0 */
 987         RCAR_GP_PIN(0, 8),
 988 };
 989 static const unsigned int scif0_clk_mux[] = {
 990         SCK0_MARK,
 991 };
 992 static const unsigned int scif0_ctrl_pins[] = {
 993         /* RTS0#, CTS0# */
 994         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
 995 };
 996 static const unsigned int scif0_ctrl_mux[] = {
 997         RTS0_N_MARK, CTS0_N_MARK,
 998 };
 999
1000 /* - SCIF1 ------------------------------------------------------------------ */
1001 static const unsigned int scif1_data_pins[] = {
1002         /* RX1, TX1 */
1003         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1004 };
1005 static const unsigned int scif1_data_mux[] = {
1006         RX1_MARK, TX1_MARK,
1007 };
1008 static const unsigned int scif1_clk_pins[] = {
1009         /* SCK1 */
1010         RCAR_GP_PIN(0, 14),
1011 };
1012 static const unsigned int scif1_clk_mux[] = {
1013         SCK1_MARK,
1014 };
1015 static const unsigned int scif1_ctrl_pins[] = {
1016         /* RTS1#, CTS1# */
1017         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1018 };
1019 static const unsigned int scif1_ctrl_mux[] = {
1020         RTS1_N_MARK, CTS1_N_MARK,
1021 };
1022
1023 /* - SCIF3 ------------------------------------------------------------------ */
1024 static const unsigned int scif3_data_pins[] = {
1025         /* RX3, TX3 */
1026         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1027 };
1028 static const unsigned int scif3_data_mux[] = {
1029         RX3_MARK, TX3_MARK,
1030 };
1031 static const unsigned int scif3_clk_pins[] = {
1032         /* SCK3 */
1033         RCAR_GP_PIN(0, 1),
1034 };
1035 static const unsigned int scif3_clk_mux[] = {
1036         SCK3_MARK,
1037 };
1038 static const unsigned int scif3_ctrl_pins[] = {
1039         /* RTS3#, CTS3# */
1040         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
1041 };
1042 static const unsigned int scif3_ctrl_mux[] = {
1043         RTS3_N_MARK, CTS3_N_MARK,
1044 };
1045
1046 /* - SCIF4 ------------------------------------------------------------------ */
1047 static const unsigned int scif4_data_pins[] = {
1048         /* RX4, TX4 */
1049         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
1050 };
1051 static const unsigned int scif4_data_mux[] = {
1052         RX4_MARK, TX4_MARK,
1053 };
1054 static const unsigned int scif4_clk_pins[] = {
1055         /* SCK4 */
1056         RCAR_GP_PIN(1, 5),
1057 };
1058 static const unsigned int scif4_clk_mux[] = {
1059         SCK4_MARK,
1060 };
1061 static const unsigned int scif4_ctrl_pins[] = {
1062         /* RTS4#, CTS4# */
1063         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
1064 };
1065 static const unsigned int scif4_ctrl_mux[] = {
1066         RTS4_N_MARK, CTS4_N_MARK,
1067 };
1068
1069 /* - SCIF Clock ------------------------------------------------------------- */
1070 static const unsigned int scif_clk_pins[] = {
1071         /* SCIF_CLK */
1072         RCAR_GP_PIN(0, 0),
1073 };
1074 static const unsigned int scif_clk_mux[] = {
1075         SCIF_CLK_MARK,
1076 };
1077
1078 /* - TSN0 ------------------------------------------------ */
1079 static const unsigned int tsn0_link_a_pins[] = {
1080         /* TSN0_LINK_A */
1081         RCAR_GP_PIN(0, 11),
1082 };
1083 static const unsigned int tsn0_link_a_mux[] = {
1084         TSN0_LINK_A_MARK,
1085 };
1086 static const unsigned int tsn0_magic_a_pins[] = {
1087         /* TSN0_MAGIC_A */
1088         RCAR_GP_PIN(0, 17),
1089 };
1090 static const unsigned int tsn0_magic_a_mux[] = {
1091         TSN0_MAGIC_A_MARK,
1092 };
1093 static const unsigned int tsn0_phy_int_a_pins[] = {
1094         /* TSN0_PHY_INT_A */
1095         RCAR_GP_PIN(0, 18),
1096 };
1097 static const unsigned int tsn0_phy_int_a_mux[] = {
1098         TSN0_PHY_INT_A_MARK,
1099 };
1100 static const unsigned int tsn0_mdio_a_pins[] = {
1101         /* TSN0_MDC_A, TSN0_MDIO_A */
1102         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1103 };
1104 static const unsigned int tsn0_mdio_a_mux[] = {
1105         TSN0_MDC_A_MARK, TSN0_MDIO_A_MARK,
1106 };
1107 static const unsigned int tsn0_link_b_pins[] = {
1108         /* TSN0_LINK_B */
1109         RCAR_GP_PIN(3, 8),
1110 };
1111 static const unsigned int tsn0_link_b_mux[] = {
1112         TSN0_LINK_B_MARK,
1113 };
1114 static const unsigned int tsn0_magic_b_pins[] = {
1115         /* TSN0_MAGIC_B */
1116         RCAR_GP_PIN(3, 12),
1117 };
1118 static const unsigned int tsn0_magic_b_mux[] = {
1119         TSN0_MAGIC_B_MARK,
1120 };
1121 static const unsigned int tsn0_phy_int_b_pins[] = {
1122         /* TSN0_PHY_INT_B */
1123         RCAR_GP_PIN(3, 10),
1124 };
1125 static const unsigned int tsn0_phy_int_b_mux[] = {
1126         TSN0_PHY_INT_B_MARK,
1127 };
1128 static const unsigned int tsn0_mdio_b_pins[] = {
1129         /* TSN0_MDC_B, TSN0_MDIO_B */
1130         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 2),
1131 };
1132 static const unsigned int tsn0_mdio_b_mux[] = {
1133         TSN0_MDC_B_MARK, TSN0_MDIO_B_MARK,
1134 };
1135 static const unsigned int tsn0_avtp_pps_pins[] = {
1136         /* TSN0_AVTP_PPS */
1137         RCAR_GP_PIN(3, 16),
1138 };
1139 static const unsigned int tsn0_avtp_pps_mux[] = {
1140         TSN0_AVTP_PPS_MARK,
1141 };
1142 static const unsigned int tsn0_avtp_capture_a_pins[] = {
1143         /* TSN0_AVTP_CAPTURE_A */
1144         RCAR_GP_PIN(0, 1),
1145 };
1146 static const unsigned int tsn0_avtp_capture_a_mux[] = {
1147         TSN0_AVTP_CAPTURE_A_MARK,
1148 };
1149 static const unsigned int tsn0_avtp_match_a_pins[] = {
1150         /* TSN0_AVTP_MATCH_A */
1151         RCAR_GP_PIN(0, 2),
1152 };
1153 static const unsigned int tsn0_avtp_match_a_mux[] = {
1154         TSN0_AVTP_MATCH_A_MARK,
1155 };
1156 static const unsigned int tsn0_avtp_capture_b_pins[] = {
1157         /* TSN0_AVTP_CAPTURE_B */
1158         RCAR_GP_PIN(3, 18),
1159 };
1160 static const unsigned int tsn0_avtp_capture_b_mux[] = {
1161         TSN0_AVTP_CAPTURE_B_MARK,
1162 };
1163 static const unsigned int tsn0_avtp_match_b_pins[] = {
1164         /* TSN0_AVTP_MATCH_B */
1165         RCAR_GP_PIN(3, 17),
1166 };
1167 static const unsigned int tsn0_avtp_match_b_mux[] = {
1168         TSN0_AVTP_MATCH_B_MARK,
1169 };
1170
1171 /* - TSN1 ------------------------------------------------ */
1172 static const unsigned int tsn1_link_a_pins[] = {
1173         /* TSN1_LINK_A */
1174         RCAR_GP_PIN(0, 15),
1175 };
1176 static const unsigned int tsn1_link_a_mux[] = {
1177         TSN1_LINK_A_MARK,
1178 };
1179 static const unsigned int tsn1_phy_int_a_pins[] = {
1180         /* TSN1_PHY_INT_A */
1181         RCAR_GP_PIN(0, 19),
1182 };
1183 static const unsigned int tsn1_phy_int_a_mux[] = {
1184         TSN1_PHY_INT_A_MARK,
1185 };
1186 static const unsigned int tsn1_mdio_a_pins[] = {
1187         /* TSN1_MDC_A, TSN1_MDIO_A */
1188         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
1189 };
1190 static const unsigned int tsn1_mdio_a_mux[] = {
1191         TSN1_MDC_A_MARK, TSN1_MDIO_A_MARK,
1192 };
1193 static const unsigned int tsn1_link_b_pins[] = {
1194         /* TSN1_LINK_B */
1195         RCAR_GP_PIN(3, 6),
1196 };
1197 static const unsigned int tsn1_link_b_mux[] = {
1198         TSN1_LINK_B_MARK,
1199 };
1200 static const unsigned int tsn1_phy_int_b_pins[] = {
1201         /* TSN1_PHY_INT_B */
1202         RCAR_GP_PIN(3, 11),
1203 };
1204 static const unsigned int tsn1_phy_int_b_mux[] = {
1205         TSN1_PHY_INT_B_MARK,
1206 };
1207 static const unsigned int tsn1_mdio_b_pins[] = {
1208         /* TSN1_MDC_B, TSN1_MDIO_B */
1209         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
1210 };
1211 static const unsigned int tsn1_mdio_b_mux[] = {
1212         TSN1_MDC_B_MARK, TSN1_MDIO_B_MARK,
1213 };
1214 static const unsigned int tsn1_avtp_pps_pins[] = {
1215         /* TSN1_AVTP_PPS */
1216         RCAR_GP_PIN(3, 13),
1217 };
1218 static const unsigned int tsn1_avtp_pps_mux[] = {
1219         TSN0_AVTP_PPS_MARK,
1220 };
1221 static const unsigned int tsn1_avtp_capture_a_pins[] = {
1222         /* TSN1_AVTP_CAPTURE_A */
1223         RCAR_GP_PIN(0, 7),
1224 };
1225 static const unsigned int tsn1_avtp_capture_a_mux[] = {
1226         TSN1_AVTP_CAPTURE_A_MARK,
1227 };
1228 static const unsigned int tsn1_avtp_match_a_pins[] = {
1229         /* TSN1_AVTP_MATCH_A */
1230         RCAR_GP_PIN(0, 6),
1231 };
1232 static const unsigned int tsn1_avtp_match_a_mux[] = {
1233         TSN1_AVTP_MATCH_A_MARK,
1234 };
1235 static const unsigned int tsn1_avtp_capture_b_pins[] = {
1236         /* TSN1_AVTP_CAPTURE_B */
1237         RCAR_GP_PIN(3, 15),
1238 };
1239 static const unsigned int tsn1_avtp_capture_b_mux[] = {
1240         TSN1_AVTP_CAPTURE_B_MARK,
1241 };
1242 static const unsigned int tsn1_avtp_match_b_pins[] = {
1243         /* TSN1_AVTP_MATCH_B */
1244         RCAR_GP_PIN(3, 14),
1245 };
1246 static const unsigned int tsn1_avtp_match_b_mux[] = {
1247         TSN1_AVTP_MATCH_B_MARK,
1248 };
1249
1250 /* - TSN2 ------------------------------------------------ */
1251 static const unsigned int tsn2_link_a_pins[] = {
1252         /* TSN2_LINK_A */
1253         RCAR_GP_PIN(0, 16),
1254 };
1255 static const unsigned int tsn2_link_a_mux[] = {
1256         TSN2_LINK_A_MARK,
1257 };
1258 static const unsigned int tsn2_phy_int_a_pins[] = {
1259         /* TSN2_PHY_INT_A */
1260         RCAR_GP_PIN(0, 20),
1261 };
1262 static const unsigned int tsn2_phy_int_a_mux[] = {
1263         TSN2_PHY_INT_A_MARK,
1264 };
1265 static const unsigned int tsn2_mdio_a_pins[] = {
1266         /* TSN2_MDC_A, TSN2_MDIO_A */
1267         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
1268 };
1269 static const unsigned int tsn2_mdio_a_mux[] = {
1270         TSN2_MDC_A_MARK, TSN2_MDIO_A_MARK,
1271 };
1272 static const unsigned int tsn2_link_b_pins[] = {
1273         /* TSN2_LINK_B */
1274         RCAR_GP_PIN(3, 7),
1275 };
1276 static const unsigned int tsn2_link_b_mux[] = {
1277         TSN2_LINK_B_MARK,
1278 };
1279 static const unsigned int tsn2_phy_int_b_pins[] = {
1280         /* TSN2_PHY_INT_B */
1281         RCAR_GP_PIN(3, 9),
1282 };
1283 static const unsigned int tsn2_phy_int_b_mux[] = {
1284         TSN2_PHY_INT_B_MARK,
1285 };
1286 static const unsigned int tsn2_mdio_b_pins[] = {
1287         /* TSN2_MDC_B, TSN2_MDIO_B */
1288         RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 1),
1289 };
1290 static const unsigned int tsn2_mdio_b_mux[] = {
1291         TSN2_MDC_B_MARK, TSN2_MDIO_B_MARK,
1292 };
1293
1294 static const struct sh_pfc_pin_group pinmux_groups[] = {
1295         SH_PFC_PIN_GROUP(hscif0_data),
1296         SH_PFC_PIN_GROUP(hscif0_clk),
1297         SH_PFC_PIN_GROUP(hscif0_ctrl),
1298         SH_PFC_PIN_GROUP(hscif1_data),
1299         SH_PFC_PIN_GROUP(hscif1_clk),
1300         SH_PFC_PIN_GROUP(hscif1_ctrl),
1301         SH_PFC_PIN_GROUP(hscif2_data),
1302         SH_PFC_PIN_GROUP(hscif2_clk),
1303         SH_PFC_PIN_GROUP(hscif2_ctrl),
1304         SH_PFC_PIN_GROUP(hscif3_data),
1305         SH_PFC_PIN_GROUP(hscif3_clk),
1306         SH_PFC_PIN_GROUP(hscif3_ctrl),
1307         SH_PFC_PIN_GROUP(i2c0),
1308         SH_PFC_PIN_GROUP(i2c1),
1309         SH_PFC_PIN_GROUP(i2c2),
1310         SH_PFC_PIN_GROUP(i2c3),
1311         SH_PFC_PIN_GROUP(i2c4),
1312         SH_PFC_PIN_GROUP(i2c5),
1313         SH_PFC_PIN_GROUP(intc_ex_irq0),
1314         SH_PFC_PIN_GROUP(intc_ex_irq1),
1315         SH_PFC_PIN_GROUP(intc_ex_irq2),
1316         SH_PFC_PIN_GROUP(intc_ex_irq3),
1317         SH_PFC_PIN_GROUP(intc_ex_irq4),
1318         SH_PFC_PIN_GROUP(intc_ex_irq5),
1319         BUS_DATA_PIN_GROUP(mmc_data, 1),
1320         BUS_DATA_PIN_GROUP(mmc_data, 4),
1321         BUS_DATA_PIN_GROUP(mmc_data, 8),
1322         SH_PFC_PIN_GROUP(mmc_ctrl),
1323         SH_PFC_PIN_GROUP(mmc_cd),
1324         SH_PFC_PIN_GROUP(mmc_wp),
1325         SH_PFC_PIN_GROUP(mmc_ds),
1326         SH_PFC_PIN_GROUP(msiof0_clk),
1327         SH_PFC_PIN_GROUP(msiof0_sync),
1328         SH_PFC_PIN_GROUP(msiof0_ss1),
1329         SH_PFC_PIN_GROUP(msiof0_ss2),
1330         SH_PFC_PIN_GROUP(msiof0_txd),
1331         SH_PFC_PIN_GROUP(msiof0_rxd),
1332         SH_PFC_PIN_GROUP(msiof1_clk),
1333         SH_PFC_PIN_GROUP(msiof1_sync),
1334         SH_PFC_PIN_GROUP(msiof1_ss1),
1335         SH_PFC_PIN_GROUP(msiof1_ss2),
1336         SH_PFC_PIN_GROUP(msiof1_txd),
1337         SH_PFC_PIN_GROUP(msiof1_rxd),
1338         SH_PFC_PIN_GROUP(msiof2_clk),
1339         SH_PFC_PIN_GROUP(msiof2_sync),
1340         SH_PFC_PIN_GROUP(msiof2_ss1),
1341         SH_PFC_PIN_GROUP(msiof2_ss2),
1342         SH_PFC_PIN_GROUP(msiof2_txd),
1343         SH_PFC_PIN_GROUP(msiof2_rxd),
1344         SH_PFC_PIN_GROUP(msiof3_clk),
1345         SH_PFC_PIN_GROUP(msiof3_sync),
1346         SH_PFC_PIN_GROUP(msiof3_ss1),
1347         SH_PFC_PIN_GROUP(msiof3_ss2),
1348         SH_PFC_PIN_GROUP(msiof3_txd),
1349         SH_PFC_PIN_GROUP(msiof3_rxd),
1350         SH_PFC_PIN_GROUP(pcie0_clkreq_n),
1351         SH_PFC_PIN_GROUP(pcie1_clkreq_n),
1352         SH_PFC_PIN_GROUP(qspi0_ctrl),
1353         BUS_DATA_PIN_GROUP(qspi0_data, 2),
1354         BUS_DATA_PIN_GROUP(qspi0_data, 4),
1355         SH_PFC_PIN_GROUP(qspi1_ctrl),
1356         BUS_DATA_PIN_GROUP(qspi1_data, 2),
1357         BUS_DATA_PIN_GROUP(qspi1_data, 4),
1358         SH_PFC_PIN_GROUP(scif0_data),
1359         SH_PFC_PIN_GROUP(scif0_clk),
1360         SH_PFC_PIN_GROUP(scif0_ctrl),
1361         SH_PFC_PIN_GROUP(scif1_data),
1362         SH_PFC_PIN_GROUP(scif1_clk),
1363         SH_PFC_PIN_GROUP(scif1_ctrl),
1364         SH_PFC_PIN_GROUP(scif3_data),
1365         SH_PFC_PIN_GROUP(scif3_clk),
1366         SH_PFC_PIN_GROUP(scif3_ctrl),
1367         SH_PFC_PIN_GROUP(scif4_data),
1368         SH_PFC_PIN_GROUP(scif4_clk),
1369         SH_PFC_PIN_GROUP(scif4_ctrl),
1370         SH_PFC_PIN_GROUP(scif_clk),
1371         SH_PFC_PIN_GROUP(tsn0_link_a),
1372         SH_PFC_PIN_GROUP(tsn0_magic_a),
1373         SH_PFC_PIN_GROUP(tsn0_phy_int_a),
1374         SH_PFC_PIN_GROUP(tsn0_mdio_a),
1375         SH_PFC_PIN_GROUP(tsn0_link_b),
1376         SH_PFC_PIN_GROUP(tsn0_magic_b),
1377         SH_PFC_PIN_GROUP(tsn0_phy_int_b),
1378         SH_PFC_PIN_GROUP(tsn0_mdio_b),
1379         SH_PFC_PIN_GROUP(tsn0_avtp_pps),
1380         SH_PFC_PIN_GROUP(tsn0_avtp_capture_a),
1381         SH_PFC_PIN_GROUP(tsn0_avtp_match_a),
1382         SH_PFC_PIN_GROUP(tsn0_avtp_capture_b),
1383         SH_PFC_PIN_GROUP(tsn0_avtp_match_b),
1384         SH_PFC_PIN_GROUP(tsn1_link_a),
1385         SH_PFC_PIN_GROUP(tsn1_phy_int_a),
1386         SH_PFC_PIN_GROUP(tsn1_mdio_a),
1387         SH_PFC_PIN_GROUP(tsn1_link_b),
1388         SH_PFC_PIN_GROUP(tsn1_phy_int_b),
1389         SH_PFC_PIN_GROUP(tsn1_mdio_b),
1390         SH_PFC_PIN_GROUP(tsn1_avtp_pps),
1391         SH_PFC_PIN_GROUP(tsn1_avtp_capture_a),
1392         SH_PFC_PIN_GROUP(tsn1_avtp_match_a),
1393         SH_PFC_PIN_GROUP(tsn1_avtp_capture_b),
1394         SH_PFC_PIN_GROUP(tsn1_avtp_match_b),
1395         SH_PFC_PIN_GROUP(tsn2_link_a),
1396         SH_PFC_PIN_GROUP(tsn2_phy_int_a),
1397         SH_PFC_PIN_GROUP(tsn2_mdio_a),
1398         SH_PFC_PIN_GROUP(tsn2_link_b),
1399         SH_PFC_PIN_GROUP(tsn2_phy_int_b),
1400         SH_PFC_PIN_GROUP(tsn2_mdio_b),
1401 };
1402
1403 static const char * const hscif0_groups[] = {
1404         "hscif0_data",
1405         "hscif0_clk",
1406         "hscif0_ctrl",
1407 };
1408
1409 static const char * const hscif1_groups[] = {
1410         "hscif1_data",
1411         "hscif1_clk",
1412         "hscif1_ctrl",
1413 };
1414
1415 static const char * const hscif2_groups[] = {
1416         "hscif2_data",
1417         "hscif2_clk",
1418         "hscif2_ctrl",
1419 };
1420
1421 static const char * const hscif3_groups[] = {
1422         "hscif3_data",
1423         "hscif3_clk",
1424         "hscif3_ctrl",
1425 };
1426
1427 static const char * const i2c0_groups[] = {
1428         "i2c0",
1429 };
1430
1431 static const char * const i2c1_groups[] = {
1432         "i2c1",
1433 };
1434
1435 static const char * const i2c2_groups[] = {
1436         "i2c2",
1437 };
1438
1439 static const char * const i2c3_groups[] = {
1440         "i2c3",
1441 };
1442
1443 static const char * const i2c4_groups[] = {
1444         "i2c4",
1445 };
1446
1447 static const char * const i2c5_groups[] = {
1448         "i2c5",
1449 };
1450
1451 static const char * const intc_ex_groups[] = {
1452         "intc_ex_irq0",
1453         "intc_ex_irq1",
1454         "intc_ex_irq2",
1455         "intc_ex_irq3",
1456         "intc_ex_irq4",
1457         "intc_ex_irq5",
1458 };
1459
1460 static const char * const mmc_groups[] = {
1461         "mmc_data1",
1462         "mmc_data4",
1463         "mmc_data8",
1464         "mmc_ctrl",
1465         "mmc_cd",
1466         "mmc_wp",
1467         "mmc_ds",
1468 };
1469
1470 static const char * const msiof0_groups[] = {
1471         "msiof0_clk",
1472         "msiof0_sync",
1473         "msiof0_ss1",
1474         "msiof0_ss2",
1475         "msiof0_txd",
1476         "msiof0_rxd",
1477 };
1478
1479 static const char * const msiof1_groups[] = {
1480         "msiof1_clk",
1481         "msiof1_sync",
1482         "msiof1_ss1",
1483         "msiof1_ss2",
1484         "msiof1_txd",
1485         "msiof1_rxd",
1486 };
1487
1488 static const char * const msiof2_groups[] = {
1489         "msiof2_clk",
1490         "msiof2_sync",
1491         "msiof2_ss1",
1492         "msiof2_ss2",
1493         "msiof2_txd",
1494         "msiof2_rxd",
1495 };
1496
1497 static const char * const msiof3_groups[] = {
1498         "msiof3_clk",
1499         "msiof3_sync",
1500         "msiof3_ss1",
1501         "msiof3_ss2",
1502         "msiof3_txd",
1503         "msiof3_rxd",
1504 };
1505
1506 static const char * const pcie_groups[] = {
1507         "pcie0_clkreq_n",
1508         "pcie1_clkreq_n",
1509 };
1510
1511 static const char * const qspi0_groups[] = {
1512         "qspi0_ctrl",
1513         "qspi0_data2",
1514         "qspi0_data4",
1515 };
1516
1517 static const char * const qspi1_groups[] = {
1518         "qspi1_ctrl",
1519         "qspi1_data2",
1520         "qspi1_data4",
1521 };
1522
1523 static const char * const scif0_groups[] = {
1524         "scif0_data",
1525         "scif0_clk",
1526         "scif0_ctrl",
1527 };
1528
1529 static const char * const scif1_groups[] = {
1530         "scif1_data",
1531         "scif1_clk",
1532         "scif1_ctrl",
1533 };
1534
1535 static const char * const scif3_groups[] = {
1536         "scif3_data",
1537         "scif3_clk",
1538         "scif3_ctrl",
1539 };
1540
1541 static const char * const scif4_groups[] = {
1542         "scif4_data",
1543         "scif4_clk",
1544         "scif4_ctrl",
1545 };
1546
1547 static const char * const scif_clk_groups[] = {
1548         "scif_clk",
1549 };
1550
1551 static const char * const tsn0_groups[] = {
1552         "tsn0_link_a",
1553         "tsn0_magic_a",
1554         "tsn0_phy_int_a",
1555         "tsn0_mdio_a",
1556         "tsn0_link_b",
1557         "tsn0_magic_b",
1558         "tsn0_phy_int_b",
1559         "tsn0_mdio_b",
1560         "tsn0_avtp_pps",
1561         "tsn0_avtp_capture_a",
1562         "tsn0_avtp_match_a",
1563         "tsn0_avtp_capture_b",
1564         "tsn0_avtp_match_b",
1565 };
1566
1567 static const char * const tsn1_groups[] = {
1568         "tsn1_link_a",
1569         "tsn1_phy_int_a",
1570         "tsn1_mdio_a",
1571         "tsn1_link_b",
1572         "tsn1_phy_int_b",
1573         "tsn1_mdio_b",
1574         "tsn1_avtp_pps",
1575         "tsn1_avtp_capture_a",
1576         "tsn1_avtp_match_a",
1577         "tsn1_avtp_capture_b",
1578         "tsn1_avtp_match_b",
1579 };
1580
1581 static const char * const tsn2_groups[] = {
1582         "tsn2_link_a",
1583         "tsn2_phy_int_a",
1584         "tsn2_mdio_a",
1585         "tsn2_link_b",
1586         "tsn2_phy_int_b",
1587         "tsn2_mdio_b",
1588 };
1589
1590 static const struct sh_pfc_function pinmux_functions[] = {
1591         SH_PFC_FUNCTION(hscif0),
1592         SH_PFC_FUNCTION(hscif1),
1593         SH_PFC_FUNCTION(hscif2),
1594         SH_PFC_FUNCTION(hscif3),
1595         SH_PFC_FUNCTION(i2c0),
1596         SH_PFC_FUNCTION(i2c1),
1597         SH_PFC_FUNCTION(i2c2),
1598         SH_PFC_FUNCTION(i2c3),
1599         SH_PFC_FUNCTION(i2c4),
1600         SH_PFC_FUNCTION(i2c5),
1601         SH_PFC_FUNCTION(intc_ex),
1602         SH_PFC_FUNCTION(mmc),
1603         SH_PFC_FUNCTION(msiof0),
1604         SH_PFC_FUNCTION(msiof1),
1605         SH_PFC_FUNCTION(msiof2),
1606         SH_PFC_FUNCTION(msiof3),
1607         SH_PFC_FUNCTION(pcie),
1608         SH_PFC_FUNCTION(qspi0),
1609         SH_PFC_FUNCTION(qspi1),
1610         SH_PFC_FUNCTION(scif0),
1611         SH_PFC_FUNCTION(scif1),
1612         SH_PFC_FUNCTION(scif3),
1613         SH_PFC_FUNCTION(scif4),
1614         SH_PFC_FUNCTION(scif_clk),
1615         SH_PFC_FUNCTION(tsn0),
1616         SH_PFC_FUNCTION(tsn1),
1617         SH_PFC_FUNCTION(tsn2),
1618 };
1619
1620 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1621 #define F_(x, y)        FN_##y
1622 #define FM(x)           FN_##x
1623         { PINMUX_CFG_REG("GPSR0", 0xe6050040, 32, 1, GROUP(
1624                 0, 0,
1625                 0, 0,
1626                 0, 0,
1627                 0, 0,
1628                 0, 0,
1629                 0, 0,
1630                 0, 0,
1631                 0, 0,
1632                 0, 0,
1633                 0, 0,
1634                 0, 0,
1635                 GP_0_20_FN,     GPSR0_20,
1636                 GP_0_19_FN,     GPSR0_19,
1637                 GP_0_18_FN,     GPSR0_18,
1638                 GP_0_17_FN,     GPSR0_17,
1639                 GP_0_16_FN,     GPSR0_16,
1640                 GP_0_15_FN,     GPSR0_15,
1641                 GP_0_14_FN,     GPSR0_14,
1642                 GP_0_13_FN,     GPSR0_13,
1643                 GP_0_12_FN,     GPSR0_12,
1644                 GP_0_11_FN,     GPSR0_11,
1645                 GP_0_10_FN,     GPSR0_10,
1646                 GP_0_9_FN,      GPSR0_9,
1647                 GP_0_8_FN,      GPSR0_8,
1648                 GP_0_7_FN,      GPSR0_7,
1649                 GP_0_6_FN,      GPSR0_6,
1650                 GP_0_5_FN,      GPSR0_5,
1651                 GP_0_4_FN,      GPSR0_4,
1652                 GP_0_3_FN,      GPSR0_3,
1653                 GP_0_2_FN,      GPSR0_2,
1654                 GP_0_1_FN,      GPSR0_1,
1655                 GP_0_0_FN,      GPSR0_0, ))
1656         },
1657         { PINMUX_CFG_REG("GPSR1", 0xe6050840, 32, 1, GROUP(
1658                 0, 0,
1659                 0, 0,
1660                 0, 0,
1661                 0, 0,
1662                 0, 0,
1663                 0, 0,
1664                 0, 0,
1665                 GP_1_24_FN,     GPSR1_24,
1666                 GP_1_23_FN,     GPSR1_23,
1667                 GP_1_22_FN,     GPSR1_22,
1668                 GP_1_21_FN,     GPSR1_21,
1669                 GP_1_20_FN,     GPSR1_20,
1670                 GP_1_19_FN,     GPSR1_19,
1671                 GP_1_18_FN,     GPSR1_18,
1672                 GP_1_17_FN,     GPSR1_17,
1673                 GP_1_16_FN,     GPSR1_16,
1674                 GP_1_15_FN,     GPSR1_15,
1675                 GP_1_14_FN,     GPSR1_14,
1676                 GP_1_13_FN,     GPSR1_13,
1677                 GP_1_12_FN,     GPSR1_12,
1678                 GP_1_11_FN,     GPSR1_11,
1679                 GP_1_10_FN,     GPSR1_10,
1680                 GP_1_9_FN,      GPSR1_9,
1681                 GP_1_8_FN,      GPSR1_8,
1682                 GP_1_7_FN,      GPSR1_7,
1683                 GP_1_6_FN,      GPSR1_6,
1684                 GP_1_5_FN,      GPSR1_5,
1685                 GP_1_4_FN,      GPSR1_4,
1686                 GP_1_3_FN,      GPSR1_3,
1687                 GP_1_2_FN,      GPSR1_2,
1688                 GP_1_1_FN,      GPSR1_1,
1689                 GP_1_0_FN,      GPSR1_0, ))
1690         },
1691         { PINMUX_CFG_REG("GPSR2", 0xe6051040, 32, 1, GROUP(
1692                 0, 0,
1693                 0, 0,
1694                 0, 0,
1695                 0, 0,
1696                 0, 0,
1697                 0, 0,
1698                 0, 0,
1699                 0, 0,
1700                 0, 0,
1701                 0, 0,
1702                 0, 0,
1703                 0, 0,
1704                 0, 0,
1705                 0, 0,
1706                 0, 0,
1707                 GP_2_16_FN,     GPSR2_16,
1708                 GP_2_15_FN,     GPSR2_15,
1709                 GP_2_14_FN,     GPSR2_14,
1710                 GP_2_13_FN,     GPSR2_13,
1711                 GP_2_12_FN,     GPSR2_12,
1712                 GP_2_11_FN,     GPSR2_11,
1713                 GP_2_10_FN,     GPSR2_10,
1714                 GP_2_9_FN,      GPSR2_9,
1715                 GP_2_8_FN,      GPSR2_8,
1716                 GP_2_7_FN,      GPSR2_7,
1717                 GP_2_6_FN,      GPSR2_6,
1718                 GP_2_5_FN,      GPSR2_5,
1719                 GP_2_4_FN,      GPSR2_4,
1720                 GP_2_3_FN,      GPSR2_3,
1721                 GP_2_2_FN,      GPSR2_2,
1722                 GP_2_1_FN,      GPSR2_1,
1723                 GP_2_0_FN,      GPSR2_0, ))
1724         },
1725         { PINMUX_CFG_REG("GPSR3", 0xe6051840, 32, 1, GROUP(
1726                 0, 0,
1727                 0, 0,
1728                 0, 0,
1729                 0, 0,
1730                 0, 0,
1731                 0, 0,
1732                 0, 0,
1733                 0, 0,
1734                 0, 0,
1735                 0, 0,
1736                 0, 0,
1737                 0, 0,
1738                 0, 0,
1739                 GP_3_18_FN,     GPSR3_18,
1740                 GP_3_17_FN,     GPSR3_17,
1741                 GP_3_16_FN,     GPSR3_16,
1742                 GP_3_15_FN,     GPSR3_15,
1743                 GP_3_14_FN,     GPSR3_14,
1744                 GP_3_13_FN,     GPSR3_13,
1745                 GP_3_12_FN,     GPSR3_12,
1746                 GP_3_11_FN,     GPSR3_11,
1747                 GP_3_10_FN,     GPSR3_10,
1748                 GP_3_9_FN,      GPSR3_9,
1749                 GP_3_8_FN,      GPSR3_8,
1750                 GP_3_7_FN,      GPSR3_7,
1751                 GP_3_6_FN,      GPSR3_6,
1752                 GP_3_5_FN,      GPSR3_5,
1753                 GP_3_4_FN,      GPSR3_4,
1754                 GP_3_3_FN,      GPSR3_3,
1755                 GP_3_2_FN,      GPSR3_2,
1756                 GP_3_1_FN,      GPSR3_1,
1757                 GP_3_0_FN,      GPSR3_0, ))
1758         },
1759 #undef F_
1760 #undef FM
1761
1762 #define F_(x, y)        x,
1763 #define FM(x)           FN_##x,
1764         { PINMUX_CFG_REG("IP0SR0", 0xe6050060, 32, 4, GROUP(
1765                 IP0SR0_31_28
1766                 IP0SR0_27_24
1767                 IP0SR0_23_20
1768                 IP0SR0_19_16
1769                 IP0SR0_15_12
1770                 IP0SR0_11_8
1771                 IP0SR0_7_4
1772                 IP0SR0_3_0))
1773         },
1774         { PINMUX_CFG_REG("IP1SR0", 0xe6050064, 32, 4, GROUP(
1775                 IP1SR0_31_28
1776                 IP1SR0_27_24
1777                 IP1SR0_23_20
1778                 IP1SR0_19_16
1779                 IP1SR0_15_12
1780                 IP1SR0_11_8
1781                 IP1SR0_7_4
1782                 IP1SR0_3_0))
1783         },
1784         { PINMUX_CFG_REG("IP2SR0", 0xe6050068, 32, 4, GROUP(
1785                 IP2SR0_31_28
1786                 IP2SR0_27_24
1787                 IP2SR0_23_20
1788                 IP2SR0_19_16
1789                 IP2SR0_15_12
1790                 IP2SR0_11_8
1791                 IP2SR0_7_4
1792                 IP2SR0_3_0))
1793         },
1794         { PINMUX_CFG_REG("IP0SR1", 0xe6050860, 32, 4, GROUP(
1795                 IP0SR1_31_28
1796                 IP0SR1_27_24
1797                 IP0SR1_23_20
1798                 IP0SR1_19_16
1799                 IP0SR1_15_12
1800                 IP0SR1_11_8
1801                 IP0SR1_7_4
1802                 IP0SR1_3_0))
1803         },
1804 #undef F_
1805 #undef FM
1806
1807 #define F_(x, y)        x,
1808 #define FM(x)           FN_##x,
1809         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6050900, 32,
1810                              GROUP(-20, 2, 2, 2, 2, 2, 2),
1811                              GROUP(
1812                 /* RESERVED 31-12 */
1813                 MOD_SEL1_11_10
1814                 MOD_SEL1_9_8
1815                 MOD_SEL1_7_6
1816                 MOD_SEL1_5_4
1817                 MOD_SEL1_3_2
1818                 MOD_SEL1_1_0))
1819         },
1820         { /* sentinel */ },
1821 };
1822
1823 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
1824         { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6050080) {
1825                 { RCAR_GP_PIN(0,  7), 28, 3 },  /* TX0 */
1826                 { RCAR_GP_PIN(0,  6), 24, 3 },  /* RX0 */
1827                 { RCAR_GP_PIN(0,  5), 20, 3 },  /* HRTS0_N */
1828                 { RCAR_GP_PIN(0,  4), 16, 3 },  /* HCTS0_N */
1829                 { RCAR_GP_PIN(0,  3), 12, 3 },  /* HTX0 */
1830                 { RCAR_GP_PIN(0,  2),  8, 3 },  /* HRX0 */
1831                 { RCAR_GP_PIN(0,  1),  4, 3 },  /* HSCK0 */
1832                 { RCAR_GP_PIN(0,  0),  0, 3 },  /* SCIF_CLK */
1833         } },
1834         { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6050084) {
1835                 { RCAR_GP_PIN(0, 15), 28, 3 },  /* MSIOF0_SS1 */
1836                 { RCAR_GP_PIN(0, 14), 24, 3 },  /* MSIOF0_SCK */
1837                 { RCAR_GP_PIN(0, 13), 20, 3 },  /* MSIOF0_TXD */
1838                 { RCAR_GP_PIN(0, 12), 16, 3 },  /* MSIOF0_RXD */
1839                 { RCAR_GP_PIN(0, 11), 12, 3 },  /* MSIOF0_SYNC */
1840                 { RCAR_GP_PIN(0, 10),  8, 3 },  /* CTS0_N */
1841                 { RCAR_GP_PIN(0,  9),  4, 3 },  /* RTS0_N */
1842                 { RCAR_GP_PIN(0,  8),  0, 3 },  /* SCK0 */
1843         } },
1844         { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6050088) {
1845                 { RCAR_GP_PIN(0, 20), 16, 3 },  /* IRQ3 */
1846                 { RCAR_GP_PIN(0, 19), 12, 3 },  /* IRQ2 */
1847                 { RCAR_GP_PIN(0, 18),  8, 3 },  /* IRQ1 */
1848                 { RCAR_GP_PIN(0, 17),  4, 3 },  /* IRQ0 */
1849                 { RCAR_GP_PIN(0, 16),  0, 3 },  /* MSIOF0_SS2 */
1850         } },
1851         { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050880) {
1852                 { RCAR_GP_PIN(1,  7), 28, 3 },  /* GP1_07 */
1853                 { RCAR_GP_PIN(1,  6), 24, 3 },  /* GP1_06 */
1854                 { RCAR_GP_PIN(1,  5), 20, 3 },  /* GP1_05 */
1855                 { RCAR_GP_PIN(1,  4), 16, 3 },  /* GP1_04 */
1856                 { RCAR_GP_PIN(1,  3), 12, 3 },  /* GP1_03 */
1857                 { RCAR_GP_PIN(1,  2),  8, 3 },  /* GP1_02 */
1858                 { RCAR_GP_PIN(1,  1),  4, 3 },  /* GP1_01 */
1859                 { RCAR_GP_PIN(1,  0),  0, 3 },  /* GP1_00 */
1860         } },
1861         { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050884) {
1862                 { RCAR_GP_PIN(1, 15), 28, 3 },  /* MMC_SD_D2 */
1863                 { RCAR_GP_PIN(1, 14), 24, 3 },  /* MMC_SD_D1 */
1864                 { RCAR_GP_PIN(1, 13), 20, 3 },  /* MMC_SD_D0 */
1865                 { RCAR_GP_PIN(1, 12), 16, 3 },  /* MMC_SD_CLK */
1866                 { RCAR_GP_PIN(1, 11), 12, 3 },  /* GP1_11 */
1867                 { RCAR_GP_PIN(1, 10),  8, 3 },  /* GP1_10 */
1868                 { RCAR_GP_PIN(1,  9),  4, 3 },  /* GP1_09 */
1869                 { RCAR_GP_PIN(1,  8),  0, 3 },  /* GP1_08 */
1870         } },
1871         { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050888) {
1872                 { RCAR_GP_PIN(1, 23), 28, 3 },  /* SD_CD */
1873                 { RCAR_GP_PIN(1, 22), 24, 3 },  /* MMC_SD_CMD */
1874                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* MMC_D7 */
1875                 { RCAR_GP_PIN(1, 20), 16, 3 },  /* MMC_DS */
1876                 { RCAR_GP_PIN(1, 19), 12, 3 },  /* MMC_D6 */
1877                 { RCAR_GP_PIN(1, 18),  8, 3 },  /* MMC_D4 */
1878                 { RCAR_GP_PIN(1, 17),  4, 3 },  /* MMC_D5 */
1879                 { RCAR_GP_PIN(1, 16),  0, 3 },  /* MMC_SD_D3 */
1880         } },
1881         { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605088c) {
1882                 { RCAR_GP_PIN(1, 24),  0, 3 },  /* SD_WP */
1883         } },
1884         { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6051080) {
1885                 { RCAR_GP_PIN(2,  7), 28, 2 },  /* QSPI1_MOSI_IO0 */
1886                 { RCAR_GP_PIN(2,  6), 24, 2 },  /* QSPI1_IO2 */
1887                 { RCAR_GP_PIN(2,  5), 20, 2 },  /* QSPI1_MISO_IO1 */
1888                 { RCAR_GP_PIN(2,  4), 16, 2 },  /* QSPI1_IO3 */
1889                 { RCAR_GP_PIN(2,  3), 12, 2 },  /* QSPI1_SSL */
1890                 { RCAR_GP_PIN(2,  2),  8, 2 },  /* RPC_RESET_N */
1891                 { RCAR_GP_PIN(2,  1),  4, 2 },  /* RPC_WP_N */
1892                 { RCAR_GP_PIN(2,  0),  0, 2 },  /* RPC_INT_N */
1893         } },
1894         { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6051084) {
1895                 { RCAR_GP_PIN(2, 15), 28, 3 },  /* PCIE0_CLKREQ_N */
1896                 { RCAR_GP_PIN(2, 14), 24, 2 },  /* QSPI0_IO3 */
1897                 { RCAR_GP_PIN(2, 13), 20, 2 },  /* QSPI0_SSL */
1898                 { RCAR_GP_PIN(2, 12), 16, 2 },  /* QSPI0_MISO_IO1 */
1899                 { RCAR_GP_PIN(2, 11), 12, 2 },  /* QSPI0_IO2 */
1900                 { RCAR_GP_PIN(2, 10),  8, 2 },  /* QSPI0_SPCLK */
1901                 { RCAR_GP_PIN(2,  9),  4, 2 },  /* QSPI0_MOSI_IO0 */
1902                 { RCAR_GP_PIN(2,  8),  0, 2 },  /* QSPI1_SPCLK */
1903         } },
1904         { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6051088) {
1905                 { RCAR_GP_PIN(2, 16),  0, 3 },  /* PCIE1_CLKREQ_N */
1906         } },
1907         { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6051880) {
1908                 { RCAR_GP_PIN(3,  7), 28, 3 },  /* TSN2_LINK_B */
1909                 { RCAR_GP_PIN(3,  6), 24, 3 },  /* TSN1_LINK_B */
1910                 { RCAR_GP_PIN(3,  5), 20, 3 },  /* TSN1_MDC_B */
1911                 { RCAR_GP_PIN(3,  4), 16, 3 },  /* TSN0_MDC_B */
1912                 { RCAR_GP_PIN(3,  3), 12, 3 },  /* TSN2_MDC_B */
1913                 { RCAR_GP_PIN(3,  2),  8, 3 },  /* TSN0_MDIO_B */
1914                 { RCAR_GP_PIN(3,  1),  4, 3 },  /* TSN2_MDIO_B */
1915                 { RCAR_GP_PIN(3,  0),  0, 3 },  /* TSN1_MDIO_B */
1916         } },
1917         { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6051884) {
1918                 { RCAR_GP_PIN(3, 15), 28, 3 },  /* TSN1_AVTP_CAPTURE_B */
1919                 { RCAR_GP_PIN(3, 14), 24, 3 },  /* TSN1_AVTP_MATCH_B */
1920                 { RCAR_GP_PIN(3, 13), 20, 3 },  /* TSN1_AVTP_PPS */
1921                 { RCAR_GP_PIN(3, 12), 16, 3 },  /* TSN0_MAGIC_B */
1922                 { RCAR_GP_PIN(3, 11), 12, 3 },  /* TSN1_PHY_INT_B */
1923                 { RCAR_GP_PIN(3, 10),  8, 3 },  /* TSN0_PHY_INT_B */
1924                 { RCAR_GP_PIN(3,  9),  4, 3 },  /* TSN2_PHY_INT_B */
1925                 { RCAR_GP_PIN(3,  8),  0, 3 },  /* TSN0_LINK_B */
1926         } },
1927         { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6051888) {
1928                 { RCAR_GP_PIN(3, 18),  8, 3 },  /* TSN0_AVTP_CAPTURE_B */
1929                 { RCAR_GP_PIN(3, 17),  4, 3 },  /* TSN0_AVTP_MATCH_B */
1930                 { RCAR_GP_PIN(3, 16),  0, 3 },  /* TSN0_AVTP_PPS */
1931         } },
1932         { /* sentinel */ },
1933 };
1934
1935 enum ioctrl_regs {
1936         POC0,
1937         POC1,
1938         POC2,
1939         POC3,
1940         TD0SEL1,
1941 };
1942
1943 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
1944         [POC0] = { 0xe60500a0, },
1945         [POC1] = { 0xe60508a0, },
1946         [POC2] = { 0xe60510a0, },
1947         [POC3] = { 0xe60518a0, },
1948         [TD0SEL1] = { 0xe6050920, },
1949         { /* sentinel */ },
1950 };
1951
1952 static int r8a779f0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
1953 {
1954         int bit = pin & 0x1f;
1955
1956         *pocctrl = pinmux_ioctrl_regs[POC0].reg;
1957         if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 20))
1958                 return bit;
1959
1960         *pocctrl = pinmux_ioctrl_regs[POC1].reg;
1961         if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 24))
1962                 return bit;
1963
1964         *pocctrl = pinmux_ioctrl_regs[POC3].reg;
1965         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 18))
1966                 return bit;
1967
1968         return -EINVAL;
1969 }
1970
1971 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
1972         { PINMUX_BIAS_REG("PUEN0", 0xe60500c0, "PUD0", 0xe60500e0) {
1973                 [ 0] = RCAR_GP_PIN(0,  0),      /* SCIF_CLK */
1974                 [ 1] = RCAR_GP_PIN(0,  1),      /* HSCK0 */
1975                 [ 2] = RCAR_GP_PIN(0,  2),      /* HRX0 */
1976                 [ 3] = RCAR_GP_PIN(0,  3),      /* HTX0 */
1977                 [ 4] = RCAR_GP_PIN(0,  4),      /* HCTS0_N */
1978                 [ 5] = RCAR_GP_PIN(0,  5),      /* HRTS0_N */
1979                 [ 6] = RCAR_GP_PIN(0,  6),      /* RX0 */
1980                 [ 7] = RCAR_GP_PIN(0,  7),      /* TX0 */
1981                 [ 8] = RCAR_GP_PIN(0,  8),      /* SCK0 */
1982                 [ 9] = RCAR_GP_PIN(0,  9),      /* RTS0_N */
1983                 [10] = RCAR_GP_PIN(0, 10),      /* CTS0_N */
1984                 [11] = RCAR_GP_PIN(0, 11),      /* MSIOF0_SYNC */
1985                 [12] = RCAR_GP_PIN(0, 12),      /* MSIOF0_RXD */
1986                 [13] = RCAR_GP_PIN(0, 13),      /* MSIOF0_TXD */
1987                 [14] = RCAR_GP_PIN(0, 14),      /* MSIOF0_SCK */
1988                 [15] = RCAR_GP_PIN(0, 15),      /* MSIOF0_SS1 */
1989                 [16] = RCAR_GP_PIN(0, 16),      /* MSIOF0_SS2 */
1990                 [17] = RCAR_GP_PIN(0, 17),      /* IRQ0 */
1991                 [18] = RCAR_GP_PIN(0, 18),      /* IRQ1 */
1992                 [19] = RCAR_GP_PIN(0, 19),      /* IRQ2 */
1993                 [20] = RCAR_GP_PIN(0, 20),      /* IRQ3 */
1994                 [21] = SH_PFC_PIN_NONE,
1995                 [22] = SH_PFC_PIN_NONE,
1996                 [23] = SH_PFC_PIN_NONE,
1997                 [24] = SH_PFC_PIN_NONE,
1998                 [25] = SH_PFC_PIN_NONE,
1999                 [26] = SH_PFC_PIN_NONE,
2000                 [27] = SH_PFC_PIN_NONE,
2001                 [28] = SH_PFC_PIN_NONE,
2002                 [29] = SH_PFC_PIN_NONE,
2003                 [30] = SH_PFC_PIN_NONE,
2004                 [31] = SH_PFC_PIN_NONE,
2005         } },
2006         { PINMUX_BIAS_REG("PUEN1", 0xe60508c0, "PUD1", 0xe60508e0) {
2007                 [ 0] = RCAR_GP_PIN(1,  0),      /* GP1_00 */
2008                 [ 1] = RCAR_GP_PIN(1,  1),      /* GP1_01 */
2009                 [ 2] = RCAR_GP_PIN(1,  2),      /* GP1_02 */
2010                 [ 3] = RCAR_GP_PIN(1,  3),      /* GP1_03 */
2011                 [ 4] = RCAR_GP_PIN(1,  4),      /* GP1_04 */
2012                 [ 5] = RCAR_GP_PIN(1,  5),      /* GP1_05 */
2013                 [ 6] = RCAR_GP_PIN(1,  6),      /* GP1_06 */
2014                 [ 7] = RCAR_GP_PIN(1,  7),      /* GP1_07 */
2015                 [ 8] = RCAR_GP_PIN(1,  8),      /* GP1_08 */
2016                 [ 9] = RCAR_GP_PIN(1,  9),      /* GP1_09 */
2017                 [10] = RCAR_GP_PIN(1, 10),      /* GP1_10 */
2018                 [11] = RCAR_GP_PIN(1, 11),      /* GP1_11 */
2019                 [12] = RCAR_GP_PIN(1, 12),      /* MMC_SD_CLK */
2020                 [13] = RCAR_GP_PIN(1, 13),      /* MMC_SD_D0 */
2021                 [14] = RCAR_GP_PIN(1, 14),      /* MMC_SD_D1 */
2022                 [15] = RCAR_GP_PIN(1, 15),      /* MMC_SD_D2 */
2023                 [16] = RCAR_GP_PIN(1, 16),      /* MMC_SD_D3 */
2024                 [17] = RCAR_GP_PIN(1, 17),      /* MMC_D5 */
2025                 [18] = RCAR_GP_PIN(1, 18),      /* MMC_D4 */
2026                 [19] = RCAR_GP_PIN(1, 19),      /* MMC_D6 */
2027                 [20] = RCAR_GP_PIN(1, 20),      /* MMC_DS */
2028                 [21] = RCAR_GP_PIN(1, 21),      /* MMC_D7 */
2029                 [22] = RCAR_GP_PIN(1, 22),      /* MMC_SD_CMD */
2030                 [23] = RCAR_GP_PIN(1, 23),      /* SD_CD */
2031                 [24] = RCAR_GP_PIN(1, 24),      /* SD_WP */
2032                 [25] = SH_PFC_PIN_NONE,
2033                 [26] = SH_PFC_PIN_NONE,
2034                 [27] = SH_PFC_PIN_NONE,
2035                 [28] = SH_PFC_PIN_NONE,
2036                 [29] = SH_PFC_PIN_NONE,
2037                 [30] = SH_PFC_PIN_NONE,
2038                 [31] = SH_PFC_PIN_NONE,
2039         } },
2040         { PINMUX_BIAS_REG("PUEN2", 0xe60510c0, "PUD2", 0xe60510e0) {
2041                 [ 0] = RCAR_GP_PIN(2,  0),      /* RPC_INT_N */
2042                 [ 1] = RCAR_GP_PIN(2,  1),      /* RPC_WP_N */
2043                 [ 2] = RCAR_GP_PIN(2,  2),      /* RPC_RESET_N */
2044                 [ 3] = RCAR_GP_PIN(2,  3),      /* QSPI1_SSL */
2045                 [ 4] = RCAR_GP_PIN(2,  4),      /* QSPI1_IO3 */
2046                 [ 5] = RCAR_GP_PIN(2,  5),      /* QSPI1_MISO_IO1 */
2047                 [ 6] = RCAR_GP_PIN(2,  6),      /* QSPI1_IO2 */
2048                 [ 7] = RCAR_GP_PIN(2,  7),      /* QSPI1_MOSI_IO0 */
2049                 [ 8] = RCAR_GP_PIN(2,  8),      /* QSPI1_SPCLK */
2050                 [ 9] = RCAR_GP_PIN(2,  9),      /* QSPI0_MOSI_IO0 */
2051                 [10] = RCAR_GP_PIN(2, 10),      /* QSPI0_SPCLK */
2052                 [11] = RCAR_GP_PIN(2, 11),      /* QSPI0_IO2 */
2053                 [12] = RCAR_GP_PIN(2, 12),      /* QSPI0_MISO_IO1 */
2054                 [13] = RCAR_GP_PIN(2, 13),      /* QSPI0_SSL */
2055                 [14] = RCAR_GP_PIN(2, 14),      /* QSPI0_IO3 */
2056                 [15] = RCAR_GP_PIN(2, 15),      /* PCIE0_CLKREQ_N */
2057                 [16] = RCAR_GP_PIN(2, 16),      /* PCIE1_CLKREQ_N */
2058                 [17] = SH_PFC_PIN_NONE,
2059                 [18] = SH_PFC_PIN_NONE,
2060                 [19] = SH_PFC_PIN_NONE,
2061                 [20] = SH_PFC_PIN_NONE,
2062                 [21] = SH_PFC_PIN_NONE,
2063                 [22] = SH_PFC_PIN_NONE,
2064                 [23] = SH_PFC_PIN_NONE,
2065                 [24] = SH_PFC_PIN_NONE,
2066                 [25] = SH_PFC_PIN_NONE,
2067                 [26] = SH_PFC_PIN_NONE,
2068                 [27] = SH_PFC_PIN_NONE,
2069                 [28] = SH_PFC_PIN_NONE,
2070                 [29] = SH_PFC_PIN_NONE,
2071                 [30] = SH_PFC_PIN_NONE,
2072                 [31] = SH_PFC_PIN_NONE,
2073         } },
2074         { PINMUX_BIAS_REG("PUEN3", 0xe60518c0, "PUD3", 0xe60518e0) {
2075                 [ 0] = RCAR_GP_PIN(3,  0),      /* TSN1_MDIO_B */
2076                 [ 1] = RCAR_GP_PIN(3,  1),      /* TSN2_MDIO_B */
2077                 [ 2] = RCAR_GP_PIN(3,  2),      /* TSN0_MDIO_B */
2078                 [ 3] = RCAR_GP_PIN(3,  3),      /* TSN2_MDC_B */
2079                 [ 4] = RCAR_GP_PIN(3,  4),      /* TSN0_MDC_B */
2080                 [ 5] = RCAR_GP_PIN(3,  5),      /* TSN1_MDC_B */
2081                 [ 6] = RCAR_GP_PIN(3,  6),      /* TSN1_LINK_B */
2082                 [ 7] = RCAR_GP_PIN(3,  7),      /* TSN2_LINK_B */
2083                 [ 8] = RCAR_GP_PIN(3,  8),      /* TSN0_LINK_B */
2084                 [ 9] = RCAR_GP_PIN(3,  9),      /* TSN2_PHY_INT_B */
2085                 [10] = RCAR_GP_PIN(3, 10),      /* TSN0_PHY_INT_B */
2086                 [11] = RCAR_GP_PIN(3, 11),      /* TSN1_PHY_INT_B */
2087                 [12] = RCAR_GP_PIN(3, 12),      /* TSN0_MAGIC_B */
2088                 [13] = RCAR_GP_PIN(3, 13),      /* TSN1_AVTP_PPS */
2089                 [14] = RCAR_GP_PIN(3, 14),      /* TSN1_AVTP_MATCH_B */
2090                 [15] = RCAR_GP_PIN(3, 15),      /* TSN1_AVTP_CAPTURE_B */
2091                 [16] = RCAR_GP_PIN(3, 16),      /* TSN0_AVTP_PPS */
2092                 [17] = RCAR_GP_PIN(3, 17),      /* TSN0_AVTP_MATCH_B */
2093                 [18] = RCAR_GP_PIN(3, 18),      /* TSN0_AVTP_CAPTURE_B */
2094                 [19] = SH_PFC_PIN_NONE,
2095                 [20] = SH_PFC_PIN_NONE,
2096                 [21] = SH_PFC_PIN_NONE,
2097                 [22] = SH_PFC_PIN_NONE,
2098                 [23] = SH_PFC_PIN_NONE,
2099                 [24] = SH_PFC_PIN_NONE,
2100                 [25] = SH_PFC_PIN_NONE,
2101                 [26] = SH_PFC_PIN_NONE,
2102                 [27] = SH_PFC_PIN_NONE,
2103                 [28] = SH_PFC_PIN_NONE,
2104                 [29] = SH_PFC_PIN_NONE,
2105                 [30] = SH_PFC_PIN_NONE,
2106                 [31] = SH_PFC_PIN_NONE,
2107         } },
2108         { /* sentinel */ },
2109 };
2110
2111 static const struct sh_pfc_soc_operations r8a779f0_pfc_ops = {
2112         .pin_to_pocctrl = r8a779f0_pin_to_pocctrl,
2113         .get_bias = rcar_pinmux_get_bias,
2114         .set_bias = rcar_pinmux_set_bias,
2115 };
2116
2117 const struct sh_pfc_soc_info r8a779f0_pinmux_info = {
2118         .name = "r8a779f0_pfc",
2119         .ops = &r8a779f0_pfc_ops,
2120         .unlock_reg = 0x1ff,    /* PMMRn mask */
2121
2122         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2123
2124         .pins = pinmux_pins,
2125         .nr_pins = ARRAY_SIZE(pinmux_pins),
2126         .groups = pinmux_groups,
2127         .nr_groups = ARRAY_SIZE(pinmux_groups),
2128         .functions = pinmux_functions,
2129         .nr_functions = ARRAY_SIZE(pinmux_functions),
2130
2131         .cfg_regs = pinmux_config_regs,
2132         .drive_regs = pinmux_drive_regs,
2133         .bias_regs = pinmux_bias_regs,
2134         .ioctrl_regs = pinmux_ioctrl_regs,
2135
2136         .pinmux_data = pinmux_data,
2137         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2138 };