1 // SPDX-License-Identifier: GPL-2.0
3 * R8A779A0 processor support - PFC hardware block.
5 * Copyright (C) 2020 Renesas Electronics Corp.
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
10 #include <linux/errno.h>
12 #include <linux/kernel.h>
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
18 #define CPU_ALL_GP(fn, sfx) \
19 PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS), \
20 PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
22 PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
23 PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
24 PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
25 PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
26 PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
27 PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
28 PORT_GP_CFG_1(0, 23, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
29 PORT_GP_CFG_1(0, 24, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
30 PORT_GP_CFG_1(0, 25, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
31 PORT_GP_CFG_1(0, 26, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
32 PORT_GP_CFG_1(0, 27, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
33 PORT_GP_CFG_31(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
34 PORT_GP_CFG_2(2, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_1(2, 2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
36 PORT_GP_CFG_1(2, 3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
37 PORT_GP_CFG_1(2, 4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
38 PORT_GP_CFG_1(2, 5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
39 PORT_GP_CFG_1(2, 6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
40 PORT_GP_CFG_1(2, 7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
41 PORT_GP_CFG_1(2, 8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
42 PORT_GP_CFG_1(2, 9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
43 PORT_GP_CFG_1(2, 10, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
44 PORT_GP_CFG_1(2, 11, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
45 PORT_GP_CFG_1(2, 12, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
46 PORT_GP_CFG_1(2, 13, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
47 PORT_GP_CFG_1(2, 14, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
48 PORT_GP_CFG_1(2, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
49 PORT_GP_CFG_1(2, 16, fn, sfx, CFG_FLAGS), \
50 PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \
51 PORT_GP_CFG_1(2, 18, fn, sfx, CFG_FLAGS), \
52 PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \
53 PORT_GP_CFG_1(2, 20, fn, sfx, CFG_FLAGS), \
54 PORT_GP_CFG_1(2, 21, fn, sfx, CFG_FLAGS), \
55 PORT_GP_CFG_1(2, 22, fn, sfx, CFG_FLAGS), \
56 PORT_GP_CFG_1(2, 23, fn, sfx, CFG_FLAGS), \
57 PORT_GP_CFG_1(2, 24, fn, sfx, CFG_FLAGS), \
58 PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS), \
59 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
60 PORT_GP_CFG_1(4, 18, fn, sfx, CFG_FLAGS), \
61 PORT_GP_CFG_1(4, 19, fn, sfx, CFG_FLAGS), \
62 PORT_GP_CFG_1(4, 20, fn, sfx, CFG_FLAGS), \
63 PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS), \
64 PORT_GP_CFG_1(4, 22, fn, sfx, CFG_FLAGS), \
65 PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS), \
66 PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS), \
67 PORT_GP_CFG_1(4, 25, fn, sfx, CFG_FLAGS), \
68 PORT_GP_CFG_1(4, 26, fn, sfx, CFG_FLAGS), \
69 PORT_GP_CFG_18(5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
70 PORT_GP_CFG_1(5, 18, fn, sfx, CFG_FLAGS), \
71 PORT_GP_CFG_1(5, 19, fn, sfx, CFG_FLAGS), \
72 PORT_GP_CFG_1(5, 20, fn, sfx, CFG_FLAGS), \
73 PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
74 PORT_GP_CFG_1(6, 18, fn, sfx, CFG_FLAGS), \
75 PORT_GP_CFG_1(6, 19, fn, sfx, CFG_FLAGS), \
76 PORT_GP_CFG_1(6, 20, fn, sfx, CFG_FLAGS), \
77 PORT_GP_CFG_18(7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
78 PORT_GP_CFG_1(7, 18, fn, sfx, CFG_FLAGS), \
79 PORT_GP_CFG_1(7, 19, fn, sfx, CFG_FLAGS), \
80 PORT_GP_CFG_1(7, 20, fn, sfx, CFG_FLAGS), \
81 PORT_GP_CFG_18(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
82 PORT_GP_CFG_1(8, 18, fn, sfx, CFG_FLAGS), \
83 PORT_GP_CFG_1(8, 19, fn, sfx, CFG_FLAGS), \
84 PORT_GP_CFG_1(8, 20, fn, sfx, CFG_FLAGS), \
85 PORT_GP_CFG_18(9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
86 PORT_GP_CFG_1(9, 18, fn, sfx, CFG_FLAGS), \
87 PORT_GP_CFG_1(9, 19, fn, sfx, CFG_FLAGS), \
88 PORT_GP_CFG_1(9, 20, fn, sfx, CFG_FLAGS)
90 #define CPU_ALL_NOGP(fn) \
91 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
92 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
93 PIN_NOGP_CFG(DCUTRST_N_LPDRST_N, "DCUTRST#_LPDRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
94 PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
95 PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
96 PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
99 * F_() : just information
100 * FM() : macro for FN_xxx / xxx_MARK
104 #define GPSR0_27 FM(MMC_D7)
105 #define GPSR0_26 FM(MMC_D6)
106 #define GPSR0_25 FM(MMC_D5)
107 #define GPSR0_24 FM(MMC_D4)
108 #define GPSR0_23 FM(MMC_SD_CLK)
109 #define GPSR0_22 FM(MMC_SD_D3)
110 #define GPSR0_21 FM(MMC_SD_D2)
111 #define GPSR0_20 FM(MMC_SD_D1)
112 #define GPSR0_19 FM(MMC_SD_D0)
113 #define GPSR0_18 FM(MMC_SD_CMD)
114 #define GPSR0_17 FM(MMC_DS)
115 #define GPSR0_16 FM(SD_CD)
116 #define GPSR0_15 FM(SD_WP)
117 #define GPSR0_14 FM(RPC_INT_N)
118 #define GPSR0_13 FM(RPC_WP_N)
119 #define GPSR0_12 FM(RPC_RESET_N)
120 #define GPSR0_11 FM(QSPI1_SSL)
121 #define GPSR0_10 FM(QSPI1_IO3)
122 #define GPSR0_9 FM(QSPI1_IO2)
123 #define GPSR0_8 FM(QSPI1_MISO_IO1)
124 #define GPSR0_7 FM(QSPI1_MOSI_IO0)
125 #define GPSR0_6 FM(QSPI1_SPCLK)
126 #define GPSR0_5 FM(QSPI0_SSL)
127 #define GPSR0_4 FM(QSPI0_IO3)
128 #define GPSR0_3 FM(QSPI0_IO2)
129 #define GPSR0_2 FM(QSPI0_MISO_IO1)
130 #define GPSR0_1 FM(QSPI0_MOSI_IO0)
131 #define GPSR0_0 FM(QSPI0_SPCLK)
134 #define GPSR1_30 F_(GP1_30, IP3SR1_27_24)
135 #define GPSR1_29 F_(GP1_29, IP3SR1_23_20)
136 #define GPSR1_28 F_(GP1_28, IP3SR1_19_16)
137 #define GPSR1_27 F_(IRQ3, IP3SR1_15_12)
138 #define GPSR1_26 F_(IRQ2, IP3SR1_11_8)
139 #define GPSR1_25 F_(IRQ1, IP3SR1_7_4)
140 #define GPSR1_24 F_(IRQ0, IP3SR1_3_0)
141 #define GPSR1_23 F_(MSIOF2_SS2, IP2SR1_31_28)
142 #define GPSR1_22 F_(MSIOF2_SS1, IP2SR1_27_24)
143 #define GPSR1_21 F_(MSIOF2_SYNC, IP2SR1_23_20)
144 #define GPSR1_20 F_(MSIOF2_SCK, IP2SR1_19_16)
145 #define GPSR1_19 F_(MSIOF2_TXD, IP2SR1_15_12)
146 #define GPSR1_18 F_(MSIOF2_RXD, IP2SR1_11_8)
147 #define GPSR1_17 F_(MSIOF1_SS2, IP2SR1_7_4)
148 #define GPSR1_16 F_(MSIOF1_SS1, IP2SR1_3_0)
149 #define GPSR1_15 F_(MSIOF1_SYNC, IP1SR1_31_28)
150 #define GPSR1_14 F_(MSIOF1_SCK, IP1SR1_27_24)
151 #define GPSR1_13 F_(MSIOF1_TXD, IP1SR1_23_20)
152 #define GPSR1_12 F_(MSIOF1_RXD, IP1SR1_19_16)
153 #define GPSR1_11 F_(MSIOF0_SS2, IP1SR1_15_12)
154 #define GPSR1_10 F_(MSIOF0_SS1, IP1SR1_11_8)
155 #define GPSR1_9 F_(MSIOF0_SYNC, IP1SR1_7_4)
156 #define GPSR1_8 F_(MSIOF0_SCK, IP1SR1_3_0)
157 #define GPSR1_7 F_(MSIOF0_TXD, IP0SR1_31_28)
158 #define GPSR1_6 F_(MSIOF0_RXD, IP0SR1_27_24)
159 #define GPSR1_5 F_(HTX0, IP0SR1_23_20)
160 #define GPSR1_4 F_(HCTS0_N, IP0SR1_19_16)
161 #define GPSR1_3 F_(HRTS0_N, IP0SR1_15_12)
162 #define GPSR1_2 F_(HSCK0, IP0SR1_11_8)
163 #define GPSR1_1 F_(HRX0, IP0SR1_7_4)
164 #define GPSR1_0 F_(SCIF_CLK, IP0SR1_3_0)
167 #define GPSR2_24 FM(TCLK2_A)
168 #define GPSR2_23 F_(TCLK1_A, IP2SR2_31_28)
169 #define GPSR2_22 F_(TPU0TO1, IP2SR2_27_24)
170 #define GPSR2_21 F_(TPU0TO0, IP2SR2_23_20)
171 #define GPSR2_20 F_(CLK_EXTFXR, IP2SR2_19_16)
172 #define GPSR2_19 F_(RXDB_EXTFXR, IP2SR2_15_12)
173 #define GPSR2_18 F_(FXR_TXDB, IP2SR2_11_8)
174 #define GPSR2_17 F_(RXDA_EXTFXR_A, IP2SR2_7_4)
175 #define GPSR2_16 F_(FXR_TXDA_A, IP2SR2_3_0)
176 #define GPSR2_15 F_(GP2_15, IP1SR2_31_28)
177 #define GPSR2_14 F_(GP2_14, IP1SR2_27_24)
178 #define GPSR2_13 F_(GP2_13, IP1SR2_23_20)
179 #define GPSR2_12 F_(GP2_12, IP1SR2_19_16)
180 #define GPSR2_11 F_(GP2_11, IP1SR2_15_12)
181 #define GPSR2_10 F_(GP2_10, IP1SR2_11_8)
182 #define GPSR2_9 F_(GP2_09, IP1SR2_7_4)
183 #define GPSR2_8 F_(GP2_08, IP1SR2_3_0)
184 #define GPSR2_7 F_(GP2_07, IP0SR2_31_28)
185 #define GPSR2_6 F_(GP2_06, IP0SR2_27_24)
186 #define GPSR2_5 F_(GP2_05, IP0SR2_23_20)
187 #define GPSR2_4 F_(GP2_04, IP0SR2_19_16)
188 #define GPSR2_3 F_(GP2_03, IP0SR2_15_12)
189 #define GPSR2_2 F_(GP2_02, IP0SR2_11_8)
190 #define GPSR2_1 F_(IPC_CLKOUT, IP0SR2_7_4)
191 #define GPSR2_0 F_(IPC_CLKIN, IP0SR2_3_0)
194 #define GPSR3_16 FM(CANFD7_RX)
195 #define GPSR3_15 FM(CANFD7_TX)
196 #define GPSR3_14 FM(CANFD6_RX)
197 #define GPSR3_13 F_(CANFD6_TX, IP1SR3_23_20)
198 #define GPSR3_12 F_(CANFD5_RX, IP1SR3_19_16)
199 #define GPSR3_11 F_(CANFD5_TX, IP1SR3_15_12)
200 #define GPSR3_10 F_(CANFD4_RX, IP1SR3_11_8)
201 #define GPSR3_9 F_(CANFD4_TX, IP1SR3_7_4)
202 #define GPSR3_8 F_(CANFD3_RX, IP1SR3_3_0)
203 #define GPSR3_7 F_(CANFD3_TX, IP0SR3_31_28)
204 #define GPSR3_6 F_(CANFD2_RX, IP0SR3_27_24)
205 #define GPSR3_5 F_(CANFD2_TX, IP0SR3_23_20)
206 #define GPSR3_4 FM(CANFD1_RX)
207 #define GPSR3_3 FM(CANFD1_TX)
208 #define GPSR3_2 F_(CANFD0_RX, IP0SR3_11_8)
209 #define GPSR3_1 F_(CANFD0_TX, IP0SR3_7_4)
210 #define GPSR3_0 FM(CAN_CLK)
213 #define GPSR4_26 FM(AVS1)
214 #define GPSR4_25 FM(AVS0)
215 #define GPSR4_24 FM(PCIE3_CLKREQ_N)
216 #define GPSR4_23 FM(PCIE2_CLKREQ_N)
217 #define GPSR4_22 FM(PCIE1_CLKREQ_N)
218 #define GPSR4_21 FM(PCIE0_CLKREQ_N)
219 #define GPSR4_20 F_(AVB0_AVTP_PPS, IP2SR4_19_16)
220 #define GPSR4_19 F_(AVB0_AVTP_CAPTURE, IP2SR4_15_12)
221 #define GPSR4_18 F_(AVB0_AVTP_MATCH, IP2SR4_11_8)
222 #define GPSR4_17 F_(AVB0_LINK, IP2SR4_7_4)
223 #define GPSR4_16 FM(AVB0_PHY_INT)
224 #define GPSR4_15 F_(AVB0_MAGIC, IP1SR4_31_28)
225 #define GPSR4_14 F_(AVB0_MDC, IP1SR4_27_24)
226 #define GPSR4_13 F_(AVB0_MDIO, IP1SR4_23_20)
227 #define GPSR4_12 F_(AVB0_TXCREFCLK, IP1SR4_19_16)
228 #define GPSR4_11 F_(AVB0_TD3, IP1SR4_15_12)
229 #define GPSR4_10 F_(AVB0_TD2, IP1SR4_11_8)
230 #define GPSR4_9 F_(AVB0_TD1, IP1SR4_7_4)
231 #define GPSR4_8 F_(AVB0_TD0, IP1SR4_3_0)
232 #define GPSR4_7 F_(AVB0_TXC, IP0SR4_31_28)
233 #define GPSR4_6 F_(AVB0_TX_CTL, IP0SR4_27_24)
234 #define GPSR4_5 F_(AVB0_RD3, IP0SR4_23_20)
235 #define GPSR4_4 F_(AVB0_RD2, IP0SR4_19_16)
236 #define GPSR4_3 F_(AVB0_RD1, IP0SR4_15_12)
237 #define GPSR4_2 F_(AVB0_RD0, IP0SR4_11_8)
238 #define GPSR4_1 F_(AVB0_RXC, IP0SR4_7_4)
239 #define GPSR4_0 F_(AVB0_RX_CTL, IP0SR4_3_0)
242 #define GPSR5_20 F_(AVB1_AVTP_PPS, IP2SR5_19_16)
243 #define GPSR5_19 F_(AVB1_AVTP_CAPTURE, IP2SR5_15_12)
244 #define GPSR5_18 F_(AVB1_AVTP_MATCH, IP2SR5_11_8)
245 #define GPSR5_17 F_(AVB1_LINK, IP2SR5_7_4)
246 #define GPSR5_16 FM(AVB1_PHY_INT)
247 #define GPSR5_15 F_(AVB1_MAGIC, IP1SR5_31_28)
248 #define GPSR5_14 F_(AVB1_MDC, IP1SR5_27_24)
249 #define GPSR5_13 F_(AVB1_MDIO, IP1SR5_23_20)
250 #define GPSR5_12 F_(AVB1_TXCREFCLK, IP1SR5_19_16)
251 #define GPSR5_11 F_(AVB1_TD3, IP1SR5_15_12)
252 #define GPSR5_10 F_(AVB1_TD2, IP1SR5_11_8)
253 #define GPSR5_9 F_(AVB1_TD1, IP1SR5_7_4)
254 #define GPSR5_8 F_(AVB1_TD0, IP1SR5_3_0)
255 #define GPSR5_7 F_(AVB1_TXC, IP0SR5_31_28)
256 #define GPSR5_6 F_(AVB1_TX_CTL, IP0SR5_27_24)
257 #define GPSR5_5 F_(AVB1_RD3, IP0SR5_23_20)
258 #define GPSR5_4 F_(AVB1_RD2, IP0SR5_19_16)
259 #define GPSR5_3 F_(AVB1_RD1, IP0SR5_15_12)
260 #define GPSR5_2 F_(AVB1_RD0, IP0SR5_11_8)
261 #define GPSR5_1 F_(AVB1_RXC, IP0SR5_7_4)
262 #define GPSR5_0 F_(AVB1_RX_CTL, IP0SR5_3_0)
265 #define GPSR6_20 FM(AVB2_AVTP_PPS)
266 #define GPSR6_19 FM(AVB2_AVTP_CAPTURE)
267 #define GPSR6_18 FM(AVB2_AVTP_MATCH)
268 #define GPSR6_17 FM(AVB2_LINK)
269 #define GPSR6_16 FM(AVB2_PHY_INT)
270 #define GPSR6_15 FM(AVB2_MAGIC)
271 #define GPSR6_14 FM(AVB2_MDC)
272 #define GPSR6_13 FM(AVB2_MDIO)
273 #define GPSR6_12 FM(AVB2_TXCREFCLK)
274 #define GPSR6_11 FM(AVB2_TD3)
275 #define GPSR6_10 FM(AVB2_TD2)
276 #define GPSR6_9 FM(AVB2_TD1)
277 #define GPSR6_8 FM(AVB2_TD0)
278 #define GPSR6_7 FM(AVB2_TXC)
279 #define GPSR6_6 FM(AVB2_TX_CTL)
280 #define GPSR6_5 FM(AVB2_RD3)
281 #define GPSR6_4 FM(AVB2_RD2)
282 #define GPSR6_3 FM(AVB2_RD1)
283 #define GPSR6_2 FM(AVB2_RD0)
284 #define GPSR6_1 FM(AVB2_RXC)
285 #define GPSR6_0 FM(AVB2_RX_CTL)
288 #define GPSR7_20 FM(AVB3_AVTP_PPS)
289 #define GPSR7_19 FM(AVB3_AVTP_CAPTURE)
290 #define GPSR7_18 FM(AVB3_AVTP_MATCH)
291 #define GPSR7_17 FM(AVB3_LINK)
292 #define GPSR7_16 FM(AVB3_PHY_INT)
293 #define GPSR7_15 FM(AVB3_MAGIC)
294 #define GPSR7_14 FM(AVB3_MDC)
295 #define GPSR7_13 FM(AVB3_MDIO)
296 #define GPSR7_12 FM(AVB3_TXCREFCLK)
297 #define GPSR7_11 FM(AVB3_TD3)
298 #define GPSR7_10 FM(AVB3_TD2)
299 #define GPSR7_9 FM(AVB3_TD1)
300 #define GPSR7_8 FM(AVB3_TD0)
301 #define GPSR7_7 FM(AVB3_TXC)
302 #define GPSR7_6 FM(AVB3_TX_CTL)
303 #define GPSR7_5 FM(AVB3_RD3)
304 #define GPSR7_4 FM(AVB3_RD2)
305 #define GPSR7_3 FM(AVB3_RD1)
306 #define GPSR7_2 FM(AVB3_RD0)
307 #define GPSR7_1 FM(AVB3_RXC)
308 #define GPSR7_0 FM(AVB3_RX_CTL)
311 #define GPSR8_20 FM(AVB4_AVTP_PPS)
312 #define GPSR8_19 FM(AVB4_AVTP_CAPTURE)
313 #define GPSR8_18 FM(AVB4_AVTP_MATCH)
314 #define GPSR8_17 FM(AVB4_LINK)
315 #define GPSR8_16 FM(AVB4_PHY_INT)
316 #define GPSR8_15 FM(AVB4_MAGIC)
317 #define GPSR8_14 FM(AVB4_MDC)
318 #define GPSR8_13 FM(AVB4_MDIO)
319 #define GPSR8_12 FM(AVB4_TXCREFCLK)
320 #define GPSR8_11 FM(AVB4_TD3)
321 #define GPSR8_10 FM(AVB4_TD2)
322 #define GPSR8_9 FM(AVB4_TD1)
323 #define GPSR8_8 FM(AVB4_TD0)
324 #define GPSR8_7 FM(AVB4_TXC)
325 #define GPSR8_6 FM(AVB4_TX_CTL)
326 #define GPSR8_5 FM(AVB4_RD3)
327 #define GPSR8_4 FM(AVB4_RD2)
328 #define GPSR8_3 FM(AVB4_RD1)
329 #define GPSR8_2 FM(AVB4_RD0)
330 #define GPSR8_1 FM(AVB4_RXC)
331 #define GPSR8_0 FM(AVB4_RX_CTL)
334 #define GPSR9_20 FM(AVB5_AVTP_PPS)
335 #define GPSR9_19 FM(AVB5_AVTP_CAPTURE)
336 #define GPSR9_18 FM(AVB5_AVTP_MATCH)
337 #define GPSR9_17 FM(AVB5_LINK)
338 #define GPSR9_16 FM(AVB5_PHY_INT)
339 #define GPSR9_15 FM(AVB5_MAGIC)
340 #define GPSR9_14 FM(AVB5_MDC)
341 #define GPSR9_13 FM(AVB5_MDIO)
342 #define GPSR9_12 FM(AVB5_TXCREFCLK)
343 #define GPSR9_11 FM(AVB5_TD3)
344 #define GPSR9_10 FM(AVB5_TD2)
345 #define GPSR9_9 FM(AVB5_TD1)
346 #define GPSR9_8 FM(AVB5_TD0)
347 #define GPSR9_7 FM(AVB5_TXC)
348 #define GPSR9_6 FM(AVB5_TX_CTL)
349 #define GPSR9_5 FM(AVB5_RD3)
350 #define GPSR9_4 FM(AVB5_RD2)
351 #define GPSR9_3 FM(AVB5_RD1)
352 #define GPSR9_2 FM(AVB5_RD0)
353 #define GPSR9_1 FM(AVB5_RXC)
354 #define GPSR9_0 FM(AVB5_RX_CTL)
356 /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
357 #define IP0SR1_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP0SR1_7_4 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP0SR1_11_8 FM(HSCK0) FM(SCK0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP0SR1_15_12 FM(HRTS0_N) FM(RTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP0SR1_19_16 FM(HCTS0_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP0SR1_23_20 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP0SR1_27_24 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP0SR1_31_28 FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR3) FM(A7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
366 #define IP1SR1_3_0 FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR4) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP1SR1_7_4 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP1SR1_11_8 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP1SR1_15_12 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR7) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP1SR1_19_16 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DG2) FM(A12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP1SR1_23_20 FM(MSIOF1_TXD) FM(HRX3) FM(SCK3) F_(0, 0) FM(DU_DG3) FM(A13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP1SR1_27_24 FM(MSIOF1_SCK) FM(HSCK3) FM(CTS3_N) F_(0, 0) FM(DU_DG4) FM(A14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP1SR1_31_28 FM(MSIOF1_SYNC) FM(HRTS3_N) FM(RTS3_N) F_(0, 0) FM(DU_DG5) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 /* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
375 #define IP2SR1_3_0 FM(MSIOF1_SS1) FM(HCTS3_N) FM(RX3) F_(0, 0) FM(DU_DG6) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP2SR1_7_4 FM(MSIOF1_SS2) FM(HTX3) FM(TX3) F_(0, 0) FM(DU_DG7) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP2SR1_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) FM(DU_DB2) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP2SR1_15_12 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) FM(DU_DB3) FM(A19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP2SR1_19_16 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) FM(DU_DB4) FM(A20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP2SR1_23_20 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1_A) F_(0, 0) FM(DU_DB5) FM(A21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP2SR1_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1_A) F_(0, 0) FM(DU_DB6) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP2SR1_31_28 FM(MSIOF2_SS2) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(DU_DB7) FM(A23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
385 #define IP3SR1_3_0 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKOUT) FM(A24) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP3SR1_7_4 FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_HSYNC) FM(A25) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP3SR1_11_8 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_VSYNC) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP3SR1_15_12 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_ODDF_DISP_CDE) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP3SR1_19_16 FM(GP1_28) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP3SR1_23_20 FM(GP1_29) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP3SR1_27_24 FM(GP1_30) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP3SR1_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
395 #define IP0SR2_3_0 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP0SR2_7_4 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP0SR2_11_8 FM(GP2_02) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP0SR2_15_12 FM(GP2_03) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399 #define IP0SR2_19_16 FM(GP2_04) F_(0, 0) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) FM(D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP0SR2_23_20 FM(GP2_05) FM(HSCK2) FM(MSIOF4_TXD) FM(SCK4) F_(0, 0) FM(D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 #define IP0SR2_27_24 FM(GP2_06) FM(HCTS2_N) FM(MSIOF4_SCK) FM(CTS4_N) F_(0, 0) FM(D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402 #define IP0SR2_31_28 FM(GP2_07) FM(HRTS2_N) FM(MSIOF4_SYNC) FM(RTS4_N) F_(0, 0) FM(D8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
404 #define IP1SR2_3_0 FM(GP2_08) FM(HRX2) FM(MSIOF4_SS1) FM(RX4) F_(0, 0) FM(D9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405 #define IP1SR2_7_4 FM(GP2_09) FM(HTX2) FM(MSIOF4_SS2) FM(TX4) F_(0, 0) FM(D10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
406 #define IP1SR2_11_8 FM(GP2_10) FM(TCLK2_B) FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) FM(D11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
407 #define IP1SR2_15_12 FM(GP2_11) FM(TCLK3) FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) FM(D12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
408 #define IP1SR2_19_16 FM(GP2_12) FM(TCLK4) FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) FM(D13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
409 #define IP1SR2_23_20 FM(GP2_13) F_(0, 0) FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410 #define IP1SR2_27_24 FM(GP2_14) FM(IRQ4) FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
411 #define IP1SR2_31_28 FM(GP2_15) FM(IRQ5) FM(MSIOF5_SS2) FM(CPG_CPCKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
412 /* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
413 #define IP2SR2_3_0 FM(FXR_TXDA_A) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
414 #define IP2SR2_7_4 FM(RXDA_EXTFXR_A) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(BS_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
415 #define IP2SR2_11_8 FM(FXR_TXDB) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
416 #define IP2SR2_15_12 FM(RXDB_EXTFXR) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
417 #define IP2SR2_19_16 FM(CLK_EXTFXR) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
418 #define IP2SR2_23_20 FM(TPU0TO0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_WR_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
419 #define IP2SR2_27_24 FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
420 #define IP2SR2_31_28 FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(EX_WAIT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
422 /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
423 #define IP0SR3_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
424 #define IP0SR3_7_4 FM(CANFD0_TX) FM(FXR_TXDA_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
425 #define IP0SR3_11_8 FM(CANFD0_RX) FM(RXDA_EXTFXR_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
426 #define IP0SR3_15_12 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
427 #define IP0SR3_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
428 #define IP0SR3_23_20 FM(CANFD2_TX) FM(TPU0TO2) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
429 #define IP0SR3_27_24 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
430 #define IP0SR3_31_28 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
431 /* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
432 #define IP1SR3_3_0 FM(CANFD3_RX) F_(0, 0) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
433 #define IP1SR3_7_4 FM(CANFD4_TX) F_(0, 0) FM(PWM4) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
434 #define IP1SR3_11_8 FM(CANFD4_RX) F_(0, 0) F_(0, 0) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
435 #define IP1SR3_15_12 FM(CANFD5_TX) F_(0, 0) F_(0, 0) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
436 #define IP1SR3_19_16 FM(CANFD5_RX) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
437 #define IP1SR3_23_20 FM(CANFD6_TX) F_(0, 0) F_(0, 0) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
438 #define IP1SR3_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
439 #define IP1SR3_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
441 /* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
442 #define IP0SR4_3_0 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
443 #define IP0SR4_7_4 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
444 #define IP0SR4_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
445 #define IP0SR4_15_12 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
446 #define IP0SR4_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
447 #define IP0SR4_23_20 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
448 #define IP0SR4_27_24 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
449 #define IP0SR4_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
450 /* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
451 #define IP1SR4_3_0 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
452 #define IP1SR4_7_4 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
453 #define IP1SR4_11_8 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
454 #define IP1SR4_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
455 #define IP1SR4_19_16 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
456 #define IP1SR4_23_20 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
457 #define IP1SR4_27_24 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
458 #define IP1SR4_31_28 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
459 /* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
460 #define IP2SR4_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
461 #define IP2SR4_7_4 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
462 #define IP2SR4_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
463 #define IP2SR4_15_12 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
464 #define IP2SR4_19_16 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
465 #define IP2SR4_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
466 #define IP2SR4_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
467 #define IP2SR4_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
469 /* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
470 #define IP0SR5_3_0 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
471 #define IP0SR5_7_4 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
472 #define IP0SR5_11_8 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
473 #define IP0SR5_15_12 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
474 #define IP0SR5_19_16 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define IP0SR5_23_20 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
476 #define IP0SR5_27_24 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
477 #define IP0SR5_31_28 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
478 /* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
479 #define IP1SR5_3_0 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
480 #define IP1SR5_7_4 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
481 #define IP1SR5_11_8 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
482 #define IP1SR5_15_12 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
483 #define IP1SR5_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
484 #define IP1SR5_23_20 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
485 #define IP1SR5_27_24 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
486 #define IP1SR5_31_28 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
487 /* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
488 #define IP2SR5_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
489 #define IP2SR5_7_4 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
490 #define IP2SR5_11_8 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
491 #define IP2SR5_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
492 #define IP2SR5_19_16 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
493 #define IP2SR5_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
494 #define IP2SR5_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
495 #define IP2SR5_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
497 #define PINMUX_GPSR \
503 GPSR0_26 GPSR1_26 GPSR4_26 \
504 GPSR0_25 GPSR1_25 GPSR4_25 \
505 GPSR0_24 GPSR1_24 GPSR2_24 GPSR4_24 \
506 GPSR0_23 GPSR1_23 GPSR2_23 GPSR4_23 \
507 GPSR0_22 GPSR1_22 GPSR2_22 GPSR4_22 \
508 GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
509 GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 GPSR8_20 GPSR9_20 \
510 GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 GPSR8_19 GPSR9_19 \
511 GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 GPSR8_18 GPSR9_18 \
512 GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 GPSR8_17 GPSR9_17 \
513 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 GPSR8_16 GPSR9_16 \
514 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 GPSR8_15 GPSR9_15 \
515 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 GPSR8_14 GPSR9_14 \
516 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 GPSR9_13 \
517 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 GPSR9_12 \
518 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 GPSR9_11 \
519 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 GPSR9_10 \
520 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 GPSR9_9 \
521 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 GPSR9_8 \
522 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 GPSR9_7 \
523 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 GPSR9_6 \
524 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 GPSR9_5 \
525 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 GPSR9_4 \
526 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 GPSR9_3 \
527 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 GPSR9_2 \
528 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 GPSR9_1 \
529 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0 GPSR9_0
531 #define PINMUX_IPSR \
533 FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \
534 FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \
535 FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \
536 FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
537 FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
538 FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \
539 FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \
540 FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 FM(IP3SR1_31_28) IP3SR1_31_28 \
542 FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
543 FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
544 FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \
545 FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \
546 FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 FM(IP2SR2_19_16) IP2SR2_19_16 \
547 FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2SR2_23_20 \
548 FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \
549 FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \
551 FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 \
552 FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 \
553 FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 \
554 FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 \
555 FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 \
556 FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 \
557 FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 \
558 FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 \
560 FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 \
561 FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \
562 FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \
563 FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \
564 FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \
565 FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \
566 FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \
567 FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \
569 FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \
570 FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \
571 FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \
572 FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \
573 FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \
574 FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 FM(IP2SR5_23_20) IP2SR5_23_20 \
575 FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 FM(IP2SR5_27_24) IP2SR5_27_24 \
576 FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 FM(IP2SR5_31_28) IP2SR5_31_28
578 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
579 #define MOD_SEL2_14_15 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3)
580 #define MOD_SEL2_12_13 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3)
581 #define MOD_SEL2_10_11 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3)
582 #define MOD_SEL2_8_9 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3)
583 #define MOD_SEL2_6_7 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3)
584 #define MOD_SEL2_4_5 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3)
585 #define MOD_SEL2_2_3 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3)
587 #define PINMUX_MOD_SELS \
597 #define PINMUX_PHYS \
598 FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \
599 FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5) FM(SCL6) FM(SDA6)
609 #define FM(x) FN_##x,
610 PINMUX_FUNCTION_BEGIN,
620 #define FM(x) x##_MARK,
631 static const u16 pinmux_data[] = {
632 PINMUX_DATA_GP_ALL(),
634 PINMUX_SINGLE(MMC_D7),
635 PINMUX_SINGLE(MMC_D6),
636 PINMUX_SINGLE(MMC_D5),
637 PINMUX_SINGLE(MMC_D4),
638 PINMUX_SINGLE(MMC_SD_CLK),
639 PINMUX_SINGLE(MMC_SD_D3),
640 PINMUX_SINGLE(MMC_SD_D2),
641 PINMUX_SINGLE(MMC_SD_D1),
642 PINMUX_SINGLE(MMC_SD_D0),
643 PINMUX_SINGLE(MMC_SD_CMD),
644 PINMUX_SINGLE(MMC_DS),
646 PINMUX_SINGLE(SD_CD),
647 PINMUX_SINGLE(SD_WP),
649 PINMUX_SINGLE(RPC_INT_N),
650 PINMUX_SINGLE(RPC_WP_N),
651 PINMUX_SINGLE(RPC_RESET_N),
653 PINMUX_SINGLE(QSPI1_SSL),
654 PINMUX_SINGLE(QSPI1_IO3),
655 PINMUX_SINGLE(QSPI1_IO2),
656 PINMUX_SINGLE(QSPI1_MISO_IO1),
657 PINMUX_SINGLE(QSPI1_MOSI_IO0),
658 PINMUX_SINGLE(QSPI1_SPCLK),
659 PINMUX_SINGLE(QSPI0_SSL),
660 PINMUX_SINGLE(QSPI0_IO3),
661 PINMUX_SINGLE(QSPI0_IO2),
662 PINMUX_SINGLE(QSPI0_MISO_IO1),
663 PINMUX_SINGLE(QSPI0_MOSI_IO0),
664 PINMUX_SINGLE(QSPI0_SPCLK),
666 PINMUX_SINGLE(TCLK2_A),
668 PINMUX_SINGLE(CANFD7_RX),
669 PINMUX_SINGLE(CANFD7_TX),
670 PINMUX_SINGLE(CANFD6_RX),
671 PINMUX_SINGLE(CANFD1_RX),
672 PINMUX_SINGLE(CANFD1_TX),
673 PINMUX_SINGLE(CAN_CLK),
678 PINMUX_SINGLE(PCIE3_CLKREQ_N),
679 PINMUX_SINGLE(PCIE2_CLKREQ_N),
680 PINMUX_SINGLE(PCIE1_CLKREQ_N),
681 PINMUX_SINGLE(PCIE0_CLKREQ_N),
683 PINMUX_SINGLE(AVB0_PHY_INT),
684 PINMUX_SINGLE(AVB0_MAGIC),
685 PINMUX_SINGLE(AVB0_MDC),
686 PINMUX_SINGLE(AVB0_MDIO),
687 PINMUX_SINGLE(AVB0_TXCREFCLK),
689 PINMUX_SINGLE(AVB1_PHY_INT),
690 PINMUX_SINGLE(AVB1_MAGIC),
691 PINMUX_SINGLE(AVB1_MDC),
692 PINMUX_SINGLE(AVB1_MDIO),
693 PINMUX_SINGLE(AVB1_TXCREFCLK),
695 PINMUX_SINGLE(AVB2_AVTP_PPS),
696 PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
697 PINMUX_SINGLE(AVB2_AVTP_MATCH),
698 PINMUX_SINGLE(AVB2_LINK),
699 PINMUX_SINGLE(AVB2_PHY_INT),
700 PINMUX_SINGLE(AVB2_MAGIC),
701 PINMUX_SINGLE(AVB2_MDC),
702 PINMUX_SINGLE(AVB2_MDIO),
703 PINMUX_SINGLE(AVB2_TXCREFCLK),
704 PINMUX_SINGLE(AVB2_TD3),
705 PINMUX_SINGLE(AVB2_TD2),
706 PINMUX_SINGLE(AVB2_TD1),
707 PINMUX_SINGLE(AVB2_TD0),
708 PINMUX_SINGLE(AVB2_TXC),
709 PINMUX_SINGLE(AVB2_TX_CTL),
710 PINMUX_SINGLE(AVB2_RD3),
711 PINMUX_SINGLE(AVB2_RD2),
712 PINMUX_SINGLE(AVB2_RD1),
713 PINMUX_SINGLE(AVB2_RD0),
714 PINMUX_SINGLE(AVB2_RXC),
715 PINMUX_SINGLE(AVB2_RX_CTL),
717 PINMUX_SINGLE(AVB3_AVTP_PPS),
718 PINMUX_SINGLE(AVB3_AVTP_CAPTURE),
719 PINMUX_SINGLE(AVB3_AVTP_MATCH),
720 PINMUX_SINGLE(AVB3_LINK),
721 PINMUX_SINGLE(AVB3_PHY_INT),
722 PINMUX_SINGLE(AVB3_MAGIC),
723 PINMUX_SINGLE(AVB3_MDC),
724 PINMUX_SINGLE(AVB3_MDIO),
725 PINMUX_SINGLE(AVB3_TXCREFCLK),
726 PINMUX_SINGLE(AVB3_TD3),
727 PINMUX_SINGLE(AVB3_TD2),
728 PINMUX_SINGLE(AVB3_TD1),
729 PINMUX_SINGLE(AVB3_TD0),
730 PINMUX_SINGLE(AVB3_TXC),
731 PINMUX_SINGLE(AVB3_TX_CTL),
732 PINMUX_SINGLE(AVB3_RD3),
733 PINMUX_SINGLE(AVB3_RD2),
734 PINMUX_SINGLE(AVB3_RD1),
735 PINMUX_SINGLE(AVB3_RD0),
736 PINMUX_SINGLE(AVB3_RXC),
737 PINMUX_SINGLE(AVB3_RX_CTL),
739 PINMUX_SINGLE(AVB4_AVTP_PPS),
740 PINMUX_SINGLE(AVB4_AVTP_CAPTURE),
741 PINMUX_SINGLE(AVB4_AVTP_MATCH),
742 PINMUX_SINGLE(AVB4_LINK),
743 PINMUX_SINGLE(AVB4_PHY_INT),
744 PINMUX_SINGLE(AVB4_MAGIC),
745 PINMUX_SINGLE(AVB4_MDC),
746 PINMUX_SINGLE(AVB4_MDIO),
747 PINMUX_SINGLE(AVB4_TXCREFCLK),
748 PINMUX_SINGLE(AVB4_TD3),
749 PINMUX_SINGLE(AVB4_TD2),
750 PINMUX_SINGLE(AVB4_TD1),
751 PINMUX_SINGLE(AVB4_TD0),
752 PINMUX_SINGLE(AVB4_TXC),
753 PINMUX_SINGLE(AVB4_TX_CTL),
754 PINMUX_SINGLE(AVB4_RD3),
755 PINMUX_SINGLE(AVB4_RD2),
756 PINMUX_SINGLE(AVB4_RD1),
757 PINMUX_SINGLE(AVB4_RD0),
758 PINMUX_SINGLE(AVB4_RXC),
759 PINMUX_SINGLE(AVB4_RX_CTL),
761 PINMUX_SINGLE(AVB5_AVTP_PPS),
762 PINMUX_SINGLE(AVB5_AVTP_CAPTURE),
763 PINMUX_SINGLE(AVB5_AVTP_MATCH),
764 PINMUX_SINGLE(AVB5_LINK),
765 PINMUX_SINGLE(AVB5_PHY_INT),
766 PINMUX_SINGLE(AVB5_MAGIC),
767 PINMUX_SINGLE(AVB5_MDC),
768 PINMUX_SINGLE(AVB5_MDIO),
769 PINMUX_SINGLE(AVB5_TXCREFCLK),
770 PINMUX_SINGLE(AVB5_TD3),
771 PINMUX_SINGLE(AVB5_TD2),
772 PINMUX_SINGLE(AVB5_TD1),
773 PINMUX_SINGLE(AVB5_TD0),
774 PINMUX_SINGLE(AVB5_TXC),
775 PINMUX_SINGLE(AVB5_TX_CTL),
776 PINMUX_SINGLE(AVB5_RD3),
777 PINMUX_SINGLE(AVB5_RD2),
778 PINMUX_SINGLE(AVB5_RD1),
779 PINMUX_SINGLE(AVB5_RD0),
780 PINMUX_SINGLE(AVB5_RXC),
781 PINMUX_SINGLE(AVB5_RX_CTL),
784 PINMUX_IPSR_GPSR(IP0SR1_3_0, SCIF_CLK),
785 PINMUX_IPSR_GPSR(IP0SR1_3_0, A0),
787 PINMUX_IPSR_GPSR(IP0SR1_7_4, HRX0),
788 PINMUX_IPSR_GPSR(IP0SR1_7_4, RX0),
789 PINMUX_IPSR_GPSR(IP0SR1_7_4, A1),
791 PINMUX_IPSR_GPSR(IP0SR1_11_8, HSCK0),
792 PINMUX_IPSR_GPSR(IP0SR1_11_8, SCK0),
793 PINMUX_IPSR_GPSR(IP0SR1_11_8, A2),
795 PINMUX_IPSR_GPSR(IP0SR1_15_12, HRTS0_N),
796 PINMUX_IPSR_GPSR(IP0SR1_15_12, RTS0_N),
797 PINMUX_IPSR_GPSR(IP0SR1_15_12, A3),
799 PINMUX_IPSR_GPSR(IP0SR1_19_16, HCTS0_N),
800 PINMUX_IPSR_GPSR(IP0SR1_19_16, CTS0_N),
801 PINMUX_IPSR_GPSR(IP0SR1_19_16, A4),
803 PINMUX_IPSR_GPSR(IP0SR1_23_20, HTX0),
804 PINMUX_IPSR_GPSR(IP0SR1_23_20, TX0),
805 PINMUX_IPSR_GPSR(IP0SR1_23_20, A5),
807 PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_RXD),
808 PINMUX_IPSR_GPSR(IP0SR1_27_24, DU_DR2),
809 PINMUX_IPSR_GPSR(IP0SR1_27_24, A6),
811 PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_TXD),
812 PINMUX_IPSR_GPSR(IP0SR1_31_28, DU_DR3),
813 PINMUX_IPSR_GPSR(IP0SR1_31_28, A7),
816 PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SCK),
817 PINMUX_IPSR_GPSR(IP1SR1_3_0, DU_DR4),
818 PINMUX_IPSR_GPSR(IP1SR1_3_0, A8),
820 PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_SYNC),
821 PINMUX_IPSR_GPSR(IP1SR1_7_4, DU_DR5),
822 PINMUX_IPSR_GPSR(IP1SR1_7_4, A9),
824 PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SS1),
825 PINMUX_IPSR_GPSR(IP1SR1_11_8, DU_DR6),
826 PINMUX_IPSR_GPSR(IP1SR1_11_8, A10),
828 PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_SS2),
829 PINMUX_IPSR_GPSR(IP1SR1_15_12, DU_DR7),
830 PINMUX_IPSR_GPSR(IP1SR1_15_12, A11),
832 PINMUX_IPSR_GPSR(IP1SR1_19_16, MSIOF1_RXD),
833 PINMUX_IPSR_GPSR(IP1SR1_19_16, DU_DG2),
834 PINMUX_IPSR_GPSR(IP1SR1_19_16, A12),
836 PINMUX_IPSR_GPSR(IP1SR1_23_20, MSIOF1_TXD),
837 PINMUX_IPSR_GPSR(IP1SR1_23_20, HRX3),
838 PINMUX_IPSR_GPSR(IP1SR1_23_20, SCK3),
839 PINMUX_IPSR_GPSR(IP1SR1_23_20, DU_DG3),
840 PINMUX_IPSR_GPSR(IP1SR1_23_20, A13),
842 PINMUX_IPSR_GPSR(IP1SR1_27_24, MSIOF1_SCK),
843 PINMUX_IPSR_GPSR(IP1SR1_27_24, HSCK3),
844 PINMUX_IPSR_GPSR(IP1SR1_27_24, CTS3_N),
845 PINMUX_IPSR_GPSR(IP1SR1_27_24, DU_DG4),
846 PINMUX_IPSR_GPSR(IP1SR1_27_24, A14),
848 PINMUX_IPSR_GPSR(IP1SR1_31_28, MSIOF1_SYNC),
849 PINMUX_IPSR_GPSR(IP1SR1_31_28, HRTS3_N),
850 PINMUX_IPSR_GPSR(IP1SR1_31_28, RTS3_N),
851 PINMUX_IPSR_GPSR(IP1SR1_31_28, DU_DG5),
852 PINMUX_IPSR_GPSR(IP1SR1_31_28, A15),
855 PINMUX_IPSR_GPSR(IP2SR1_3_0, MSIOF1_SS1),
856 PINMUX_IPSR_GPSR(IP2SR1_3_0, HCTS3_N),
857 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX3),
858 PINMUX_IPSR_GPSR(IP2SR1_3_0, DU_DG6),
859 PINMUX_IPSR_GPSR(IP2SR1_3_0, A16),
861 PINMUX_IPSR_GPSR(IP2SR1_7_4, MSIOF1_SS2),
862 PINMUX_IPSR_GPSR(IP2SR1_7_4, HTX3),
863 PINMUX_IPSR_GPSR(IP2SR1_7_4, TX3),
864 PINMUX_IPSR_GPSR(IP2SR1_7_4, DU_DG7),
865 PINMUX_IPSR_GPSR(IP2SR1_7_4, A17),
867 PINMUX_IPSR_GPSR(IP2SR1_11_8, MSIOF2_RXD),
868 PINMUX_IPSR_GPSR(IP2SR1_11_8, HSCK1),
869 PINMUX_IPSR_GPSR(IP2SR1_11_8, SCK1),
870 PINMUX_IPSR_GPSR(IP2SR1_11_8, DU_DB2),
871 PINMUX_IPSR_GPSR(IP2SR1_11_8, A18),
873 PINMUX_IPSR_GPSR(IP2SR1_15_12, MSIOF2_TXD),
874 PINMUX_IPSR_GPSR(IP2SR1_15_12, HCTS1_N),
875 PINMUX_IPSR_GPSR(IP2SR1_15_12, CTS1_N),
876 PINMUX_IPSR_GPSR(IP2SR1_15_12, DU_DB3),
877 PINMUX_IPSR_GPSR(IP2SR1_15_12, A19),
879 PINMUX_IPSR_GPSR(IP2SR1_19_16, MSIOF2_SCK),
880 PINMUX_IPSR_GPSR(IP2SR1_19_16, HRTS1_N),
881 PINMUX_IPSR_GPSR(IP2SR1_19_16, RTS1_N),
882 PINMUX_IPSR_GPSR(IP2SR1_19_16, DU_DB4),
883 PINMUX_IPSR_GPSR(IP2SR1_19_16, A20),
885 PINMUX_IPSR_GPSR(IP2SR1_23_20, MSIOF2_SYNC),
886 PINMUX_IPSR_GPSR(IP2SR1_23_20, HRX1),
887 PINMUX_IPSR_GPSR(IP2SR1_23_20, RX1_A),
888 PINMUX_IPSR_GPSR(IP2SR1_23_20, DU_DB5),
889 PINMUX_IPSR_GPSR(IP2SR1_23_20, A21),
891 PINMUX_IPSR_GPSR(IP2SR1_27_24, MSIOF2_SS1),
892 PINMUX_IPSR_GPSR(IP2SR1_27_24, HTX1),
893 PINMUX_IPSR_GPSR(IP2SR1_27_24, TX1_A),
894 PINMUX_IPSR_GPSR(IP2SR1_27_24, DU_DB6),
895 PINMUX_IPSR_GPSR(IP2SR1_27_24, A22),
897 PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF2_SS2),
898 PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK1_B),
899 PINMUX_IPSR_GPSR(IP2SR1_31_28, DU_DB7),
900 PINMUX_IPSR_GPSR(IP2SR1_31_28, A23),
903 PINMUX_IPSR_GPSR(IP3SR1_3_0, IRQ0),
904 PINMUX_IPSR_GPSR(IP3SR1_3_0, DU_DOTCLKOUT),
905 PINMUX_IPSR_GPSR(IP3SR1_3_0, A24),
907 PINMUX_IPSR_GPSR(IP3SR1_7_4, IRQ1),
908 PINMUX_IPSR_GPSR(IP3SR1_7_4, DU_HSYNC),
909 PINMUX_IPSR_GPSR(IP3SR1_7_4, A25),
911 PINMUX_IPSR_GPSR(IP3SR1_11_8, IRQ2),
912 PINMUX_IPSR_GPSR(IP3SR1_11_8, DU_VSYNC),
913 PINMUX_IPSR_GPSR(IP3SR1_11_8, CS1_N_A26),
915 PINMUX_IPSR_GPSR(IP3SR1_15_12, IRQ3),
916 PINMUX_IPSR_GPSR(IP3SR1_15_12, DU_ODDF_DISP_CDE),
917 PINMUX_IPSR_GPSR(IP3SR1_15_12, CS0_N),
919 PINMUX_IPSR_GPSR(IP3SR1_19_16, GP1_28),
920 PINMUX_IPSR_GPSR(IP3SR1_19_16, D0),
922 PINMUX_IPSR_GPSR(IP3SR1_23_20, GP1_29),
923 PINMUX_IPSR_GPSR(IP3SR1_23_20, D1),
925 PINMUX_IPSR_GPSR(IP3SR1_27_24, GP1_30),
926 PINMUX_IPSR_GPSR(IP3SR1_27_24, D2),
929 PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKIN),
930 PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKEN_IN),
931 PINMUX_IPSR_GPSR(IP0SR2_3_0, DU_DOTCLKIN),
933 PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKOUT),
934 PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKEN_OUT),
937 PINMUX_IPSR_MSEL(IP0SR2_11_8, GP2_02, SEL_I2C0_0),
938 PINMUX_IPSR_MSEL(IP0SR2_11_8, D3, SEL_I2C0_0),
939 PINMUX_IPSR_PHYS(IP0SR2_11_8, SCL0, SEL_I2C0_3),
942 PINMUX_IPSR_MSEL(IP0SR2_15_12, GP2_03, SEL_I2C0_0),
943 PINMUX_IPSR_MSEL(IP0SR2_15_12, D4, SEL_I2C0_0),
944 PINMUX_IPSR_PHYS(IP0SR2_15_12, SDA0, SEL_I2C0_3),
947 PINMUX_IPSR_MSEL(IP0SR2_19_16, GP2_04, SEL_I2C1_0),
948 PINMUX_IPSR_MSEL(IP0SR2_19_16, MSIOF4_RXD, SEL_I2C1_0),
949 PINMUX_IPSR_MSEL(IP0SR2_19_16, D5, SEL_I2C1_0),
950 PINMUX_IPSR_PHYS(IP0SR2_19_16, SCL1, SEL_I2C1_3),
953 PINMUX_IPSR_MSEL(IP0SR2_23_20, GP2_05, SEL_I2C1_0),
954 PINMUX_IPSR_MSEL(IP0SR2_23_20, HSCK2, SEL_I2C1_0),
955 PINMUX_IPSR_MSEL(IP0SR2_23_20, MSIOF4_TXD, SEL_I2C1_0),
956 PINMUX_IPSR_MSEL(IP0SR2_23_20, SCK4, SEL_I2C1_0),
957 PINMUX_IPSR_MSEL(IP0SR2_23_20, D6, SEL_I2C1_0),
958 PINMUX_IPSR_PHYS(IP0SR2_23_20, SDA1, SEL_I2C1_3),
961 PINMUX_IPSR_MSEL(IP0SR2_27_24, GP2_06, SEL_I2C2_0),
962 PINMUX_IPSR_MSEL(IP0SR2_27_24, HCTS2_N, SEL_I2C2_0),
963 PINMUX_IPSR_MSEL(IP0SR2_27_24, MSIOF4_SCK, SEL_I2C2_0),
964 PINMUX_IPSR_MSEL(IP0SR2_27_24, CTS4_N, SEL_I2C2_0),
965 PINMUX_IPSR_MSEL(IP0SR2_27_24, D7, SEL_I2C2_0),
966 PINMUX_IPSR_PHYS(IP0SR2_27_24, SCL2, SEL_I2C2_3),
969 PINMUX_IPSR_MSEL(IP0SR2_31_28, GP2_07, SEL_I2C2_0),
970 PINMUX_IPSR_MSEL(IP0SR2_31_28, HRTS2_N, SEL_I2C2_0),
971 PINMUX_IPSR_MSEL(IP0SR2_31_28, MSIOF4_SYNC, SEL_I2C2_0),
972 PINMUX_IPSR_MSEL(IP0SR2_31_28, RTS4_N, SEL_I2C2_0),
973 PINMUX_IPSR_MSEL(IP0SR2_31_28, D8, SEL_I2C2_0),
974 PINMUX_IPSR_PHYS(IP0SR2_31_28, SDA2, SEL_I2C2_3),
977 PINMUX_IPSR_MSEL(IP1SR2_3_0, GP2_08, SEL_I2C3_0),
978 PINMUX_IPSR_MSEL(IP1SR2_3_0, HRX2, SEL_I2C3_0),
979 PINMUX_IPSR_MSEL(IP1SR2_3_0, MSIOF4_SS1, SEL_I2C3_0),
980 PINMUX_IPSR_MSEL(IP1SR2_3_0, RX4, SEL_I2C3_0),
981 PINMUX_IPSR_MSEL(IP1SR2_3_0, D9, SEL_I2C3_0),
982 PINMUX_IPSR_PHYS(IP1SR2_3_0, SCL3, SEL_I2C3_3),
985 PINMUX_IPSR_MSEL(IP1SR2_7_4, GP2_09, SEL_I2C3_0),
986 PINMUX_IPSR_MSEL(IP1SR2_7_4, HTX2, SEL_I2C3_0),
987 PINMUX_IPSR_MSEL(IP1SR2_7_4, MSIOF4_SS2, SEL_I2C3_0),
988 PINMUX_IPSR_MSEL(IP1SR2_7_4, TX4, SEL_I2C3_0),
989 PINMUX_IPSR_MSEL(IP1SR2_7_4, D10, SEL_I2C3_0),
990 PINMUX_IPSR_PHYS(IP1SR2_7_4, SDA3, SEL_I2C3_3),
993 PINMUX_IPSR_MSEL(IP1SR2_11_8, GP2_10, SEL_I2C4_0),
994 PINMUX_IPSR_MSEL(IP1SR2_11_8, TCLK2_B, SEL_I2C4_0),
995 PINMUX_IPSR_MSEL(IP1SR2_11_8, MSIOF5_RXD, SEL_I2C4_0),
996 PINMUX_IPSR_MSEL(IP1SR2_11_8, D11, SEL_I2C4_0),
997 PINMUX_IPSR_PHYS(IP1SR2_11_8, SCL4, SEL_I2C4_3),
1000 PINMUX_IPSR_MSEL(IP1SR2_15_12, GP2_11, SEL_I2C4_0),
1001 PINMUX_IPSR_MSEL(IP1SR2_15_12, TCLK3, SEL_I2C4_0),
1002 PINMUX_IPSR_MSEL(IP1SR2_15_12, MSIOF5_TXD, SEL_I2C4_0),
1003 PINMUX_IPSR_MSEL(IP1SR2_15_12, D12, SEL_I2C4_0),
1004 PINMUX_IPSR_PHYS(IP1SR2_15_12, SDA4, SEL_I2C4_3),
1007 PINMUX_IPSR_MSEL(IP1SR2_19_16, GP2_12, SEL_I2C5_0),
1008 PINMUX_IPSR_MSEL(IP1SR2_19_16, TCLK4, SEL_I2C5_0),
1009 PINMUX_IPSR_MSEL(IP1SR2_19_16, MSIOF5_SCK, SEL_I2C5_0),
1010 PINMUX_IPSR_MSEL(IP1SR2_19_16, D13, SEL_I2C5_0),
1011 PINMUX_IPSR_PHYS(IP1SR2_19_16, SCL5, SEL_I2C5_3),
1014 PINMUX_IPSR_MSEL(IP1SR2_23_20, GP2_13, SEL_I2C5_0),
1015 PINMUX_IPSR_MSEL(IP1SR2_23_20, MSIOF5_SYNC, SEL_I2C5_0),
1016 PINMUX_IPSR_MSEL(IP1SR2_23_20, D14, SEL_I2C5_0),
1017 PINMUX_IPSR_PHYS(IP1SR2_23_20, SDA5, SEL_I2C5_3),
1020 PINMUX_IPSR_MSEL(IP1SR2_27_24, GP2_14, SEL_I2C6_0),
1021 PINMUX_IPSR_MSEL(IP1SR2_27_24, IRQ4, SEL_I2C6_0),
1022 PINMUX_IPSR_MSEL(IP1SR2_27_24, MSIOF5_SS1, SEL_I2C6_0),
1023 PINMUX_IPSR_MSEL(IP1SR2_27_24, D15, SEL_I2C6_0),
1024 PINMUX_IPSR_PHYS(IP1SR2_27_24, SCL6, SEL_I2C6_3),
1027 PINMUX_IPSR_MSEL(IP1SR2_31_28, GP2_15, SEL_I2C6_0),
1028 PINMUX_IPSR_MSEL(IP1SR2_31_28, IRQ5, SEL_I2C6_0),
1029 PINMUX_IPSR_MSEL(IP1SR2_31_28, MSIOF5_SS2, SEL_I2C6_0),
1030 PINMUX_IPSR_MSEL(IP1SR2_31_28, CPG_CPCKOUT, SEL_I2C6_0),
1031 PINMUX_IPSR_PHYS(IP1SR2_31_28, SDA6, SEL_I2C6_3),
1034 PINMUX_IPSR_GPSR(IP2SR2_3_0, FXR_TXDA_A),
1035 PINMUX_IPSR_GPSR(IP2SR2_3_0, MSIOF3_SS1),
1037 PINMUX_IPSR_GPSR(IP2SR2_7_4, RXDA_EXTFXR_A),
1038 PINMUX_IPSR_GPSR(IP2SR2_7_4, MSIOF3_SS2),
1039 PINMUX_IPSR_GPSR(IP2SR2_7_4, BS_N),
1041 PINMUX_IPSR_GPSR(IP2SR2_11_8, FXR_TXDB),
1042 PINMUX_IPSR_GPSR(IP2SR2_11_8, MSIOF3_RXD),
1043 PINMUX_IPSR_GPSR(IP2SR2_11_8, RD_N),
1045 PINMUX_IPSR_GPSR(IP2SR2_15_12, RXDB_EXTFXR),
1046 PINMUX_IPSR_GPSR(IP2SR2_15_12, MSIOF3_TXD),
1047 PINMUX_IPSR_GPSR(IP2SR2_15_12, WE0_N),
1049 PINMUX_IPSR_GPSR(IP2SR2_19_16, CLK_EXTFXR),
1050 PINMUX_IPSR_GPSR(IP2SR2_19_16, MSIOF3_SCK),
1051 PINMUX_IPSR_GPSR(IP2SR2_19_16, WE1_N),
1053 PINMUX_IPSR_GPSR(IP2SR2_23_20, TPU0TO0),
1054 PINMUX_IPSR_GPSR(IP2SR2_23_20, MSIOF3_SYNC),
1055 PINMUX_IPSR_GPSR(IP2SR2_23_20, RD_WR_N),
1057 PINMUX_IPSR_GPSR(IP2SR2_27_24, TPU0TO1),
1058 PINMUX_IPSR_GPSR(IP2SR2_27_24, CLKOUT),
1060 PINMUX_IPSR_GPSR(IP2SR2_31_28, TCLK1_A),
1061 PINMUX_IPSR_GPSR(IP2SR2_31_28, EX_WAIT0),
1064 PINMUX_IPSR_GPSR(IP0SR3_7_4, CANFD0_TX),
1065 PINMUX_IPSR_GPSR(IP0SR3_7_4, FXR_TXDA_B),
1066 PINMUX_IPSR_GPSR(IP0SR3_7_4, TX1_B),
1068 PINMUX_IPSR_GPSR(IP0SR3_11_8, CANFD0_RX),
1069 PINMUX_IPSR_GPSR(IP0SR3_11_8, RXDA_EXTFXR_B),
1070 PINMUX_IPSR_GPSR(IP0SR3_11_8, RX1_B),
1072 PINMUX_IPSR_GPSR(IP0SR3_23_20, CANFD2_TX),
1073 PINMUX_IPSR_GPSR(IP0SR3_23_20, TPU0TO2),
1074 PINMUX_IPSR_GPSR(IP0SR3_23_20, PWM0),
1076 PINMUX_IPSR_GPSR(IP0SR3_27_24, CANFD2_RX),
1077 PINMUX_IPSR_GPSR(IP0SR3_27_24, TPU0TO3),
1078 PINMUX_IPSR_GPSR(IP0SR3_27_24, PWM1),
1080 PINMUX_IPSR_GPSR(IP0SR3_31_28, CANFD3_TX),
1081 PINMUX_IPSR_GPSR(IP0SR3_31_28, PWM2),
1084 PINMUX_IPSR_GPSR(IP1SR3_3_0, CANFD3_RX),
1085 PINMUX_IPSR_GPSR(IP1SR3_3_0, PWM3),
1087 PINMUX_IPSR_GPSR(IP1SR3_7_4, CANFD4_TX),
1088 PINMUX_IPSR_GPSR(IP1SR3_7_4, PWM4),
1089 PINMUX_IPSR_GPSR(IP1SR3_7_4, FXR_CLKOUT1),
1091 PINMUX_IPSR_GPSR(IP1SR3_11_8, CANFD4_RX),
1092 PINMUX_IPSR_GPSR(IP1SR3_11_8, FXR_CLKOUT2),
1094 PINMUX_IPSR_GPSR(IP1SR3_15_12, CANFD5_TX),
1095 PINMUX_IPSR_GPSR(IP1SR3_15_12, FXR_TXENA_N),
1097 PINMUX_IPSR_GPSR(IP1SR3_19_16, CANFD5_RX),
1098 PINMUX_IPSR_GPSR(IP1SR3_19_16, FXR_TXENB_N),
1100 PINMUX_IPSR_GPSR(IP1SR3_23_20, CANFD6_TX),
1101 PINMUX_IPSR_GPSR(IP1SR3_23_20, STPWT_EXTFXR),
1104 PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_RX_CTL),
1105 PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_MII_RX_DV),
1107 PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_RXC),
1108 PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_MII_RXC),
1110 PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_RD0),
1111 PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_MII_RD0),
1113 PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_RD1),
1114 PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_MII_RD1),
1116 PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_RD2),
1117 PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_MII_RD2),
1119 PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_RD3),
1120 PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_MII_RD3),
1122 PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_TX_CTL),
1123 PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_MII_TX_EN),
1125 PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_TXC),
1126 PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_MII_TXC),
1129 PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_TD0),
1130 PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_MII_TD0),
1132 PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_TD1),
1133 PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_MII_TD1),
1135 PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_TD2),
1136 PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_MII_TD2),
1138 PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_TD3),
1139 PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_MII_TD3),
1141 PINMUX_IPSR_GPSR(IP1SR4_19_16, AVB0_TXCREFCLK),
1143 PINMUX_IPSR_GPSR(IP1SR4_23_20, AVB0_MDIO),
1145 PINMUX_IPSR_GPSR(IP1SR4_27_24, AVB0_MDC),
1147 PINMUX_IPSR_GPSR(IP1SR4_31_28, AVB0_MAGIC),
1150 PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_LINK),
1151 PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_MII_TX_ER),
1153 PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_AVTP_MATCH),
1154 PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_MII_RX_ER),
1155 PINMUX_IPSR_GPSR(IP2SR4_11_8, CC5_OSCOUT),
1157 PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_AVTP_CAPTURE),
1158 PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_MII_CRS),
1160 PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_AVTP_PPS),
1161 PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_MII_COL),
1164 PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_RX_CTL),
1165 PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_MII_RX_DV),
1167 PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_RXC),
1168 PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_MII_RXC),
1170 PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_RD0),
1171 PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_MII_RD0),
1173 PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_RD1),
1174 PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_MII_RD1),
1176 PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_RD2),
1177 PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_MII_RD2),
1179 PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_RD3),
1180 PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_MII_RD3),
1182 PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_TX_CTL),
1183 PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_MII_TX_EN),
1185 PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_TXC),
1186 PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_MII_TXC),
1189 PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_TD0),
1190 PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_MII_TD0),
1192 PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_TD1),
1193 PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_MII_TD1),
1195 PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_TD2),
1196 PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_MII_TD2),
1198 PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_TD3),
1199 PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_MII_TD3),
1201 PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB1_TXCREFCLK),
1203 PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB1_MDIO),
1205 PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB1_MDC),
1207 PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB1_MAGIC),
1210 PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_LINK),
1211 PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_MII_TX_ER),
1213 PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_AVTP_MATCH),
1214 PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_MII_RX_ER),
1216 PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_AVTP_CAPTURE),
1217 PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_MII_CRS),
1219 PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_AVTP_PPS),
1220 PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_MII_COL),
1224 * Pins not associated with a GPIO port.
1231 static const struct sh_pfc_pin pinmux_pins[] = {
1232 PINMUX_GPIO_GP_ALL(),
1235 /* - AVB0 ------------------------------------------------ */
1236 static const unsigned int avb0_link_pins[] = {
1240 static const unsigned int avb0_link_mux[] = {
1243 static const unsigned int avb0_magic_pins[] = {
1247 static const unsigned int avb0_magic_mux[] = {
1250 static const unsigned int avb0_phy_int_pins[] = {
1254 static const unsigned int avb0_phy_int_mux[] = {
1257 static const unsigned int avb0_mdio_pins[] = {
1258 /* AVB0_MDC, AVB0_MDIO */
1259 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1261 static const unsigned int avb0_mdio_mux[] = {
1262 AVB0_MDC_MARK, AVB0_MDIO_MARK,
1264 static const unsigned int avb0_rgmii_pins[] = {
1266 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
1267 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
1269 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1270 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1271 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1272 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1273 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1274 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1276 static const unsigned int avb0_rgmii_mux[] = {
1277 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
1278 AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
1279 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
1280 AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
1282 static const unsigned int avb0_txcrefclk_pins[] = {
1283 /* AVB0_TXCREFCLK */
1286 static const unsigned int avb0_txcrefclk_mux[] = {
1287 AVB0_TXCREFCLK_MARK,
1289 static const unsigned int avb0_avtp_pps_pins[] = {
1293 static const unsigned int avb0_avtp_pps_mux[] = {
1296 static const unsigned int avb0_avtp_capture_pins[] = {
1297 /* AVB0_AVTP_CAPTURE */
1300 static const unsigned int avb0_avtp_capture_mux[] = {
1301 AVB0_AVTP_CAPTURE_MARK,
1303 static const unsigned int avb0_avtp_match_pins[] = {
1304 /* AVB0_AVTP_MATCH */
1307 static const unsigned int avb0_avtp_match_mux[] = {
1308 AVB0_AVTP_MATCH_MARK,
1311 /* - AVB1 ------------------------------------------------ */
1312 static const unsigned int avb1_link_pins[] = {
1316 static const unsigned int avb1_link_mux[] = {
1319 static const unsigned int avb1_magic_pins[] = {
1323 static const unsigned int avb1_magic_mux[] = {
1326 static const unsigned int avb1_phy_int_pins[] = {
1330 static const unsigned int avb1_phy_int_mux[] = {
1333 static const unsigned int avb1_mdio_pins[] = {
1334 /* AVB1_MDC, AVB1_MDIO */
1335 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 13),
1337 static const unsigned int avb1_mdio_mux[] = {
1338 AVB1_MDC_MARK, AVB1_MDIO_MARK,
1340 static const unsigned int avb1_rgmii_pins[] = {
1342 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
1343 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
1345 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1346 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1347 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1348 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
1349 RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1350 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1352 static const unsigned int avb1_rgmii_mux[] = {
1353 AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
1354 AVB1_TD0_MARK, AVB1_TD1_MARK, AVB1_TD2_MARK, AVB1_TD3_MARK,
1355 AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
1356 AVB1_RD0_MARK, AVB1_RD1_MARK, AVB1_RD2_MARK, AVB1_RD3_MARK,
1358 static const unsigned int avb1_txcrefclk_pins[] = {
1359 /* AVB1_TXCREFCLK */
1362 static const unsigned int avb1_txcrefclk_mux[] = {
1363 AVB1_TXCREFCLK_MARK,
1365 static const unsigned int avb1_avtp_pps_pins[] = {
1369 static const unsigned int avb1_avtp_pps_mux[] = {
1372 static const unsigned int avb1_avtp_capture_pins[] = {
1373 /* AVB1_AVTP_CAPTURE */
1376 static const unsigned int avb1_avtp_capture_mux[] = {
1377 AVB1_AVTP_CAPTURE_MARK,
1379 static const unsigned int avb1_avtp_match_pins[] = {
1380 /* AVB1_AVTP_MATCH */
1383 static const unsigned int avb1_avtp_match_mux[] = {
1384 AVB1_AVTP_MATCH_MARK,
1387 /* - AVB2 ------------------------------------------------ */
1388 static const unsigned int avb2_link_pins[] = {
1392 static const unsigned int avb2_link_mux[] = {
1395 static const unsigned int avb2_magic_pins[] = {
1399 static const unsigned int avb2_magic_mux[] = {
1402 static const unsigned int avb2_phy_int_pins[] = {
1406 static const unsigned int avb2_phy_int_mux[] = {
1409 static const unsigned int avb2_mdio_pins[] = {
1410 /* AVB2_MDC, AVB2_MDIO */
1411 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 13),
1413 static const unsigned int avb2_mdio_mux[] = {
1414 AVB2_MDC_MARK, AVB2_MDIO_MARK,
1416 static const unsigned int avb2_rgmii_pins[] = {
1418 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
1419 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
1421 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1422 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1423 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1424 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
1425 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1426 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1428 static const unsigned int avb2_rgmii_mux[] = {
1429 AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
1430 AVB2_TD0_MARK, AVB2_TD1_MARK, AVB2_TD2_MARK, AVB2_TD3_MARK,
1431 AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
1432 AVB2_RD0_MARK, AVB2_RD1_MARK, AVB2_RD2_MARK, AVB2_RD3_MARK,
1434 static const unsigned int avb2_txcrefclk_pins[] = {
1435 /* AVB2_TXCREFCLK */
1438 static const unsigned int avb2_txcrefclk_mux[] = {
1439 AVB2_TXCREFCLK_MARK,
1441 static const unsigned int avb2_avtp_pps_pins[] = {
1445 static const unsigned int avb2_avtp_pps_mux[] = {
1448 static const unsigned int avb2_avtp_capture_pins[] = {
1449 /* AVB2_AVTP_CAPTURE */
1452 static const unsigned int avb2_avtp_capture_mux[] = {
1453 AVB2_AVTP_CAPTURE_MARK,
1455 static const unsigned int avb2_avtp_match_pins[] = {
1456 /* AVB2_AVTP_MATCH */
1459 static const unsigned int avb2_avtp_match_mux[] = {
1460 AVB2_AVTP_MATCH_MARK,
1463 /* - AVB3 ------------------------------------------------ */
1464 static const unsigned int avb3_link_pins[] = {
1468 static const unsigned int avb3_link_mux[] = {
1471 static const unsigned int avb3_magic_pins[] = {
1475 static const unsigned int avb3_magic_mux[] = {
1478 static const unsigned int avb3_phy_int_pins[] = {
1482 static const unsigned int avb3_phy_int_mux[] = {
1485 static const unsigned int avb3_mdio_pins[] = {
1486 /* AVB3_MDC, AVB3_MDIO */
1487 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 13),
1489 static const unsigned int avb3_mdio_mux[] = {
1490 AVB3_MDC_MARK, AVB3_MDIO_MARK,
1492 static const unsigned int avb3_rgmii_pins[] = {
1494 * AVB3_TX_CTL, AVB3_TXC, AVB3_TD0, AVB3_TD1, AVB3_TD2, AVB3_TD3,
1495 * AVB3_RX_CTL, AVB3_RXC, AVB3_RD0, AVB3_RD1, AVB3_RD2, AVB3_RD3,
1497 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1498 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1499 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1500 RCAR_GP_PIN(7, 0), RCAR_GP_PIN(7, 1),
1501 RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1502 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1504 static const unsigned int avb3_rgmii_mux[] = {
1505 AVB3_TX_CTL_MARK, AVB3_TXC_MARK,
1506 AVB3_TD0_MARK, AVB3_TD1_MARK, AVB3_TD2_MARK, AVB3_TD3_MARK,
1507 AVB3_RX_CTL_MARK, AVB3_RXC_MARK,
1508 AVB3_RD0_MARK, AVB3_RD1_MARK, AVB3_RD2_MARK, AVB3_RD3_MARK,
1510 static const unsigned int avb3_txcrefclk_pins[] = {
1511 /* AVB3_TXCREFCLK */
1514 static const unsigned int avb3_txcrefclk_mux[] = {
1515 AVB3_TXCREFCLK_MARK,
1517 static const unsigned int avb3_avtp_pps_pins[] = {
1521 static const unsigned int avb3_avtp_pps_mux[] = {
1524 static const unsigned int avb3_avtp_capture_pins[] = {
1525 /* AVB3_AVTP_CAPTURE */
1528 static const unsigned int avb3_avtp_capture_mux[] = {
1529 AVB3_AVTP_CAPTURE_MARK,
1531 static const unsigned int avb3_avtp_match_pins[] = {
1532 /* AVB3_AVTP_MATCH */
1535 static const unsigned int avb3_avtp_match_mux[] = {
1536 AVB3_AVTP_MATCH_MARK,
1539 /* - AVB4 ------------------------------------------------ */
1540 static const unsigned int avb4_link_pins[] = {
1544 static const unsigned int avb4_link_mux[] = {
1547 static const unsigned int avb4_magic_pins[] = {
1551 static const unsigned int avb4_magic_mux[] = {
1554 static const unsigned int avb4_phy_int_pins[] = {
1558 static const unsigned int avb4_phy_int_mux[] = {
1561 static const unsigned int avb4_mdio_pins[] = {
1562 /* AVB4_MDC, AVB4_MDIO */
1563 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 13),
1565 static const unsigned int avb4_mdio_mux[] = {
1566 AVB4_MDC_MARK, AVB4_MDIO_MARK,
1568 static const unsigned int avb4_rgmii_pins[] = {
1570 * AVB4_TX_CTL, AVB4_TXC, AVB4_TD0, AVB4_TD1, AVB4_TD2, AVB4_TD3,
1571 * AVB4_RX_CTL, AVB4_RXC, AVB4_RD0, AVB4_RD1, AVB4_RD2, AVB4_RD3,
1573 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1574 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1575 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1576 RCAR_GP_PIN(8, 0), RCAR_GP_PIN(8, 1),
1577 RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1578 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1580 static const unsigned int avb4_rgmii_mux[] = {
1581 AVB4_TX_CTL_MARK, AVB4_TXC_MARK,
1582 AVB4_TD0_MARK, AVB4_TD1_MARK, AVB4_TD2_MARK, AVB4_TD3_MARK,
1583 AVB4_RX_CTL_MARK, AVB4_RXC_MARK,
1584 AVB4_RD0_MARK, AVB4_RD1_MARK, AVB4_RD2_MARK, AVB4_RD3_MARK,
1586 static const unsigned int avb4_txcrefclk_pins[] = {
1587 /* AVB4_TXCREFCLK */
1590 static const unsigned int avb4_txcrefclk_mux[] = {
1591 AVB4_TXCREFCLK_MARK,
1593 static const unsigned int avb4_avtp_pps_pins[] = {
1597 static const unsigned int avb4_avtp_pps_mux[] = {
1600 static const unsigned int avb4_avtp_capture_pins[] = {
1601 /* AVB4_AVTP_CAPTURE */
1604 static const unsigned int avb4_avtp_capture_mux[] = {
1605 AVB4_AVTP_CAPTURE_MARK,
1607 static const unsigned int avb4_avtp_match_pins[] = {
1608 /* AVB4_AVTP_MATCH */
1611 static const unsigned int avb4_avtp_match_mux[] = {
1612 AVB4_AVTP_MATCH_MARK,
1615 /* - AVB5 ------------------------------------------------ */
1616 static const unsigned int avb5_link_pins[] = {
1620 static const unsigned int avb5_link_mux[] = {
1623 static const unsigned int avb5_magic_pins[] = {
1627 static const unsigned int avb5_magic_mux[] = {
1630 static const unsigned int avb5_phy_int_pins[] = {
1634 static const unsigned int avb5_phy_int_mux[] = {
1637 static const unsigned int avb5_mdio_pins[] = {
1638 /* AVB5_MDC, AVB5_MDIO */
1639 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 13),
1641 static const unsigned int avb5_mdio_mux[] = {
1642 AVB5_MDC_MARK, AVB5_MDIO_MARK,
1644 static const unsigned int avb5_rgmii_pins[] = {
1646 * AVB5_TX_CTL, AVB5_TXC, AVB5_TD0, AVB5_TD1, AVB5_TD2, AVB5_TD3,
1647 * AVB5_RX_CTL, AVB5_RXC, AVB5_RD0, AVB5_RD1, AVB5_RD2, AVB5_RD3,
1649 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1650 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1651 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1652 RCAR_GP_PIN(9, 0), RCAR_GP_PIN(9, 1),
1653 RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1654 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1656 static const unsigned int avb5_rgmii_mux[] = {
1657 AVB5_TX_CTL_MARK, AVB5_TXC_MARK,
1658 AVB5_TD0_MARK, AVB5_TD1_MARK, AVB5_TD2_MARK, AVB5_TD3_MARK,
1659 AVB5_RX_CTL_MARK, AVB5_RXC_MARK,
1660 AVB5_RD0_MARK, AVB5_RD1_MARK, AVB5_RD2_MARK, AVB5_RD3_MARK,
1662 static const unsigned int avb5_txcrefclk_pins[] = {
1663 /* AVB5_TXCREFCLK */
1666 static const unsigned int avb5_txcrefclk_mux[] = {
1667 AVB5_TXCREFCLK_MARK,
1669 static const unsigned int avb5_avtp_pps_pins[] = {
1673 static const unsigned int avb5_avtp_pps_mux[] = {
1676 static const unsigned int avb5_avtp_capture_pins[] = {
1677 /* AVB5_AVTP_CAPTURE */
1680 static const unsigned int avb5_avtp_capture_mux[] = {
1681 AVB5_AVTP_CAPTURE_MARK,
1683 static const unsigned int avb5_avtp_match_pins[] = {
1684 /* AVB5_AVTP_MATCH */
1687 static const unsigned int avb5_avtp_match_mux[] = {
1688 AVB5_AVTP_MATCH_MARK,
1691 /* - CANFD0 ----------------------------------------------------------------- */
1692 static const unsigned int canfd0_data_pins[] = {
1693 /* CANFD0_TX, CANFD0_RX */
1694 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
1696 static const unsigned int canfd0_data_mux[] = {
1697 CANFD0_TX_MARK, CANFD0_RX_MARK,
1700 /* - CANFD1 ----------------------------------------------------------------- */
1701 static const unsigned int canfd1_data_pins[] = {
1702 /* CANFD1_TX, CANFD1_RX */
1703 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1705 static const unsigned int canfd1_data_mux[] = {
1706 CANFD1_TX_MARK, CANFD1_RX_MARK,
1709 /* - CANFD2 ----------------------------------------------------------------- */
1710 static const unsigned int canfd2_data_pins[] = {
1711 /* CANFD2_TX, CANFD2_RX */
1712 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
1714 static const unsigned int canfd2_data_mux[] = {
1715 CANFD2_TX_MARK, CANFD2_RX_MARK,
1718 /* - CANFD3 ----------------------------------------------------------------- */
1719 static const unsigned int canfd3_data_pins[] = {
1720 /* CANFD3_TX, CANFD3_RX */
1721 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
1723 static const unsigned int canfd3_data_mux[] = {
1724 CANFD3_TX_MARK, CANFD3_RX_MARK,
1727 /* - CANFD4 ----------------------------------------------------------------- */
1728 static const unsigned int canfd4_data_pins[] = {
1729 /* CANFD4_TX, CANFD4_RX */
1730 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1732 static const unsigned int canfd4_data_mux[] = {
1733 CANFD4_TX_MARK, CANFD4_RX_MARK,
1736 /* - CANFD5 ----------------------------------------------------------------- */
1737 static const unsigned int canfd5_data_pins[] = {
1738 /* CANFD5_TX, CANFD5_RX */
1739 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1741 static const unsigned int canfd5_data_mux[] = {
1742 CANFD5_TX_MARK, CANFD5_RX_MARK,
1745 /* - CANFD6 ----------------------------------------------------------------- */
1746 static const unsigned int canfd6_data_pins[] = {
1747 /* CANFD6_TX, CANFD6_RX */
1748 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1750 static const unsigned int canfd6_data_mux[] = {
1751 CANFD6_TX_MARK, CANFD6_RX_MARK,
1754 /* - CANFD7 ----------------------------------------------------------------- */
1755 static const unsigned int canfd7_data_pins[] = {
1756 /* CANFD7_TX, CANFD7_RX */
1757 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1759 static const unsigned int canfd7_data_mux[] = {
1760 CANFD7_TX_MARK, CANFD7_RX_MARK,
1763 /* - CANFD Clock ------------------------------------------------------------ */
1764 static const unsigned int can_clk_pins[] = {
1768 static const unsigned int can_clk_mux[] = {
1772 /* - DU --------------------------------------------------------------------- */
1773 static const unsigned int du_rgb888_pins[] = {
1774 /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
1775 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
1776 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1777 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
1778 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
1779 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1780 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1782 static const unsigned int du_rgb888_mux[] = {
1783 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
1784 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
1785 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
1786 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
1787 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
1788 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
1790 static const unsigned int du_clk_out_pins[] = {
1794 static const unsigned int du_clk_out_mux[] = {
1797 static const unsigned int du_sync_pins[] = {
1798 /* DU_HSYNC, DU_VSYNC */
1799 RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 26),
1801 static const unsigned int du_sync_mux[] = {
1802 DU_HSYNC_MARK, DU_VSYNC_MARK,
1804 static const unsigned int du_oddf_pins[] = {
1805 /* DU_EXODDF/DU_ODDF/DISP/CDE */
1808 static const unsigned int du_oddf_mux[] = {
1809 DU_ODDF_DISP_CDE_MARK,
1812 /* - HSCIF0 ----------------------------------------------------------------- */
1813 static const unsigned int hscif0_data_pins[] = {
1815 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),
1817 static const unsigned int hscif0_data_mux[] = {
1818 HRX0_MARK, HTX0_MARK,
1820 static const unsigned int hscif0_clk_pins[] = {
1824 static const unsigned int hscif0_clk_mux[] = {
1827 static const unsigned int hscif0_ctrl_pins[] = {
1828 /* HRTS0#, HCTS0# */
1829 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
1831 static const unsigned int hscif0_ctrl_mux[] = {
1832 HRTS0_N_MARK, HCTS0_N_MARK,
1835 /* - HSCIF1 ----------------------------------------------------------------- */
1836 static const unsigned int hscif1_data_pins[] = {
1838 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
1840 static const unsigned int hscif1_data_mux[] = {
1841 HRX1_MARK, HTX1_MARK,
1843 static const unsigned int hscif1_clk_pins[] = {
1847 static const unsigned int hscif1_clk_mux[] = {
1850 static const unsigned int hscif1_ctrl_pins[] = {
1851 /* HRTS1#, HCTS1# */
1852 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),
1854 static const unsigned int hscif1_ctrl_mux[] = {
1855 HRTS1_N_MARK, HCTS1_N_MARK,
1858 /* - HSCIF2 ----------------------------------------------------------------- */
1859 static const unsigned int hscif2_data_pins[] = {
1861 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1863 static const unsigned int hscif2_data_mux[] = {
1864 HRX2_MARK, HTX2_MARK,
1866 static const unsigned int hscif2_clk_pins[] = {
1870 static const unsigned int hscif2_clk_mux[] = {
1873 static const unsigned int hscif2_ctrl_pins[] = {
1874 /* HRTS2#, HCTS2# */
1875 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
1877 static const unsigned int hscif2_ctrl_mux[] = {
1878 HRTS2_N_MARK, HCTS2_N_MARK,
1881 /* - HSCIF3 ----------------------------------------------------------------- */
1882 static const unsigned int hscif3_data_pins[] = {
1884 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 17),
1886 static const unsigned int hscif3_data_mux[] = {
1887 HRX3_MARK, HTX3_MARK,
1889 static const unsigned int hscif3_clk_pins[] = {
1893 static const unsigned int hscif3_clk_mux[] = {
1896 static const unsigned int hscif3_ctrl_pins[] = {
1897 /* HRTS3#, HCTS3# */
1898 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
1900 static const unsigned int hscif3_ctrl_mux[] = {
1901 HRTS3_N_MARK, HCTS3_N_MARK,
1904 /* - I2C0 ------------------------------------------------------------------- */
1905 static const unsigned int i2c0_pins[] = {
1907 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1909 static const unsigned int i2c0_mux[] = {
1910 SDA0_MARK, SCL0_MARK,
1913 /* - I2C1 ------------------------------------------------------------------- */
1914 static const unsigned int i2c1_pins[] = {
1916 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1918 static const unsigned int i2c1_mux[] = {
1919 SDA1_MARK, SCL1_MARK,
1922 /* - I2C2 ------------------------------------------------------------------- */
1923 static const unsigned int i2c2_pins[] = {
1925 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
1927 static const unsigned int i2c2_mux[] = {
1928 SDA2_MARK, SCL2_MARK,
1931 /* - I2C3 ------------------------------------------------------------------- */
1932 static const unsigned int i2c3_pins[] = {
1934 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
1936 static const unsigned int i2c3_mux[] = {
1937 SDA3_MARK, SCL3_MARK,
1940 /* - I2C4 ------------------------------------------------------------------- */
1941 static const unsigned int i2c4_pins[] = {
1943 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1945 static const unsigned int i2c4_mux[] = {
1946 SDA4_MARK, SCL4_MARK,
1949 /* - I2C5 ------------------------------------------------------------------- */
1950 static const unsigned int i2c5_pins[] = {
1952 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
1954 static const unsigned int i2c5_mux[] = {
1955 SDA5_MARK, SCL5_MARK,
1958 /* - I2C6 ------------------------------------------------------------------- */
1959 static const unsigned int i2c6_pins[] = {
1961 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14),
1963 static const unsigned int i2c6_mux[] = {
1964 SDA6_MARK, SCL6_MARK,
1967 /* - INTC-EX ---------------------------------------------------------------- */
1968 static const unsigned int intc_ex_irq0_pins[] = {
1972 static const unsigned int intc_ex_irq0_mux[] = {
1975 static const unsigned int intc_ex_irq1_pins[] = {
1979 static const unsigned int intc_ex_irq1_mux[] = {
1982 static const unsigned int intc_ex_irq2_pins[] = {
1986 static const unsigned int intc_ex_irq2_mux[] = {
1989 static const unsigned int intc_ex_irq3_pins[] = {
1993 static const unsigned int intc_ex_irq3_mux[] = {
1996 static const unsigned int intc_ex_irq4_pins[] = {
2000 static const unsigned int intc_ex_irq4_mux[] = {
2003 static const unsigned int intc_ex_irq5_pins[] = {
2007 static const unsigned int intc_ex_irq5_mux[] = {
2011 /* - MMC -------------------------------------------------------------------- */
2012 static const unsigned int mmc_data1_pins[] = {
2016 static const unsigned int mmc_data1_mux[] = {
2019 static const unsigned int mmc_data4_pins[] = {
2021 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
2022 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
2024 static const unsigned int mmc_data4_mux[] = {
2025 MMC_SD_D0_MARK, MMC_SD_D1_MARK,
2026 MMC_SD_D2_MARK, MMC_SD_D3_MARK,
2028 static const unsigned int mmc_data8_pins[] = {
2029 /* MMC_SD_D[0:3], MMC_D[4:7] */
2030 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
2031 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
2032 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2033 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27),
2035 static const unsigned int mmc_data8_mux[] = {
2036 MMC_SD_D0_MARK, MMC_SD_D1_MARK,
2037 MMC_SD_D2_MARK, MMC_SD_D3_MARK,
2038 MMC_D4_MARK, MMC_D5_MARK,
2039 MMC_D6_MARK, MMC_D7_MARK,
2041 static const unsigned int mmc_ctrl_pins[] = {
2042 /* MMC_SD_CLK, MMC_SD_CMD */
2043 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 18),
2045 static const unsigned int mmc_ctrl_mux[] = {
2046 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
2048 static const unsigned int mmc_cd_pins[] = {
2052 static const unsigned int mmc_cd_mux[] = {
2055 static const unsigned int mmc_wp_pins[] = {
2059 static const unsigned int mmc_wp_mux[] = {
2062 static const unsigned int mmc_ds_pins[] = {
2066 static const unsigned int mmc_ds_mux[] = {
2070 /* - MSIOF0 ----------------------------------------------------------------- */
2071 static const unsigned int msiof0_clk_pins[] = {
2075 static const unsigned int msiof0_clk_mux[] = {
2078 static const unsigned int msiof0_sync_pins[] = {
2082 static const unsigned int msiof0_sync_mux[] = {
2085 static const unsigned int msiof0_ss1_pins[] = {
2089 static const unsigned int msiof0_ss1_mux[] = {
2092 static const unsigned int msiof0_ss2_pins[] = {
2096 static const unsigned int msiof0_ss2_mux[] = {
2099 static const unsigned int msiof0_txd_pins[] = {
2103 static const unsigned int msiof0_txd_mux[] = {
2106 static const unsigned int msiof0_rxd_pins[] = {
2110 static const unsigned int msiof0_rxd_mux[] = {
2114 /* - MSIOF1 ----------------------------------------------------------------- */
2115 static const unsigned int msiof1_clk_pins[] = {
2119 static const unsigned int msiof1_clk_mux[] = {
2122 static const unsigned int msiof1_sync_pins[] = {
2126 static const unsigned int msiof1_sync_mux[] = {
2129 static const unsigned int msiof1_ss1_pins[] = {
2133 static const unsigned int msiof1_ss1_mux[] = {
2136 static const unsigned int msiof1_ss2_pins[] = {
2140 static const unsigned int msiof1_ss2_mux[] = {
2143 static const unsigned int msiof1_txd_pins[] = {
2147 static const unsigned int msiof1_txd_mux[] = {
2150 static const unsigned int msiof1_rxd_pins[] = {
2154 static const unsigned int msiof1_rxd_mux[] = {
2158 /* - MSIOF2 ----------------------------------------------------------------- */
2159 static const unsigned int msiof2_clk_pins[] = {
2163 static const unsigned int msiof2_clk_mux[] = {
2166 static const unsigned int msiof2_sync_pins[] = {
2170 static const unsigned int msiof2_sync_mux[] = {
2173 static const unsigned int msiof2_ss1_pins[] = {
2177 static const unsigned int msiof2_ss1_mux[] = {
2180 static const unsigned int msiof2_ss2_pins[] = {
2184 static const unsigned int msiof2_ss2_mux[] = {
2187 static const unsigned int msiof2_txd_pins[] = {
2191 static const unsigned int msiof2_txd_mux[] = {
2194 static const unsigned int msiof2_rxd_pins[] = {
2198 static const unsigned int msiof2_rxd_mux[] = {
2202 /* - MSIOF3 ----------------------------------------------------------------- */
2203 static const unsigned int msiof3_clk_pins[] = {
2207 static const unsigned int msiof3_clk_mux[] = {
2210 static const unsigned int msiof3_sync_pins[] = {
2214 static const unsigned int msiof3_sync_mux[] = {
2217 static const unsigned int msiof3_ss1_pins[] = {
2221 static const unsigned int msiof3_ss1_mux[] = {
2224 static const unsigned int msiof3_ss2_pins[] = {
2228 static const unsigned int msiof3_ss2_mux[] = {
2231 static const unsigned int msiof3_txd_pins[] = {
2235 static const unsigned int msiof3_txd_mux[] = {
2238 static const unsigned int msiof3_rxd_pins[] = {
2242 static const unsigned int msiof3_rxd_mux[] = {
2246 /* - MSIOF4 ----------------------------------------------------------------- */
2247 static const unsigned int msiof4_clk_pins[] = {
2251 static const unsigned int msiof4_clk_mux[] = {
2254 static const unsigned int msiof4_sync_pins[] = {
2258 static const unsigned int msiof4_sync_mux[] = {
2261 static const unsigned int msiof4_ss1_pins[] = {
2265 static const unsigned int msiof4_ss1_mux[] = {
2268 static const unsigned int msiof4_ss2_pins[] = {
2272 static const unsigned int msiof4_ss2_mux[] = {
2275 static const unsigned int msiof4_txd_pins[] = {
2279 static const unsigned int msiof4_txd_mux[] = {
2282 static const unsigned int msiof4_rxd_pins[] = {
2286 static const unsigned int msiof4_rxd_mux[] = {
2290 /* - MSIOF5 ----------------------------------------------------------------- */
2291 static const unsigned int msiof5_clk_pins[] = {
2295 static const unsigned int msiof5_clk_mux[] = {
2298 static const unsigned int msiof5_sync_pins[] = {
2302 static const unsigned int msiof5_sync_mux[] = {
2305 static const unsigned int msiof5_ss1_pins[] = {
2309 static const unsigned int msiof5_ss1_mux[] = {
2312 static const unsigned int msiof5_ss2_pins[] = {
2316 static const unsigned int msiof5_ss2_mux[] = {
2319 static const unsigned int msiof5_txd_pins[] = {
2323 static const unsigned int msiof5_txd_mux[] = {
2326 static const unsigned int msiof5_rxd_pins[] = {
2330 static const unsigned int msiof5_rxd_mux[] = {
2334 /* - PWM0 ------------------------------------------------------------------- */
2335 static const unsigned int pwm0_pins[] = {
2339 static const unsigned int pwm0_mux[] = {
2343 /* - PWM1 ------------------------------------------------------------------- */
2344 static const unsigned int pwm1_pins[] = {
2348 static const unsigned int pwm1_mux[] = {
2352 /* - PWM2 ------------------------------------------------------------------- */
2353 static const unsigned int pwm2_pins[] = {
2357 static const unsigned int pwm2_mux[] = {
2361 /* - PWM3 ------------------------------------------------------------------- */
2362 static const unsigned int pwm3_pins[] = {
2366 static const unsigned int pwm3_mux[] = {
2370 /* - PWM4 ------------------------------------------------------------------- */
2371 static const unsigned int pwm4_pins[] = {
2375 static const unsigned int pwm4_mux[] = {
2379 /* - QSPI0 ------------------------------------------------------------------ */
2380 static const unsigned int qspi0_ctrl_pins[] = {
2382 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 5),
2384 static const unsigned int qspi0_ctrl_mux[] = {
2385 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2387 static const unsigned int qspi0_data2_pins[] = {
2388 /* MOSI_IO0, MISO_IO1 */
2389 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
2391 static const unsigned int qspi0_data2_mux[] = {
2392 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2394 static const unsigned int qspi0_data4_pins[] = {
2395 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2396 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
2397 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2399 static const unsigned int qspi0_data4_mux[] = {
2400 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2401 QSPI0_IO2_MARK, QSPI0_IO3_MARK
2404 /* - QSPI1 ------------------------------------------------------------------ */
2405 static const unsigned int qspi1_ctrl_pins[] = {
2407 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 11),
2409 static const unsigned int qspi1_ctrl_mux[] = {
2410 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2412 static const unsigned int qspi1_data2_pins[] = {
2413 /* MOSI_IO0, MISO_IO1 */
2414 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
2416 static const unsigned int qspi1_data2_mux[] = {
2417 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2419 static const unsigned int qspi1_data4_pins[] = {
2420 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2421 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
2422 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2424 static const unsigned int qspi1_data4_mux[] = {
2425 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2426 QSPI1_IO2_MARK, QSPI1_IO3_MARK
2429 /* - SCIF0 ------------------------------------------------------------------ */
2430 static const unsigned int scif0_data_pins[] = {
2432 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),
2434 static const unsigned int scif0_data_mux[] = {
2437 static const unsigned int scif0_clk_pins[] = {
2441 static const unsigned int scif0_clk_mux[] = {
2444 static const unsigned int scif0_ctrl_pins[] = {
2446 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
2448 static const unsigned int scif0_ctrl_mux[] = {
2449 RTS0_N_MARK, CTS0_N_MARK,
2452 /* - SCIF1 ------------------------------------------------------------------ */
2453 static const unsigned int scif1_data_a_pins[] = {
2455 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
2457 static const unsigned int scif1_data_a_mux[] = {
2458 RX1_A_MARK, TX1_A_MARK,
2460 static const unsigned int scif1_data_b_pins[] = {
2462 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 1),
2464 static const unsigned int scif1_data_b_mux[] = {
2465 RX1_B_MARK, TX1_B_MARK,
2467 static const unsigned int scif1_clk_pins[] = {
2471 static const unsigned int scif1_clk_mux[] = {
2474 static const unsigned int scif1_ctrl_pins[] = {
2476 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),
2478 static const unsigned int scif1_ctrl_mux[] = {
2479 RTS1_N_MARK, CTS1_N_MARK,
2482 /* - SCIF3 ------------------------------------------------------------------ */
2483 static const unsigned int scif3_data_pins[] = {
2485 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2487 static const unsigned int scif3_data_mux[] = {
2490 static const unsigned int scif3_clk_pins[] = {
2494 static const unsigned int scif3_clk_mux[] = {
2497 static const unsigned int scif3_ctrl_pins[] = {
2499 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2501 static const unsigned int scif3_ctrl_mux[] = {
2502 RTS3_N_MARK, CTS3_N_MARK,
2505 /* - SCIF4 ------------------------------------------------------------------ */
2506 static const unsigned int scif4_data_pins[] = {
2508 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2510 static const unsigned int scif4_data_mux[] = {
2513 static const unsigned int scif4_clk_pins[] = {
2517 static const unsigned int scif4_clk_mux[] = {
2520 static const unsigned int scif4_ctrl_pins[] = {
2522 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
2524 static const unsigned int scif4_ctrl_mux[] = {
2525 RTS4_N_MARK, CTS4_N_MARK,
2528 /* - SCIF Clock ------------------------------------------------------------- */
2529 static const unsigned int scif_clk_pins[] = {
2533 static const unsigned int scif_clk_mux[] = {
2537 /* - TMU -------------------------------------------------------------------- */
2538 static const unsigned int tmu_tclk1_a_pins[] = {
2542 static const unsigned int tmu_tclk1_a_mux[] = {
2545 static const unsigned int tmu_tclk1_b_pins[] = {
2549 static const unsigned int tmu_tclk1_b_mux[] = {
2553 static const unsigned int tmu_tclk2_a_pins[] = {
2557 static const unsigned int tmu_tclk2_a_mux[] = {
2560 static const unsigned int tmu_tclk2_b_pins[] = {
2564 static const unsigned int tmu_tclk2_b_mux[] = {
2568 static const unsigned int tmu_tclk3_pins[] = {
2572 static const unsigned int tmu_tclk3_mux[] = {
2576 static const unsigned int tmu_tclk4_pins[] = {
2580 static const unsigned int tmu_tclk4_mux[] = {
2584 /* - TPU ------------------------------------------------------------------- */
2585 static const unsigned int tpu_to0_pins[] = {
2589 static const unsigned int tpu_to0_mux[] = {
2592 static const unsigned int tpu_to1_pins[] = {
2596 static const unsigned int tpu_to1_mux[] = {
2599 static const unsigned int tpu_to2_pins[] = {
2603 static const unsigned int tpu_to2_mux[] = {
2606 static const unsigned int tpu_to3_pins[] = {
2610 static const unsigned int tpu_to3_mux[] = {
2614 static const struct sh_pfc_pin_group pinmux_groups[] = {
2615 SH_PFC_PIN_GROUP(avb0_link),
2616 SH_PFC_PIN_GROUP(avb0_magic),
2617 SH_PFC_PIN_GROUP(avb0_phy_int),
2618 SH_PFC_PIN_GROUP(avb0_mdio),
2619 SH_PFC_PIN_GROUP(avb0_rgmii),
2620 SH_PFC_PIN_GROUP(avb0_txcrefclk),
2621 SH_PFC_PIN_GROUP(avb0_avtp_pps),
2622 SH_PFC_PIN_GROUP(avb0_avtp_capture),
2623 SH_PFC_PIN_GROUP(avb0_avtp_match),
2625 SH_PFC_PIN_GROUP(avb1_link),
2626 SH_PFC_PIN_GROUP(avb1_magic),
2627 SH_PFC_PIN_GROUP(avb1_phy_int),
2628 SH_PFC_PIN_GROUP(avb1_mdio),
2629 SH_PFC_PIN_GROUP(avb1_rgmii),
2630 SH_PFC_PIN_GROUP(avb1_txcrefclk),
2631 SH_PFC_PIN_GROUP(avb1_avtp_pps),
2632 SH_PFC_PIN_GROUP(avb1_avtp_capture),
2633 SH_PFC_PIN_GROUP(avb1_avtp_match),
2635 SH_PFC_PIN_GROUP(avb2_link),
2636 SH_PFC_PIN_GROUP(avb2_magic),
2637 SH_PFC_PIN_GROUP(avb2_phy_int),
2638 SH_PFC_PIN_GROUP(avb2_mdio),
2639 SH_PFC_PIN_GROUP(avb2_rgmii),
2640 SH_PFC_PIN_GROUP(avb2_txcrefclk),
2641 SH_PFC_PIN_GROUP(avb2_avtp_pps),
2642 SH_PFC_PIN_GROUP(avb2_avtp_capture),
2643 SH_PFC_PIN_GROUP(avb2_avtp_match),
2645 SH_PFC_PIN_GROUP(avb3_link),
2646 SH_PFC_PIN_GROUP(avb3_magic),
2647 SH_PFC_PIN_GROUP(avb3_phy_int),
2648 SH_PFC_PIN_GROUP(avb3_mdio),
2649 SH_PFC_PIN_GROUP(avb3_rgmii),
2650 SH_PFC_PIN_GROUP(avb3_txcrefclk),
2651 SH_PFC_PIN_GROUP(avb3_avtp_pps),
2652 SH_PFC_PIN_GROUP(avb3_avtp_capture),
2653 SH_PFC_PIN_GROUP(avb3_avtp_match),
2655 SH_PFC_PIN_GROUP(avb4_link),
2656 SH_PFC_PIN_GROUP(avb4_magic),
2657 SH_PFC_PIN_GROUP(avb4_phy_int),
2658 SH_PFC_PIN_GROUP(avb4_mdio),
2659 SH_PFC_PIN_GROUP(avb4_rgmii),
2660 SH_PFC_PIN_GROUP(avb4_txcrefclk),
2661 SH_PFC_PIN_GROUP(avb4_avtp_pps),
2662 SH_PFC_PIN_GROUP(avb4_avtp_capture),
2663 SH_PFC_PIN_GROUP(avb4_avtp_match),
2665 SH_PFC_PIN_GROUP(avb5_link),
2666 SH_PFC_PIN_GROUP(avb5_magic),
2667 SH_PFC_PIN_GROUP(avb5_phy_int),
2668 SH_PFC_PIN_GROUP(avb5_mdio),
2669 SH_PFC_PIN_GROUP(avb5_rgmii),
2670 SH_PFC_PIN_GROUP(avb5_txcrefclk),
2671 SH_PFC_PIN_GROUP(avb5_avtp_pps),
2672 SH_PFC_PIN_GROUP(avb5_avtp_capture),
2673 SH_PFC_PIN_GROUP(avb5_avtp_match),
2675 SH_PFC_PIN_GROUP(canfd0_data),
2676 SH_PFC_PIN_GROUP(canfd1_data),
2677 SH_PFC_PIN_GROUP(canfd2_data),
2678 SH_PFC_PIN_GROUP(canfd3_data),
2679 SH_PFC_PIN_GROUP(canfd4_data),
2680 SH_PFC_PIN_GROUP(canfd5_data),
2681 SH_PFC_PIN_GROUP(canfd6_data),
2682 SH_PFC_PIN_GROUP(canfd7_data),
2683 SH_PFC_PIN_GROUP(can_clk),
2685 SH_PFC_PIN_GROUP(du_rgb888),
2686 SH_PFC_PIN_GROUP(du_clk_out),
2687 SH_PFC_PIN_GROUP(du_sync),
2688 SH_PFC_PIN_GROUP(du_oddf),
2690 SH_PFC_PIN_GROUP(hscif0_data),
2691 SH_PFC_PIN_GROUP(hscif0_clk),
2692 SH_PFC_PIN_GROUP(hscif0_ctrl),
2693 SH_PFC_PIN_GROUP(hscif1_data),
2694 SH_PFC_PIN_GROUP(hscif1_clk),
2695 SH_PFC_PIN_GROUP(hscif1_ctrl),
2696 SH_PFC_PIN_GROUP(hscif2_data),
2697 SH_PFC_PIN_GROUP(hscif2_clk),
2698 SH_PFC_PIN_GROUP(hscif2_ctrl),
2699 SH_PFC_PIN_GROUP(hscif3_data),
2700 SH_PFC_PIN_GROUP(hscif3_clk),
2701 SH_PFC_PIN_GROUP(hscif3_ctrl),
2703 SH_PFC_PIN_GROUP(i2c0),
2704 SH_PFC_PIN_GROUP(i2c1),
2705 SH_PFC_PIN_GROUP(i2c2),
2706 SH_PFC_PIN_GROUP(i2c3),
2707 SH_PFC_PIN_GROUP(i2c4),
2708 SH_PFC_PIN_GROUP(i2c5),
2709 SH_PFC_PIN_GROUP(i2c6),
2711 SH_PFC_PIN_GROUP(intc_ex_irq0),
2712 SH_PFC_PIN_GROUP(intc_ex_irq1),
2713 SH_PFC_PIN_GROUP(intc_ex_irq2),
2714 SH_PFC_PIN_GROUP(intc_ex_irq3),
2715 SH_PFC_PIN_GROUP(intc_ex_irq4),
2716 SH_PFC_PIN_GROUP(intc_ex_irq5),
2718 SH_PFC_PIN_GROUP(mmc_data1),
2719 SH_PFC_PIN_GROUP(mmc_data4),
2720 SH_PFC_PIN_GROUP(mmc_data8),
2721 SH_PFC_PIN_GROUP(mmc_ctrl),
2722 SH_PFC_PIN_GROUP(mmc_cd),
2723 SH_PFC_PIN_GROUP(mmc_wp),
2724 SH_PFC_PIN_GROUP(mmc_ds),
2726 SH_PFC_PIN_GROUP(msiof0_clk),
2727 SH_PFC_PIN_GROUP(msiof0_sync),
2728 SH_PFC_PIN_GROUP(msiof0_ss1),
2729 SH_PFC_PIN_GROUP(msiof0_ss2),
2730 SH_PFC_PIN_GROUP(msiof0_txd),
2731 SH_PFC_PIN_GROUP(msiof0_rxd),
2732 SH_PFC_PIN_GROUP(msiof1_clk),
2733 SH_PFC_PIN_GROUP(msiof1_sync),
2734 SH_PFC_PIN_GROUP(msiof1_ss1),
2735 SH_PFC_PIN_GROUP(msiof1_ss2),
2736 SH_PFC_PIN_GROUP(msiof1_txd),
2737 SH_PFC_PIN_GROUP(msiof1_rxd),
2738 SH_PFC_PIN_GROUP(msiof2_clk),
2739 SH_PFC_PIN_GROUP(msiof2_sync),
2740 SH_PFC_PIN_GROUP(msiof2_ss1),
2741 SH_PFC_PIN_GROUP(msiof2_ss2),
2742 SH_PFC_PIN_GROUP(msiof2_txd),
2743 SH_PFC_PIN_GROUP(msiof2_rxd),
2744 SH_PFC_PIN_GROUP(msiof3_clk),
2745 SH_PFC_PIN_GROUP(msiof3_sync),
2746 SH_PFC_PIN_GROUP(msiof3_ss1),
2747 SH_PFC_PIN_GROUP(msiof3_ss2),
2748 SH_PFC_PIN_GROUP(msiof3_txd),
2749 SH_PFC_PIN_GROUP(msiof3_rxd),
2750 SH_PFC_PIN_GROUP(msiof4_clk),
2751 SH_PFC_PIN_GROUP(msiof4_sync),
2752 SH_PFC_PIN_GROUP(msiof4_ss1),
2753 SH_PFC_PIN_GROUP(msiof4_ss2),
2754 SH_PFC_PIN_GROUP(msiof4_txd),
2755 SH_PFC_PIN_GROUP(msiof4_rxd),
2756 SH_PFC_PIN_GROUP(msiof5_clk),
2757 SH_PFC_PIN_GROUP(msiof5_sync),
2758 SH_PFC_PIN_GROUP(msiof5_ss1),
2759 SH_PFC_PIN_GROUP(msiof5_ss2),
2760 SH_PFC_PIN_GROUP(msiof5_txd),
2761 SH_PFC_PIN_GROUP(msiof5_rxd),
2763 SH_PFC_PIN_GROUP(pwm0),
2764 SH_PFC_PIN_GROUP(pwm1),
2765 SH_PFC_PIN_GROUP(pwm2),
2766 SH_PFC_PIN_GROUP(pwm3),
2767 SH_PFC_PIN_GROUP(pwm4),
2769 SH_PFC_PIN_GROUP(qspi0_ctrl),
2770 SH_PFC_PIN_GROUP(qspi0_data2),
2771 SH_PFC_PIN_GROUP(qspi0_data4),
2772 SH_PFC_PIN_GROUP(qspi1_ctrl),
2773 SH_PFC_PIN_GROUP(qspi1_data2),
2774 SH_PFC_PIN_GROUP(qspi1_data4),
2776 SH_PFC_PIN_GROUP(scif0_data),
2777 SH_PFC_PIN_GROUP(scif0_clk),
2778 SH_PFC_PIN_GROUP(scif0_ctrl),
2779 SH_PFC_PIN_GROUP(scif1_data_a),
2780 SH_PFC_PIN_GROUP(scif1_data_b),
2781 SH_PFC_PIN_GROUP(scif1_clk),
2782 SH_PFC_PIN_GROUP(scif1_ctrl),
2783 SH_PFC_PIN_GROUP(scif3_data),
2784 SH_PFC_PIN_GROUP(scif3_clk),
2785 SH_PFC_PIN_GROUP(scif3_ctrl),
2786 SH_PFC_PIN_GROUP(scif4_data),
2787 SH_PFC_PIN_GROUP(scif4_clk),
2788 SH_PFC_PIN_GROUP(scif4_ctrl),
2789 SH_PFC_PIN_GROUP(scif_clk),
2791 SH_PFC_PIN_GROUP(tmu_tclk1_a),
2792 SH_PFC_PIN_GROUP(tmu_tclk1_b),
2793 SH_PFC_PIN_GROUP(tmu_tclk2_a),
2794 SH_PFC_PIN_GROUP(tmu_tclk2_b),
2795 SH_PFC_PIN_GROUP(tmu_tclk3),
2796 SH_PFC_PIN_GROUP(tmu_tclk4),
2798 SH_PFC_PIN_GROUP(tpu_to0),
2799 SH_PFC_PIN_GROUP(tpu_to1),
2800 SH_PFC_PIN_GROUP(tpu_to2),
2801 SH_PFC_PIN_GROUP(tpu_to3),
2804 static const char * const avb0_groups[] = {
2812 "avb0_avtp_capture",
2816 static const char * const avb1_groups[] = {
2824 "avb1_avtp_capture",
2828 static const char * const avb2_groups[] = {
2836 "avb2_avtp_capture",
2840 static const char * const avb3_groups[] = {
2848 "avb3_avtp_capture",
2852 static const char * const avb4_groups[] = {
2860 "avb4_avtp_capture",
2864 static const char * const avb5_groups[] = {
2872 "avb5_avtp_capture",
2876 static const char * const canfd0_groups[] = {
2880 static const char * const canfd1_groups[] = {
2884 static const char * const canfd2_groups[] = {
2888 static const char * const canfd3_groups[] = {
2892 static const char * const canfd4_groups[] = {
2896 static const char * const canfd5_groups[] = {
2900 static const char * const canfd6_groups[] = {
2904 static const char * const canfd7_groups[] = {
2908 static const char * const can_clk_groups[] = {
2912 static const char * const du_groups[] = {
2919 static const char * const hscif0_groups[] = {
2925 static const char * const hscif1_groups[] = {
2931 static const char * const hscif2_groups[] = {
2937 static const char * const hscif3_groups[] = {
2943 static const char * const i2c0_groups[] = {
2947 static const char * const i2c1_groups[] = {
2951 static const char * const i2c2_groups[] = {
2955 static const char * const i2c3_groups[] = {
2959 static const char * const i2c4_groups[] = {
2963 static const char * const i2c5_groups[] = {
2967 static const char * const i2c6_groups[] = {
2971 static const char * const intc_ex_groups[] = {
2980 static const char * const mmc_groups[] = {
2990 static const char * const msiof0_groups[] = {
2999 static const char * const msiof1_groups[] = {
3008 static const char * const msiof2_groups[] = {
3017 static const char * const msiof3_groups[] = {
3026 static const char * const msiof4_groups[] = {
3035 static const char * const msiof5_groups[] = {
3044 static const char * const pwm0_groups[] = {
3048 static const char * const pwm1_groups[] = {
3052 static const char * const pwm2_groups[] = {
3056 static const char * const pwm3_groups[] = {
3060 static const char * const pwm4_groups[] = {
3064 static const char * const qspi0_groups[] = {
3070 static const char * const qspi1_groups[] = {
3076 static const char * const scif0_groups[] = {
3082 static const char * const scif1_groups[] = {
3089 static const char * const scif3_groups[] = {
3095 static const char * const scif4_groups[] = {
3101 static const char * const scif_clk_groups[] = {
3105 static const char * const tmu_groups[] = {
3114 static const char * const tpu_groups[] = {
3121 static const struct sh_pfc_function pinmux_functions[] = {
3122 SH_PFC_FUNCTION(avb0),
3123 SH_PFC_FUNCTION(avb1),
3124 SH_PFC_FUNCTION(avb2),
3125 SH_PFC_FUNCTION(avb3),
3126 SH_PFC_FUNCTION(avb4),
3127 SH_PFC_FUNCTION(avb5),
3129 SH_PFC_FUNCTION(canfd0),
3130 SH_PFC_FUNCTION(canfd1),
3131 SH_PFC_FUNCTION(canfd2),
3132 SH_PFC_FUNCTION(canfd3),
3133 SH_PFC_FUNCTION(canfd4),
3134 SH_PFC_FUNCTION(canfd5),
3135 SH_PFC_FUNCTION(canfd6),
3136 SH_PFC_FUNCTION(canfd7),
3137 SH_PFC_FUNCTION(can_clk),
3139 SH_PFC_FUNCTION(du),
3141 SH_PFC_FUNCTION(hscif0),
3142 SH_PFC_FUNCTION(hscif1),
3143 SH_PFC_FUNCTION(hscif2),
3144 SH_PFC_FUNCTION(hscif3),
3146 SH_PFC_FUNCTION(i2c0),
3147 SH_PFC_FUNCTION(i2c1),
3148 SH_PFC_FUNCTION(i2c2),
3149 SH_PFC_FUNCTION(i2c3),
3150 SH_PFC_FUNCTION(i2c4),
3151 SH_PFC_FUNCTION(i2c5),
3152 SH_PFC_FUNCTION(i2c6),
3154 SH_PFC_FUNCTION(intc_ex),
3156 SH_PFC_FUNCTION(mmc),
3158 SH_PFC_FUNCTION(msiof0),
3159 SH_PFC_FUNCTION(msiof1),
3160 SH_PFC_FUNCTION(msiof2),
3161 SH_PFC_FUNCTION(msiof3),
3162 SH_PFC_FUNCTION(msiof4),
3163 SH_PFC_FUNCTION(msiof5),
3165 SH_PFC_FUNCTION(pwm0),
3166 SH_PFC_FUNCTION(pwm1),
3167 SH_PFC_FUNCTION(pwm2),
3168 SH_PFC_FUNCTION(pwm3),
3169 SH_PFC_FUNCTION(pwm4),
3171 SH_PFC_FUNCTION(qspi0),
3172 SH_PFC_FUNCTION(qspi1),
3174 SH_PFC_FUNCTION(scif0),
3175 SH_PFC_FUNCTION(scif1),
3176 SH_PFC_FUNCTION(scif3),
3177 SH_PFC_FUNCTION(scif4),
3178 SH_PFC_FUNCTION(scif_clk),
3180 SH_PFC_FUNCTION(tmu),
3182 SH_PFC_FUNCTION(tpu),
3185 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3186 #define F_(x, y) FN_##y
3187 #define FM(x) FN_##x
3188 { PINMUX_CFG_REG("GPSR0", 0xe6058040, 32, 1, GROUP(
3193 GP_0_27_FN, GPSR0_27,
3194 GP_0_26_FN, GPSR0_26,
3195 GP_0_25_FN, GPSR0_25,
3196 GP_0_24_FN, GPSR0_24,
3197 GP_0_23_FN, GPSR0_23,
3198 GP_0_22_FN, GPSR0_22,
3199 GP_0_21_FN, GPSR0_21,
3200 GP_0_20_FN, GPSR0_20,
3201 GP_0_19_FN, GPSR0_19,
3202 GP_0_18_FN, GPSR0_18,
3203 GP_0_17_FN, GPSR0_17,
3204 GP_0_16_FN, GPSR0_16,
3205 GP_0_15_FN, GPSR0_15,
3206 GP_0_14_FN, GPSR0_14,
3207 GP_0_13_FN, GPSR0_13,
3208 GP_0_12_FN, GPSR0_12,
3209 GP_0_11_FN, GPSR0_11,
3210 GP_0_10_FN, GPSR0_10,
3220 GP_0_0_FN, GPSR0_0, ))
3222 { PINMUX_CFG_REG("GPSR1", 0xe6050040, 32, 1, GROUP(
3224 GP_1_30_FN, GPSR1_30,
3225 GP_1_29_FN, GPSR1_29,
3226 GP_1_28_FN, GPSR1_28,
3227 GP_1_27_FN, GPSR1_27,
3228 GP_1_26_FN, GPSR1_26,
3229 GP_1_25_FN, GPSR1_25,
3230 GP_1_24_FN, GPSR1_24,
3231 GP_1_23_FN, GPSR1_23,
3232 GP_1_22_FN, GPSR1_22,
3233 GP_1_21_FN, GPSR1_21,
3234 GP_1_20_FN, GPSR1_20,
3235 GP_1_19_FN, GPSR1_19,
3236 GP_1_18_FN, GPSR1_18,
3237 GP_1_17_FN, GPSR1_17,
3238 GP_1_16_FN, GPSR1_16,
3239 GP_1_15_FN, GPSR1_15,
3240 GP_1_14_FN, GPSR1_14,
3241 GP_1_13_FN, GPSR1_13,
3242 GP_1_12_FN, GPSR1_12,
3243 GP_1_11_FN, GPSR1_11,
3244 GP_1_10_FN, GPSR1_10,
3254 GP_1_0_FN, GPSR1_0, ))
3256 { PINMUX_CFG_REG("GPSR2", 0xe6050840, 32, 1, GROUP(
3264 GP_2_24_FN, GPSR2_24,
3265 GP_2_23_FN, GPSR2_23,
3266 GP_2_22_FN, GPSR2_22,
3267 GP_2_21_FN, GPSR2_21,
3268 GP_2_20_FN, GPSR2_20,
3269 GP_2_19_FN, GPSR2_19,
3270 GP_2_18_FN, GPSR2_18,
3271 GP_2_17_FN, GPSR2_17,
3272 GP_2_16_FN, GPSR2_16,
3273 GP_2_15_FN, GPSR2_15,
3274 GP_2_14_FN, GPSR2_14,
3275 GP_2_13_FN, GPSR2_13,
3276 GP_2_12_FN, GPSR2_12,
3277 GP_2_11_FN, GPSR2_11,
3278 GP_2_10_FN, GPSR2_10,
3288 GP_2_0_FN, GPSR2_0, ))
3290 { PINMUX_CFG_REG("GPSR3", 0xe6058840, 32, 1, GROUP(
3306 GP_3_16_FN, GPSR3_16,
3307 GP_3_15_FN, GPSR3_15,
3308 GP_3_14_FN, GPSR3_14,
3309 GP_3_13_FN, GPSR3_13,
3310 GP_3_12_FN, GPSR3_12,
3311 GP_3_11_FN, GPSR3_11,
3312 GP_3_10_FN, GPSR3_10,
3322 GP_3_0_FN, GPSR3_0, ))
3324 { PINMUX_CFG_REG("GPSR4", 0xe6060040, 32, 1, GROUP(
3330 GP_4_26_FN, GPSR4_26,
3331 GP_4_25_FN, GPSR4_25,
3332 GP_4_24_FN, GPSR4_24,
3333 GP_4_23_FN, GPSR4_23,
3334 GP_4_22_FN, GPSR4_22,
3335 GP_4_21_FN, GPSR4_21,
3336 GP_4_20_FN, GPSR4_20,
3337 GP_4_19_FN, GPSR4_19,
3338 GP_4_18_FN, GPSR4_18,
3339 GP_4_17_FN, GPSR4_17,
3340 GP_4_16_FN, GPSR4_16,
3341 GP_4_15_FN, GPSR4_15,
3342 GP_4_14_FN, GPSR4_14,
3343 GP_4_13_FN, GPSR4_13,
3344 GP_4_12_FN, GPSR4_12,
3345 GP_4_11_FN, GPSR4_11,
3346 GP_4_10_FN, GPSR4_10,
3356 GP_4_0_FN, GPSR4_0, ))
3358 { PINMUX_CFG_REG("GPSR5", 0xe6060840, 32, 1, GROUP(
3370 GP_5_20_FN, GPSR5_20,
3371 GP_5_19_FN, GPSR5_19,
3372 GP_5_18_FN, GPSR5_18,
3373 GP_5_17_FN, GPSR5_17,
3374 GP_5_16_FN, GPSR5_16,
3375 GP_5_15_FN, GPSR5_15,
3376 GP_5_14_FN, GPSR5_14,
3377 GP_5_13_FN, GPSR5_13,
3378 GP_5_12_FN, GPSR5_12,
3379 GP_5_11_FN, GPSR5_11,
3380 GP_5_10_FN, GPSR5_10,
3390 GP_5_0_FN, GPSR5_0, ))
3392 { PINMUX_CFG_REG("GPSR6", 0xe6068040, 32, 1, GROUP(
3404 GP_6_20_FN, GPSR6_20,
3405 GP_6_19_FN, GPSR6_19,
3406 GP_6_18_FN, GPSR6_18,
3407 GP_6_17_FN, GPSR6_17,
3408 GP_6_16_FN, GPSR6_16,
3409 GP_6_15_FN, GPSR6_15,
3410 GP_6_14_FN, GPSR6_14,
3411 GP_6_13_FN, GPSR6_13,
3412 GP_6_12_FN, GPSR6_12,
3413 GP_6_11_FN, GPSR6_11,
3414 GP_6_10_FN, GPSR6_10,
3424 GP_6_0_FN, GPSR6_0, ))
3426 { PINMUX_CFG_REG("GPSR7", 0xe6068840, 32, 1, GROUP(
3438 GP_7_20_FN, GPSR7_20,
3439 GP_7_19_FN, GPSR7_19,
3440 GP_7_18_FN, GPSR7_18,
3441 GP_7_17_FN, GPSR7_17,
3442 GP_7_16_FN, GPSR7_16,
3443 GP_7_15_FN, GPSR7_15,
3444 GP_7_14_FN, GPSR7_14,
3445 GP_7_13_FN, GPSR7_13,
3446 GP_7_12_FN, GPSR7_12,
3447 GP_7_11_FN, GPSR7_11,
3448 GP_7_10_FN, GPSR7_10,
3458 GP_7_0_FN, GPSR7_0, ))
3460 { PINMUX_CFG_REG("GPSR8", 0xe6069040, 32, 1, GROUP(
3472 GP_8_20_FN, GPSR8_20,
3473 GP_8_19_FN, GPSR8_19,
3474 GP_8_18_FN, GPSR8_18,
3475 GP_8_17_FN, GPSR8_17,
3476 GP_8_16_FN, GPSR8_16,
3477 GP_8_15_FN, GPSR8_15,
3478 GP_8_14_FN, GPSR8_14,
3479 GP_8_13_FN, GPSR8_13,
3480 GP_8_12_FN, GPSR8_12,
3481 GP_8_11_FN, GPSR8_11,
3482 GP_8_10_FN, GPSR8_10,
3492 GP_8_0_FN, GPSR8_0, ))
3494 { PINMUX_CFG_REG("GPSR9", 0xe6069840, 32, 1, GROUP(
3506 GP_9_20_FN, GPSR9_20,
3507 GP_9_19_FN, GPSR9_19,
3508 GP_9_18_FN, GPSR9_18,
3509 GP_9_17_FN, GPSR9_17,
3510 GP_9_16_FN, GPSR9_16,
3511 GP_9_15_FN, GPSR9_15,
3512 GP_9_14_FN, GPSR9_14,
3513 GP_9_13_FN, GPSR9_13,
3514 GP_9_12_FN, GPSR9_12,
3515 GP_9_11_FN, GPSR9_11,
3516 GP_9_10_FN, GPSR9_10,
3526 GP_9_0_FN, GPSR9_0, ))
3532 #define FM(x) FN_##x,
3533 { PINMUX_CFG_REG("IP0SR1", 0xe6050060, 32, 4, GROUP(
3543 { PINMUX_CFG_REG("IP1SR1", 0xe6050064, 32, 4, GROUP(
3553 { PINMUX_CFG_REG("IP2SR1", 0xe6050068, 32, 4, GROUP(
3563 { PINMUX_CFG_REG("IP3SR1", 0xe605006c, 32, 4, GROUP(
3573 { PINMUX_CFG_REG("IP0SR2", 0xe6050860, 32, 4, GROUP(
3583 { PINMUX_CFG_REG("IP1SR2", 0xe6050864, 32, 4, GROUP(
3593 { PINMUX_CFG_REG("IP2SR2", 0xe6050868, 32, 4, GROUP(
3603 { PINMUX_CFG_REG("IP0SR3", 0xe6058860, 32, 4, GROUP(
3613 { PINMUX_CFG_REG("IP1SR3", 0xe6058864, 32, 4, GROUP(
3623 { PINMUX_CFG_REG("IP0SR4", 0xe6060060, 32, 4, GROUP(
3633 { PINMUX_CFG_REG("IP1SR4", 0xe6060064, 32, 4, GROUP(
3643 { PINMUX_CFG_REG("IP2SR4", 0xe6060068, 32, 4, GROUP(
3653 { PINMUX_CFG_REG("IP0SR5", 0xe6060860, 32, 4, GROUP(
3663 { PINMUX_CFG_REG("IP1SR5", 0xe6060864, 32, 4, GROUP(
3673 { PINMUX_CFG_REG("IP2SR5", 0xe6060868, 32, 4, GROUP(
3687 #define FM(x) FN_##x,
3688 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6050900, 32,
3689 GROUP(4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 1, 1),
3691 /* RESERVED 31, 30, 29, 28 */
3692 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3693 /* RESERVED 27, 26, 25, 24 */
3694 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3695 /* RESERVED 23, 22, 21, 20 */
3696 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3697 /* RESERVED 19, 18, 17, 16 */
3698 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3712 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3713 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6058080) {
3714 { RCAR_GP_PIN(0, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */
3715 { RCAR_GP_PIN(0, 6), 24, 2 }, /* QSPI1_SPCLK */
3716 { RCAR_GP_PIN(0, 5), 20, 2 }, /* QSPI0_SSL */
3717 { RCAR_GP_PIN(0, 4), 16, 2 }, /* QSPI0_IO3 */
3718 { RCAR_GP_PIN(0, 3), 12, 2 }, /* QSPI0_IO2 */
3719 { RCAR_GP_PIN(0, 2), 8, 2 }, /* QSPI0_MISO_IO1 */
3720 { RCAR_GP_PIN(0, 1), 4, 2 }, /* QSPI0_MOSI_IO0 */
3721 { RCAR_GP_PIN(0, 0), 0, 2 }, /* QSPI0_SPCLK */
3723 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6058084) {
3724 { RCAR_GP_PIN(0, 15), 28, 3 }, /* SD_WP */
3725 { RCAR_GP_PIN(0, 14), 24, 2 }, /* RPC_INT_N */
3726 { RCAR_GP_PIN(0, 13), 20, 2 }, /* RPC_WP_N */
3727 { RCAR_GP_PIN(0, 12), 16, 2 }, /* RPC_RESET_N */
3728 { RCAR_GP_PIN(0, 11), 12, 2 }, /* QSPI1_SSL */
3729 { RCAR_GP_PIN(0, 10), 8, 2 }, /* QSPI1_IO3 */
3730 { RCAR_GP_PIN(0, 9), 4, 2 }, /* QSPI1_IO2 */
3731 { RCAR_GP_PIN(0, 8), 0, 2 }, /* QSPI1_MISO_IO1 */
3733 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6058088) {
3734 { RCAR_GP_PIN(0, 23), 28, 3 }, /* MMC_SD_CLK */
3735 { RCAR_GP_PIN(0, 22), 24, 3 }, /* MMC_SD_D3 */
3736 { RCAR_GP_PIN(0, 21), 20, 3 }, /* MMC_SD_D2 */
3737 { RCAR_GP_PIN(0, 20), 16, 3 }, /* MMC_SD_D1 */
3738 { RCAR_GP_PIN(0, 19), 12, 3 }, /* MMC_SD_D0 */
3739 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MMC_SD_CMD */
3740 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MMC_DS */
3741 { RCAR_GP_PIN(0, 16), 0, 3 }, /* SD_CD */
3743 { PINMUX_DRIVE_REG("DRV3CTRL0", 0xe605808c) {
3744 { RCAR_GP_PIN(0, 27), 12, 3 }, /* MMC_D7 */
3745 { RCAR_GP_PIN(0, 26), 8, 3 }, /* MMC_D6 */
3746 { RCAR_GP_PIN(0, 25), 4, 3 }, /* MMC_D5 */
3747 { RCAR_GP_PIN(0, 24), 0, 3 }, /* MMC_D4 */
3749 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050080) {
3750 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_TXD */
3751 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_RXD */
3752 { RCAR_GP_PIN(1, 5), 20, 3 }, /* HTX0 */
3753 { RCAR_GP_PIN(1, 4), 16, 3 }, /* HCTS0_N */
3754 { RCAR_GP_PIN(1, 3), 12, 3 }, /* HRTS0_N */
3755 { RCAR_GP_PIN(1, 2), 8, 3 }, /* HSCK0 */
3756 { RCAR_GP_PIN(1, 1), 4, 3 }, /* HRX0 */
3757 { RCAR_GP_PIN(1, 0), 0, 3 }, /* SCIF_CLK */
3759 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050084) {
3760 { RCAR_GP_PIN(1, 15), 28, 3 }, /* MSIOF1_SYNC */
3761 { RCAR_GP_PIN(1, 14), 24, 3 }, /* MSIOF1_SCK */
3762 { RCAR_GP_PIN(1, 13), 20, 3 }, /* MSIOF1_TXD */
3763 { RCAR_GP_PIN(1, 12), 16, 3 }, /* MSIOF1_RXD */
3764 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_SS2 */
3765 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SS1 */
3766 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_SYNC */
3767 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SCK */
3769 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050088) {
3770 { RCAR_GP_PIN(1, 23), 28, 3 }, /* MSIOF2_SS2 */
3771 { RCAR_GP_PIN(1, 22), 24, 3 }, /* MSIOF2_SS1 */
3772 { RCAR_GP_PIN(1, 21), 20, 3 }, /* MSIOF2_SYNC */
3773 { RCAR_GP_PIN(1, 20), 16, 3 }, /* MSIOF2_SCK */
3774 { RCAR_GP_PIN(1, 19), 12, 3 }, /* MSIOF2_TXD */
3775 { RCAR_GP_PIN(1, 18), 8, 3 }, /* MSIOF2_RXD */
3776 { RCAR_GP_PIN(1, 17), 4, 3 }, /* MSIOF1_SS2 */
3777 { RCAR_GP_PIN(1, 16), 0, 3 }, /* MSIOF1_SS1 */
3779 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605008c) {
3780 { RCAR_GP_PIN(1, 30), 24, 3 }, /* GP1_30 */
3781 { RCAR_GP_PIN(1, 29), 20, 3 }, /* GP1_29 */
3782 { RCAR_GP_PIN(1, 28), 16, 3 }, /* GP1_28 */
3783 { RCAR_GP_PIN(1, 27), 12, 3 }, /* IRQ3 */
3784 { RCAR_GP_PIN(1, 26), 8, 3 }, /* IRQ2 */
3785 { RCAR_GP_PIN(1, 25), 4, 3 }, /* IRQ1 */
3786 { RCAR_GP_PIN(1, 24), 0, 3 }, /* IRQ0 */
3788 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6050880) {
3789 { RCAR_GP_PIN(2, 7), 28, 3 }, /* GP2_07 */
3790 { RCAR_GP_PIN(2, 6), 24, 3 }, /* GP2_06 */
3791 { RCAR_GP_PIN(2, 5), 20, 3 }, /* GP2_05 */
3792 { RCAR_GP_PIN(2, 4), 16, 3 }, /* GP2_04 */
3793 { RCAR_GP_PIN(2, 3), 12, 3 }, /* GP2_03 */
3794 { RCAR_GP_PIN(2, 2), 8, 3 }, /* GP2_02 */
3795 { RCAR_GP_PIN(2, 1), 4, 2 }, /* IPC_CLKOUT */
3796 { RCAR_GP_PIN(2, 0), 0, 2 }, /* IPC_CLKIN */
3798 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6050884) {
3799 { RCAR_GP_PIN(2, 15), 28, 3 }, /* GP2_15 */
3800 { RCAR_GP_PIN(2, 14), 24, 3 }, /* GP2_14 */
3801 { RCAR_GP_PIN(2, 13), 20, 3 }, /* GP2_13 */
3802 { RCAR_GP_PIN(2, 12), 16, 3 }, /* GP2_12 */
3803 { RCAR_GP_PIN(2, 11), 12, 3 }, /* GP2_11 */
3804 { RCAR_GP_PIN(2, 10), 8, 3 }, /* GP2_10 */
3805 { RCAR_GP_PIN(2, 9), 4, 3 }, /* GP2_9 */
3806 { RCAR_GP_PIN(2, 8), 0, 3 }, /* GP2_8 */
3808 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6050888) {
3809 { RCAR_GP_PIN(2, 23), 28, 3 }, /* TCLK1_A */
3810 { RCAR_GP_PIN(2, 22), 24, 3 }, /* TPU0TO1 */
3811 { RCAR_GP_PIN(2, 21), 20, 3 }, /* TPU0TO0 */
3812 { RCAR_GP_PIN(2, 20), 16, 3 }, /* CLK_EXTFXR */
3813 { RCAR_GP_PIN(2, 19), 12, 3 }, /* RXDB_EXTFXR */
3814 { RCAR_GP_PIN(2, 18), 8, 3 }, /* FXR_TXDB */
3815 { RCAR_GP_PIN(2, 17), 4, 3 }, /* RXDA_EXTFXR_A */
3816 { RCAR_GP_PIN(2, 16), 0, 3 }, /* FXR_TXDA_A */
3818 { PINMUX_DRIVE_REG("DRV3CTRL2", 0xe605088c) {
3819 { RCAR_GP_PIN(2, 24), 0, 3 }, /* TCLK2_A */
3821 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6058880) {
3822 { RCAR_GP_PIN(3, 7), 28, 3 }, /* CANFD3_TX */
3823 { RCAR_GP_PIN(3, 6), 24, 3 }, /* CANFD2_RX */
3824 { RCAR_GP_PIN(3, 5), 20, 3 }, /* CANFD2_TX */
3825 { RCAR_GP_PIN(3, 4), 16, 3 }, /* CANFD1_RX */
3826 { RCAR_GP_PIN(3, 3), 12, 3 }, /* CANFD1_TX */
3827 { RCAR_GP_PIN(3, 2), 8, 3 }, /* CANFD0_RX */
3828 { RCAR_GP_PIN(3, 1), 4, 2 }, /* CANFD0_TX */
3829 { RCAR_GP_PIN(3, 0), 0, 2 }, /* CAN_CLK */
3831 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6058884) {
3832 { RCAR_GP_PIN(3, 15), 28, 3 }, /* CANFD7_TX */
3833 { RCAR_GP_PIN(3, 14), 24, 3 }, /* CANFD6_RX */
3834 { RCAR_GP_PIN(3, 13), 20, 3 }, /* CANFD6_TX */
3835 { RCAR_GP_PIN(3, 12), 16, 3 }, /* CANFD5_RX */
3836 { RCAR_GP_PIN(3, 11), 12, 3 }, /* CANFD5_TX */
3837 { RCAR_GP_PIN(3, 10), 8, 3 }, /* CANFD4_RX */
3838 { RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX*/
3839 { RCAR_GP_PIN(3, 8), 0, 3 }, /* CANFD3_RX */
3841 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6058888) {
3842 { RCAR_GP_PIN(3, 16), 0, 3 }, /* CANFD7_RX */
3844 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xe6060080) {
3845 { RCAR_GP_PIN(4, 7), 28, 3 }, /* AVB0_TXC */
3846 { RCAR_GP_PIN(4, 6), 24, 3 }, /* AVB0_TX_CTL */
3847 { RCAR_GP_PIN(4, 5), 20, 3 }, /* AVB0_RD3 */
3848 { RCAR_GP_PIN(4, 4), 16, 3 }, /* AVB0_RD2 */
3849 { RCAR_GP_PIN(4, 3), 12, 3 }, /* AVB0_RD1 */
3850 { RCAR_GP_PIN(4, 2), 8, 3 }, /* AVB0_RD0 */
3851 { RCAR_GP_PIN(4, 1), 4, 3 }, /* AVB0_RXC */
3852 { RCAR_GP_PIN(4, 0), 0, 3 }, /* AVB0_RX_CTL */
3854 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xe6060084) {
3855 { RCAR_GP_PIN(4, 15), 28, 3 }, /* AVB0_MAGIC */
3856 { RCAR_GP_PIN(4, 14), 24, 3 }, /* AVB0_MDC */
3857 { RCAR_GP_PIN(4, 13), 20, 3 }, /* AVB0_MDIO */
3858 { RCAR_GP_PIN(4, 12), 16, 3 }, /* AVB0_TXCREFCLK */
3859 { RCAR_GP_PIN(4, 11), 12, 3 }, /* AVB0_TD3 */
3860 { RCAR_GP_PIN(4, 10), 8, 3 }, /* AVB0_TD2 */
3861 { RCAR_GP_PIN(4, 9), 4, 3 }, /* AVB0_TD1*/
3862 { RCAR_GP_PIN(4, 8), 0, 3 }, /* AVB0_TD0 */
3864 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xe6060088) {
3865 { RCAR_GP_PIN(4, 23), 28, 3 }, /* PCIE2_CLKREQ_N */
3866 { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */
3867 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
3868 { RCAR_GP_PIN(4, 20), 16, 3 }, /* AVB0_AVTP_PPS */
3869 { RCAR_GP_PIN(4, 19), 12, 3 }, /* AVB0_AVTP_CAPTURE */
3870 { RCAR_GP_PIN(4, 18), 8, 3 }, /* AVB0_AVTP_MATCH */
3871 { RCAR_GP_PIN(4, 17), 4, 3 }, /* AVB0_LINK */
3872 { RCAR_GP_PIN(4, 16), 0, 3 }, /* AVB0_PHY_INT */
3874 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xe606008c) {
3875 { RCAR_GP_PIN(4, 26), 8, 3 }, /* AVS1 */
3876 { RCAR_GP_PIN(4, 25), 4, 3 }, /* AVS0 */
3877 { RCAR_GP_PIN(4, 24), 0, 3 }, /* PCIE3_CLKREQ_N */
3879 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xe6060880) {
3880 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB1_TXC */
3881 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB1_TX_CTL */
3882 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB1_RD3 */
3883 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB1_RD2 */
3884 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB1_RD1 */
3885 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB1_RD0 */
3886 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB1_RXC */
3887 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB1_RX_CTL */
3889 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xe6060884) {
3890 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB1_MAGIC */
3891 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB1_MDC */
3892 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB1_MDIO */
3893 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB1_TXCREFCLK */
3894 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB1_TD3 */
3895 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB1_TD2 */
3896 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB1_TD1*/
3897 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB1_TD0 */
3899 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xe6060888) {
3900 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB1_AVTP_PPS */
3901 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB1_AVTP_CAPTURE */
3902 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB1_AVTP_MATCH */
3903 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB1_LINK */
3904 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB1_PHY_INT */
3906 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xe6068080) {
3907 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB2_TXC */
3908 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB2_TX_CTL */
3909 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB2_RD3 */
3910 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB2_RD2 */
3911 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB2_RD1 */
3912 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB2_RD0 */
3913 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB2_RXC */
3914 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB2_RX_CTL */
3916 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xe6068084) {
3917 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB2_MAGIC */
3918 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB2_MDC */
3919 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB2_MDIO */
3920 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB2_TXCREFCLK */
3921 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB2_TD3 */
3922 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB2_TD2 */
3923 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB2_TD1*/
3924 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB2_TD0 */
3926 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xe6068088) {
3927 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB2_AVTP_PPS */
3928 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB2_AVTP_CAPTURE */
3929 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB2_AVTP_MATCH */
3930 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB2_LINK */
3931 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB2_PHY_INT */
3933 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xe6068880) {
3934 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB3_TXC */
3935 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB3_TX_CTL */
3936 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB3_RD3 */
3937 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB3_RD2 */
3938 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB3_RD1 */
3939 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB3_RD0 */
3940 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB3_RXC */
3941 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB3_RX_CTL */
3943 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xe6068884) {
3944 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB3_MAGIC */
3945 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB3_MDC */
3946 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB3_MDIO */
3947 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB3_TXCREFCLK */
3948 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB3_TD3 */
3949 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB3_TD2 */
3950 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB3_TD1*/
3951 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB3_TD0 */
3953 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xe6068888) {
3954 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB3_AVTP_PPS */
3955 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB3_AVTP_CAPTURE */
3956 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB3_AVTP_MATCH */
3957 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB3_LINK */
3958 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB3_PHY_INT */
3960 { PINMUX_DRIVE_REG("DRV0CTRL8", 0xe6069080) {
3961 { RCAR_GP_PIN(8, 7), 28, 3 }, /* AVB4_TXC */
3962 { RCAR_GP_PIN(8, 6), 24, 3 }, /* AVB4_TX_CTL */
3963 { RCAR_GP_PIN(8, 5), 20, 3 }, /* AVB4_RD3 */
3964 { RCAR_GP_PIN(8, 4), 16, 3 }, /* AVB4_RD2 */
3965 { RCAR_GP_PIN(8, 3), 12, 3 }, /* AVB4_RD1 */
3966 { RCAR_GP_PIN(8, 2), 8, 3 }, /* AVB4_RD0 */
3967 { RCAR_GP_PIN(8, 1), 4, 3 }, /* AVB4_RXC */
3968 { RCAR_GP_PIN(8, 0), 0, 3 }, /* AVB4_RX_CTL */
3970 { PINMUX_DRIVE_REG("DRV1CTRL8", 0xe6069084) {
3971 { RCAR_GP_PIN(8, 15), 28, 3 }, /* AVB4_MAGIC */
3972 { RCAR_GP_PIN(8, 14), 24, 3 }, /* AVB4_MDC */
3973 { RCAR_GP_PIN(8, 13), 20, 3 }, /* AVB4_MDIO */
3974 { RCAR_GP_PIN(8, 12), 16, 3 }, /* AVB4_TXCREFCLK */
3975 { RCAR_GP_PIN(8, 11), 12, 3 }, /* AVB4_TD3 */
3976 { RCAR_GP_PIN(8, 10), 8, 3 }, /* AVB4_TD2 */
3977 { RCAR_GP_PIN(8, 9), 4, 3 }, /* AVB4_TD1*/
3978 { RCAR_GP_PIN(8, 8), 0, 3 }, /* AVB4_TD0 */
3980 { PINMUX_DRIVE_REG("DRV2CTRL8", 0xe6069088) {
3981 { RCAR_GP_PIN(8, 20), 16, 3 }, /* AVB4_AVTP_PPS */
3982 { RCAR_GP_PIN(8, 19), 12, 3 }, /* AVB4_AVTP_CAPTURE */
3983 { RCAR_GP_PIN(8, 18), 8, 3 }, /* AVB4_AVTP_MATCH */
3984 { RCAR_GP_PIN(8, 17), 4, 3 }, /* AVB4_LINK */
3985 { RCAR_GP_PIN(8, 16), 0, 3 }, /* AVB4_PHY_INT */
3987 { PINMUX_DRIVE_REG("DRV0CTRL9", 0xe6069880) {
3988 { RCAR_GP_PIN(9, 7), 28, 3 }, /* AVB5_TXC */
3989 { RCAR_GP_PIN(9, 6), 24, 3 }, /* AVB5_TX_CTL */
3990 { RCAR_GP_PIN(9, 5), 20, 3 }, /* AVB5_RD3 */
3991 { RCAR_GP_PIN(9, 4), 16, 3 }, /* AVB5_RD2 */
3992 { RCAR_GP_PIN(9, 3), 12, 3 }, /* AVB5_RD1 */
3993 { RCAR_GP_PIN(9, 2), 8, 3 }, /* AVB5_RD0 */
3994 { RCAR_GP_PIN(9, 1), 4, 3 }, /* AVB5_RXC */
3995 { RCAR_GP_PIN(9, 0), 0, 3 }, /* AVB5_RX_CTL */
3997 { PINMUX_DRIVE_REG("DRV1CTRL9", 0xe6069884) {
3998 { RCAR_GP_PIN(9, 15), 28, 3 }, /* AVB5_MAGIC */
3999 { RCAR_GP_PIN(9, 14), 24, 3 }, /* AVB5_MDC */
4000 { RCAR_GP_PIN(9, 13), 20, 3 }, /* AVB5_MDIO */
4001 { RCAR_GP_PIN(9, 12), 16, 3 }, /* AVB5_TXCREFCLK */
4002 { RCAR_GP_PIN(9, 11), 12, 3 }, /* AVB5_TD3 */
4003 { RCAR_GP_PIN(9, 10), 8, 3 }, /* AVB5_TD2 */
4004 { RCAR_GP_PIN(9, 9), 4, 3 }, /* AVB5_TD1*/
4005 { RCAR_GP_PIN(9, 8), 0, 3 }, /* AVB5_TD0 */
4007 { PINMUX_DRIVE_REG("DRV2CTRL9", 0xe6069888) {
4008 { RCAR_GP_PIN(9, 20), 16, 3 }, /* AVB5_AVTP_PPS */
4009 { RCAR_GP_PIN(9, 19), 12, 3 }, /* AVB5_AVTP_CAPTURE */
4010 { RCAR_GP_PIN(9, 18), 8, 3 }, /* AVB5_AVTP_MATCH */
4011 { RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */
4012 { RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */
4030 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
4031 [POC0] = { 0xe60580a0, },
4032 [POC1] = { 0xe60500a0, },
4033 [POC2] = { 0xe60508a0, },
4034 [POC4] = { 0xe60600a0, },
4035 [POC5] = { 0xe60608a0, },
4036 [POC6] = { 0xe60680a0, },
4037 [POC7] = { 0xe60688a0, },
4038 [POC8] = { 0xe60690a0, },
4039 [POC9] = { 0xe60698a0, },
4040 [TD1SEL0] = { 0xe6058124, },
4044 static int r8a779a0_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
4047 int bit = pin & 0x1f;
4049 *pocctrl = pinmux_ioctrl_regs[POC0].reg;
4050 if (pin >= RCAR_GP_PIN(0, 15) && pin <= RCAR_GP_PIN(0, 27))
4053 *pocctrl = pinmux_ioctrl_regs[POC1].reg;
4054 if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 30))
4057 *pocctrl = pinmux_ioctrl_regs[POC2].reg;
4058 if (pin >= RCAR_GP_PIN(2, 2) && pin <= RCAR_GP_PIN(2, 15))
4061 *pocctrl = pinmux_ioctrl_regs[POC4].reg;
4062 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
4065 *pocctrl = pinmux_ioctrl_regs[POC5].reg;
4066 if (pin >= RCAR_GP_PIN(5, 0) && pin <= RCAR_GP_PIN(5, 17))
4069 *pocctrl = pinmux_ioctrl_regs[POC6].reg;
4070 if (pin >= RCAR_GP_PIN(6, 0) && pin <= RCAR_GP_PIN(6, 17))
4073 *pocctrl = pinmux_ioctrl_regs[POC7].reg;
4074 if (pin >= RCAR_GP_PIN(7, 0) && pin <= RCAR_GP_PIN(7, 17))
4077 *pocctrl = pinmux_ioctrl_regs[POC8].reg;
4078 if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 17))
4081 *pocctrl = pinmux_ioctrl_regs[POC9].reg;
4082 if (pin >= RCAR_GP_PIN(9, 0) && pin <= RCAR_GP_PIN(9, 17))
4088 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
4089 { PINMUX_BIAS_REG("PUEN0", 0xe60580c0, "PUD0", 0xe60580e0) {
4090 [ 0] = RCAR_GP_PIN(0, 0), /* QSPI0_SPCLK */
4091 [ 1] = RCAR_GP_PIN(0, 1), /* QSPI0_MOSI_IO0 */
4092 [ 2] = RCAR_GP_PIN(0, 2), /* QSPI0_MISO_IO1 */
4093 [ 3] = RCAR_GP_PIN(0, 3), /* QSPI0_IO2 */
4094 [ 4] = RCAR_GP_PIN(0, 4), /* QSPI0_IO3 */
4095 [ 5] = RCAR_GP_PIN(0, 5), /* QSPI0_SSL */
4096 [ 6] = RCAR_GP_PIN(0, 6), /* QSPI1_SPCLK */
4097 [ 7] = RCAR_GP_PIN(0, 7), /* QSPI1_MOSI_IO0 */
4098 [ 8] = RCAR_GP_PIN(0, 8), /* QSPI1_MISO_IO1 */
4099 [ 9] = RCAR_GP_PIN(0, 9), /* QSPI1_IO2 */
4100 [10] = RCAR_GP_PIN(0, 10), /* QSPI1_IO3 */
4101 [11] = RCAR_GP_PIN(0, 11), /* QSPI1_SSL */
4102 [12] = RCAR_GP_PIN(0, 12), /* RPC_RESET_N */
4103 [13] = RCAR_GP_PIN(0, 13), /* RPC_WP_N */
4104 [14] = RCAR_GP_PIN(0, 14), /* RPC_INT_N */
4105 [15] = RCAR_GP_PIN(0, 15), /* SD_WP */
4106 [16] = RCAR_GP_PIN(0, 16), /* SD_CD */
4107 [17] = RCAR_GP_PIN(0, 17), /* MMC_DS */
4108 [18] = RCAR_GP_PIN(0, 18), /* MMC_SD_CMD */
4109 [19] = RCAR_GP_PIN(0, 19), /* MMC_SD_D0 */
4110 [20] = RCAR_GP_PIN(0, 20), /* MMC_SD_D1 */
4111 [21] = RCAR_GP_PIN(0, 21), /* MMC_SD_D2 */
4112 [22] = RCAR_GP_PIN(0, 22), /* MMC_SD_D3 */
4113 [23] = RCAR_GP_PIN(0, 23), /* MMC_SD_CLK */
4114 [24] = RCAR_GP_PIN(0, 24), /* MMC_D4 */
4115 [25] = RCAR_GP_PIN(0, 25), /* MMC_D5 */
4116 [26] = RCAR_GP_PIN(0, 26), /* MMC_D6 */
4117 [27] = RCAR_GP_PIN(0, 27), /* MMC_D7 */
4118 [28] = SH_PFC_PIN_NONE,
4119 [29] = SH_PFC_PIN_NONE,
4120 [30] = SH_PFC_PIN_NONE,
4121 [31] = SH_PFC_PIN_NONE,
4123 { PINMUX_BIAS_REG("PUEN1", 0xe60500c0, "PUD1", 0xe60500e0) {
4124 [ 0] = RCAR_GP_PIN(1, 0), /* SCIF_CLK */
4125 [ 1] = RCAR_GP_PIN(1, 1), /* HRX0 */
4126 [ 2] = RCAR_GP_PIN(1, 2), /* HSCK0 */
4127 [ 3] = RCAR_GP_PIN(1, 3), /* HRTS0_N */
4128 [ 4] = RCAR_GP_PIN(1, 4), /* HCTS0_N */
4129 [ 5] = RCAR_GP_PIN(1, 5), /* HTX0 */
4130 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_RXD */
4131 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_TXD */
4132 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SCK */
4133 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_SYNC */
4134 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SS1 */
4135 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_SS2 */
4136 [12] = RCAR_GP_PIN(1, 12), /* MSIOF1_RXD */
4137 [13] = RCAR_GP_PIN(1, 13), /* MSIOF1_TXD */
4138 [14] = RCAR_GP_PIN(1, 14), /* MSIOF1_SCK */
4139 [15] = RCAR_GP_PIN(1, 15), /* MSIOF1_SYNC */
4140 [16] = RCAR_GP_PIN(1, 16), /* MSIOF1_SS1 */
4141 [17] = RCAR_GP_PIN(1, 17), /* MSIOF1_SS2 */
4142 [18] = RCAR_GP_PIN(1, 18), /* MSIOF2_RXD */
4143 [19] = RCAR_GP_PIN(1, 19), /* MSIOF2_TXD */
4144 [20] = RCAR_GP_PIN(1, 20), /* MSIOF2_SCK */
4145 [21] = RCAR_GP_PIN(1, 21), /* MSIOF2_SYNC */
4146 [22] = RCAR_GP_PIN(1, 22), /* MSIOF2_SS1 */
4147 [23] = RCAR_GP_PIN(1, 23), /* MSIOF2_SS2 */
4148 [24] = RCAR_GP_PIN(1, 24), /* IRQ0 */
4149 [25] = RCAR_GP_PIN(1, 25), /* IRQ1 */
4150 [26] = RCAR_GP_PIN(1, 26), /* IRQ2 */
4151 [27] = RCAR_GP_PIN(1, 27), /* IRQ3 */
4152 [28] = RCAR_GP_PIN(1, 28), /* GP1_28 */
4153 [29] = RCAR_GP_PIN(1, 29), /* GP1_29 */
4154 [30] = RCAR_GP_PIN(1, 30), /* GP1_30 */
4155 [31] = SH_PFC_PIN_NONE,
4157 { PINMUX_BIAS_REG("PUEN2", 0xe60508c0, "PUD2", 0xe60508e0) {
4158 [ 0] = RCAR_GP_PIN(2, 0), /* IPC_CLKIN */
4159 [ 1] = RCAR_GP_PIN(2, 1), /* IPC_CLKOUT */
4160 [ 2] = RCAR_GP_PIN(2, 2), /* GP2_02 */
4161 [ 3] = RCAR_GP_PIN(2, 3), /* GP2_03 */
4162 [ 4] = RCAR_GP_PIN(2, 4), /* GP2_04 */
4163 [ 5] = RCAR_GP_PIN(2, 5), /* GP2_05 */
4164 [ 6] = RCAR_GP_PIN(2, 6), /* GP2_06 */
4165 [ 7] = RCAR_GP_PIN(2, 7), /* GP2_07 */
4166 [ 8] = RCAR_GP_PIN(2, 8), /* GP2_08 */
4167 [ 9] = RCAR_GP_PIN(2, 9), /* GP2_09 */
4168 [10] = RCAR_GP_PIN(2, 10), /* GP2_10 */
4169 [11] = RCAR_GP_PIN(2, 11), /* GP2_11 */
4170 [12] = RCAR_GP_PIN(2, 12), /* GP2_12 */
4171 [13] = RCAR_GP_PIN(2, 13), /* GP2_13 */
4172 [14] = RCAR_GP_PIN(2, 14), /* GP2_14 */
4173 [15] = RCAR_GP_PIN(2, 15), /* GP2_15 */
4174 [16] = RCAR_GP_PIN(2, 16), /* FXR_TXDA_A */
4175 [17] = RCAR_GP_PIN(2, 17), /* RXDA_EXTFXR_A */
4176 [18] = RCAR_GP_PIN(2, 18), /* FXR_TXDB */
4177 [19] = RCAR_GP_PIN(2, 19), /* RXDB_EXTFXR */
4178 [20] = RCAR_GP_PIN(2, 20), /* CLK_EXTFXR */
4179 [21] = RCAR_GP_PIN(2, 21), /* TPU0TO0 */
4180 [22] = RCAR_GP_PIN(2, 22), /* TPU0TO1 */
4181 [23] = RCAR_GP_PIN(2, 23), /* TCLK1_A */
4182 [24] = RCAR_GP_PIN(2, 24), /* TCLK2_A */
4183 [25] = SH_PFC_PIN_NONE,
4184 [26] = SH_PFC_PIN_NONE,
4185 [27] = SH_PFC_PIN_NONE,
4186 [28] = SH_PFC_PIN_NONE,
4187 [29] = SH_PFC_PIN_NONE,
4188 [30] = SH_PFC_PIN_NONE,
4189 [31] = SH_PFC_PIN_NONE,
4191 { PINMUX_BIAS_REG("PUEN3", 0xe60588c0, "PUD3", 0xe60588e0) {
4192 [ 0] = RCAR_GP_PIN(3, 0), /* CAN_CLK */
4193 [ 1] = RCAR_GP_PIN(3, 1), /* CANFD0_TX */
4194 [ 2] = RCAR_GP_PIN(3, 2), /* CANFD0_RX */
4195 [ 3] = RCAR_GP_PIN(3, 3), /* CANFD1_TX */
4196 [ 4] = RCAR_GP_PIN(3, 4), /* CANFD1_RX */
4197 [ 5] = RCAR_GP_PIN(3, 5), /* CANFD2_TX */
4198 [ 6] = RCAR_GP_PIN(3, 6), /* CANFD2_RX */
4199 [ 7] = RCAR_GP_PIN(3, 7), /* CANFD3_TX */
4200 [ 8] = RCAR_GP_PIN(3, 8), /* CANFD3_RX */
4201 [ 9] = RCAR_GP_PIN(3, 9), /* CANFD4_TX */
4202 [10] = RCAR_GP_PIN(3, 10), /* CANFD4_RX */
4203 [11] = RCAR_GP_PIN(3, 11), /* CANFD5_TX */
4204 [12] = RCAR_GP_PIN(3, 12), /* CANFD5_RX */
4205 [13] = RCAR_GP_PIN(3, 13), /* CANFD6_TX */
4206 [14] = RCAR_GP_PIN(3, 14), /* CANFD6_RX */
4207 [15] = RCAR_GP_PIN(3, 15), /* CANFD7_TX */
4208 [16] = RCAR_GP_PIN(3, 16), /* CANFD7_RX */
4209 [17] = SH_PFC_PIN_NONE,
4210 [18] = SH_PFC_PIN_NONE,
4211 [19] = SH_PFC_PIN_NONE,
4212 [20] = SH_PFC_PIN_NONE,
4213 [21] = SH_PFC_PIN_NONE,
4214 [22] = SH_PFC_PIN_NONE,
4215 [23] = SH_PFC_PIN_NONE,
4216 [24] = SH_PFC_PIN_NONE,
4217 [25] = SH_PFC_PIN_NONE,
4218 [26] = SH_PFC_PIN_NONE,
4219 [27] = SH_PFC_PIN_NONE,
4220 [28] = SH_PFC_PIN_NONE,
4221 [29] = SH_PFC_PIN_NONE,
4222 [30] = SH_PFC_PIN_NONE,
4223 [31] = SH_PFC_PIN_NONE,
4225 { PINMUX_BIAS_REG("PUEN4", 0xe60600c0, "PUD4", 0xe60600e0) {
4226 [ 0] = RCAR_GP_PIN(4, 0), /* AVB0_RX_CTL */
4227 [ 1] = RCAR_GP_PIN(4, 1), /* AVB0_RXC */
4228 [ 2] = RCAR_GP_PIN(4, 2), /* AVB0_RD0 */
4229 [ 3] = RCAR_GP_PIN(4, 3), /* AVB0_RD1 */
4230 [ 4] = RCAR_GP_PIN(4, 4), /* AVB0_RD2 */
4231 [ 5] = RCAR_GP_PIN(4, 5), /* AVB0_RD3 */
4232 [ 6] = RCAR_GP_PIN(4, 6), /* AVB0_TX_CTL */
4233 [ 7] = RCAR_GP_PIN(4, 7), /* AVB0_TXC */
4234 [ 8] = RCAR_GP_PIN(4, 8), /* AVB0_TD0 */
4235 [ 9] = RCAR_GP_PIN(4, 9), /* AVB0_TD1 */
4236 [10] = RCAR_GP_PIN(4, 10), /* AVB0_TD2 */
4237 [11] = RCAR_GP_PIN(4, 11), /* AVB0_TD3 */
4238 [12] = RCAR_GP_PIN(4, 12), /* AVB0_TXREFCLK */
4239 [13] = RCAR_GP_PIN(4, 13), /* AVB0_MDIO */
4240 [14] = RCAR_GP_PIN(4, 14), /* AVB0_MDC */
4241 [15] = RCAR_GP_PIN(4, 15), /* AVB0_MAGIC */
4242 [16] = RCAR_GP_PIN(4, 16), /* AVB0_PHY_INT */
4243 [17] = RCAR_GP_PIN(4, 17), /* AVB0_LINK */
4244 [18] = RCAR_GP_PIN(4, 18), /* AVB0_AVTP_MATCH */
4245 [19] = RCAR_GP_PIN(4, 19), /* AVB0_AVTP_CAPTURE */
4246 [20] = RCAR_GP_PIN(4, 20), /* AVB0_AVTP_PPS */
4247 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
4248 [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */
4249 [23] = RCAR_GP_PIN(4, 23), /* PCIE2_CLKREQ_N */
4250 [24] = RCAR_GP_PIN(4, 24), /* PCIE3_CLKREQ_N */
4251 [25] = RCAR_GP_PIN(4, 25), /* AVS0 */
4252 [26] = RCAR_GP_PIN(4, 26), /* AVS1 */
4253 [27] = SH_PFC_PIN_NONE,
4254 [28] = SH_PFC_PIN_NONE,
4255 [29] = SH_PFC_PIN_NONE,
4256 [30] = SH_PFC_PIN_NONE,
4257 [31] = SH_PFC_PIN_NONE,
4259 { PINMUX_BIAS_REG("PUEN5", 0xe60608c0, "PUD5", 0xe60608e0) {
4260 [ 0] = RCAR_GP_PIN(5, 0), /* AVB1_RX_CTL */
4261 [ 1] = RCAR_GP_PIN(5, 1), /* AVB1_RXC */
4262 [ 2] = RCAR_GP_PIN(5, 2), /* AVB1_RD0 */
4263 [ 3] = RCAR_GP_PIN(5, 3), /* AVB1_RD1 */
4264 [ 4] = RCAR_GP_PIN(5, 4), /* AVB1_RD2 */
4265 [ 5] = RCAR_GP_PIN(5, 5), /* AVB1_RD3 */
4266 [ 6] = RCAR_GP_PIN(5, 6), /* AVB1_TX_CTL */
4267 [ 7] = RCAR_GP_PIN(5, 7), /* AVB1_TXC */
4268 [ 8] = RCAR_GP_PIN(5, 8), /* AVB1_TD0 */
4269 [ 9] = RCAR_GP_PIN(5, 9), /* AVB1_TD1 */
4270 [10] = RCAR_GP_PIN(5, 10), /* AVB1_TD2 */
4271 [11] = RCAR_GP_PIN(5, 11), /* AVB1_TD3 */
4272 [12] = RCAR_GP_PIN(5, 12), /* AVB1_TXCREFCLK */
4273 [13] = RCAR_GP_PIN(5, 13), /* AVB1_MDIO */
4274 [14] = RCAR_GP_PIN(5, 14), /* AVB1_MDC */
4275 [15] = RCAR_GP_PIN(5, 15), /* AVB1_MAGIC */
4276 [16] = RCAR_GP_PIN(5, 16), /* AVB1_PHY_INT */
4277 [17] = RCAR_GP_PIN(5, 17), /* AVB1_LINK */
4278 [18] = RCAR_GP_PIN(5, 18), /* AVB1_AVTP_MATCH */
4279 [19] = RCAR_GP_PIN(5, 19), /* AVB1_AVTP_CAPTURE */
4280 [20] = RCAR_GP_PIN(5, 20), /* AVB1_AVTP_PPS */
4281 [21] = SH_PFC_PIN_NONE,
4282 [22] = SH_PFC_PIN_NONE,
4283 [23] = SH_PFC_PIN_NONE,
4284 [24] = SH_PFC_PIN_NONE,
4285 [25] = SH_PFC_PIN_NONE,
4286 [26] = SH_PFC_PIN_NONE,
4287 [27] = SH_PFC_PIN_NONE,
4288 [28] = SH_PFC_PIN_NONE,
4289 [29] = SH_PFC_PIN_NONE,
4290 [30] = SH_PFC_PIN_NONE,
4291 [31] = SH_PFC_PIN_NONE,
4293 { PINMUX_BIAS_REG("PUEN6", 0xe60680c0, "PUD6", 0xe60680e0) {
4294 [ 0] = RCAR_GP_PIN(6, 0), /* AVB2_RX_CTL */
4295 [ 1] = RCAR_GP_PIN(6, 1), /* AVB2_RXC */
4296 [ 2] = RCAR_GP_PIN(6, 2), /* AVB2_RD0 */
4297 [ 3] = RCAR_GP_PIN(6, 3), /* AVB2_RD1 */
4298 [ 4] = RCAR_GP_PIN(6, 4), /* AVB2_RD2 */
4299 [ 5] = RCAR_GP_PIN(6, 5), /* AVB2_RD3 */
4300 [ 6] = RCAR_GP_PIN(6, 6), /* AVB2_TX_CTL */
4301 [ 7] = RCAR_GP_PIN(6, 7), /* AVB2_TXC */
4302 [ 8] = RCAR_GP_PIN(6, 8), /* AVB2_TD0 */
4303 [ 9] = RCAR_GP_PIN(6, 9), /* AVB2_TD1 */
4304 [10] = RCAR_GP_PIN(6, 10), /* AVB2_TD2 */
4305 [11] = RCAR_GP_PIN(6, 11), /* AVB2_TD3 */
4306 [12] = RCAR_GP_PIN(6, 12), /* AVB2_TXCREFCLK */
4307 [13] = RCAR_GP_PIN(6, 13), /* AVB2_MDIO */
4308 [14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC*/
4309 [15] = RCAR_GP_PIN(6, 15), /* AVB2_MAGIC */
4310 [16] = RCAR_GP_PIN(6, 16), /* AVB2_PHY_INT */
4311 [17] = RCAR_GP_PIN(6, 17), /* AVB2_LINK */
4312 [18] = RCAR_GP_PIN(6, 18), /* AVB2_AVTP_MATCH */
4313 [19] = RCAR_GP_PIN(6, 19), /* AVB2_AVTP_CAPTURE */
4314 [20] = RCAR_GP_PIN(6, 20), /* AVB2_AVTP_PPS */
4315 [21] = SH_PFC_PIN_NONE,
4316 [22] = SH_PFC_PIN_NONE,
4317 [23] = SH_PFC_PIN_NONE,
4318 [24] = SH_PFC_PIN_NONE,
4319 [25] = SH_PFC_PIN_NONE,
4320 [26] = SH_PFC_PIN_NONE,
4321 [27] = SH_PFC_PIN_NONE,
4322 [28] = SH_PFC_PIN_NONE,
4323 [29] = SH_PFC_PIN_NONE,
4324 [30] = SH_PFC_PIN_NONE,
4325 [31] = SH_PFC_PIN_NONE,
4327 { PINMUX_BIAS_REG("PUEN7", 0xe60688c0, "PUD7", 0xe60688e0) {
4328 [ 0] = RCAR_GP_PIN(7, 0), /* AVB3_RX_CTL */
4329 [ 1] = RCAR_GP_PIN(7, 1), /* AVB3_RXC */
4330 [ 2] = RCAR_GP_PIN(7, 2), /* AVB3_RD0 */
4331 [ 3] = RCAR_GP_PIN(7, 3), /* AVB3_RD1 */
4332 [ 4] = RCAR_GP_PIN(7, 4), /* AVB3_RD2 */
4333 [ 5] = RCAR_GP_PIN(7, 5), /* AVB3_RD3 */
4334 [ 6] = RCAR_GP_PIN(7, 6), /* AVB3_TX_CTL */
4335 [ 7] = RCAR_GP_PIN(7, 7), /* AVB3_TXC */
4336 [ 8] = RCAR_GP_PIN(7, 8), /* AVB3_TD0 */
4337 [ 9] = RCAR_GP_PIN(7, 9), /* AVB3_TD1 */
4338 [10] = RCAR_GP_PIN(7, 10), /* AVB3_TD2 */
4339 [11] = RCAR_GP_PIN(7, 11), /* AVB3_TD3 */
4340 [12] = RCAR_GP_PIN(7, 12), /* AVB3_TXCREFCLK */
4341 [13] = RCAR_GP_PIN(7, 13), /* AVB3_MDIO */
4342 [14] = RCAR_GP_PIN(7, 14), /* AVB3_MDC */
4343 [15] = RCAR_GP_PIN(7, 15), /* AVB3_MAGIC */
4344 [16] = RCAR_GP_PIN(7, 16), /* AVB3_PHY_INT */
4345 [17] = RCAR_GP_PIN(7, 17), /* AVB3_LINK */
4346 [18] = RCAR_GP_PIN(7, 18), /* AVB3_AVTP_MATCH */
4347 [19] = RCAR_GP_PIN(7, 19), /* AVB3_AVTP_CAPTURE */
4348 [20] = RCAR_GP_PIN(7, 20), /* AVB3_AVTP_PPS */
4349 [21] = SH_PFC_PIN_NONE,
4350 [22] = SH_PFC_PIN_NONE,
4351 [23] = SH_PFC_PIN_NONE,
4352 [24] = SH_PFC_PIN_NONE,
4353 [25] = SH_PFC_PIN_NONE,
4354 [26] = SH_PFC_PIN_NONE,
4355 [27] = SH_PFC_PIN_NONE,
4356 [28] = SH_PFC_PIN_NONE,
4357 [29] = SH_PFC_PIN_NONE,
4358 [30] = SH_PFC_PIN_NONE,
4359 [31] = SH_PFC_PIN_NONE,
4361 { PINMUX_BIAS_REG("PUEN8", 0xe60690c0, "PUD8", 0xe60690e0) {
4362 [ 0] = RCAR_GP_PIN(8, 0), /* AVB4_RX_CTL */
4363 [ 1] = RCAR_GP_PIN(8, 1), /* AVB4_RXC */
4364 [ 2] = RCAR_GP_PIN(8, 2), /* AVB4_RD0 */
4365 [ 3] = RCAR_GP_PIN(8, 3), /* AVB4_RD1 */
4366 [ 4] = RCAR_GP_PIN(8, 4), /* AVB4_RD2 */
4367 [ 5] = RCAR_GP_PIN(8, 5), /* AVB4_RD3 */
4368 [ 6] = RCAR_GP_PIN(8, 6), /* AVB4_TX_CTL */
4369 [ 7] = RCAR_GP_PIN(8, 7), /* AVB4_TXC */
4370 [ 8] = RCAR_GP_PIN(8, 8), /* AVB4_TD0 */
4371 [ 9] = RCAR_GP_PIN(8, 9), /* AVB4_TD1 */
4372 [10] = RCAR_GP_PIN(8, 10), /* AVB4_TD2 */
4373 [11] = RCAR_GP_PIN(8, 11), /* AVB4_TD3 */
4374 [12] = RCAR_GP_PIN(8, 12), /* AVB4_TXCREFCLK */
4375 [13] = RCAR_GP_PIN(8, 13), /* AVB4_MDIO */
4376 [14] = RCAR_GP_PIN(8, 14), /* AVB4_MDC */
4377 [15] = RCAR_GP_PIN(8, 15), /* AVB4_MAGIC */
4378 [16] = RCAR_GP_PIN(8, 16), /* AVB4_PHY_INT */
4379 [17] = RCAR_GP_PIN(8, 17), /* AVB4_LINK */
4380 [18] = RCAR_GP_PIN(8, 18), /* AVB4_AVTP_MATCH */
4381 [19] = RCAR_GP_PIN(8, 19), /* AVB4_AVTP_CAPTURE */
4382 [20] = RCAR_GP_PIN(8, 20), /* AVB4_AVTP_PPS */
4383 [21] = SH_PFC_PIN_NONE,
4384 [22] = SH_PFC_PIN_NONE,
4385 [23] = SH_PFC_PIN_NONE,
4386 [24] = SH_PFC_PIN_NONE,
4387 [25] = SH_PFC_PIN_NONE,
4388 [26] = SH_PFC_PIN_NONE,
4389 [27] = SH_PFC_PIN_NONE,
4390 [28] = SH_PFC_PIN_NONE,
4391 [29] = SH_PFC_PIN_NONE,
4392 [30] = SH_PFC_PIN_NONE,
4393 [31] = SH_PFC_PIN_NONE,
4395 { PINMUX_BIAS_REG("PUEN9", 0xe60698c0, "PUD9", 0xe60698e0) {
4396 [ 0] = RCAR_GP_PIN(9, 0), /* AVB5_RX_CTL */
4397 [ 1] = RCAR_GP_PIN(9, 1), /* AVB5_RXC */
4398 [ 2] = RCAR_GP_PIN(9, 2), /* AVB5_RD0 */
4399 [ 3] = RCAR_GP_PIN(9, 3), /* AVB5_RD1 */
4400 [ 4] = RCAR_GP_PIN(9, 4), /* AVB5_RD2 */
4401 [ 5] = RCAR_GP_PIN(9, 5), /* AVB5_RD3 */
4402 [ 6] = RCAR_GP_PIN(9, 6), /* AVB5_TX_CTL */
4403 [ 7] = RCAR_GP_PIN(9, 7), /* AVB5_TXC */
4404 [ 8] = RCAR_GP_PIN(9, 8), /* AVB5_TD0 */
4405 [ 9] = RCAR_GP_PIN(9, 9), /* AVB5_TD1 */
4406 [10] = RCAR_GP_PIN(9, 10), /* AVB5_TD2 */
4407 [11] = RCAR_GP_PIN(9, 11), /* AVB5_TD3 */
4408 [12] = RCAR_GP_PIN(9, 12), /* AVB5_TXCREFCLK */
4409 [13] = RCAR_GP_PIN(9, 13), /* AVB5_MDIO */
4410 [14] = RCAR_GP_PIN(9, 14), /* AVB5_MDC */
4411 [15] = RCAR_GP_PIN(9, 15), /* AVB5_MAGIC */
4412 [16] = RCAR_GP_PIN(9, 16), /* AVB5_PHY_INT */
4413 [17] = RCAR_GP_PIN(9, 17), /* AVB5_LINK */
4414 [18] = RCAR_GP_PIN(9, 18), /* AVB5_AVTP_MATCH */
4415 [19] = RCAR_GP_PIN(9, 19), /* AVB5_AVTP_CAPTURE */
4416 [20] = RCAR_GP_PIN(9, 20), /* AVB5_AVTP_PPS */
4417 [21] = SH_PFC_PIN_NONE,
4418 [22] = SH_PFC_PIN_NONE,
4419 [23] = SH_PFC_PIN_NONE,
4420 [24] = SH_PFC_PIN_NONE,
4421 [25] = SH_PFC_PIN_NONE,
4422 [26] = SH_PFC_PIN_NONE,
4423 [27] = SH_PFC_PIN_NONE,
4424 [28] = SH_PFC_PIN_NONE,
4425 [29] = SH_PFC_PIN_NONE,
4426 [30] = SH_PFC_PIN_NONE,
4427 [31] = SH_PFC_PIN_NONE,
4432 static const struct sh_pfc_soc_operations pinmux_ops = {
4433 .pin_to_pocctrl = r8a779a0_pin_to_pocctrl,
4434 .get_bias = rcar_pinmux_get_bias,
4435 .set_bias = rcar_pinmux_set_bias,
4438 const struct sh_pfc_soc_info r8a779a0_pinmux_info = {
4439 .name = "r8a779a0_pfc",
4441 .unlock_reg = 0x1ff, /* PMMRn mask */
4443 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4445 .pins = pinmux_pins,
4446 .nr_pins = ARRAY_SIZE(pinmux_pins),
4447 .groups = pinmux_groups,
4448 .nr_groups = ARRAY_SIZE(pinmux_groups),
4449 .functions = pinmux_functions,
4450 .nr_functions = ARRAY_SIZE(pinmux_functions),
4452 .cfg_regs = pinmux_config_regs,
4453 .drive_regs = pinmux_drive_regs,
4454 .bias_regs = pinmux_bias_regs,
4455 .ioctrl_regs = pinmux_ioctrl_regs,
4457 .pinmux_data = pinmux_data,
4458 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
projects / platform / kernel / linux-rpi.git / blob