1 // SPDX-License-Identifier: GPL-2.0
3 * R8A779A0 processor support - PFC hardware block.
5 * Copyright (C) 2020 Renesas Electronics Corp.
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
10 #include <linux/errno.h>
12 #include <linux/kernel.h>
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
18 #define CPU_ALL_GP(fn, sfx) \
19 PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS), \
20 PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
22 PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
23 PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
24 PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
25 PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
26 PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
27 PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
28 PORT_GP_CFG_1(0, 23, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
29 PORT_GP_CFG_1(0, 24, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
30 PORT_GP_CFG_1(0, 25, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
31 PORT_GP_CFG_1(0, 26, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
32 PORT_GP_CFG_1(0, 27, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
33 PORT_GP_CFG_31(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
34 PORT_GP_CFG_2(2, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_1(2, 2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
36 PORT_GP_CFG_1(2, 3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
37 PORT_GP_CFG_1(2, 4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
38 PORT_GP_CFG_1(2, 5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
39 PORT_GP_CFG_1(2, 6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
40 PORT_GP_CFG_1(2, 7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
41 PORT_GP_CFG_1(2, 8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
42 PORT_GP_CFG_1(2, 9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
43 PORT_GP_CFG_1(2, 10, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
44 PORT_GP_CFG_1(2, 11, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
45 PORT_GP_CFG_1(2, 12, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
46 PORT_GP_CFG_1(2, 13, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
47 PORT_GP_CFG_1(2, 14, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
48 PORT_GP_CFG_1(2, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
49 PORT_GP_CFG_1(2, 16, fn, sfx, CFG_FLAGS), \
50 PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \
51 PORT_GP_CFG_1(2, 18, fn, sfx, CFG_FLAGS), \
52 PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \
53 PORT_GP_CFG_1(2, 20, fn, sfx, CFG_FLAGS), \
54 PORT_GP_CFG_1(2, 21, fn, sfx, CFG_FLAGS), \
55 PORT_GP_CFG_1(2, 22, fn, sfx, CFG_FLAGS), \
56 PORT_GP_CFG_1(2, 23, fn, sfx, CFG_FLAGS), \
57 PORT_GP_CFG_1(2, 24, fn, sfx, CFG_FLAGS), \
58 PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS), \
59 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
60 PORT_GP_CFG_1(4, 18, fn, sfx, CFG_FLAGS), \
61 PORT_GP_CFG_1(4, 19, fn, sfx, CFG_FLAGS), \
62 PORT_GP_CFG_1(4, 20, fn, sfx, CFG_FLAGS), \
63 PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS), \
64 PORT_GP_CFG_1(4, 22, fn, sfx, CFG_FLAGS), \
65 PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS), \
66 PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS), \
67 PORT_GP_CFG_1(4, 25, fn, sfx, CFG_FLAGS), \
68 PORT_GP_CFG_1(4, 26, fn, sfx, CFG_FLAGS), \
69 PORT_GP_CFG_18(5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
70 PORT_GP_CFG_1(5, 18, fn, sfx, CFG_FLAGS), \
71 PORT_GP_CFG_1(5, 19, fn, sfx, CFG_FLAGS), \
72 PORT_GP_CFG_1(5, 20, fn, sfx, CFG_FLAGS), \
73 PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
74 PORT_GP_CFG_1(6, 18, fn, sfx, CFG_FLAGS), \
75 PORT_GP_CFG_1(6, 19, fn, sfx, CFG_FLAGS), \
76 PORT_GP_CFG_1(6, 20, fn, sfx, CFG_FLAGS), \
77 PORT_GP_CFG_18(7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
78 PORT_GP_CFG_1(7, 18, fn, sfx, CFG_FLAGS), \
79 PORT_GP_CFG_1(7, 19, fn, sfx, CFG_FLAGS), \
80 PORT_GP_CFG_1(7, 20, fn, sfx, CFG_FLAGS), \
81 PORT_GP_CFG_18(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
82 PORT_GP_CFG_1(8, 18, fn, sfx, CFG_FLAGS), \
83 PORT_GP_CFG_1(8, 19, fn, sfx, CFG_FLAGS), \
84 PORT_GP_CFG_1(8, 20, fn, sfx, CFG_FLAGS), \
85 PORT_GP_CFG_18(9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
86 PORT_GP_CFG_1(9, 18, fn, sfx, CFG_FLAGS), \
87 PORT_GP_CFG_1(9, 19, fn, sfx, CFG_FLAGS), \
88 PORT_GP_CFG_1(9, 20, fn, sfx, CFG_FLAGS)
90 #define CPU_ALL_NOGP(fn) \
91 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
92 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
93 PIN_NOGP_CFG(DCUTRST_N_LPDRST_N, "DCUTRST#_LPDRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
94 PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
95 PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
96 PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
99 * F_() : just information
100 * FM() : macro for FN_xxx / xxx_MARK
104 #define GPSR0_27 FM(MMC_D7)
105 #define GPSR0_26 FM(MMC_D6)
106 #define GPSR0_25 FM(MMC_D5)
107 #define GPSR0_24 FM(MMC_D4)
108 #define GPSR0_23 FM(MMC_SD_CLK)
109 #define GPSR0_22 FM(MMC_SD_D3)
110 #define GPSR0_21 FM(MMC_SD_D2)
111 #define GPSR0_20 FM(MMC_SD_D1)
112 #define GPSR0_19 FM(MMC_SD_D0)
113 #define GPSR0_18 FM(MMC_SD_CMD)
114 #define GPSR0_17 FM(MMC_DS)
115 #define GPSR0_16 FM(SD_CD)
116 #define GPSR0_15 FM(SD_WP)
117 #define GPSR0_14 FM(RPC_INT_N)
118 #define GPSR0_13 FM(RPC_WP_N)
119 #define GPSR0_12 FM(RPC_RESET_N)
120 #define GPSR0_11 FM(QSPI1_SSL)
121 #define GPSR0_10 FM(QSPI1_IO3)
122 #define GPSR0_9 FM(QSPI1_IO2)
123 #define GPSR0_8 FM(QSPI1_MISO_IO1)
124 #define GPSR0_7 FM(QSPI1_MOSI_IO0)
125 #define GPSR0_6 FM(QSPI1_SPCLK)
126 #define GPSR0_5 FM(QSPI0_SSL)
127 #define GPSR0_4 FM(QSPI0_IO3)
128 #define GPSR0_3 FM(QSPI0_IO2)
129 #define GPSR0_2 FM(QSPI0_MISO_IO1)
130 #define GPSR0_1 FM(QSPI0_MOSI_IO0)
131 #define GPSR0_0 FM(QSPI0_SPCLK)
134 #define GPSR1_30 F_(GP1_30, IP3SR1_27_24)
135 #define GPSR1_29 F_(GP1_29, IP3SR1_23_20)
136 #define GPSR1_28 F_(GP1_28, IP3SR1_19_16)
137 #define GPSR1_27 F_(IRQ3, IP3SR1_15_12)
138 #define GPSR1_26 F_(IRQ2, IP3SR1_11_8)
139 #define GPSR1_25 F_(IRQ1, IP3SR1_7_4)
140 #define GPSR1_24 F_(IRQ0, IP3SR1_3_0)
141 #define GPSR1_23 F_(MSIOF2_SS2, IP2SR1_31_28)
142 #define GPSR1_22 F_(MSIOF2_SS1, IP2SR1_27_24)
143 #define GPSR1_21 F_(MSIOF2_SYNC, IP2SR1_23_20)
144 #define GPSR1_20 F_(MSIOF2_SCK, IP2SR1_19_16)
145 #define GPSR1_19 F_(MSIOF2_TXD, IP2SR1_15_12)
146 #define GPSR1_18 F_(MSIOF2_RXD, IP2SR1_11_8)
147 #define GPSR1_17 F_(MSIOF1_SS2, IP2SR1_7_4)
148 #define GPSR1_16 F_(MSIOF1_SS1, IP2SR1_3_0)
149 #define GPSR1_15 F_(MSIOF1_SYNC, IP1SR1_31_28)
150 #define GPSR1_14 F_(MSIOF1_SCK, IP1SR1_27_24)
151 #define GPSR1_13 F_(MSIOF1_TXD, IP1SR1_23_20)
152 #define GPSR1_12 F_(MSIOF1_RXD, IP1SR1_19_16)
153 #define GPSR1_11 F_(MSIOF0_SS2, IP1SR1_15_12)
154 #define GPSR1_10 F_(MSIOF0_SS1, IP1SR1_11_8)
155 #define GPSR1_9 F_(MSIOF0_SYNC, IP1SR1_7_4)
156 #define GPSR1_8 F_(MSIOF0_SCK, IP1SR1_3_0)
157 #define GPSR1_7 F_(MSIOF0_TXD, IP0SR1_31_28)
158 #define GPSR1_6 F_(MSIOF0_RXD, IP0SR1_27_24)
159 #define GPSR1_5 F_(HTX0, IP0SR1_23_20)
160 #define GPSR1_4 F_(HCTS0_N, IP0SR1_19_16)
161 #define GPSR1_3 F_(HRTS0_N, IP0SR1_15_12)
162 #define GPSR1_2 F_(HSCK0, IP0SR1_11_8)
163 #define GPSR1_1 F_(HRX0, IP0SR1_7_4)
164 #define GPSR1_0 F_(SCIF_CLK, IP0SR1_3_0)
167 #define GPSR2_24 FM(TCLK2_A)
168 #define GPSR2_23 F_(TCLK1_A, IP2SR2_31_28)
169 #define GPSR2_22 F_(TPU0TO1, IP2SR2_27_24)
170 #define GPSR2_21 F_(TPU0TO0, IP2SR2_23_20)
171 #define GPSR2_20 F_(CLK_EXTFXR, IP2SR2_19_16)
172 #define GPSR2_19 F_(RXDB_EXTFXR, IP2SR2_15_12)
173 #define GPSR2_18 F_(FXR_TXDB, IP2SR2_11_8)
174 #define GPSR2_17 F_(RXDA_EXTFXR_A, IP2SR2_7_4)
175 #define GPSR2_16 F_(FXR_TXDA_A, IP2SR2_3_0)
176 #define GPSR2_15 F_(GP2_15, IP1SR2_31_28)
177 #define GPSR2_14 F_(GP2_14, IP1SR2_27_24)
178 #define GPSR2_13 F_(GP2_13, IP1SR2_23_20)
179 #define GPSR2_12 F_(GP2_12, IP1SR2_19_16)
180 #define GPSR2_11 F_(GP2_11, IP1SR2_15_12)
181 #define GPSR2_10 F_(GP2_10, IP1SR2_11_8)
182 #define GPSR2_9 F_(GP2_09, IP1SR2_7_4)
183 #define GPSR2_8 F_(GP2_08, IP1SR2_3_0)
184 #define GPSR2_7 F_(GP2_07, IP0SR2_31_28)
185 #define GPSR2_6 F_(GP2_06, IP0SR2_27_24)
186 #define GPSR2_5 F_(GP2_05, IP0SR2_23_20)
187 #define GPSR2_4 F_(GP2_04, IP0SR2_19_16)
188 #define GPSR2_3 F_(GP2_03, IP0SR2_15_12)
189 #define GPSR2_2 F_(GP2_02, IP0SR2_11_8)
190 #define GPSR2_1 F_(IPC_CLKOUT, IP0SR2_7_4)
191 #define GPSR2_0 F_(IPC_CLKIN, IP0SR2_3_0)
194 #define GPSR3_16 FM(CANFD7_RX)
195 #define GPSR3_15 FM(CANFD7_TX)
196 #define GPSR3_14 FM(CANFD6_RX)
197 #define GPSR3_13 F_(CANFD6_TX, IP1SR3_23_20)
198 #define GPSR3_12 F_(CANFD5_RX, IP1SR3_19_16)
199 #define GPSR3_11 F_(CANFD5_TX, IP1SR3_15_12)
200 #define GPSR3_10 F_(CANFD4_RX, IP1SR3_11_8)
201 #define GPSR3_9 F_(CANFD4_TX, IP1SR3_7_4)
202 #define GPSR3_8 F_(CANFD3_RX, IP1SR3_3_0)
203 #define GPSR3_7 F_(CANFD3_TX, IP0SR3_31_28)
204 #define GPSR3_6 F_(CANFD2_RX, IP0SR3_27_24)
205 #define GPSR3_5 F_(CANFD2_TX, IP0SR3_23_20)
206 #define GPSR3_4 FM(CANFD1_RX)
207 #define GPSR3_3 FM(CANFD1_TX)
208 #define GPSR3_2 F_(CANFD0_RX, IP0SR3_11_8)
209 #define GPSR3_1 F_(CANFD0_TX, IP0SR3_7_4)
210 #define GPSR3_0 FM(CAN_CLK)
213 #define GPSR4_26 FM(AVS1)
214 #define GPSR4_25 FM(AVS0)
215 #define GPSR4_24 FM(PCIE3_CLKREQ_N)
216 #define GPSR4_23 FM(PCIE2_CLKREQ_N)
217 #define GPSR4_22 FM(PCIE1_CLKREQ_N)
218 #define GPSR4_21 FM(PCIE0_CLKREQ_N)
219 #define GPSR4_20 F_(AVB0_AVTP_PPS, IP2SR4_19_16)
220 #define GPSR4_19 F_(AVB0_AVTP_CAPTURE, IP2SR4_15_12)
221 #define GPSR4_18 F_(AVB0_AVTP_MATCH, IP2SR4_11_8)
222 #define GPSR4_17 F_(AVB0_LINK, IP2SR4_7_4)
223 #define GPSR4_16 FM(AVB0_PHY_INT)
224 #define GPSR4_15 F_(AVB0_MAGIC, IP1SR4_31_28)
225 #define GPSR4_14 F_(AVB0_MDC, IP1SR4_27_24)
226 #define GPSR4_13 F_(AVB0_MDIO, IP1SR4_23_20)
227 #define GPSR4_12 F_(AVB0_TXCREFCLK, IP1SR4_19_16)
228 #define GPSR4_11 F_(AVB0_TD3, IP1SR4_15_12)
229 #define GPSR4_10 F_(AVB0_TD2, IP1SR4_11_8)
230 #define GPSR4_9 F_(AVB0_TD1, IP1SR4_7_4)
231 #define GPSR4_8 F_(AVB0_TD0, IP1SR4_3_0)
232 #define GPSR4_7 F_(AVB0_TXC, IP0SR4_31_28)
233 #define GPSR4_6 F_(AVB0_TX_CTL, IP0SR4_27_24)
234 #define GPSR4_5 F_(AVB0_RD3, IP0SR4_23_20)
235 #define GPSR4_4 F_(AVB0_RD2, IP0SR4_19_16)
236 #define GPSR4_3 F_(AVB0_RD1, IP0SR4_15_12)
237 #define GPSR4_2 F_(AVB0_RD0, IP0SR4_11_8)
238 #define GPSR4_1 F_(AVB0_RXC, IP0SR4_7_4)
239 #define GPSR4_0 F_(AVB0_RX_CTL, IP0SR4_3_0)
242 #define GPSR5_20 F_(AVB1_AVTP_PPS, IP2SR5_19_16)
243 #define GPSR5_19 F_(AVB1_AVTP_CAPTURE, IP2SR5_15_12)
244 #define GPSR5_18 F_(AVB1_AVTP_MATCH, IP2SR5_11_8)
245 #define GPSR5_17 F_(AVB1_LINK, IP2SR5_7_4)
246 #define GPSR5_16 FM(AVB1_PHY_INT)
247 #define GPSR5_15 F_(AVB1_MAGIC, IP1SR5_31_28)
248 #define GPSR5_14 F_(AVB1_MDC, IP1SR5_27_24)
249 #define GPSR5_13 F_(AVB1_MDIO, IP1SR5_23_20)
250 #define GPSR5_12 F_(AVB1_TXCREFCLK, IP1SR5_19_16)
251 #define GPSR5_11 F_(AVB1_TD3, IP1SR5_15_12)
252 #define GPSR5_10 F_(AVB1_TD2, IP1SR5_11_8)
253 #define GPSR5_9 F_(AVB1_TD1, IP1SR5_7_4)
254 #define GPSR5_8 F_(AVB1_TD0, IP1SR5_3_0)
255 #define GPSR5_7 F_(AVB1_TXC, IP0SR5_31_28)
256 #define GPSR5_6 F_(AVB1_TX_CTL, IP0SR5_27_24)
257 #define GPSR5_5 F_(AVB1_RD3, IP0SR5_23_20)
258 #define GPSR5_4 F_(AVB1_RD2, IP0SR5_19_16)
259 #define GPSR5_3 F_(AVB1_RD1, IP0SR5_15_12)
260 #define GPSR5_2 F_(AVB1_RD0, IP0SR5_11_8)
261 #define GPSR5_1 F_(AVB1_RXC, IP0SR5_7_4)
262 #define GPSR5_0 F_(AVB1_RX_CTL, IP0SR5_3_0)
265 #define GPSR6_20 FM(AVB2_AVTP_PPS)
266 #define GPSR6_19 FM(AVB2_AVTP_CAPTURE)
267 #define GPSR6_18 FM(AVB2_AVTP_MATCH)
268 #define GPSR6_17 FM(AVB2_LINK)
269 #define GPSR6_16 FM(AVB2_PHY_INT)
270 #define GPSR6_15 FM(AVB2_MAGIC)
271 #define GPSR6_14 FM(AVB2_MDC)
272 #define GPSR6_13 FM(AVB2_MDIO)
273 #define GPSR6_12 FM(AVB2_TXCREFCLK)
274 #define GPSR6_11 FM(AVB2_TD3)
275 #define GPSR6_10 FM(AVB2_TD2)
276 #define GPSR6_9 FM(AVB2_TD1)
277 #define GPSR6_8 FM(AVB2_TD0)
278 #define GPSR6_7 FM(AVB2_TXC)
279 #define GPSR6_6 FM(AVB2_TX_CTL)
280 #define GPSR6_5 FM(AVB2_RD3)
281 #define GPSR6_4 FM(AVB2_RD2)
282 #define GPSR6_3 FM(AVB2_RD1)
283 #define GPSR6_2 FM(AVB2_RD0)
284 #define GPSR6_1 FM(AVB2_RXC)
285 #define GPSR6_0 FM(AVB2_RX_CTL)
288 #define GPSR7_20 FM(AVB3_AVTP_PPS)
289 #define GPSR7_19 FM(AVB3_AVTP_CAPTURE)
290 #define GPSR7_18 FM(AVB3_AVTP_MATCH)
291 #define GPSR7_17 FM(AVB3_LINK)
292 #define GPSR7_16 FM(AVB3_PHY_INT)
293 #define GPSR7_15 FM(AVB3_MAGIC)
294 #define GPSR7_14 FM(AVB3_MDC)
295 #define GPSR7_13 FM(AVB3_MDIO)
296 #define GPSR7_12 FM(AVB3_TXCREFCLK)
297 #define GPSR7_11 FM(AVB3_TD3)
298 #define GPSR7_10 FM(AVB3_TD2)
299 #define GPSR7_9 FM(AVB3_TD1)
300 #define GPSR7_8 FM(AVB3_TD0)
301 #define GPSR7_7 FM(AVB3_TXC)
302 #define GPSR7_6 FM(AVB3_TX_CTL)
303 #define GPSR7_5 FM(AVB3_RD3)
304 #define GPSR7_4 FM(AVB3_RD2)
305 #define GPSR7_3 FM(AVB3_RD1)
306 #define GPSR7_2 FM(AVB3_RD0)
307 #define GPSR7_1 FM(AVB3_RXC)
308 #define GPSR7_0 FM(AVB3_RX_CTL)
311 #define GPSR8_20 FM(AVB4_AVTP_PPS)
312 #define GPSR8_19 FM(AVB4_AVTP_CAPTURE)
313 #define GPSR8_18 FM(AVB4_AVTP_MATCH)
314 #define GPSR8_17 FM(AVB4_LINK)
315 #define GPSR8_16 FM(AVB4_PHY_INT)
316 #define GPSR8_15 FM(AVB4_MAGIC)
317 #define GPSR8_14 FM(AVB4_MDC)
318 #define GPSR8_13 FM(AVB4_MDIO)
319 #define GPSR8_12 FM(AVB4_TXCREFCLK)
320 #define GPSR8_11 FM(AVB4_TD3)
321 #define GPSR8_10 FM(AVB4_TD2)
322 #define GPSR8_9 FM(AVB4_TD1)
323 #define GPSR8_8 FM(AVB4_TD0)
324 #define GPSR8_7 FM(AVB4_TXC)
325 #define GPSR8_6 FM(AVB4_TX_CTL)
326 #define GPSR8_5 FM(AVB4_RD3)
327 #define GPSR8_4 FM(AVB4_RD2)
328 #define GPSR8_3 FM(AVB4_RD1)
329 #define GPSR8_2 FM(AVB4_RD0)
330 #define GPSR8_1 FM(AVB4_RXC)
331 #define GPSR8_0 FM(AVB4_RX_CTL)
334 #define GPSR9_20 FM(AVB5_AVTP_PPS)
335 #define GPSR9_19 FM(AVB5_AVTP_CAPTURE)
336 #define GPSR9_18 FM(AVB5_AVTP_MATCH)
337 #define GPSR9_17 FM(AVB5_LINK)
338 #define GPSR9_16 FM(AVB5_PHY_INT)
339 #define GPSR9_15 FM(AVB5_MAGIC)
340 #define GPSR9_14 FM(AVB5_MDC)
341 #define GPSR9_13 FM(AVB5_MDIO)
342 #define GPSR9_12 FM(AVB5_TXCREFCLK)
343 #define GPSR9_11 FM(AVB5_TD3)
344 #define GPSR9_10 FM(AVB5_TD2)
345 #define GPSR9_9 FM(AVB5_TD1)
346 #define GPSR9_8 FM(AVB5_TD0)
347 #define GPSR9_7 FM(AVB5_TXC)
348 #define GPSR9_6 FM(AVB5_TX_CTL)
349 #define GPSR9_5 FM(AVB5_RD3)
350 #define GPSR9_4 FM(AVB5_RD2)
351 #define GPSR9_3 FM(AVB5_RD1)
352 #define GPSR9_2 FM(AVB5_RD0)
353 #define GPSR9_1 FM(AVB5_RXC)
354 #define GPSR9_0 FM(AVB5_RX_CTL)
356 /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
357 #define IP0SR1_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP0SR1_7_4 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP0SR1_11_8 FM(HSCK0) FM(SCK0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP0SR1_15_12 FM(HRTS0_N) FM(RTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP0SR1_19_16 FM(HCTS0_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP0SR1_23_20 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP0SR1_27_24 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP0SR1_31_28 FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR3) FM(A7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
366 #define IP1SR1_3_0 FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR4) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP1SR1_7_4 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP1SR1_11_8 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP1SR1_15_12 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR7) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP1SR1_19_16 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DG2) FM(A12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP1SR1_23_20 FM(MSIOF1_TXD) FM(HRX3) FM(SCK3) F_(0, 0) FM(DU_DG3) FM(A13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP1SR1_27_24 FM(MSIOF1_SCK) FM(HSCK3) FM(CTS3_N) F_(0, 0) FM(DU_DG4) FM(A14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP1SR1_31_28 FM(MSIOF1_SYNC) FM(HRTS3_N) FM(RTS3_N) F_(0, 0) FM(DU_DG5) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 /* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
375 #define IP2SR1_3_0 FM(MSIOF1_SS1) FM(HCTS3_N) FM(RX3) F_(0, 0) FM(DU_DG6) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP2SR1_7_4 FM(MSIOF1_SS2) FM(HTX3) FM(TX3) F_(0, 0) FM(DU_DG7) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP2SR1_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) FM(DU_DB2) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP2SR1_15_12 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) FM(DU_DB3) FM(A19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP2SR1_19_16 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) FM(DU_DB4) FM(A20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP2SR1_23_20 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1_A) F_(0, 0) FM(DU_DB5) FM(A21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP2SR1_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1_A) F_(0, 0) FM(DU_DB6) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP2SR1_31_28 FM(MSIOF2_SS2) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(DU_DB7) FM(A23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
385 #define IP3SR1_3_0 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKOUT) FM(A24) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP3SR1_7_4 FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_HSYNC) FM(A25) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP3SR1_11_8 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_VSYNC) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP3SR1_15_12 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_ODDF_DISP_CDE) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP3SR1_19_16 FM(GP1_28) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP3SR1_23_20 FM(GP1_29) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP3SR1_27_24 FM(GP1_30) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP3SR1_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
395 #define IP0SR2_3_0 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP0SR2_7_4 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP0SR2_11_8 FM(GP2_02) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP0SR2_15_12 FM(GP2_03) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399 #define IP0SR2_19_16 FM(GP2_04) F_(0, 0) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) FM(D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP0SR2_23_20 FM(GP2_05) FM(HSCK2) FM(MSIOF4_TXD) FM(SCK4) F_(0, 0) FM(D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 #define IP0SR2_27_24 FM(GP2_06) FM(HCTS2_N) FM(MSIOF4_SCK) FM(CTS4_N) F_(0, 0) FM(D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402 #define IP0SR2_31_28 FM(GP2_07) FM(HRTS2_N) FM(MSIOF4_SYNC) FM(RTS4_N) F_(0, 0) FM(D8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
404 #define IP1SR2_3_0 FM(GP2_08) FM(HRX2) FM(MSIOF4_SS1) FM(RX4) F_(0, 0) FM(D9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405 #define IP1SR2_7_4 FM(GP2_09) FM(HTX2) FM(MSIOF4_SS2) FM(TX4) F_(0, 0) FM(D10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
406 #define IP1SR2_11_8 FM(GP2_10) FM(TCLK2_B) FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) FM(D11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
407 #define IP1SR2_15_12 FM(GP2_11) FM(TCLK3) FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) FM(D12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
408 #define IP1SR2_19_16 FM(GP2_12) FM(TCLK4) FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) FM(D13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
409 #define IP1SR2_23_20 FM(GP2_13) F_(0, 0) FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410 #define IP1SR2_27_24 FM(GP2_14) FM(IRQ4) FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
411 #define IP1SR2_31_28 FM(GP2_15) FM(IRQ5) FM(MSIOF5_SS2) FM(CPG_CPCKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
412 /* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
413 #define IP2SR2_3_0 FM(FXR_TXDA_A) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
414 #define IP2SR2_7_4 FM(RXDA_EXTFXR_A) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(BS_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
415 #define IP2SR2_11_8 FM(FXR_TXDB) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
416 #define IP2SR2_15_12 FM(RXDB_EXTFXR) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
417 #define IP2SR2_19_16 FM(CLK_EXTFXR) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
418 #define IP2SR2_23_20 FM(TPU0TO0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_WR_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
419 #define IP2SR2_27_24 FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
420 #define IP2SR2_31_28 FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(EX_WAIT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
422 /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
423 #define IP0SR3_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
424 #define IP0SR3_7_4 FM(CANFD0_TX) FM(FXR_TXDA_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
425 #define IP0SR3_11_8 FM(CANFD0_RX) FM(RXDA_EXTFXR_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
426 #define IP0SR3_15_12 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
427 #define IP0SR3_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
428 #define IP0SR3_23_20 FM(CANFD2_TX) FM(TPU0TO2) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
429 #define IP0SR3_27_24 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
430 #define IP0SR3_31_28 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
431 /* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
432 #define IP1SR3_3_0 FM(CANFD3_RX) F_(0, 0) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
433 #define IP1SR3_7_4 FM(CANFD4_TX) F_(0, 0) FM(PWM4) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
434 #define IP1SR3_11_8 FM(CANFD4_RX) F_(0, 0) F_(0, 0) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
435 #define IP1SR3_15_12 FM(CANFD5_TX) F_(0, 0) F_(0, 0) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
436 #define IP1SR3_19_16 FM(CANFD5_RX) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
437 #define IP1SR3_23_20 FM(CANFD6_TX) F_(0, 0) F_(0, 0) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
438 #define IP1SR3_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
439 #define IP1SR3_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
441 /* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
442 #define IP0SR4_3_0 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
443 #define IP0SR4_7_4 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
444 #define IP0SR4_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
445 #define IP0SR4_15_12 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
446 #define IP0SR4_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
447 #define IP0SR4_23_20 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
448 #define IP0SR4_27_24 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
449 #define IP0SR4_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
450 /* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
451 #define IP1SR4_3_0 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
452 #define IP1SR4_7_4 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
453 #define IP1SR4_11_8 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
454 #define IP1SR4_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
455 #define IP1SR4_19_16 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
456 #define IP1SR4_23_20 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
457 #define IP1SR4_27_24 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
458 #define IP1SR4_31_28 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
459 /* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
460 #define IP2SR4_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
461 #define IP2SR4_7_4 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
462 #define IP2SR4_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
463 #define IP2SR4_15_12 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
464 #define IP2SR4_19_16 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
465 #define IP2SR4_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
466 #define IP2SR4_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
467 #define IP2SR4_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
469 /* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
470 #define IP0SR5_3_0 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
471 #define IP0SR5_7_4 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
472 #define IP0SR5_11_8 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
473 #define IP0SR5_15_12 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
474 #define IP0SR5_19_16 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define IP0SR5_23_20 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
476 #define IP0SR5_27_24 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
477 #define IP0SR5_31_28 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
478 /* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
479 #define IP1SR5_3_0 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
480 #define IP1SR5_7_4 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
481 #define IP1SR5_11_8 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
482 #define IP1SR5_15_12 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
483 #define IP1SR5_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
484 #define IP1SR5_23_20 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
485 #define IP1SR5_27_24 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
486 #define IP1SR5_31_28 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
487 /* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
488 #define IP2SR5_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
489 #define IP2SR5_7_4 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
490 #define IP2SR5_11_8 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
491 #define IP2SR5_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
492 #define IP2SR5_19_16 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
493 #define IP2SR5_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
494 #define IP2SR5_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
495 #define IP2SR5_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
497 #define PINMUX_GPSR \
503 GPSR0_26 GPSR1_26 GPSR4_26 \
504 GPSR0_25 GPSR1_25 GPSR4_25 \
505 GPSR0_24 GPSR1_24 GPSR2_24 GPSR4_24 \
506 GPSR0_23 GPSR1_23 GPSR2_23 GPSR4_23 \
507 GPSR0_22 GPSR1_22 GPSR2_22 GPSR4_22 \
508 GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
509 GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 GPSR8_20 GPSR9_20 \
510 GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 GPSR8_19 GPSR9_19 \
511 GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 GPSR8_18 GPSR9_18 \
512 GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 GPSR8_17 GPSR9_17 \
513 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 GPSR8_16 GPSR9_16 \
514 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 GPSR8_15 GPSR9_15 \
515 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 GPSR8_14 GPSR9_14 \
516 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 GPSR9_13 \
517 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 GPSR9_12 \
518 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 GPSR9_11 \
519 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 GPSR9_10 \
520 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 GPSR9_9 \
521 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 GPSR9_8 \
522 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 GPSR9_7 \
523 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 GPSR9_6 \
524 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 GPSR9_5 \
525 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 GPSR9_4 \
526 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 GPSR9_3 \
527 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 GPSR9_2 \
528 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 GPSR9_1 \
529 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0 GPSR9_0
531 #define PINMUX_IPSR \
533 FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \
534 FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \
535 FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \
536 FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
537 FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
538 FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \
539 FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \
540 FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 FM(IP3SR1_31_28) IP3SR1_31_28 \
542 FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
543 FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
544 FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \
545 FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \
546 FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 FM(IP2SR2_19_16) IP2SR2_19_16 \
547 FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2SR2_23_20 \
548 FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \
549 FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \
551 FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 \
552 FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 \
553 FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 \
554 FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 \
555 FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 \
556 FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 \
557 FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 \
558 FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 \
560 FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 \
561 FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \
562 FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \
563 FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \
564 FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \
565 FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \
566 FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \
567 FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \
569 FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \
570 FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \
571 FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \
572 FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \
573 FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \
574 FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 FM(IP2SR5_23_20) IP2SR5_23_20 \
575 FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 FM(IP2SR5_27_24) IP2SR5_27_24 \
576 FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 FM(IP2SR5_31_28) IP2SR5_31_28
578 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
579 #define MOD_SEL2_15_14 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3)
580 #define MOD_SEL2_13_12 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3)
581 #define MOD_SEL2_11_10 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3)
582 #define MOD_SEL2_9_8 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3)
583 #define MOD_SEL2_7_6 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3)
584 #define MOD_SEL2_5_4 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3)
585 #define MOD_SEL2_3_2 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3)
587 #define PINMUX_MOD_SELS \
597 #define PINMUX_PHYS \
598 FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \
599 FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5) FM(SCL6) FM(SDA6)
609 #define FM(x) FN_##x,
610 PINMUX_FUNCTION_BEGIN,
620 #define FM(x) x##_MARK,
631 static const u16 pinmux_data[] = {
632 /* Using GP_2_[2-15] requires disabling I2C in MOD_SEL2 */
633 #define GP_2_2_FN GP_2_2_FN, FN_SEL_I2C0_0
634 #define GP_2_3_FN GP_2_3_FN, FN_SEL_I2C0_0
635 #define GP_2_4_FN GP_2_4_FN, FN_SEL_I2C1_0
636 #define GP_2_5_FN GP_2_5_FN, FN_SEL_I2C1_0
637 #define GP_2_6_FN GP_2_6_FN, FN_SEL_I2C2_0
638 #define GP_2_7_FN GP_2_7_FN, FN_SEL_I2C2_0
639 #define GP_2_8_FN GP_2_8_FN, FN_SEL_I2C3_0
640 #define GP_2_9_FN GP_2_9_FN, FN_SEL_I2C3_0
641 #define GP_2_10_FN GP_2_10_FN, FN_SEL_I2C4_0
642 #define GP_2_11_FN GP_2_11_FN, FN_SEL_I2C4_0
643 #define GP_2_12_FN GP_2_12_FN, FN_SEL_I2C5_0
644 #define GP_2_13_FN GP_2_13_FN, FN_SEL_I2C5_0
645 #define GP_2_14_FN GP_2_14_FN, FN_SEL_I2C6_0
646 #define GP_2_15_FN GP_2_15_FN, FN_SEL_I2C6_0
647 PINMUX_DATA_GP_ALL(),
663 PINMUX_SINGLE(MMC_D7),
664 PINMUX_SINGLE(MMC_D6),
665 PINMUX_SINGLE(MMC_D5),
666 PINMUX_SINGLE(MMC_D4),
667 PINMUX_SINGLE(MMC_SD_CLK),
668 PINMUX_SINGLE(MMC_SD_D3),
669 PINMUX_SINGLE(MMC_SD_D2),
670 PINMUX_SINGLE(MMC_SD_D1),
671 PINMUX_SINGLE(MMC_SD_D0),
672 PINMUX_SINGLE(MMC_SD_CMD),
673 PINMUX_SINGLE(MMC_DS),
675 PINMUX_SINGLE(SD_CD),
676 PINMUX_SINGLE(SD_WP),
678 PINMUX_SINGLE(RPC_INT_N),
679 PINMUX_SINGLE(RPC_WP_N),
680 PINMUX_SINGLE(RPC_RESET_N),
682 PINMUX_SINGLE(QSPI1_SSL),
683 PINMUX_SINGLE(QSPI1_IO3),
684 PINMUX_SINGLE(QSPI1_IO2),
685 PINMUX_SINGLE(QSPI1_MISO_IO1),
686 PINMUX_SINGLE(QSPI1_MOSI_IO0),
687 PINMUX_SINGLE(QSPI1_SPCLK),
688 PINMUX_SINGLE(QSPI0_SSL),
689 PINMUX_SINGLE(QSPI0_IO3),
690 PINMUX_SINGLE(QSPI0_IO2),
691 PINMUX_SINGLE(QSPI0_MISO_IO1),
692 PINMUX_SINGLE(QSPI0_MOSI_IO0),
693 PINMUX_SINGLE(QSPI0_SPCLK),
695 PINMUX_SINGLE(TCLK2_A),
697 PINMUX_SINGLE(CANFD7_RX),
698 PINMUX_SINGLE(CANFD7_TX),
699 PINMUX_SINGLE(CANFD6_RX),
700 PINMUX_SINGLE(CANFD1_RX),
701 PINMUX_SINGLE(CANFD1_TX),
702 PINMUX_SINGLE(CAN_CLK),
707 PINMUX_SINGLE(PCIE3_CLKREQ_N),
708 PINMUX_SINGLE(PCIE2_CLKREQ_N),
709 PINMUX_SINGLE(PCIE1_CLKREQ_N),
710 PINMUX_SINGLE(PCIE0_CLKREQ_N),
712 PINMUX_SINGLE(AVB0_PHY_INT),
713 PINMUX_SINGLE(AVB0_MAGIC),
714 PINMUX_SINGLE(AVB0_MDC),
715 PINMUX_SINGLE(AVB0_MDIO),
716 PINMUX_SINGLE(AVB0_TXCREFCLK),
718 PINMUX_SINGLE(AVB1_PHY_INT),
719 PINMUX_SINGLE(AVB1_MAGIC),
720 PINMUX_SINGLE(AVB1_MDC),
721 PINMUX_SINGLE(AVB1_MDIO),
722 PINMUX_SINGLE(AVB1_TXCREFCLK),
724 PINMUX_SINGLE(AVB2_AVTP_PPS),
725 PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
726 PINMUX_SINGLE(AVB2_AVTP_MATCH),
727 PINMUX_SINGLE(AVB2_LINK),
728 PINMUX_SINGLE(AVB2_PHY_INT),
729 PINMUX_SINGLE(AVB2_MAGIC),
730 PINMUX_SINGLE(AVB2_MDC),
731 PINMUX_SINGLE(AVB2_MDIO),
732 PINMUX_SINGLE(AVB2_TXCREFCLK),
733 PINMUX_SINGLE(AVB2_TD3),
734 PINMUX_SINGLE(AVB2_TD2),
735 PINMUX_SINGLE(AVB2_TD1),
736 PINMUX_SINGLE(AVB2_TD0),
737 PINMUX_SINGLE(AVB2_TXC),
738 PINMUX_SINGLE(AVB2_TX_CTL),
739 PINMUX_SINGLE(AVB2_RD3),
740 PINMUX_SINGLE(AVB2_RD2),
741 PINMUX_SINGLE(AVB2_RD1),
742 PINMUX_SINGLE(AVB2_RD0),
743 PINMUX_SINGLE(AVB2_RXC),
744 PINMUX_SINGLE(AVB2_RX_CTL),
746 PINMUX_SINGLE(AVB3_AVTP_PPS),
747 PINMUX_SINGLE(AVB3_AVTP_CAPTURE),
748 PINMUX_SINGLE(AVB3_AVTP_MATCH),
749 PINMUX_SINGLE(AVB3_LINK),
750 PINMUX_SINGLE(AVB3_PHY_INT),
751 PINMUX_SINGLE(AVB3_MAGIC),
752 PINMUX_SINGLE(AVB3_MDC),
753 PINMUX_SINGLE(AVB3_MDIO),
754 PINMUX_SINGLE(AVB3_TXCREFCLK),
755 PINMUX_SINGLE(AVB3_TD3),
756 PINMUX_SINGLE(AVB3_TD2),
757 PINMUX_SINGLE(AVB3_TD1),
758 PINMUX_SINGLE(AVB3_TD0),
759 PINMUX_SINGLE(AVB3_TXC),
760 PINMUX_SINGLE(AVB3_TX_CTL),
761 PINMUX_SINGLE(AVB3_RD3),
762 PINMUX_SINGLE(AVB3_RD2),
763 PINMUX_SINGLE(AVB3_RD1),
764 PINMUX_SINGLE(AVB3_RD0),
765 PINMUX_SINGLE(AVB3_RXC),
766 PINMUX_SINGLE(AVB3_RX_CTL),
768 PINMUX_SINGLE(AVB4_AVTP_PPS),
769 PINMUX_SINGLE(AVB4_AVTP_CAPTURE),
770 PINMUX_SINGLE(AVB4_AVTP_MATCH),
771 PINMUX_SINGLE(AVB4_LINK),
772 PINMUX_SINGLE(AVB4_PHY_INT),
773 PINMUX_SINGLE(AVB4_MAGIC),
774 PINMUX_SINGLE(AVB4_MDC),
775 PINMUX_SINGLE(AVB4_MDIO),
776 PINMUX_SINGLE(AVB4_TXCREFCLK),
777 PINMUX_SINGLE(AVB4_TD3),
778 PINMUX_SINGLE(AVB4_TD2),
779 PINMUX_SINGLE(AVB4_TD1),
780 PINMUX_SINGLE(AVB4_TD0),
781 PINMUX_SINGLE(AVB4_TXC),
782 PINMUX_SINGLE(AVB4_TX_CTL),
783 PINMUX_SINGLE(AVB4_RD3),
784 PINMUX_SINGLE(AVB4_RD2),
785 PINMUX_SINGLE(AVB4_RD1),
786 PINMUX_SINGLE(AVB4_RD0),
787 PINMUX_SINGLE(AVB4_RXC),
788 PINMUX_SINGLE(AVB4_RX_CTL),
790 PINMUX_SINGLE(AVB5_AVTP_PPS),
791 PINMUX_SINGLE(AVB5_AVTP_CAPTURE),
792 PINMUX_SINGLE(AVB5_AVTP_MATCH),
793 PINMUX_SINGLE(AVB5_LINK),
794 PINMUX_SINGLE(AVB5_PHY_INT),
795 PINMUX_SINGLE(AVB5_MAGIC),
796 PINMUX_SINGLE(AVB5_MDC),
797 PINMUX_SINGLE(AVB5_MDIO),
798 PINMUX_SINGLE(AVB5_TXCREFCLK),
799 PINMUX_SINGLE(AVB5_TD3),
800 PINMUX_SINGLE(AVB5_TD2),
801 PINMUX_SINGLE(AVB5_TD1),
802 PINMUX_SINGLE(AVB5_TD0),
803 PINMUX_SINGLE(AVB5_TXC),
804 PINMUX_SINGLE(AVB5_TX_CTL),
805 PINMUX_SINGLE(AVB5_RD3),
806 PINMUX_SINGLE(AVB5_RD2),
807 PINMUX_SINGLE(AVB5_RD1),
808 PINMUX_SINGLE(AVB5_RD0),
809 PINMUX_SINGLE(AVB5_RXC),
810 PINMUX_SINGLE(AVB5_RX_CTL),
813 PINMUX_IPSR_GPSR(IP0SR1_3_0, SCIF_CLK),
814 PINMUX_IPSR_GPSR(IP0SR1_3_0, A0),
816 PINMUX_IPSR_GPSR(IP0SR1_7_4, HRX0),
817 PINMUX_IPSR_GPSR(IP0SR1_7_4, RX0),
818 PINMUX_IPSR_GPSR(IP0SR1_7_4, A1),
820 PINMUX_IPSR_GPSR(IP0SR1_11_8, HSCK0),
821 PINMUX_IPSR_GPSR(IP0SR1_11_8, SCK0),
822 PINMUX_IPSR_GPSR(IP0SR1_11_8, A2),
824 PINMUX_IPSR_GPSR(IP0SR1_15_12, HRTS0_N),
825 PINMUX_IPSR_GPSR(IP0SR1_15_12, RTS0_N),
826 PINMUX_IPSR_GPSR(IP0SR1_15_12, A3),
828 PINMUX_IPSR_GPSR(IP0SR1_19_16, HCTS0_N),
829 PINMUX_IPSR_GPSR(IP0SR1_19_16, CTS0_N),
830 PINMUX_IPSR_GPSR(IP0SR1_19_16, A4),
832 PINMUX_IPSR_GPSR(IP0SR1_23_20, HTX0),
833 PINMUX_IPSR_GPSR(IP0SR1_23_20, TX0),
834 PINMUX_IPSR_GPSR(IP0SR1_23_20, A5),
836 PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_RXD),
837 PINMUX_IPSR_GPSR(IP0SR1_27_24, DU_DR2),
838 PINMUX_IPSR_GPSR(IP0SR1_27_24, A6),
840 PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_TXD),
841 PINMUX_IPSR_GPSR(IP0SR1_31_28, DU_DR3),
842 PINMUX_IPSR_GPSR(IP0SR1_31_28, A7),
845 PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SCK),
846 PINMUX_IPSR_GPSR(IP1SR1_3_0, DU_DR4),
847 PINMUX_IPSR_GPSR(IP1SR1_3_0, A8),
849 PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_SYNC),
850 PINMUX_IPSR_GPSR(IP1SR1_7_4, DU_DR5),
851 PINMUX_IPSR_GPSR(IP1SR1_7_4, A9),
853 PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SS1),
854 PINMUX_IPSR_GPSR(IP1SR1_11_8, DU_DR6),
855 PINMUX_IPSR_GPSR(IP1SR1_11_8, A10),
857 PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_SS2),
858 PINMUX_IPSR_GPSR(IP1SR1_15_12, DU_DR7),
859 PINMUX_IPSR_GPSR(IP1SR1_15_12, A11),
861 PINMUX_IPSR_GPSR(IP1SR1_19_16, MSIOF1_RXD),
862 PINMUX_IPSR_GPSR(IP1SR1_19_16, DU_DG2),
863 PINMUX_IPSR_GPSR(IP1SR1_19_16, A12),
865 PINMUX_IPSR_GPSR(IP1SR1_23_20, MSIOF1_TXD),
866 PINMUX_IPSR_GPSR(IP1SR1_23_20, HRX3),
867 PINMUX_IPSR_GPSR(IP1SR1_23_20, SCK3),
868 PINMUX_IPSR_GPSR(IP1SR1_23_20, DU_DG3),
869 PINMUX_IPSR_GPSR(IP1SR1_23_20, A13),
871 PINMUX_IPSR_GPSR(IP1SR1_27_24, MSIOF1_SCK),
872 PINMUX_IPSR_GPSR(IP1SR1_27_24, HSCK3),
873 PINMUX_IPSR_GPSR(IP1SR1_27_24, CTS3_N),
874 PINMUX_IPSR_GPSR(IP1SR1_27_24, DU_DG4),
875 PINMUX_IPSR_GPSR(IP1SR1_27_24, A14),
877 PINMUX_IPSR_GPSR(IP1SR1_31_28, MSIOF1_SYNC),
878 PINMUX_IPSR_GPSR(IP1SR1_31_28, HRTS3_N),
879 PINMUX_IPSR_GPSR(IP1SR1_31_28, RTS3_N),
880 PINMUX_IPSR_GPSR(IP1SR1_31_28, DU_DG5),
881 PINMUX_IPSR_GPSR(IP1SR1_31_28, A15),
884 PINMUX_IPSR_GPSR(IP2SR1_3_0, MSIOF1_SS1),
885 PINMUX_IPSR_GPSR(IP2SR1_3_0, HCTS3_N),
886 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX3),
887 PINMUX_IPSR_GPSR(IP2SR1_3_0, DU_DG6),
888 PINMUX_IPSR_GPSR(IP2SR1_3_0, A16),
890 PINMUX_IPSR_GPSR(IP2SR1_7_4, MSIOF1_SS2),
891 PINMUX_IPSR_GPSR(IP2SR1_7_4, HTX3),
892 PINMUX_IPSR_GPSR(IP2SR1_7_4, TX3),
893 PINMUX_IPSR_GPSR(IP2SR1_7_4, DU_DG7),
894 PINMUX_IPSR_GPSR(IP2SR1_7_4, A17),
896 PINMUX_IPSR_GPSR(IP2SR1_11_8, MSIOF2_RXD),
897 PINMUX_IPSR_GPSR(IP2SR1_11_8, HSCK1),
898 PINMUX_IPSR_GPSR(IP2SR1_11_8, SCK1),
899 PINMUX_IPSR_GPSR(IP2SR1_11_8, DU_DB2),
900 PINMUX_IPSR_GPSR(IP2SR1_11_8, A18),
902 PINMUX_IPSR_GPSR(IP2SR1_15_12, MSIOF2_TXD),
903 PINMUX_IPSR_GPSR(IP2SR1_15_12, HCTS1_N),
904 PINMUX_IPSR_GPSR(IP2SR1_15_12, CTS1_N),
905 PINMUX_IPSR_GPSR(IP2SR1_15_12, DU_DB3),
906 PINMUX_IPSR_GPSR(IP2SR1_15_12, A19),
908 PINMUX_IPSR_GPSR(IP2SR1_19_16, MSIOF2_SCK),
909 PINMUX_IPSR_GPSR(IP2SR1_19_16, HRTS1_N),
910 PINMUX_IPSR_GPSR(IP2SR1_19_16, RTS1_N),
911 PINMUX_IPSR_GPSR(IP2SR1_19_16, DU_DB4),
912 PINMUX_IPSR_GPSR(IP2SR1_19_16, A20),
914 PINMUX_IPSR_GPSR(IP2SR1_23_20, MSIOF2_SYNC),
915 PINMUX_IPSR_GPSR(IP2SR1_23_20, HRX1),
916 PINMUX_IPSR_GPSR(IP2SR1_23_20, RX1_A),
917 PINMUX_IPSR_GPSR(IP2SR1_23_20, DU_DB5),
918 PINMUX_IPSR_GPSR(IP2SR1_23_20, A21),
920 PINMUX_IPSR_GPSR(IP2SR1_27_24, MSIOF2_SS1),
921 PINMUX_IPSR_GPSR(IP2SR1_27_24, HTX1),
922 PINMUX_IPSR_GPSR(IP2SR1_27_24, TX1_A),
923 PINMUX_IPSR_GPSR(IP2SR1_27_24, DU_DB6),
924 PINMUX_IPSR_GPSR(IP2SR1_27_24, A22),
926 PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF2_SS2),
927 PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK1_B),
928 PINMUX_IPSR_GPSR(IP2SR1_31_28, DU_DB7),
929 PINMUX_IPSR_GPSR(IP2SR1_31_28, A23),
932 PINMUX_IPSR_GPSR(IP3SR1_3_0, IRQ0),
933 PINMUX_IPSR_GPSR(IP3SR1_3_0, DU_DOTCLKOUT),
934 PINMUX_IPSR_GPSR(IP3SR1_3_0, A24),
936 PINMUX_IPSR_GPSR(IP3SR1_7_4, IRQ1),
937 PINMUX_IPSR_GPSR(IP3SR1_7_4, DU_HSYNC),
938 PINMUX_IPSR_GPSR(IP3SR1_7_4, A25),
940 PINMUX_IPSR_GPSR(IP3SR1_11_8, IRQ2),
941 PINMUX_IPSR_GPSR(IP3SR1_11_8, DU_VSYNC),
942 PINMUX_IPSR_GPSR(IP3SR1_11_8, CS1_N_A26),
944 PINMUX_IPSR_GPSR(IP3SR1_15_12, IRQ3),
945 PINMUX_IPSR_GPSR(IP3SR1_15_12, DU_ODDF_DISP_CDE),
946 PINMUX_IPSR_GPSR(IP3SR1_15_12, CS0_N),
948 PINMUX_IPSR_GPSR(IP3SR1_19_16, GP1_28),
949 PINMUX_IPSR_GPSR(IP3SR1_19_16, D0),
951 PINMUX_IPSR_GPSR(IP3SR1_23_20, GP1_29),
952 PINMUX_IPSR_GPSR(IP3SR1_23_20, D1),
954 PINMUX_IPSR_GPSR(IP3SR1_27_24, GP1_30),
955 PINMUX_IPSR_GPSR(IP3SR1_27_24, D2),
958 PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKIN),
959 PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKEN_IN),
960 PINMUX_IPSR_GPSR(IP0SR2_3_0, DU_DOTCLKIN),
962 PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKOUT),
963 PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKEN_OUT),
966 PINMUX_IPSR_MSEL(IP0SR2_11_8, GP2_02, SEL_I2C0_0),
967 PINMUX_IPSR_MSEL(IP0SR2_11_8, D3, SEL_I2C0_0),
968 PINMUX_IPSR_PHYS(IP0SR2_11_8, SCL0, SEL_I2C0_3),
971 PINMUX_IPSR_MSEL(IP0SR2_15_12, GP2_03, SEL_I2C0_0),
972 PINMUX_IPSR_MSEL(IP0SR2_15_12, D4, SEL_I2C0_0),
973 PINMUX_IPSR_PHYS(IP0SR2_15_12, SDA0, SEL_I2C0_3),
976 PINMUX_IPSR_MSEL(IP0SR2_19_16, GP2_04, SEL_I2C1_0),
977 PINMUX_IPSR_MSEL(IP0SR2_19_16, MSIOF4_RXD, SEL_I2C1_0),
978 PINMUX_IPSR_MSEL(IP0SR2_19_16, D5, SEL_I2C1_0),
979 PINMUX_IPSR_PHYS(IP0SR2_19_16, SCL1, SEL_I2C1_3),
982 PINMUX_IPSR_MSEL(IP0SR2_23_20, GP2_05, SEL_I2C1_0),
983 PINMUX_IPSR_MSEL(IP0SR2_23_20, HSCK2, SEL_I2C1_0),
984 PINMUX_IPSR_MSEL(IP0SR2_23_20, MSIOF4_TXD, SEL_I2C1_0),
985 PINMUX_IPSR_MSEL(IP0SR2_23_20, SCK4, SEL_I2C1_0),
986 PINMUX_IPSR_MSEL(IP0SR2_23_20, D6, SEL_I2C1_0),
987 PINMUX_IPSR_PHYS(IP0SR2_23_20, SDA1, SEL_I2C1_3),
990 PINMUX_IPSR_MSEL(IP0SR2_27_24, GP2_06, SEL_I2C2_0),
991 PINMUX_IPSR_MSEL(IP0SR2_27_24, HCTS2_N, SEL_I2C2_0),
992 PINMUX_IPSR_MSEL(IP0SR2_27_24, MSIOF4_SCK, SEL_I2C2_0),
993 PINMUX_IPSR_MSEL(IP0SR2_27_24, CTS4_N, SEL_I2C2_0),
994 PINMUX_IPSR_MSEL(IP0SR2_27_24, D7, SEL_I2C2_0),
995 PINMUX_IPSR_PHYS(IP0SR2_27_24, SCL2, SEL_I2C2_3),
998 PINMUX_IPSR_MSEL(IP0SR2_31_28, GP2_07, SEL_I2C2_0),
999 PINMUX_IPSR_MSEL(IP0SR2_31_28, HRTS2_N, SEL_I2C2_0),
1000 PINMUX_IPSR_MSEL(IP0SR2_31_28, MSIOF4_SYNC, SEL_I2C2_0),
1001 PINMUX_IPSR_MSEL(IP0SR2_31_28, RTS4_N, SEL_I2C2_0),
1002 PINMUX_IPSR_MSEL(IP0SR2_31_28, D8, SEL_I2C2_0),
1003 PINMUX_IPSR_PHYS(IP0SR2_31_28, SDA2, SEL_I2C2_3),
1006 PINMUX_IPSR_MSEL(IP1SR2_3_0, GP2_08, SEL_I2C3_0),
1007 PINMUX_IPSR_MSEL(IP1SR2_3_0, HRX2, SEL_I2C3_0),
1008 PINMUX_IPSR_MSEL(IP1SR2_3_0, MSIOF4_SS1, SEL_I2C3_0),
1009 PINMUX_IPSR_MSEL(IP1SR2_3_0, RX4, SEL_I2C3_0),
1010 PINMUX_IPSR_MSEL(IP1SR2_3_0, D9, SEL_I2C3_0),
1011 PINMUX_IPSR_PHYS(IP1SR2_3_0, SCL3, SEL_I2C3_3),
1014 PINMUX_IPSR_MSEL(IP1SR2_7_4, GP2_09, SEL_I2C3_0),
1015 PINMUX_IPSR_MSEL(IP1SR2_7_4, HTX2, SEL_I2C3_0),
1016 PINMUX_IPSR_MSEL(IP1SR2_7_4, MSIOF4_SS2, SEL_I2C3_0),
1017 PINMUX_IPSR_MSEL(IP1SR2_7_4, TX4, SEL_I2C3_0),
1018 PINMUX_IPSR_MSEL(IP1SR2_7_4, D10, SEL_I2C3_0),
1019 PINMUX_IPSR_PHYS(IP1SR2_7_4, SDA3, SEL_I2C3_3),
1022 PINMUX_IPSR_MSEL(IP1SR2_11_8, GP2_10, SEL_I2C4_0),
1023 PINMUX_IPSR_MSEL(IP1SR2_11_8, TCLK2_B, SEL_I2C4_0),
1024 PINMUX_IPSR_MSEL(IP1SR2_11_8, MSIOF5_RXD, SEL_I2C4_0),
1025 PINMUX_IPSR_MSEL(IP1SR2_11_8, D11, SEL_I2C4_0),
1026 PINMUX_IPSR_PHYS(IP1SR2_11_8, SCL4, SEL_I2C4_3),
1029 PINMUX_IPSR_MSEL(IP1SR2_15_12, GP2_11, SEL_I2C4_0),
1030 PINMUX_IPSR_MSEL(IP1SR2_15_12, TCLK3, SEL_I2C4_0),
1031 PINMUX_IPSR_MSEL(IP1SR2_15_12, MSIOF5_TXD, SEL_I2C4_0),
1032 PINMUX_IPSR_MSEL(IP1SR2_15_12, D12, SEL_I2C4_0),
1033 PINMUX_IPSR_PHYS(IP1SR2_15_12, SDA4, SEL_I2C4_3),
1036 PINMUX_IPSR_MSEL(IP1SR2_19_16, GP2_12, SEL_I2C5_0),
1037 PINMUX_IPSR_MSEL(IP1SR2_19_16, TCLK4, SEL_I2C5_0),
1038 PINMUX_IPSR_MSEL(IP1SR2_19_16, MSIOF5_SCK, SEL_I2C5_0),
1039 PINMUX_IPSR_MSEL(IP1SR2_19_16, D13, SEL_I2C5_0),
1040 PINMUX_IPSR_PHYS(IP1SR2_19_16, SCL5, SEL_I2C5_3),
1043 PINMUX_IPSR_MSEL(IP1SR2_23_20, GP2_13, SEL_I2C5_0),
1044 PINMUX_IPSR_MSEL(IP1SR2_23_20, MSIOF5_SYNC, SEL_I2C5_0),
1045 PINMUX_IPSR_MSEL(IP1SR2_23_20, D14, SEL_I2C5_0),
1046 PINMUX_IPSR_PHYS(IP1SR2_23_20, SDA5, SEL_I2C5_3),
1049 PINMUX_IPSR_MSEL(IP1SR2_27_24, GP2_14, SEL_I2C6_0),
1050 PINMUX_IPSR_MSEL(IP1SR2_27_24, IRQ4, SEL_I2C6_0),
1051 PINMUX_IPSR_MSEL(IP1SR2_27_24, MSIOF5_SS1, SEL_I2C6_0),
1052 PINMUX_IPSR_MSEL(IP1SR2_27_24, D15, SEL_I2C6_0),
1053 PINMUX_IPSR_PHYS(IP1SR2_27_24, SCL6, SEL_I2C6_3),
1056 PINMUX_IPSR_MSEL(IP1SR2_31_28, GP2_15, SEL_I2C6_0),
1057 PINMUX_IPSR_MSEL(IP1SR2_31_28, IRQ5, SEL_I2C6_0),
1058 PINMUX_IPSR_MSEL(IP1SR2_31_28, MSIOF5_SS2, SEL_I2C6_0),
1059 PINMUX_IPSR_MSEL(IP1SR2_31_28, CPG_CPCKOUT, SEL_I2C6_0),
1060 PINMUX_IPSR_PHYS(IP1SR2_31_28, SDA6, SEL_I2C6_3),
1063 PINMUX_IPSR_GPSR(IP2SR2_3_0, FXR_TXDA_A),
1064 PINMUX_IPSR_GPSR(IP2SR2_3_0, MSIOF3_SS1),
1066 PINMUX_IPSR_GPSR(IP2SR2_7_4, RXDA_EXTFXR_A),
1067 PINMUX_IPSR_GPSR(IP2SR2_7_4, MSIOF3_SS2),
1068 PINMUX_IPSR_GPSR(IP2SR2_7_4, BS_N),
1070 PINMUX_IPSR_GPSR(IP2SR2_11_8, FXR_TXDB),
1071 PINMUX_IPSR_GPSR(IP2SR2_11_8, MSIOF3_RXD),
1072 PINMUX_IPSR_GPSR(IP2SR2_11_8, RD_N),
1074 PINMUX_IPSR_GPSR(IP2SR2_15_12, RXDB_EXTFXR),
1075 PINMUX_IPSR_GPSR(IP2SR2_15_12, MSIOF3_TXD),
1076 PINMUX_IPSR_GPSR(IP2SR2_15_12, WE0_N),
1078 PINMUX_IPSR_GPSR(IP2SR2_19_16, CLK_EXTFXR),
1079 PINMUX_IPSR_GPSR(IP2SR2_19_16, MSIOF3_SCK),
1080 PINMUX_IPSR_GPSR(IP2SR2_19_16, WE1_N),
1082 PINMUX_IPSR_GPSR(IP2SR2_23_20, TPU0TO0),
1083 PINMUX_IPSR_GPSR(IP2SR2_23_20, MSIOF3_SYNC),
1084 PINMUX_IPSR_GPSR(IP2SR2_23_20, RD_WR_N),
1086 PINMUX_IPSR_GPSR(IP2SR2_27_24, TPU0TO1),
1087 PINMUX_IPSR_GPSR(IP2SR2_27_24, CLKOUT),
1089 PINMUX_IPSR_GPSR(IP2SR2_31_28, TCLK1_A),
1090 PINMUX_IPSR_GPSR(IP2SR2_31_28, EX_WAIT0),
1093 PINMUX_IPSR_GPSR(IP0SR3_7_4, CANFD0_TX),
1094 PINMUX_IPSR_GPSR(IP0SR3_7_4, FXR_TXDA_B),
1095 PINMUX_IPSR_GPSR(IP0SR3_7_4, TX1_B),
1097 PINMUX_IPSR_GPSR(IP0SR3_11_8, CANFD0_RX),
1098 PINMUX_IPSR_GPSR(IP0SR3_11_8, RXDA_EXTFXR_B),
1099 PINMUX_IPSR_GPSR(IP0SR3_11_8, RX1_B),
1101 PINMUX_IPSR_GPSR(IP0SR3_23_20, CANFD2_TX),
1102 PINMUX_IPSR_GPSR(IP0SR3_23_20, TPU0TO2),
1103 PINMUX_IPSR_GPSR(IP0SR3_23_20, PWM0),
1105 PINMUX_IPSR_GPSR(IP0SR3_27_24, CANFD2_RX),
1106 PINMUX_IPSR_GPSR(IP0SR3_27_24, TPU0TO3),
1107 PINMUX_IPSR_GPSR(IP0SR3_27_24, PWM1),
1109 PINMUX_IPSR_GPSR(IP0SR3_31_28, CANFD3_TX),
1110 PINMUX_IPSR_GPSR(IP0SR3_31_28, PWM2),
1113 PINMUX_IPSR_GPSR(IP1SR3_3_0, CANFD3_RX),
1114 PINMUX_IPSR_GPSR(IP1SR3_3_0, PWM3),
1116 PINMUX_IPSR_GPSR(IP1SR3_7_4, CANFD4_TX),
1117 PINMUX_IPSR_GPSR(IP1SR3_7_4, PWM4),
1118 PINMUX_IPSR_GPSR(IP1SR3_7_4, FXR_CLKOUT1),
1120 PINMUX_IPSR_GPSR(IP1SR3_11_8, CANFD4_RX),
1121 PINMUX_IPSR_GPSR(IP1SR3_11_8, FXR_CLKOUT2),
1123 PINMUX_IPSR_GPSR(IP1SR3_15_12, CANFD5_TX),
1124 PINMUX_IPSR_GPSR(IP1SR3_15_12, FXR_TXENA_N),
1126 PINMUX_IPSR_GPSR(IP1SR3_19_16, CANFD5_RX),
1127 PINMUX_IPSR_GPSR(IP1SR3_19_16, FXR_TXENB_N),
1129 PINMUX_IPSR_GPSR(IP1SR3_23_20, CANFD6_TX),
1130 PINMUX_IPSR_GPSR(IP1SR3_23_20, STPWT_EXTFXR),
1133 PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_RX_CTL),
1134 PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_MII_RX_DV),
1136 PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_RXC),
1137 PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_MII_RXC),
1139 PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_RD0),
1140 PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_MII_RD0),
1142 PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_RD1),
1143 PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_MII_RD1),
1145 PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_RD2),
1146 PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_MII_RD2),
1148 PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_RD3),
1149 PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_MII_RD3),
1151 PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_TX_CTL),
1152 PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_MII_TX_EN),
1154 PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_TXC),
1155 PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_MII_TXC),
1158 PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_TD0),
1159 PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_MII_TD0),
1161 PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_TD1),
1162 PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_MII_TD1),
1164 PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_TD2),
1165 PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_MII_TD2),
1167 PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_TD3),
1168 PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_MII_TD3),
1170 PINMUX_IPSR_GPSR(IP1SR4_19_16, AVB0_TXCREFCLK),
1172 PINMUX_IPSR_GPSR(IP1SR4_23_20, AVB0_MDIO),
1174 PINMUX_IPSR_GPSR(IP1SR4_27_24, AVB0_MDC),
1176 PINMUX_IPSR_GPSR(IP1SR4_31_28, AVB0_MAGIC),
1179 PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_LINK),
1180 PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_MII_TX_ER),
1182 PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_AVTP_MATCH),
1183 PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_MII_RX_ER),
1184 PINMUX_IPSR_GPSR(IP2SR4_11_8, CC5_OSCOUT),
1186 PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_AVTP_CAPTURE),
1187 PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_MII_CRS),
1189 PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_AVTP_PPS),
1190 PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_MII_COL),
1193 PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_RX_CTL),
1194 PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_MII_RX_DV),
1196 PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_RXC),
1197 PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_MII_RXC),
1199 PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_RD0),
1200 PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_MII_RD0),
1202 PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_RD1),
1203 PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_MII_RD1),
1205 PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_RD2),
1206 PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_MII_RD2),
1208 PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_RD3),
1209 PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_MII_RD3),
1211 PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_TX_CTL),
1212 PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_MII_TX_EN),
1214 PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_TXC),
1215 PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_MII_TXC),
1218 PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_TD0),
1219 PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_MII_TD0),
1221 PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_TD1),
1222 PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_MII_TD1),
1224 PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_TD2),
1225 PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_MII_TD2),
1227 PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_TD3),
1228 PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_MII_TD3),
1230 PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB1_TXCREFCLK),
1232 PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB1_MDIO),
1234 PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB1_MDC),
1236 PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB1_MAGIC),
1239 PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_LINK),
1240 PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_MII_TX_ER),
1242 PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_AVTP_MATCH),
1243 PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_MII_RX_ER),
1245 PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_AVTP_CAPTURE),
1246 PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_MII_CRS),
1248 PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_AVTP_PPS),
1249 PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_MII_COL),
1253 * Pins not associated with a GPIO port.
1260 static const struct sh_pfc_pin pinmux_pins[] = {
1261 PINMUX_GPIO_GP_ALL(),
1264 /* - AVB0 ------------------------------------------------ */
1265 static const unsigned int avb0_link_pins[] = {
1269 static const unsigned int avb0_link_mux[] = {
1272 static const unsigned int avb0_magic_pins[] = {
1276 static const unsigned int avb0_magic_mux[] = {
1279 static const unsigned int avb0_phy_int_pins[] = {
1283 static const unsigned int avb0_phy_int_mux[] = {
1286 static const unsigned int avb0_mdio_pins[] = {
1287 /* AVB0_MDC, AVB0_MDIO */
1288 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1290 static const unsigned int avb0_mdio_mux[] = {
1291 AVB0_MDC_MARK, AVB0_MDIO_MARK,
1293 static const unsigned int avb0_rgmii_pins[] = {
1295 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
1296 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
1298 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1299 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1300 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1301 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1302 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1303 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1305 static const unsigned int avb0_rgmii_mux[] = {
1306 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
1307 AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
1308 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
1309 AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
1311 static const unsigned int avb0_txcrefclk_pins[] = {
1312 /* AVB0_TXCREFCLK */
1315 static const unsigned int avb0_txcrefclk_mux[] = {
1316 AVB0_TXCREFCLK_MARK,
1318 static const unsigned int avb0_avtp_pps_pins[] = {
1322 static const unsigned int avb0_avtp_pps_mux[] = {
1325 static const unsigned int avb0_avtp_capture_pins[] = {
1326 /* AVB0_AVTP_CAPTURE */
1329 static const unsigned int avb0_avtp_capture_mux[] = {
1330 AVB0_AVTP_CAPTURE_MARK,
1332 static const unsigned int avb0_avtp_match_pins[] = {
1333 /* AVB0_AVTP_MATCH */
1336 static const unsigned int avb0_avtp_match_mux[] = {
1337 AVB0_AVTP_MATCH_MARK,
1340 /* - AVB1 ------------------------------------------------ */
1341 static const unsigned int avb1_link_pins[] = {
1345 static const unsigned int avb1_link_mux[] = {
1348 static const unsigned int avb1_magic_pins[] = {
1352 static const unsigned int avb1_magic_mux[] = {
1355 static const unsigned int avb1_phy_int_pins[] = {
1359 static const unsigned int avb1_phy_int_mux[] = {
1362 static const unsigned int avb1_mdio_pins[] = {
1363 /* AVB1_MDC, AVB1_MDIO */
1364 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 13),
1366 static const unsigned int avb1_mdio_mux[] = {
1367 AVB1_MDC_MARK, AVB1_MDIO_MARK,
1369 static const unsigned int avb1_rgmii_pins[] = {
1371 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
1372 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
1374 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1375 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1376 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1377 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
1378 RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1379 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1381 static const unsigned int avb1_rgmii_mux[] = {
1382 AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
1383 AVB1_TD0_MARK, AVB1_TD1_MARK, AVB1_TD2_MARK, AVB1_TD3_MARK,
1384 AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
1385 AVB1_RD0_MARK, AVB1_RD1_MARK, AVB1_RD2_MARK, AVB1_RD3_MARK,
1387 static const unsigned int avb1_txcrefclk_pins[] = {
1388 /* AVB1_TXCREFCLK */
1391 static const unsigned int avb1_txcrefclk_mux[] = {
1392 AVB1_TXCREFCLK_MARK,
1394 static const unsigned int avb1_avtp_pps_pins[] = {
1398 static const unsigned int avb1_avtp_pps_mux[] = {
1401 static const unsigned int avb1_avtp_capture_pins[] = {
1402 /* AVB1_AVTP_CAPTURE */
1405 static const unsigned int avb1_avtp_capture_mux[] = {
1406 AVB1_AVTP_CAPTURE_MARK,
1408 static const unsigned int avb1_avtp_match_pins[] = {
1409 /* AVB1_AVTP_MATCH */
1412 static const unsigned int avb1_avtp_match_mux[] = {
1413 AVB1_AVTP_MATCH_MARK,
1416 /* - AVB2 ------------------------------------------------ */
1417 static const unsigned int avb2_link_pins[] = {
1421 static const unsigned int avb2_link_mux[] = {
1424 static const unsigned int avb2_magic_pins[] = {
1428 static const unsigned int avb2_magic_mux[] = {
1431 static const unsigned int avb2_phy_int_pins[] = {
1435 static const unsigned int avb2_phy_int_mux[] = {
1438 static const unsigned int avb2_mdio_pins[] = {
1439 /* AVB2_MDC, AVB2_MDIO */
1440 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 13),
1442 static const unsigned int avb2_mdio_mux[] = {
1443 AVB2_MDC_MARK, AVB2_MDIO_MARK,
1445 static const unsigned int avb2_rgmii_pins[] = {
1447 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
1448 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
1450 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1451 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1452 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1453 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
1454 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1455 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1457 static const unsigned int avb2_rgmii_mux[] = {
1458 AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
1459 AVB2_TD0_MARK, AVB2_TD1_MARK, AVB2_TD2_MARK, AVB2_TD3_MARK,
1460 AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
1461 AVB2_RD0_MARK, AVB2_RD1_MARK, AVB2_RD2_MARK, AVB2_RD3_MARK,
1463 static const unsigned int avb2_txcrefclk_pins[] = {
1464 /* AVB2_TXCREFCLK */
1467 static const unsigned int avb2_txcrefclk_mux[] = {
1468 AVB2_TXCREFCLK_MARK,
1470 static const unsigned int avb2_avtp_pps_pins[] = {
1474 static const unsigned int avb2_avtp_pps_mux[] = {
1477 static const unsigned int avb2_avtp_capture_pins[] = {
1478 /* AVB2_AVTP_CAPTURE */
1481 static const unsigned int avb2_avtp_capture_mux[] = {
1482 AVB2_AVTP_CAPTURE_MARK,
1484 static const unsigned int avb2_avtp_match_pins[] = {
1485 /* AVB2_AVTP_MATCH */
1488 static const unsigned int avb2_avtp_match_mux[] = {
1489 AVB2_AVTP_MATCH_MARK,
1492 /* - AVB3 ------------------------------------------------ */
1493 static const unsigned int avb3_link_pins[] = {
1497 static const unsigned int avb3_link_mux[] = {
1500 static const unsigned int avb3_magic_pins[] = {
1504 static const unsigned int avb3_magic_mux[] = {
1507 static const unsigned int avb3_phy_int_pins[] = {
1511 static const unsigned int avb3_phy_int_mux[] = {
1514 static const unsigned int avb3_mdio_pins[] = {
1515 /* AVB3_MDC, AVB3_MDIO */
1516 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 13),
1518 static const unsigned int avb3_mdio_mux[] = {
1519 AVB3_MDC_MARK, AVB3_MDIO_MARK,
1521 static const unsigned int avb3_rgmii_pins[] = {
1523 * AVB3_TX_CTL, AVB3_TXC, AVB3_TD0, AVB3_TD1, AVB3_TD2, AVB3_TD3,
1524 * AVB3_RX_CTL, AVB3_RXC, AVB3_RD0, AVB3_RD1, AVB3_RD2, AVB3_RD3,
1526 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1527 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1528 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1529 RCAR_GP_PIN(7, 0), RCAR_GP_PIN(7, 1),
1530 RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1531 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1533 static const unsigned int avb3_rgmii_mux[] = {
1534 AVB3_TX_CTL_MARK, AVB3_TXC_MARK,
1535 AVB3_TD0_MARK, AVB3_TD1_MARK, AVB3_TD2_MARK, AVB3_TD3_MARK,
1536 AVB3_RX_CTL_MARK, AVB3_RXC_MARK,
1537 AVB3_RD0_MARK, AVB3_RD1_MARK, AVB3_RD2_MARK, AVB3_RD3_MARK,
1539 static const unsigned int avb3_txcrefclk_pins[] = {
1540 /* AVB3_TXCREFCLK */
1543 static const unsigned int avb3_txcrefclk_mux[] = {
1544 AVB3_TXCREFCLK_MARK,
1546 static const unsigned int avb3_avtp_pps_pins[] = {
1550 static const unsigned int avb3_avtp_pps_mux[] = {
1553 static const unsigned int avb3_avtp_capture_pins[] = {
1554 /* AVB3_AVTP_CAPTURE */
1557 static const unsigned int avb3_avtp_capture_mux[] = {
1558 AVB3_AVTP_CAPTURE_MARK,
1560 static const unsigned int avb3_avtp_match_pins[] = {
1561 /* AVB3_AVTP_MATCH */
1564 static const unsigned int avb3_avtp_match_mux[] = {
1565 AVB3_AVTP_MATCH_MARK,
1568 /* - AVB4 ------------------------------------------------ */
1569 static const unsigned int avb4_link_pins[] = {
1573 static const unsigned int avb4_link_mux[] = {
1576 static const unsigned int avb4_magic_pins[] = {
1580 static const unsigned int avb4_magic_mux[] = {
1583 static const unsigned int avb4_phy_int_pins[] = {
1587 static const unsigned int avb4_phy_int_mux[] = {
1590 static const unsigned int avb4_mdio_pins[] = {
1591 /* AVB4_MDC, AVB4_MDIO */
1592 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 13),
1594 static const unsigned int avb4_mdio_mux[] = {
1595 AVB4_MDC_MARK, AVB4_MDIO_MARK,
1597 static const unsigned int avb4_rgmii_pins[] = {
1599 * AVB4_TX_CTL, AVB4_TXC, AVB4_TD0, AVB4_TD1, AVB4_TD2, AVB4_TD3,
1600 * AVB4_RX_CTL, AVB4_RXC, AVB4_RD0, AVB4_RD1, AVB4_RD2, AVB4_RD3,
1602 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1603 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1604 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1605 RCAR_GP_PIN(8, 0), RCAR_GP_PIN(8, 1),
1606 RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1607 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1609 static const unsigned int avb4_rgmii_mux[] = {
1610 AVB4_TX_CTL_MARK, AVB4_TXC_MARK,
1611 AVB4_TD0_MARK, AVB4_TD1_MARK, AVB4_TD2_MARK, AVB4_TD3_MARK,
1612 AVB4_RX_CTL_MARK, AVB4_RXC_MARK,
1613 AVB4_RD0_MARK, AVB4_RD1_MARK, AVB4_RD2_MARK, AVB4_RD3_MARK,
1615 static const unsigned int avb4_txcrefclk_pins[] = {
1616 /* AVB4_TXCREFCLK */
1619 static const unsigned int avb4_txcrefclk_mux[] = {
1620 AVB4_TXCREFCLK_MARK,
1622 static const unsigned int avb4_avtp_pps_pins[] = {
1626 static const unsigned int avb4_avtp_pps_mux[] = {
1629 static const unsigned int avb4_avtp_capture_pins[] = {
1630 /* AVB4_AVTP_CAPTURE */
1633 static const unsigned int avb4_avtp_capture_mux[] = {
1634 AVB4_AVTP_CAPTURE_MARK,
1636 static const unsigned int avb4_avtp_match_pins[] = {
1637 /* AVB4_AVTP_MATCH */
1640 static const unsigned int avb4_avtp_match_mux[] = {
1641 AVB4_AVTP_MATCH_MARK,
1644 /* - AVB5 ------------------------------------------------ */
1645 static const unsigned int avb5_link_pins[] = {
1649 static const unsigned int avb5_link_mux[] = {
1652 static const unsigned int avb5_magic_pins[] = {
1656 static const unsigned int avb5_magic_mux[] = {
1659 static const unsigned int avb5_phy_int_pins[] = {
1663 static const unsigned int avb5_phy_int_mux[] = {
1666 static const unsigned int avb5_mdio_pins[] = {
1667 /* AVB5_MDC, AVB5_MDIO */
1668 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 13),
1670 static const unsigned int avb5_mdio_mux[] = {
1671 AVB5_MDC_MARK, AVB5_MDIO_MARK,
1673 static const unsigned int avb5_rgmii_pins[] = {
1675 * AVB5_TX_CTL, AVB5_TXC, AVB5_TD0, AVB5_TD1, AVB5_TD2, AVB5_TD3,
1676 * AVB5_RX_CTL, AVB5_RXC, AVB5_RD0, AVB5_RD1, AVB5_RD2, AVB5_RD3,
1678 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1679 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1680 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1681 RCAR_GP_PIN(9, 0), RCAR_GP_PIN(9, 1),
1682 RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1683 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1685 static const unsigned int avb5_rgmii_mux[] = {
1686 AVB5_TX_CTL_MARK, AVB5_TXC_MARK,
1687 AVB5_TD0_MARK, AVB5_TD1_MARK, AVB5_TD2_MARK, AVB5_TD3_MARK,
1688 AVB5_RX_CTL_MARK, AVB5_RXC_MARK,
1689 AVB5_RD0_MARK, AVB5_RD1_MARK, AVB5_RD2_MARK, AVB5_RD3_MARK,
1691 static const unsigned int avb5_txcrefclk_pins[] = {
1692 /* AVB5_TXCREFCLK */
1695 static const unsigned int avb5_txcrefclk_mux[] = {
1696 AVB5_TXCREFCLK_MARK,
1698 static const unsigned int avb5_avtp_pps_pins[] = {
1702 static const unsigned int avb5_avtp_pps_mux[] = {
1705 static const unsigned int avb5_avtp_capture_pins[] = {
1706 /* AVB5_AVTP_CAPTURE */
1709 static const unsigned int avb5_avtp_capture_mux[] = {
1710 AVB5_AVTP_CAPTURE_MARK,
1712 static const unsigned int avb5_avtp_match_pins[] = {
1713 /* AVB5_AVTP_MATCH */
1716 static const unsigned int avb5_avtp_match_mux[] = {
1717 AVB5_AVTP_MATCH_MARK,
1720 /* - CANFD0 ----------------------------------------------------------------- */
1721 static const unsigned int canfd0_data_pins[] = {
1722 /* CANFD0_TX, CANFD0_RX */
1723 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
1725 static const unsigned int canfd0_data_mux[] = {
1726 CANFD0_TX_MARK, CANFD0_RX_MARK,
1729 /* - CANFD1 ----------------------------------------------------------------- */
1730 static const unsigned int canfd1_data_pins[] = {
1731 /* CANFD1_TX, CANFD1_RX */
1732 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1734 static const unsigned int canfd1_data_mux[] = {
1735 CANFD1_TX_MARK, CANFD1_RX_MARK,
1738 /* - CANFD2 ----------------------------------------------------------------- */
1739 static const unsigned int canfd2_data_pins[] = {
1740 /* CANFD2_TX, CANFD2_RX */
1741 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
1743 static const unsigned int canfd2_data_mux[] = {
1744 CANFD2_TX_MARK, CANFD2_RX_MARK,
1747 /* - CANFD3 ----------------------------------------------------------------- */
1748 static const unsigned int canfd3_data_pins[] = {
1749 /* CANFD3_TX, CANFD3_RX */
1750 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
1752 static const unsigned int canfd3_data_mux[] = {
1753 CANFD3_TX_MARK, CANFD3_RX_MARK,
1756 /* - CANFD4 ----------------------------------------------------------------- */
1757 static const unsigned int canfd4_data_pins[] = {
1758 /* CANFD4_TX, CANFD4_RX */
1759 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1761 static const unsigned int canfd4_data_mux[] = {
1762 CANFD4_TX_MARK, CANFD4_RX_MARK,
1765 /* - CANFD5 ----------------------------------------------------------------- */
1766 static const unsigned int canfd5_data_pins[] = {
1767 /* CANFD5_TX, CANFD5_RX */
1768 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1770 static const unsigned int canfd5_data_mux[] = {
1771 CANFD5_TX_MARK, CANFD5_RX_MARK,
1774 /* - CANFD6 ----------------------------------------------------------------- */
1775 static const unsigned int canfd6_data_pins[] = {
1776 /* CANFD6_TX, CANFD6_RX */
1777 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1779 static const unsigned int canfd6_data_mux[] = {
1780 CANFD6_TX_MARK, CANFD6_RX_MARK,
1783 /* - CANFD7 ----------------------------------------------------------------- */
1784 static const unsigned int canfd7_data_pins[] = {
1785 /* CANFD7_TX, CANFD7_RX */
1786 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1788 static const unsigned int canfd7_data_mux[] = {
1789 CANFD7_TX_MARK, CANFD7_RX_MARK,
1792 /* - CANFD Clock ------------------------------------------------------------ */
1793 static const unsigned int can_clk_pins[] = {
1797 static const unsigned int can_clk_mux[] = {
1801 /* - DU --------------------------------------------------------------------- */
1802 static const unsigned int du_rgb888_pins[] = {
1803 /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
1804 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
1805 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1806 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
1807 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
1808 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1809 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1811 static const unsigned int du_rgb888_mux[] = {
1812 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
1813 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
1814 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
1815 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
1816 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
1817 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
1819 static const unsigned int du_clk_out_pins[] = {
1823 static const unsigned int du_clk_out_mux[] = {
1826 static const unsigned int du_sync_pins[] = {
1827 /* DU_HSYNC, DU_VSYNC */
1828 RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 26),
1830 static const unsigned int du_sync_mux[] = {
1831 DU_HSYNC_MARK, DU_VSYNC_MARK,
1833 static const unsigned int du_oddf_pins[] = {
1834 /* DU_EXODDF/DU_ODDF/DISP/CDE */
1837 static const unsigned int du_oddf_mux[] = {
1838 DU_ODDF_DISP_CDE_MARK,
1841 /* - HSCIF0 ----------------------------------------------------------------- */
1842 static const unsigned int hscif0_data_pins[] = {
1844 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),
1846 static const unsigned int hscif0_data_mux[] = {
1847 HRX0_MARK, HTX0_MARK,
1849 static const unsigned int hscif0_clk_pins[] = {
1853 static const unsigned int hscif0_clk_mux[] = {
1856 static const unsigned int hscif0_ctrl_pins[] = {
1857 /* HRTS0#, HCTS0# */
1858 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
1860 static const unsigned int hscif0_ctrl_mux[] = {
1861 HRTS0_N_MARK, HCTS0_N_MARK,
1864 /* - HSCIF1 ----------------------------------------------------------------- */
1865 static const unsigned int hscif1_data_pins[] = {
1867 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
1869 static const unsigned int hscif1_data_mux[] = {
1870 HRX1_MARK, HTX1_MARK,
1872 static const unsigned int hscif1_clk_pins[] = {
1876 static const unsigned int hscif1_clk_mux[] = {
1879 static const unsigned int hscif1_ctrl_pins[] = {
1880 /* HRTS1#, HCTS1# */
1881 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),
1883 static const unsigned int hscif1_ctrl_mux[] = {
1884 HRTS1_N_MARK, HCTS1_N_MARK,
1887 /* - HSCIF2 ----------------------------------------------------------------- */
1888 static const unsigned int hscif2_data_pins[] = {
1890 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1892 static const unsigned int hscif2_data_mux[] = {
1893 HRX2_MARK, HTX2_MARK,
1895 static const unsigned int hscif2_clk_pins[] = {
1899 static const unsigned int hscif2_clk_mux[] = {
1902 static const unsigned int hscif2_ctrl_pins[] = {
1903 /* HRTS2#, HCTS2# */
1904 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
1906 static const unsigned int hscif2_ctrl_mux[] = {
1907 HRTS2_N_MARK, HCTS2_N_MARK,
1910 /* - HSCIF3 ----------------------------------------------------------------- */
1911 static const unsigned int hscif3_data_pins[] = {
1913 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 17),
1915 static const unsigned int hscif3_data_mux[] = {
1916 HRX3_MARK, HTX3_MARK,
1918 static const unsigned int hscif3_clk_pins[] = {
1922 static const unsigned int hscif3_clk_mux[] = {
1925 static const unsigned int hscif3_ctrl_pins[] = {
1926 /* HRTS3#, HCTS3# */
1927 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
1929 static const unsigned int hscif3_ctrl_mux[] = {
1930 HRTS3_N_MARK, HCTS3_N_MARK,
1933 /* - I2C0 ------------------------------------------------------------------- */
1934 static const unsigned int i2c0_pins[] = {
1936 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1938 static const unsigned int i2c0_mux[] = {
1939 SDA0_MARK, SCL0_MARK,
1942 /* - I2C1 ------------------------------------------------------------------- */
1943 static const unsigned int i2c1_pins[] = {
1945 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1947 static const unsigned int i2c1_mux[] = {
1948 SDA1_MARK, SCL1_MARK,
1951 /* - I2C2 ------------------------------------------------------------------- */
1952 static const unsigned int i2c2_pins[] = {
1954 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
1956 static const unsigned int i2c2_mux[] = {
1957 SDA2_MARK, SCL2_MARK,
1960 /* - I2C3 ------------------------------------------------------------------- */
1961 static const unsigned int i2c3_pins[] = {
1963 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
1965 static const unsigned int i2c3_mux[] = {
1966 SDA3_MARK, SCL3_MARK,
1969 /* - I2C4 ------------------------------------------------------------------- */
1970 static const unsigned int i2c4_pins[] = {
1972 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1974 static const unsigned int i2c4_mux[] = {
1975 SDA4_MARK, SCL4_MARK,
1978 /* - I2C5 ------------------------------------------------------------------- */
1979 static const unsigned int i2c5_pins[] = {
1981 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
1983 static const unsigned int i2c5_mux[] = {
1984 SDA5_MARK, SCL5_MARK,
1987 /* - I2C6 ------------------------------------------------------------------- */
1988 static const unsigned int i2c6_pins[] = {
1990 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14),
1992 static const unsigned int i2c6_mux[] = {
1993 SDA6_MARK, SCL6_MARK,
1996 /* - INTC-EX ---------------------------------------------------------------- */
1997 static const unsigned int intc_ex_irq0_pins[] = {
2001 static const unsigned int intc_ex_irq0_mux[] = {
2004 static const unsigned int intc_ex_irq1_pins[] = {
2008 static const unsigned int intc_ex_irq1_mux[] = {
2011 static const unsigned int intc_ex_irq2_pins[] = {
2015 static const unsigned int intc_ex_irq2_mux[] = {
2018 static const unsigned int intc_ex_irq3_pins[] = {
2022 static const unsigned int intc_ex_irq3_mux[] = {
2025 static const unsigned int intc_ex_irq4_pins[] = {
2029 static const unsigned int intc_ex_irq4_mux[] = {
2032 static const unsigned int intc_ex_irq5_pins[] = {
2036 static const unsigned int intc_ex_irq5_mux[] = {
2040 /* - MMC -------------------------------------------------------------------- */
2041 static const unsigned int mmc_data_pins[] = {
2042 /* MMC_SD_D[0:3], MMC_D[4:7] */
2043 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
2044 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
2045 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2046 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27),
2048 static const unsigned int mmc_data_mux[] = {
2049 MMC_SD_D0_MARK, MMC_SD_D1_MARK,
2050 MMC_SD_D2_MARK, MMC_SD_D3_MARK,
2051 MMC_D4_MARK, MMC_D5_MARK,
2052 MMC_D6_MARK, MMC_D7_MARK,
2054 static const unsigned int mmc_ctrl_pins[] = {
2055 /* MMC_SD_CLK, MMC_SD_CMD */
2056 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 18),
2058 static const unsigned int mmc_ctrl_mux[] = {
2059 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
2061 static const unsigned int mmc_cd_pins[] = {
2065 static const unsigned int mmc_cd_mux[] = {
2068 static const unsigned int mmc_wp_pins[] = {
2072 static const unsigned int mmc_wp_mux[] = {
2075 static const unsigned int mmc_ds_pins[] = {
2079 static const unsigned int mmc_ds_mux[] = {
2083 /* - MSIOF0 ----------------------------------------------------------------- */
2084 static const unsigned int msiof0_clk_pins[] = {
2088 static const unsigned int msiof0_clk_mux[] = {
2091 static const unsigned int msiof0_sync_pins[] = {
2095 static const unsigned int msiof0_sync_mux[] = {
2098 static const unsigned int msiof0_ss1_pins[] = {
2102 static const unsigned int msiof0_ss1_mux[] = {
2105 static const unsigned int msiof0_ss2_pins[] = {
2109 static const unsigned int msiof0_ss2_mux[] = {
2112 static const unsigned int msiof0_txd_pins[] = {
2116 static const unsigned int msiof0_txd_mux[] = {
2119 static const unsigned int msiof0_rxd_pins[] = {
2123 static const unsigned int msiof0_rxd_mux[] = {
2127 /* - MSIOF1 ----------------------------------------------------------------- */
2128 static const unsigned int msiof1_clk_pins[] = {
2132 static const unsigned int msiof1_clk_mux[] = {
2135 static const unsigned int msiof1_sync_pins[] = {
2139 static const unsigned int msiof1_sync_mux[] = {
2142 static const unsigned int msiof1_ss1_pins[] = {
2146 static const unsigned int msiof1_ss1_mux[] = {
2149 static const unsigned int msiof1_ss2_pins[] = {
2153 static const unsigned int msiof1_ss2_mux[] = {
2156 static const unsigned int msiof1_txd_pins[] = {
2160 static const unsigned int msiof1_txd_mux[] = {
2163 static const unsigned int msiof1_rxd_pins[] = {
2167 static const unsigned int msiof1_rxd_mux[] = {
2171 /* - MSIOF2 ----------------------------------------------------------------- */
2172 static const unsigned int msiof2_clk_pins[] = {
2176 static const unsigned int msiof2_clk_mux[] = {
2179 static const unsigned int msiof2_sync_pins[] = {
2183 static const unsigned int msiof2_sync_mux[] = {
2186 static const unsigned int msiof2_ss1_pins[] = {
2190 static const unsigned int msiof2_ss1_mux[] = {
2193 static const unsigned int msiof2_ss2_pins[] = {
2197 static const unsigned int msiof2_ss2_mux[] = {
2200 static const unsigned int msiof2_txd_pins[] = {
2204 static const unsigned int msiof2_txd_mux[] = {
2207 static const unsigned int msiof2_rxd_pins[] = {
2211 static const unsigned int msiof2_rxd_mux[] = {
2215 /* - MSIOF3 ----------------------------------------------------------------- */
2216 static const unsigned int msiof3_clk_pins[] = {
2220 static const unsigned int msiof3_clk_mux[] = {
2223 static const unsigned int msiof3_sync_pins[] = {
2227 static const unsigned int msiof3_sync_mux[] = {
2230 static const unsigned int msiof3_ss1_pins[] = {
2234 static const unsigned int msiof3_ss1_mux[] = {
2237 static const unsigned int msiof3_ss2_pins[] = {
2241 static const unsigned int msiof3_ss2_mux[] = {
2244 static const unsigned int msiof3_txd_pins[] = {
2248 static const unsigned int msiof3_txd_mux[] = {
2251 static const unsigned int msiof3_rxd_pins[] = {
2255 static const unsigned int msiof3_rxd_mux[] = {
2259 /* - MSIOF4 ----------------------------------------------------------------- */
2260 static const unsigned int msiof4_clk_pins[] = {
2264 static const unsigned int msiof4_clk_mux[] = {
2267 static const unsigned int msiof4_sync_pins[] = {
2271 static const unsigned int msiof4_sync_mux[] = {
2274 static const unsigned int msiof4_ss1_pins[] = {
2278 static const unsigned int msiof4_ss1_mux[] = {
2281 static const unsigned int msiof4_ss2_pins[] = {
2285 static const unsigned int msiof4_ss2_mux[] = {
2288 static const unsigned int msiof4_txd_pins[] = {
2292 static const unsigned int msiof4_txd_mux[] = {
2295 static const unsigned int msiof4_rxd_pins[] = {
2299 static const unsigned int msiof4_rxd_mux[] = {
2303 /* - MSIOF5 ----------------------------------------------------------------- */
2304 static const unsigned int msiof5_clk_pins[] = {
2308 static const unsigned int msiof5_clk_mux[] = {
2311 static const unsigned int msiof5_sync_pins[] = {
2315 static const unsigned int msiof5_sync_mux[] = {
2318 static const unsigned int msiof5_ss1_pins[] = {
2322 static const unsigned int msiof5_ss1_mux[] = {
2325 static const unsigned int msiof5_ss2_pins[] = {
2329 static const unsigned int msiof5_ss2_mux[] = {
2332 static const unsigned int msiof5_txd_pins[] = {
2336 static const unsigned int msiof5_txd_mux[] = {
2339 static const unsigned int msiof5_rxd_pins[] = {
2343 static const unsigned int msiof5_rxd_mux[] = {
2347 /* - PWM0 ------------------------------------------------------------------- */
2348 static const unsigned int pwm0_pins[] = {
2352 static const unsigned int pwm0_mux[] = {
2356 /* - PWM1 ------------------------------------------------------------------- */
2357 static const unsigned int pwm1_pins[] = {
2361 static const unsigned int pwm1_mux[] = {
2365 /* - PWM2 ------------------------------------------------------------------- */
2366 static const unsigned int pwm2_pins[] = {
2370 static const unsigned int pwm2_mux[] = {
2374 /* - PWM3 ------------------------------------------------------------------- */
2375 static const unsigned int pwm3_pins[] = {
2379 static const unsigned int pwm3_mux[] = {
2383 /* - PWM4 ------------------------------------------------------------------- */
2384 static const unsigned int pwm4_pins[] = {
2388 static const unsigned int pwm4_mux[] = {
2392 /* - QSPI0 ------------------------------------------------------------------ */
2393 static const unsigned int qspi0_ctrl_pins[] = {
2395 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 5),
2397 static const unsigned int qspi0_ctrl_mux[] = {
2398 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2400 static const unsigned int qspi0_data_pins[] = {
2401 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2402 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
2403 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2405 static const unsigned int qspi0_data_mux[] = {
2406 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2407 QSPI0_IO2_MARK, QSPI0_IO3_MARK
2410 /* - QSPI1 ------------------------------------------------------------------ */
2411 static const unsigned int qspi1_ctrl_pins[] = {
2413 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 11),
2415 static const unsigned int qspi1_ctrl_mux[] = {
2416 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2418 static const unsigned int qspi1_data_pins[] = {
2419 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2420 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
2421 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2423 static const unsigned int qspi1_data_mux[] = {
2424 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2425 QSPI1_IO2_MARK, QSPI1_IO3_MARK
2428 /* - SCIF0 ------------------------------------------------------------------ */
2429 static const unsigned int scif0_data_pins[] = {
2431 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),
2433 static const unsigned int scif0_data_mux[] = {
2436 static const unsigned int scif0_clk_pins[] = {
2440 static const unsigned int scif0_clk_mux[] = {
2443 static const unsigned int scif0_ctrl_pins[] = {
2445 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
2447 static const unsigned int scif0_ctrl_mux[] = {
2448 RTS0_N_MARK, CTS0_N_MARK,
2451 /* - SCIF1 ------------------------------------------------------------------ */
2452 static const unsigned int scif1_data_a_pins[] = {
2454 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
2456 static const unsigned int scif1_data_a_mux[] = {
2457 RX1_A_MARK, TX1_A_MARK,
2459 static const unsigned int scif1_data_b_pins[] = {
2461 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 1),
2463 static const unsigned int scif1_data_b_mux[] = {
2464 RX1_B_MARK, TX1_B_MARK,
2466 static const unsigned int scif1_clk_pins[] = {
2470 static const unsigned int scif1_clk_mux[] = {
2473 static const unsigned int scif1_ctrl_pins[] = {
2475 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),
2477 static const unsigned int scif1_ctrl_mux[] = {
2478 RTS1_N_MARK, CTS1_N_MARK,
2481 /* - SCIF3 ------------------------------------------------------------------ */
2482 static const unsigned int scif3_data_pins[] = {
2484 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2486 static const unsigned int scif3_data_mux[] = {
2489 static const unsigned int scif3_clk_pins[] = {
2493 static const unsigned int scif3_clk_mux[] = {
2496 static const unsigned int scif3_ctrl_pins[] = {
2498 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2500 static const unsigned int scif3_ctrl_mux[] = {
2501 RTS3_N_MARK, CTS3_N_MARK,
2504 /* - SCIF4 ------------------------------------------------------------------ */
2505 static const unsigned int scif4_data_pins[] = {
2507 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2509 static const unsigned int scif4_data_mux[] = {
2512 static const unsigned int scif4_clk_pins[] = {
2516 static const unsigned int scif4_clk_mux[] = {
2519 static const unsigned int scif4_ctrl_pins[] = {
2521 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
2523 static const unsigned int scif4_ctrl_mux[] = {
2524 RTS4_N_MARK, CTS4_N_MARK,
2527 /* - SCIF Clock ------------------------------------------------------------- */
2528 static const unsigned int scif_clk_pins[] = {
2532 static const unsigned int scif_clk_mux[] = {
2536 /* - TMU -------------------------------------------------------------------- */
2537 static const unsigned int tmu_tclk1_a_pins[] = {
2541 static const unsigned int tmu_tclk1_a_mux[] = {
2544 static const unsigned int tmu_tclk1_b_pins[] = {
2548 static const unsigned int tmu_tclk1_b_mux[] = {
2552 static const unsigned int tmu_tclk2_a_pins[] = {
2556 static const unsigned int tmu_tclk2_a_mux[] = {
2559 static const unsigned int tmu_tclk2_b_pins[] = {
2563 static const unsigned int tmu_tclk2_b_mux[] = {
2567 static const unsigned int tmu_tclk3_pins[] = {
2571 static const unsigned int tmu_tclk3_mux[] = {
2575 static const unsigned int tmu_tclk4_pins[] = {
2579 static const unsigned int tmu_tclk4_mux[] = {
2583 /* - TPU ------------------------------------------------------------------- */
2584 static const unsigned int tpu_to0_pins[] = {
2588 static const unsigned int tpu_to0_mux[] = {
2591 static const unsigned int tpu_to1_pins[] = {
2595 static const unsigned int tpu_to1_mux[] = {
2598 static const unsigned int tpu_to2_pins[] = {
2602 static const unsigned int tpu_to2_mux[] = {
2605 static const unsigned int tpu_to3_pins[] = {
2609 static const unsigned int tpu_to3_mux[] = {
2613 static const struct sh_pfc_pin_group pinmux_groups[] = {
2614 SH_PFC_PIN_GROUP(avb0_link),
2615 SH_PFC_PIN_GROUP(avb0_magic),
2616 SH_PFC_PIN_GROUP(avb0_phy_int),
2617 SH_PFC_PIN_GROUP(avb0_mdio),
2618 SH_PFC_PIN_GROUP(avb0_rgmii),
2619 SH_PFC_PIN_GROUP(avb0_txcrefclk),
2620 SH_PFC_PIN_GROUP(avb0_avtp_pps),
2621 SH_PFC_PIN_GROUP(avb0_avtp_capture),
2622 SH_PFC_PIN_GROUP(avb0_avtp_match),
2624 SH_PFC_PIN_GROUP(avb1_link),
2625 SH_PFC_PIN_GROUP(avb1_magic),
2626 SH_PFC_PIN_GROUP(avb1_phy_int),
2627 SH_PFC_PIN_GROUP(avb1_mdio),
2628 SH_PFC_PIN_GROUP(avb1_rgmii),
2629 SH_PFC_PIN_GROUP(avb1_txcrefclk),
2630 SH_PFC_PIN_GROUP(avb1_avtp_pps),
2631 SH_PFC_PIN_GROUP(avb1_avtp_capture),
2632 SH_PFC_PIN_GROUP(avb1_avtp_match),
2634 SH_PFC_PIN_GROUP(avb2_link),
2635 SH_PFC_PIN_GROUP(avb2_magic),
2636 SH_PFC_PIN_GROUP(avb2_phy_int),
2637 SH_PFC_PIN_GROUP(avb2_mdio),
2638 SH_PFC_PIN_GROUP(avb2_rgmii),
2639 SH_PFC_PIN_GROUP(avb2_txcrefclk),
2640 SH_PFC_PIN_GROUP(avb2_avtp_pps),
2641 SH_PFC_PIN_GROUP(avb2_avtp_capture),
2642 SH_PFC_PIN_GROUP(avb2_avtp_match),
2644 SH_PFC_PIN_GROUP(avb3_link),
2645 SH_PFC_PIN_GROUP(avb3_magic),
2646 SH_PFC_PIN_GROUP(avb3_phy_int),
2647 SH_PFC_PIN_GROUP(avb3_mdio),
2648 SH_PFC_PIN_GROUP(avb3_rgmii),
2649 SH_PFC_PIN_GROUP(avb3_txcrefclk),
2650 SH_PFC_PIN_GROUP(avb3_avtp_pps),
2651 SH_PFC_PIN_GROUP(avb3_avtp_capture),
2652 SH_PFC_PIN_GROUP(avb3_avtp_match),
2654 SH_PFC_PIN_GROUP(avb4_link),
2655 SH_PFC_PIN_GROUP(avb4_magic),
2656 SH_PFC_PIN_GROUP(avb4_phy_int),
2657 SH_PFC_PIN_GROUP(avb4_mdio),
2658 SH_PFC_PIN_GROUP(avb4_rgmii),
2659 SH_PFC_PIN_GROUP(avb4_txcrefclk),
2660 SH_PFC_PIN_GROUP(avb4_avtp_pps),
2661 SH_PFC_PIN_GROUP(avb4_avtp_capture),
2662 SH_PFC_PIN_GROUP(avb4_avtp_match),
2664 SH_PFC_PIN_GROUP(avb5_link),
2665 SH_PFC_PIN_GROUP(avb5_magic),
2666 SH_PFC_PIN_GROUP(avb5_phy_int),
2667 SH_PFC_PIN_GROUP(avb5_mdio),
2668 SH_PFC_PIN_GROUP(avb5_rgmii),
2669 SH_PFC_PIN_GROUP(avb5_txcrefclk),
2670 SH_PFC_PIN_GROUP(avb5_avtp_pps),
2671 SH_PFC_PIN_GROUP(avb5_avtp_capture),
2672 SH_PFC_PIN_GROUP(avb5_avtp_match),
2674 SH_PFC_PIN_GROUP(canfd0_data),
2675 SH_PFC_PIN_GROUP(canfd1_data),
2676 SH_PFC_PIN_GROUP(canfd2_data),
2677 SH_PFC_PIN_GROUP(canfd3_data),
2678 SH_PFC_PIN_GROUP(canfd4_data),
2679 SH_PFC_PIN_GROUP(canfd5_data),
2680 SH_PFC_PIN_GROUP(canfd6_data),
2681 SH_PFC_PIN_GROUP(canfd7_data),
2682 SH_PFC_PIN_GROUP(can_clk),
2684 SH_PFC_PIN_GROUP(du_rgb888),
2685 SH_PFC_PIN_GROUP(du_clk_out),
2686 SH_PFC_PIN_GROUP(du_sync),
2687 SH_PFC_PIN_GROUP(du_oddf),
2689 SH_PFC_PIN_GROUP(hscif0_data),
2690 SH_PFC_PIN_GROUP(hscif0_clk),
2691 SH_PFC_PIN_GROUP(hscif0_ctrl),
2692 SH_PFC_PIN_GROUP(hscif1_data),
2693 SH_PFC_PIN_GROUP(hscif1_clk),
2694 SH_PFC_PIN_GROUP(hscif1_ctrl),
2695 SH_PFC_PIN_GROUP(hscif2_data),
2696 SH_PFC_PIN_GROUP(hscif2_clk),
2697 SH_PFC_PIN_GROUP(hscif2_ctrl),
2698 SH_PFC_PIN_GROUP(hscif3_data),
2699 SH_PFC_PIN_GROUP(hscif3_clk),
2700 SH_PFC_PIN_GROUP(hscif3_ctrl),
2702 SH_PFC_PIN_GROUP(i2c0),
2703 SH_PFC_PIN_GROUP(i2c1),
2704 SH_PFC_PIN_GROUP(i2c2),
2705 SH_PFC_PIN_GROUP(i2c3),
2706 SH_PFC_PIN_GROUP(i2c4),
2707 SH_PFC_PIN_GROUP(i2c5),
2708 SH_PFC_PIN_GROUP(i2c6),
2710 SH_PFC_PIN_GROUP(intc_ex_irq0),
2711 SH_PFC_PIN_GROUP(intc_ex_irq1),
2712 SH_PFC_PIN_GROUP(intc_ex_irq2),
2713 SH_PFC_PIN_GROUP(intc_ex_irq3),
2714 SH_PFC_PIN_GROUP(intc_ex_irq4),
2715 SH_PFC_PIN_GROUP(intc_ex_irq5),
2717 BUS_DATA_PIN_GROUP(mmc_data, 1),
2718 BUS_DATA_PIN_GROUP(mmc_data, 4),
2719 BUS_DATA_PIN_GROUP(mmc_data, 8),
2720 SH_PFC_PIN_GROUP(mmc_ctrl),
2721 SH_PFC_PIN_GROUP(mmc_cd),
2722 SH_PFC_PIN_GROUP(mmc_wp),
2723 SH_PFC_PIN_GROUP(mmc_ds),
2725 SH_PFC_PIN_GROUP(msiof0_clk),
2726 SH_PFC_PIN_GROUP(msiof0_sync),
2727 SH_PFC_PIN_GROUP(msiof0_ss1),
2728 SH_PFC_PIN_GROUP(msiof0_ss2),
2729 SH_PFC_PIN_GROUP(msiof0_txd),
2730 SH_PFC_PIN_GROUP(msiof0_rxd),
2731 SH_PFC_PIN_GROUP(msiof1_clk),
2732 SH_PFC_PIN_GROUP(msiof1_sync),
2733 SH_PFC_PIN_GROUP(msiof1_ss1),
2734 SH_PFC_PIN_GROUP(msiof1_ss2),
2735 SH_PFC_PIN_GROUP(msiof1_txd),
2736 SH_PFC_PIN_GROUP(msiof1_rxd),
2737 SH_PFC_PIN_GROUP(msiof2_clk),
2738 SH_PFC_PIN_GROUP(msiof2_sync),
2739 SH_PFC_PIN_GROUP(msiof2_ss1),
2740 SH_PFC_PIN_GROUP(msiof2_ss2),
2741 SH_PFC_PIN_GROUP(msiof2_txd),
2742 SH_PFC_PIN_GROUP(msiof2_rxd),
2743 SH_PFC_PIN_GROUP(msiof3_clk),
2744 SH_PFC_PIN_GROUP(msiof3_sync),
2745 SH_PFC_PIN_GROUP(msiof3_ss1),
2746 SH_PFC_PIN_GROUP(msiof3_ss2),
2747 SH_PFC_PIN_GROUP(msiof3_txd),
2748 SH_PFC_PIN_GROUP(msiof3_rxd),
2749 SH_PFC_PIN_GROUP(msiof4_clk),
2750 SH_PFC_PIN_GROUP(msiof4_sync),
2751 SH_PFC_PIN_GROUP(msiof4_ss1),
2752 SH_PFC_PIN_GROUP(msiof4_ss2),
2753 SH_PFC_PIN_GROUP(msiof4_txd),
2754 SH_PFC_PIN_GROUP(msiof4_rxd),
2755 SH_PFC_PIN_GROUP(msiof5_clk),
2756 SH_PFC_PIN_GROUP(msiof5_sync),
2757 SH_PFC_PIN_GROUP(msiof5_ss1),
2758 SH_PFC_PIN_GROUP(msiof5_ss2),
2759 SH_PFC_PIN_GROUP(msiof5_txd),
2760 SH_PFC_PIN_GROUP(msiof5_rxd),
2762 SH_PFC_PIN_GROUP(pwm0),
2763 SH_PFC_PIN_GROUP(pwm1),
2764 SH_PFC_PIN_GROUP(pwm2),
2765 SH_PFC_PIN_GROUP(pwm3),
2766 SH_PFC_PIN_GROUP(pwm4),
2768 SH_PFC_PIN_GROUP(qspi0_ctrl),
2769 BUS_DATA_PIN_GROUP(qspi0_data, 2),
2770 BUS_DATA_PIN_GROUP(qspi0_data, 4),
2771 SH_PFC_PIN_GROUP(qspi1_ctrl),
2772 BUS_DATA_PIN_GROUP(qspi1_data, 2),
2773 BUS_DATA_PIN_GROUP(qspi1_data, 4),
2775 SH_PFC_PIN_GROUP(scif0_data),
2776 SH_PFC_PIN_GROUP(scif0_clk),
2777 SH_PFC_PIN_GROUP(scif0_ctrl),
2778 SH_PFC_PIN_GROUP(scif1_data_a),
2779 SH_PFC_PIN_GROUP(scif1_data_b),
2780 SH_PFC_PIN_GROUP(scif1_clk),
2781 SH_PFC_PIN_GROUP(scif1_ctrl),
2782 SH_PFC_PIN_GROUP(scif3_data),
2783 SH_PFC_PIN_GROUP(scif3_clk),
2784 SH_PFC_PIN_GROUP(scif3_ctrl),
2785 SH_PFC_PIN_GROUP(scif4_data),
2786 SH_PFC_PIN_GROUP(scif4_clk),
2787 SH_PFC_PIN_GROUP(scif4_ctrl),
2788 SH_PFC_PIN_GROUP(scif_clk),
2790 SH_PFC_PIN_GROUP(tmu_tclk1_a),
2791 SH_PFC_PIN_GROUP(tmu_tclk1_b),
2792 SH_PFC_PIN_GROUP(tmu_tclk2_a),
2793 SH_PFC_PIN_GROUP(tmu_tclk2_b),
2794 SH_PFC_PIN_GROUP(tmu_tclk3),
2795 SH_PFC_PIN_GROUP(tmu_tclk4),
2797 SH_PFC_PIN_GROUP(tpu_to0),
2798 SH_PFC_PIN_GROUP(tpu_to1),
2799 SH_PFC_PIN_GROUP(tpu_to2),
2800 SH_PFC_PIN_GROUP(tpu_to3),
2803 static const char * const avb0_groups[] = {
2811 "avb0_avtp_capture",
2815 static const char * const avb1_groups[] = {
2823 "avb1_avtp_capture",
2827 static const char * const avb2_groups[] = {
2835 "avb2_avtp_capture",
2839 static const char * const avb3_groups[] = {
2847 "avb3_avtp_capture",
2851 static const char * const avb4_groups[] = {
2859 "avb4_avtp_capture",
2863 static const char * const avb5_groups[] = {
2871 "avb5_avtp_capture",
2875 static const char * const canfd0_groups[] = {
2879 static const char * const canfd1_groups[] = {
2883 static const char * const canfd2_groups[] = {
2887 static const char * const canfd3_groups[] = {
2891 static const char * const canfd4_groups[] = {
2895 static const char * const canfd5_groups[] = {
2899 static const char * const canfd6_groups[] = {
2903 static const char * const canfd7_groups[] = {
2907 static const char * const can_clk_groups[] = {
2911 static const char * const du_groups[] = {
2918 static const char * const hscif0_groups[] = {
2924 static const char * const hscif1_groups[] = {
2930 static const char * const hscif2_groups[] = {
2936 static const char * const hscif3_groups[] = {
2942 static const char * const i2c0_groups[] = {
2946 static const char * const i2c1_groups[] = {
2950 static const char * const i2c2_groups[] = {
2954 static const char * const i2c3_groups[] = {
2958 static const char * const i2c4_groups[] = {
2962 static const char * const i2c5_groups[] = {
2966 static const char * const i2c6_groups[] = {
2970 static const char * const intc_ex_groups[] = {
2979 static const char * const mmc_groups[] = {
2989 static const char * const msiof0_groups[] = {
2998 static const char * const msiof1_groups[] = {
3007 static const char * const msiof2_groups[] = {
3016 static const char * const msiof3_groups[] = {
3025 static const char * const msiof4_groups[] = {
3034 static const char * const msiof5_groups[] = {
3043 static const char * const pwm0_groups[] = {
3047 static const char * const pwm1_groups[] = {
3051 static const char * const pwm2_groups[] = {
3055 static const char * const pwm3_groups[] = {
3059 static const char * const pwm4_groups[] = {
3063 static const char * const qspi0_groups[] = {
3069 static const char * const qspi1_groups[] = {
3075 static const char * const scif0_groups[] = {
3081 static const char * const scif1_groups[] = {
3088 static const char * const scif3_groups[] = {
3094 static const char * const scif4_groups[] = {
3100 static const char * const scif_clk_groups[] = {
3104 static const char * const tmu_groups[] = {
3113 static const char * const tpu_groups[] = {
3120 static const struct sh_pfc_function pinmux_functions[] = {
3121 SH_PFC_FUNCTION(avb0),
3122 SH_PFC_FUNCTION(avb1),
3123 SH_PFC_FUNCTION(avb2),
3124 SH_PFC_FUNCTION(avb3),
3125 SH_PFC_FUNCTION(avb4),
3126 SH_PFC_FUNCTION(avb5),
3128 SH_PFC_FUNCTION(canfd0),
3129 SH_PFC_FUNCTION(canfd1),
3130 SH_PFC_FUNCTION(canfd2),
3131 SH_PFC_FUNCTION(canfd3),
3132 SH_PFC_FUNCTION(canfd4),
3133 SH_PFC_FUNCTION(canfd5),
3134 SH_PFC_FUNCTION(canfd6),
3135 SH_PFC_FUNCTION(canfd7),
3136 SH_PFC_FUNCTION(can_clk),
3138 SH_PFC_FUNCTION(du),
3140 SH_PFC_FUNCTION(hscif0),
3141 SH_PFC_FUNCTION(hscif1),
3142 SH_PFC_FUNCTION(hscif2),
3143 SH_PFC_FUNCTION(hscif3),
3145 SH_PFC_FUNCTION(i2c0),
3146 SH_PFC_FUNCTION(i2c1),
3147 SH_PFC_FUNCTION(i2c2),
3148 SH_PFC_FUNCTION(i2c3),
3149 SH_PFC_FUNCTION(i2c4),
3150 SH_PFC_FUNCTION(i2c5),
3151 SH_PFC_FUNCTION(i2c6),
3153 SH_PFC_FUNCTION(intc_ex),
3155 SH_PFC_FUNCTION(mmc),
3157 SH_PFC_FUNCTION(msiof0),
3158 SH_PFC_FUNCTION(msiof1),
3159 SH_PFC_FUNCTION(msiof2),
3160 SH_PFC_FUNCTION(msiof3),
3161 SH_PFC_FUNCTION(msiof4),
3162 SH_PFC_FUNCTION(msiof5),
3164 SH_PFC_FUNCTION(pwm0),
3165 SH_PFC_FUNCTION(pwm1),
3166 SH_PFC_FUNCTION(pwm2),
3167 SH_PFC_FUNCTION(pwm3),
3168 SH_PFC_FUNCTION(pwm4),
3170 SH_PFC_FUNCTION(qspi0),
3171 SH_PFC_FUNCTION(qspi1),
3173 SH_PFC_FUNCTION(scif0),
3174 SH_PFC_FUNCTION(scif1),
3175 SH_PFC_FUNCTION(scif3),
3176 SH_PFC_FUNCTION(scif4),
3177 SH_PFC_FUNCTION(scif_clk),
3179 SH_PFC_FUNCTION(tmu),
3181 SH_PFC_FUNCTION(tpu),
3184 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3185 #define F_(x, y) FN_##y
3186 #define FM(x) FN_##x
3187 { PINMUX_CFG_REG("GPSR0", 0xe6058040, 32, 1, GROUP(
3192 GP_0_27_FN, GPSR0_27,
3193 GP_0_26_FN, GPSR0_26,
3194 GP_0_25_FN, GPSR0_25,
3195 GP_0_24_FN, GPSR0_24,
3196 GP_0_23_FN, GPSR0_23,
3197 GP_0_22_FN, GPSR0_22,
3198 GP_0_21_FN, GPSR0_21,
3199 GP_0_20_FN, GPSR0_20,
3200 GP_0_19_FN, GPSR0_19,
3201 GP_0_18_FN, GPSR0_18,
3202 GP_0_17_FN, GPSR0_17,
3203 GP_0_16_FN, GPSR0_16,
3204 GP_0_15_FN, GPSR0_15,
3205 GP_0_14_FN, GPSR0_14,
3206 GP_0_13_FN, GPSR0_13,
3207 GP_0_12_FN, GPSR0_12,
3208 GP_0_11_FN, GPSR0_11,
3209 GP_0_10_FN, GPSR0_10,
3219 GP_0_0_FN, GPSR0_0, ))
3221 { PINMUX_CFG_REG("GPSR1", 0xe6050040, 32, 1, GROUP(
3223 GP_1_30_FN, GPSR1_30,
3224 GP_1_29_FN, GPSR1_29,
3225 GP_1_28_FN, GPSR1_28,
3226 GP_1_27_FN, GPSR1_27,
3227 GP_1_26_FN, GPSR1_26,
3228 GP_1_25_FN, GPSR1_25,
3229 GP_1_24_FN, GPSR1_24,
3230 GP_1_23_FN, GPSR1_23,
3231 GP_1_22_FN, GPSR1_22,
3232 GP_1_21_FN, GPSR1_21,
3233 GP_1_20_FN, GPSR1_20,
3234 GP_1_19_FN, GPSR1_19,
3235 GP_1_18_FN, GPSR1_18,
3236 GP_1_17_FN, GPSR1_17,
3237 GP_1_16_FN, GPSR1_16,
3238 GP_1_15_FN, GPSR1_15,
3239 GP_1_14_FN, GPSR1_14,
3240 GP_1_13_FN, GPSR1_13,
3241 GP_1_12_FN, GPSR1_12,
3242 GP_1_11_FN, GPSR1_11,
3243 GP_1_10_FN, GPSR1_10,
3253 GP_1_0_FN, GPSR1_0, ))
3255 { PINMUX_CFG_REG("GPSR2", 0xe6050840, 32, 1, GROUP(
3263 GP_2_24_FN, GPSR2_24,
3264 GP_2_23_FN, GPSR2_23,
3265 GP_2_22_FN, GPSR2_22,
3266 GP_2_21_FN, GPSR2_21,
3267 GP_2_20_FN, GPSR2_20,
3268 GP_2_19_FN, GPSR2_19,
3269 GP_2_18_FN, GPSR2_18,
3270 GP_2_17_FN, GPSR2_17,
3271 GP_2_16_FN, GPSR2_16,
3272 GP_2_15_FN, GPSR2_15,
3273 GP_2_14_FN, GPSR2_14,
3274 GP_2_13_FN, GPSR2_13,
3275 GP_2_12_FN, GPSR2_12,
3276 GP_2_11_FN, GPSR2_11,
3277 GP_2_10_FN, GPSR2_10,
3287 GP_2_0_FN, GPSR2_0, ))
3289 { PINMUX_CFG_REG("GPSR3", 0xe6058840, 32, 1, GROUP(
3305 GP_3_16_FN, GPSR3_16,
3306 GP_3_15_FN, GPSR3_15,
3307 GP_3_14_FN, GPSR3_14,
3308 GP_3_13_FN, GPSR3_13,
3309 GP_3_12_FN, GPSR3_12,
3310 GP_3_11_FN, GPSR3_11,
3311 GP_3_10_FN, GPSR3_10,
3321 GP_3_0_FN, GPSR3_0, ))
3323 { PINMUX_CFG_REG("GPSR4", 0xe6060040, 32, 1, GROUP(
3329 GP_4_26_FN, GPSR4_26,
3330 GP_4_25_FN, GPSR4_25,
3331 GP_4_24_FN, GPSR4_24,
3332 GP_4_23_FN, GPSR4_23,
3333 GP_4_22_FN, GPSR4_22,
3334 GP_4_21_FN, GPSR4_21,
3335 GP_4_20_FN, GPSR4_20,
3336 GP_4_19_FN, GPSR4_19,
3337 GP_4_18_FN, GPSR4_18,
3338 GP_4_17_FN, GPSR4_17,
3339 GP_4_16_FN, GPSR4_16,
3340 GP_4_15_FN, GPSR4_15,
3341 GP_4_14_FN, GPSR4_14,
3342 GP_4_13_FN, GPSR4_13,
3343 GP_4_12_FN, GPSR4_12,
3344 GP_4_11_FN, GPSR4_11,
3345 GP_4_10_FN, GPSR4_10,
3355 GP_4_0_FN, GPSR4_0, ))
3357 { PINMUX_CFG_REG("GPSR5", 0xe6060840, 32, 1, GROUP(
3369 GP_5_20_FN, GPSR5_20,
3370 GP_5_19_FN, GPSR5_19,
3371 GP_5_18_FN, GPSR5_18,
3372 GP_5_17_FN, GPSR5_17,
3373 GP_5_16_FN, GPSR5_16,
3374 GP_5_15_FN, GPSR5_15,
3375 GP_5_14_FN, GPSR5_14,
3376 GP_5_13_FN, GPSR5_13,
3377 GP_5_12_FN, GPSR5_12,
3378 GP_5_11_FN, GPSR5_11,
3379 GP_5_10_FN, GPSR5_10,
3389 GP_5_0_FN, GPSR5_0, ))
3391 { PINMUX_CFG_REG("GPSR6", 0xe6068040, 32, 1, GROUP(
3403 GP_6_20_FN, GPSR6_20,
3404 GP_6_19_FN, GPSR6_19,
3405 GP_6_18_FN, GPSR6_18,
3406 GP_6_17_FN, GPSR6_17,
3407 GP_6_16_FN, GPSR6_16,
3408 GP_6_15_FN, GPSR6_15,
3409 GP_6_14_FN, GPSR6_14,
3410 GP_6_13_FN, GPSR6_13,
3411 GP_6_12_FN, GPSR6_12,
3412 GP_6_11_FN, GPSR6_11,
3413 GP_6_10_FN, GPSR6_10,
3423 GP_6_0_FN, GPSR6_0, ))
3425 { PINMUX_CFG_REG("GPSR7", 0xe6068840, 32, 1, GROUP(
3437 GP_7_20_FN, GPSR7_20,
3438 GP_7_19_FN, GPSR7_19,
3439 GP_7_18_FN, GPSR7_18,
3440 GP_7_17_FN, GPSR7_17,
3441 GP_7_16_FN, GPSR7_16,
3442 GP_7_15_FN, GPSR7_15,
3443 GP_7_14_FN, GPSR7_14,
3444 GP_7_13_FN, GPSR7_13,
3445 GP_7_12_FN, GPSR7_12,
3446 GP_7_11_FN, GPSR7_11,
3447 GP_7_10_FN, GPSR7_10,
3457 GP_7_0_FN, GPSR7_0, ))
3459 { PINMUX_CFG_REG("GPSR8", 0xe6069040, 32, 1, GROUP(
3471 GP_8_20_FN, GPSR8_20,
3472 GP_8_19_FN, GPSR8_19,
3473 GP_8_18_FN, GPSR8_18,
3474 GP_8_17_FN, GPSR8_17,
3475 GP_8_16_FN, GPSR8_16,
3476 GP_8_15_FN, GPSR8_15,
3477 GP_8_14_FN, GPSR8_14,
3478 GP_8_13_FN, GPSR8_13,
3479 GP_8_12_FN, GPSR8_12,
3480 GP_8_11_FN, GPSR8_11,
3481 GP_8_10_FN, GPSR8_10,
3491 GP_8_0_FN, GPSR8_0, ))
3493 { PINMUX_CFG_REG("GPSR9", 0xe6069840, 32, 1, GROUP(
3505 GP_9_20_FN, GPSR9_20,
3506 GP_9_19_FN, GPSR9_19,
3507 GP_9_18_FN, GPSR9_18,
3508 GP_9_17_FN, GPSR9_17,
3509 GP_9_16_FN, GPSR9_16,
3510 GP_9_15_FN, GPSR9_15,
3511 GP_9_14_FN, GPSR9_14,
3512 GP_9_13_FN, GPSR9_13,
3513 GP_9_12_FN, GPSR9_12,
3514 GP_9_11_FN, GPSR9_11,
3515 GP_9_10_FN, GPSR9_10,
3525 GP_9_0_FN, GPSR9_0, ))
3531 #define FM(x) FN_##x,
3532 { PINMUX_CFG_REG("IP0SR1", 0xe6050060, 32, 4, GROUP(
3542 { PINMUX_CFG_REG("IP1SR1", 0xe6050064, 32, 4, GROUP(
3552 { PINMUX_CFG_REG("IP2SR1", 0xe6050068, 32, 4, GROUP(
3562 { PINMUX_CFG_REG("IP3SR1", 0xe605006c, 32, 4, GROUP(
3572 { PINMUX_CFG_REG("IP0SR2", 0xe6050860, 32, 4, GROUP(
3582 { PINMUX_CFG_REG("IP1SR2", 0xe6050864, 32, 4, GROUP(
3592 { PINMUX_CFG_REG("IP2SR2", 0xe6050868, 32, 4, GROUP(
3602 { PINMUX_CFG_REG("IP0SR3", 0xe6058860, 32, 4, GROUP(
3612 { PINMUX_CFG_REG("IP1SR3", 0xe6058864, 32, 4, GROUP(
3622 { PINMUX_CFG_REG("IP0SR4", 0xe6060060, 32, 4, GROUP(
3632 { PINMUX_CFG_REG("IP1SR4", 0xe6060064, 32, 4, GROUP(
3642 { PINMUX_CFG_REG("IP2SR4", 0xe6060068, 32, 4, GROUP(
3652 { PINMUX_CFG_REG("IP0SR5", 0xe6060860, 32, 4, GROUP(
3662 { PINMUX_CFG_REG("IP1SR5", 0xe6060864, 32, 4, GROUP(
3672 { PINMUX_CFG_REG("IP2SR5", 0xe6060868, 32, 4, GROUP(
3686 #define FM(x) FN_##x,
3687 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6050900, 32,
3688 GROUP(-16, 2, 2, 2, 2, 2, 2, 2, -2),
3690 /* RESERVED 31-16 */
3698 /* RESERVED 1-0 */ ))
3703 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3704 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6058080) {
3705 { RCAR_GP_PIN(0, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */
3706 { RCAR_GP_PIN(0, 6), 24, 2 }, /* QSPI1_SPCLK */
3707 { RCAR_GP_PIN(0, 5), 20, 2 }, /* QSPI0_SSL */
3708 { RCAR_GP_PIN(0, 4), 16, 2 }, /* QSPI0_IO3 */
3709 { RCAR_GP_PIN(0, 3), 12, 2 }, /* QSPI0_IO2 */
3710 { RCAR_GP_PIN(0, 2), 8, 2 }, /* QSPI0_MISO_IO1 */
3711 { RCAR_GP_PIN(0, 1), 4, 2 }, /* QSPI0_MOSI_IO0 */
3712 { RCAR_GP_PIN(0, 0), 0, 2 }, /* QSPI0_SPCLK */
3714 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6058084) {
3715 { RCAR_GP_PIN(0, 15), 28, 3 }, /* SD_WP */
3716 { RCAR_GP_PIN(0, 14), 24, 2 }, /* RPC_INT_N */
3717 { RCAR_GP_PIN(0, 13), 20, 2 }, /* RPC_WP_N */
3718 { RCAR_GP_PIN(0, 12), 16, 2 }, /* RPC_RESET_N */
3719 { RCAR_GP_PIN(0, 11), 12, 2 }, /* QSPI1_SSL */
3720 { RCAR_GP_PIN(0, 10), 8, 2 }, /* QSPI1_IO3 */
3721 { RCAR_GP_PIN(0, 9), 4, 2 }, /* QSPI1_IO2 */
3722 { RCAR_GP_PIN(0, 8), 0, 2 }, /* QSPI1_MISO_IO1 */
3724 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6058088) {
3725 { RCAR_GP_PIN(0, 23), 28, 3 }, /* MMC_SD_CLK */
3726 { RCAR_GP_PIN(0, 22), 24, 3 }, /* MMC_SD_D3 */
3727 { RCAR_GP_PIN(0, 21), 20, 3 }, /* MMC_SD_D2 */
3728 { RCAR_GP_PIN(0, 20), 16, 3 }, /* MMC_SD_D1 */
3729 { RCAR_GP_PIN(0, 19), 12, 3 }, /* MMC_SD_D0 */
3730 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MMC_SD_CMD */
3731 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MMC_DS */
3732 { RCAR_GP_PIN(0, 16), 0, 3 }, /* SD_CD */
3734 { PINMUX_DRIVE_REG("DRV3CTRL0", 0xe605808c) {
3735 { RCAR_GP_PIN(0, 27), 12, 3 }, /* MMC_D7 */
3736 { RCAR_GP_PIN(0, 26), 8, 3 }, /* MMC_D6 */
3737 { RCAR_GP_PIN(0, 25), 4, 3 }, /* MMC_D5 */
3738 { RCAR_GP_PIN(0, 24), 0, 3 }, /* MMC_D4 */
3740 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050080) {
3741 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_TXD */
3742 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_RXD */
3743 { RCAR_GP_PIN(1, 5), 20, 3 }, /* HTX0 */
3744 { RCAR_GP_PIN(1, 4), 16, 3 }, /* HCTS0_N */
3745 { RCAR_GP_PIN(1, 3), 12, 3 }, /* HRTS0_N */
3746 { RCAR_GP_PIN(1, 2), 8, 3 }, /* HSCK0 */
3747 { RCAR_GP_PIN(1, 1), 4, 3 }, /* HRX0 */
3748 { RCAR_GP_PIN(1, 0), 0, 3 }, /* SCIF_CLK */
3750 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050084) {
3751 { RCAR_GP_PIN(1, 15), 28, 3 }, /* MSIOF1_SYNC */
3752 { RCAR_GP_PIN(1, 14), 24, 3 }, /* MSIOF1_SCK */
3753 { RCAR_GP_PIN(1, 13), 20, 3 }, /* MSIOF1_TXD */
3754 { RCAR_GP_PIN(1, 12), 16, 3 }, /* MSIOF1_RXD */
3755 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_SS2 */
3756 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SS1 */
3757 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_SYNC */
3758 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SCK */
3760 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050088) {
3761 { RCAR_GP_PIN(1, 23), 28, 3 }, /* MSIOF2_SS2 */
3762 { RCAR_GP_PIN(1, 22), 24, 3 }, /* MSIOF2_SS1 */
3763 { RCAR_GP_PIN(1, 21), 20, 3 }, /* MSIOF2_SYNC */
3764 { RCAR_GP_PIN(1, 20), 16, 3 }, /* MSIOF2_SCK */
3765 { RCAR_GP_PIN(1, 19), 12, 3 }, /* MSIOF2_TXD */
3766 { RCAR_GP_PIN(1, 18), 8, 3 }, /* MSIOF2_RXD */
3767 { RCAR_GP_PIN(1, 17), 4, 3 }, /* MSIOF1_SS2 */
3768 { RCAR_GP_PIN(1, 16), 0, 3 }, /* MSIOF1_SS1 */
3770 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605008c) {
3771 { RCAR_GP_PIN(1, 30), 24, 3 }, /* GP1_30 */
3772 { RCAR_GP_PIN(1, 29), 20, 3 }, /* GP1_29 */
3773 { RCAR_GP_PIN(1, 28), 16, 3 }, /* GP1_28 */
3774 { RCAR_GP_PIN(1, 27), 12, 3 }, /* IRQ3 */
3775 { RCAR_GP_PIN(1, 26), 8, 3 }, /* IRQ2 */
3776 { RCAR_GP_PIN(1, 25), 4, 3 }, /* IRQ1 */
3777 { RCAR_GP_PIN(1, 24), 0, 3 }, /* IRQ0 */
3779 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6050880) {
3780 { RCAR_GP_PIN(2, 7), 28, 3 }, /* GP2_07 */
3781 { RCAR_GP_PIN(2, 6), 24, 3 }, /* GP2_06 */
3782 { RCAR_GP_PIN(2, 5), 20, 3 }, /* GP2_05 */
3783 { RCAR_GP_PIN(2, 4), 16, 3 }, /* GP2_04 */
3784 { RCAR_GP_PIN(2, 3), 12, 3 }, /* GP2_03 */
3785 { RCAR_GP_PIN(2, 2), 8, 3 }, /* GP2_02 */
3786 { RCAR_GP_PIN(2, 1), 4, 2 }, /* IPC_CLKOUT */
3787 { RCAR_GP_PIN(2, 0), 0, 2 }, /* IPC_CLKIN */
3789 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6050884) {
3790 { RCAR_GP_PIN(2, 15), 28, 3 }, /* GP2_15 */
3791 { RCAR_GP_PIN(2, 14), 24, 3 }, /* GP2_14 */
3792 { RCAR_GP_PIN(2, 13), 20, 3 }, /* GP2_13 */
3793 { RCAR_GP_PIN(2, 12), 16, 3 }, /* GP2_12 */
3794 { RCAR_GP_PIN(2, 11), 12, 3 }, /* GP2_11 */
3795 { RCAR_GP_PIN(2, 10), 8, 3 }, /* GP2_10 */
3796 { RCAR_GP_PIN(2, 9), 4, 3 }, /* GP2_9 */
3797 { RCAR_GP_PIN(2, 8), 0, 3 }, /* GP2_8 */
3799 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6050888) {
3800 { RCAR_GP_PIN(2, 23), 28, 3 }, /* TCLK1_A */
3801 { RCAR_GP_PIN(2, 22), 24, 3 }, /* TPU0TO1 */
3802 { RCAR_GP_PIN(2, 21), 20, 3 }, /* TPU0TO0 */
3803 { RCAR_GP_PIN(2, 20), 16, 3 }, /* CLK_EXTFXR */
3804 { RCAR_GP_PIN(2, 19), 12, 3 }, /* RXDB_EXTFXR */
3805 { RCAR_GP_PIN(2, 18), 8, 3 }, /* FXR_TXDB */
3806 { RCAR_GP_PIN(2, 17), 4, 3 }, /* RXDA_EXTFXR_A */
3807 { RCAR_GP_PIN(2, 16), 0, 3 }, /* FXR_TXDA_A */
3809 { PINMUX_DRIVE_REG("DRV3CTRL2", 0xe605088c) {
3810 { RCAR_GP_PIN(2, 24), 0, 3 }, /* TCLK2_A */
3812 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6058880) {
3813 { RCAR_GP_PIN(3, 7), 28, 3 }, /* CANFD3_TX */
3814 { RCAR_GP_PIN(3, 6), 24, 3 }, /* CANFD2_RX */
3815 { RCAR_GP_PIN(3, 5), 20, 3 }, /* CANFD2_TX */
3816 { RCAR_GP_PIN(3, 4), 16, 3 }, /* CANFD1_RX */
3817 { RCAR_GP_PIN(3, 3), 12, 3 }, /* CANFD1_TX */
3818 { RCAR_GP_PIN(3, 2), 8, 3 }, /* CANFD0_RX */
3819 { RCAR_GP_PIN(3, 1), 4, 2 }, /* CANFD0_TX */
3820 { RCAR_GP_PIN(3, 0), 0, 2 }, /* CAN_CLK */
3822 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6058884) {
3823 { RCAR_GP_PIN(3, 15), 28, 3 }, /* CANFD7_TX */
3824 { RCAR_GP_PIN(3, 14), 24, 3 }, /* CANFD6_RX */
3825 { RCAR_GP_PIN(3, 13), 20, 3 }, /* CANFD6_TX */
3826 { RCAR_GP_PIN(3, 12), 16, 3 }, /* CANFD5_RX */
3827 { RCAR_GP_PIN(3, 11), 12, 3 }, /* CANFD5_TX */
3828 { RCAR_GP_PIN(3, 10), 8, 3 }, /* CANFD4_RX */
3829 { RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX */
3830 { RCAR_GP_PIN(3, 8), 0, 3 }, /* CANFD3_RX */
3832 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6058888) {
3833 { RCAR_GP_PIN(3, 16), 0, 3 }, /* CANFD7_RX */
3835 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xe6060080) {
3836 { RCAR_GP_PIN(4, 7), 28, 3 }, /* AVB0_TXC */
3837 { RCAR_GP_PIN(4, 6), 24, 3 }, /* AVB0_TX_CTL */
3838 { RCAR_GP_PIN(4, 5), 20, 3 }, /* AVB0_RD3 */
3839 { RCAR_GP_PIN(4, 4), 16, 3 }, /* AVB0_RD2 */
3840 { RCAR_GP_PIN(4, 3), 12, 3 }, /* AVB0_RD1 */
3841 { RCAR_GP_PIN(4, 2), 8, 3 }, /* AVB0_RD0 */
3842 { RCAR_GP_PIN(4, 1), 4, 3 }, /* AVB0_RXC */
3843 { RCAR_GP_PIN(4, 0), 0, 3 }, /* AVB0_RX_CTL */
3845 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xe6060084) {
3846 { RCAR_GP_PIN(4, 15), 28, 3 }, /* AVB0_MAGIC */
3847 { RCAR_GP_PIN(4, 14), 24, 3 }, /* AVB0_MDC */
3848 { RCAR_GP_PIN(4, 13), 20, 3 }, /* AVB0_MDIO */
3849 { RCAR_GP_PIN(4, 12), 16, 3 }, /* AVB0_TXCREFCLK */
3850 { RCAR_GP_PIN(4, 11), 12, 3 }, /* AVB0_TD3 */
3851 { RCAR_GP_PIN(4, 10), 8, 3 }, /* AVB0_TD2 */
3852 { RCAR_GP_PIN(4, 9), 4, 3 }, /* AVB0_TD1*/
3853 { RCAR_GP_PIN(4, 8), 0, 3 }, /* AVB0_TD0 */
3855 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xe6060088) {
3856 { RCAR_GP_PIN(4, 23), 28, 3 }, /* PCIE2_CLKREQ_N */
3857 { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */
3858 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
3859 { RCAR_GP_PIN(4, 20), 16, 3 }, /* AVB0_AVTP_PPS */
3860 { RCAR_GP_PIN(4, 19), 12, 3 }, /* AVB0_AVTP_CAPTURE */
3861 { RCAR_GP_PIN(4, 18), 8, 3 }, /* AVB0_AVTP_MATCH */
3862 { RCAR_GP_PIN(4, 17), 4, 3 }, /* AVB0_LINK */
3863 { RCAR_GP_PIN(4, 16), 0, 3 }, /* AVB0_PHY_INT */
3865 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xe606008c) {
3866 { RCAR_GP_PIN(4, 26), 8, 3 }, /* AVS1 */
3867 { RCAR_GP_PIN(4, 25), 4, 3 }, /* AVS0 */
3868 { RCAR_GP_PIN(4, 24), 0, 3 }, /* PCIE3_CLKREQ_N */
3870 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xe6060880) {
3871 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB1_TXC */
3872 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB1_TX_CTL */
3873 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB1_RD3 */
3874 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB1_RD2 */
3875 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB1_RD1 */
3876 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB1_RD0 */
3877 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB1_RXC */
3878 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB1_RX_CTL */
3880 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xe6060884) {
3881 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB1_MAGIC */
3882 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB1_MDC */
3883 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB1_MDIO */
3884 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB1_TXCREFCLK */
3885 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB1_TD3 */
3886 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB1_TD2 */
3887 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB1_TD1*/
3888 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB1_TD0 */
3890 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xe6060888) {
3891 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB1_AVTP_PPS */
3892 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB1_AVTP_CAPTURE */
3893 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB1_AVTP_MATCH */
3894 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB1_LINK */
3895 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB1_PHY_INT */
3897 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xe6068080) {
3898 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB2_TXC */
3899 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB2_TX_CTL */
3900 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB2_RD3 */
3901 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB2_RD2 */
3902 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB2_RD1 */
3903 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB2_RD0 */
3904 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB2_RXC */
3905 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB2_RX_CTL */
3907 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xe6068084) {
3908 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB2_MAGIC */
3909 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB2_MDC */
3910 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB2_MDIO */
3911 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB2_TXCREFCLK */
3912 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB2_TD3 */
3913 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB2_TD2 */
3914 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB2_TD1*/
3915 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB2_TD0 */
3917 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xe6068088) {
3918 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB2_AVTP_PPS */
3919 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB2_AVTP_CAPTURE */
3920 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB2_AVTP_MATCH */
3921 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB2_LINK */
3922 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB2_PHY_INT */
3924 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xe6068880) {
3925 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB3_TXC */
3926 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB3_TX_CTL */
3927 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB3_RD3 */
3928 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB3_RD2 */
3929 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB3_RD1 */
3930 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB3_RD0 */
3931 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB3_RXC */
3932 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB3_RX_CTL */
3934 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xe6068884) {
3935 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB3_MAGIC */
3936 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB3_MDC */
3937 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB3_MDIO */
3938 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB3_TXCREFCLK */
3939 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB3_TD3 */
3940 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB3_TD2 */
3941 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB3_TD1*/
3942 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB3_TD0 */
3944 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xe6068888) {
3945 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB3_AVTP_PPS */
3946 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB3_AVTP_CAPTURE */
3947 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB3_AVTP_MATCH */
3948 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB3_LINK */
3949 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB3_PHY_INT */
3951 { PINMUX_DRIVE_REG("DRV0CTRL8", 0xe6069080) {
3952 { RCAR_GP_PIN(8, 7), 28, 3 }, /* AVB4_TXC */
3953 { RCAR_GP_PIN(8, 6), 24, 3 }, /* AVB4_TX_CTL */
3954 { RCAR_GP_PIN(8, 5), 20, 3 }, /* AVB4_RD3 */
3955 { RCAR_GP_PIN(8, 4), 16, 3 }, /* AVB4_RD2 */
3956 { RCAR_GP_PIN(8, 3), 12, 3 }, /* AVB4_RD1 */
3957 { RCAR_GP_PIN(8, 2), 8, 3 }, /* AVB4_RD0 */
3958 { RCAR_GP_PIN(8, 1), 4, 3 }, /* AVB4_RXC */
3959 { RCAR_GP_PIN(8, 0), 0, 3 }, /* AVB4_RX_CTL */
3961 { PINMUX_DRIVE_REG("DRV1CTRL8", 0xe6069084) {
3962 { RCAR_GP_PIN(8, 15), 28, 3 }, /* AVB4_MAGIC */
3963 { RCAR_GP_PIN(8, 14), 24, 3 }, /* AVB4_MDC */
3964 { RCAR_GP_PIN(8, 13), 20, 3 }, /* AVB4_MDIO */
3965 { RCAR_GP_PIN(8, 12), 16, 3 }, /* AVB4_TXCREFCLK */
3966 { RCAR_GP_PIN(8, 11), 12, 3 }, /* AVB4_TD3 */
3967 { RCAR_GP_PIN(8, 10), 8, 3 }, /* AVB4_TD2 */
3968 { RCAR_GP_PIN(8, 9), 4, 3 }, /* AVB4_TD1*/
3969 { RCAR_GP_PIN(8, 8), 0, 3 }, /* AVB4_TD0 */
3971 { PINMUX_DRIVE_REG("DRV2CTRL8", 0xe6069088) {
3972 { RCAR_GP_PIN(8, 20), 16, 3 }, /* AVB4_AVTP_PPS */
3973 { RCAR_GP_PIN(8, 19), 12, 3 }, /* AVB4_AVTP_CAPTURE */
3974 { RCAR_GP_PIN(8, 18), 8, 3 }, /* AVB4_AVTP_MATCH */
3975 { RCAR_GP_PIN(8, 17), 4, 3 }, /* AVB4_LINK */
3976 { RCAR_GP_PIN(8, 16), 0, 3 }, /* AVB4_PHY_INT */
3978 { PINMUX_DRIVE_REG("DRV0CTRL9", 0xe6069880) {
3979 { RCAR_GP_PIN(9, 7), 28, 3 }, /* AVB5_TXC */
3980 { RCAR_GP_PIN(9, 6), 24, 3 }, /* AVB5_TX_CTL */
3981 { RCAR_GP_PIN(9, 5), 20, 3 }, /* AVB5_RD3 */
3982 { RCAR_GP_PIN(9, 4), 16, 3 }, /* AVB5_RD2 */
3983 { RCAR_GP_PIN(9, 3), 12, 3 }, /* AVB5_RD1 */
3984 { RCAR_GP_PIN(9, 2), 8, 3 }, /* AVB5_RD0 */
3985 { RCAR_GP_PIN(9, 1), 4, 3 }, /* AVB5_RXC */
3986 { RCAR_GP_PIN(9, 0), 0, 3 }, /* AVB5_RX_CTL */
3988 { PINMUX_DRIVE_REG("DRV1CTRL9", 0xe6069884) {
3989 { RCAR_GP_PIN(9, 15), 28, 3 }, /* AVB5_MAGIC */
3990 { RCAR_GP_PIN(9, 14), 24, 3 }, /* AVB5_MDC */
3991 { RCAR_GP_PIN(9, 13), 20, 3 }, /* AVB5_MDIO */
3992 { RCAR_GP_PIN(9, 12), 16, 3 }, /* AVB5_TXCREFCLK */
3993 { RCAR_GP_PIN(9, 11), 12, 3 }, /* AVB5_TD3 */
3994 { RCAR_GP_PIN(9, 10), 8, 3 }, /* AVB5_TD2 */
3995 { RCAR_GP_PIN(9, 9), 4, 3 }, /* AVB5_TD1*/
3996 { RCAR_GP_PIN(9, 8), 0, 3 }, /* AVB5_TD0 */
3998 { PINMUX_DRIVE_REG("DRV2CTRL9", 0xe6069888) {
3999 { RCAR_GP_PIN(9, 20), 16, 3 }, /* AVB5_AVTP_PPS */
4000 { RCAR_GP_PIN(9, 19), 12, 3 }, /* AVB5_AVTP_CAPTURE */
4001 { RCAR_GP_PIN(9, 18), 8, 3 }, /* AVB5_AVTP_MATCH */
4002 { RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */
4003 { RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */
4021 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
4022 [POC0] = { 0xe60580a0, },
4023 [POC1] = { 0xe60500a0, },
4024 [POC2] = { 0xe60508a0, },
4025 [POC4] = { 0xe60600a0, },
4026 [POC5] = { 0xe60608a0, },
4027 [POC6] = { 0xe60680a0, },
4028 [POC7] = { 0xe60688a0, },
4029 [POC8] = { 0xe60690a0, },
4030 [POC9] = { 0xe60698a0, },
4031 [TD1SEL0] = { 0xe6058124, },
4035 static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
4037 int bit = pin & 0x1f;
4039 *pocctrl = pinmux_ioctrl_regs[POC0].reg;
4040 if (pin >= RCAR_GP_PIN(0, 15) && pin <= RCAR_GP_PIN(0, 27))
4043 *pocctrl = pinmux_ioctrl_regs[POC1].reg;
4044 if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 30))
4047 *pocctrl = pinmux_ioctrl_regs[POC2].reg;
4048 if (pin >= RCAR_GP_PIN(2, 2) && pin <= RCAR_GP_PIN(2, 15))
4051 *pocctrl = pinmux_ioctrl_regs[POC4].reg;
4052 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
4055 *pocctrl = pinmux_ioctrl_regs[POC5].reg;
4056 if (pin >= RCAR_GP_PIN(5, 0) && pin <= RCAR_GP_PIN(5, 17))
4059 *pocctrl = pinmux_ioctrl_regs[POC6].reg;
4060 if (pin >= RCAR_GP_PIN(6, 0) && pin <= RCAR_GP_PIN(6, 17))
4063 *pocctrl = pinmux_ioctrl_regs[POC7].reg;
4064 if (pin >= RCAR_GP_PIN(7, 0) && pin <= RCAR_GP_PIN(7, 17))
4067 *pocctrl = pinmux_ioctrl_regs[POC8].reg;
4068 if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 17))
4071 *pocctrl = pinmux_ioctrl_regs[POC9].reg;
4072 if (pin >= RCAR_GP_PIN(9, 0) && pin <= RCAR_GP_PIN(9, 17))
4078 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
4079 { PINMUX_BIAS_REG("PUEN0", 0xe60580c0, "PUD0", 0xe60580e0) {
4080 [ 0] = RCAR_GP_PIN(0, 0), /* QSPI0_SPCLK */
4081 [ 1] = RCAR_GP_PIN(0, 1), /* QSPI0_MOSI_IO0 */
4082 [ 2] = RCAR_GP_PIN(0, 2), /* QSPI0_MISO_IO1 */
4083 [ 3] = RCAR_GP_PIN(0, 3), /* QSPI0_IO2 */
4084 [ 4] = RCAR_GP_PIN(0, 4), /* QSPI0_IO3 */
4085 [ 5] = RCAR_GP_PIN(0, 5), /* QSPI0_SSL */
4086 [ 6] = RCAR_GP_PIN(0, 6), /* QSPI1_SPCLK */
4087 [ 7] = RCAR_GP_PIN(0, 7), /* QSPI1_MOSI_IO0 */
4088 [ 8] = RCAR_GP_PIN(0, 8), /* QSPI1_MISO_IO1 */
4089 [ 9] = RCAR_GP_PIN(0, 9), /* QSPI1_IO2 */
4090 [10] = RCAR_GP_PIN(0, 10), /* QSPI1_IO3 */
4091 [11] = RCAR_GP_PIN(0, 11), /* QSPI1_SSL */
4092 [12] = RCAR_GP_PIN(0, 12), /* RPC_RESET_N */
4093 [13] = RCAR_GP_PIN(0, 13), /* RPC_WP_N */
4094 [14] = RCAR_GP_PIN(0, 14), /* RPC_INT_N */
4095 [15] = RCAR_GP_PIN(0, 15), /* SD_WP */
4096 [16] = RCAR_GP_PIN(0, 16), /* SD_CD */
4097 [17] = RCAR_GP_PIN(0, 17), /* MMC_DS */
4098 [18] = RCAR_GP_PIN(0, 18), /* MMC_SD_CMD */
4099 [19] = RCAR_GP_PIN(0, 19), /* MMC_SD_D0 */
4100 [20] = RCAR_GP_PIN(0, 20), /* MMC_SD_D1 */
4101 [21] = RCAR_GP_PIN(0, 21), /* MMC_SD_D2 */
4102 [22] = RCAR_GP_PIN(0, 22), /* MMC_SD_D3 */
4103 [23] = RCAR_GP_PIN(0, 23), /* MMC_SD_CLK */
4104 [24] = RCAR_GP_PIN(0, 24), /* MMC_D4 */
4105 [25] = RCAR_GP_PIN(0, 25), /* MMC_D5 */
4106 [26] = RCAR_GP_PIN(0, 26), /* MMC_D6 */
4107 [27] = RCAR_GP_PIN(0, 27), /* MMC_D7 */
4108 [28] = SH_PFC_PIN_NONE,
4109 [29] = SH_PFC_PIN_NONE,
4110 [30] = SH_PFC_PIN_NONE,
4111 [31] = SH_PFC_PIN_NONE,
4113 { PINMUX_BIAS_REG("PUEN1", 0xe60500c0, "PUD1", 0xe60500e0) {
4114 [ 0] = RCAR_GP_PIN(1, 0), /* SCIF_CLK */
4115 [ 1] = RCAR_GP_PIN(1, 1), /* HRX0 */
4116 [ 2] = RCAR_GP_PIN(1, 2), /* HSCK0 */
4117 [ 3] = RCAR_GP_PIN(1, 3), /* HRTS0_N */
4118 [ 4] = RCAR_GP_PIN(1, 4), /* HCTS0_N */
4119 [ 5] = RCAR_GP_PIN(1, 5), /* HTX0 */
4120 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_RXD */
4121 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_TXD */
4122 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SCK */
4123 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_SYNC */
4124 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SS1 */
4125 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_SS2 */
4126 [12] = RCAR_GP_PIN(1, 12), /* MSIOF1_RXD */
4127 [13] = RCAR_GP_PIN(1, 13), /* MSIOF1_TXD */
4128 [14] = RCAR_GP_PIN(1, 14), /* MSIOF1_SCK */
4129 [15] = RCAR_GP_PIN(1, 15), /* MSIOF1_SYNC */
4130 [16] = RCAR_GP_PIN(1, 16), /* MSIOF1_SS1 */
4131 [17] = RCAR_GP_PIN(1, 17), /* MSIOF1_SS2 */
4132 [18] = RCAR_GP_PIN(1, 18), /* MSIOF2_RXD */
4133 [19] = RCAR_GP_PIN(1, 19), /* MSIOF2_TXD */
4134 [20] = RCAR_GP_PIN(1, 20), /* MSIOF2_SCK */
4135 [21] = RCAR_GP_PIN(1, 21), /* MSIOF2_SYNC */
4136 [22] = RCAR_GP_PIN(1, 22), /* MSIOF2_SS1 */
4137 [23] = RCAR_GP_PIN(1, 23), /* MSIOF2_SS2 */
4138 [24] = RCAR_GP_PIN(1, 24), /* IRQ0 */
4139 [25] = RCAR_GP_PIN(1, 25), /* IRQ1 */
4140 [26] = RCAR_GP_PIN(1, 26), /* IRQ2 */
4141 [27] = RCAR_GP_PIN(1, 27), /* IRQ3 */
4142 [28] = RCAR_GP_PIN(1, 28), /* GP1_28 */
4143 [29] = RCAR_GP_PIN(1, 29), /* GP1_29 */
4144 [30] = RCAR_GP_PIN(1, 30), /* GP1_30 */
4145 [31] = SH_PFC_PIN_NONE,
4147 { PINMUX_BIAS_REG("PUEN2", 0xe60508c0, "PUD2", 0xe60508e0) {
4148 [ 0] = RCAR_GP_PIN(2, 0), /* IPC_CLKIN */
4149 [ 1] = RCAR_GP_PIN(2, 1), /* IPC_CLKOUT */
4150 [ 2] = RCAR_GP_PIN(2, 2), /* GP2_02 */
4151 [ 3] = RCAR_GP_PIN(2, 3), /* GP2_03 */
4152 [ 4] = RCAR_GP_PIN(2, 4), /* GP2_04 */
4153 [ 5] = RCAR_GP_PIN(2, 5), /* GP2_05 */
4154 [ 6] = RCAR_GP_PIN(2, 6), /* GP2_06 */
4155 [ 7] = RCAR_GP_PIN(2, 7), /* GP2_07 */
4156 [ 8] = RCAR_GP_PIN(2, 8), /* GP2_08 */
4157 [ 9] = RCAR_GP_PIN(2, 9), /* GP2_09 */
4158 [10] = RCAR_GP_PIN(2, 10), /* GP2_10 */
4159 [11] = RCAR_GP_PIN(2, 11), /* GP2_11 */
4160 [12] = RCAR_GP_PIN(2, 12), /* GP2_12 */
4161 [13] = RCAR_GP_PIN(2, 13), /* GP2_13 */
4162 [14] = RCAR_GP_PIN(2, 14), /* GP2_14 */
4163 [15] = RCAR_GP_PIN(2, 15), /* GP2_15 */
4164 [16] = RCAR_GP_PIN(2, 16), /* FXR_TXDA_A */
4165 [17] = RCAR_GP_PIN(2, 17), /* RXDA_EXTFXR_A */
4166 [18] = RCAR_GP_PIN(2, 18), /* FXR_TXDB */
4167 [19] = RCAR_GP_PIN(2, 19), /* RXDB_EXTFXR */
4168 [20] = RCAR_GP_PIN(2, 20), /* CLK_EXTFXR */
4169 [21] = RCAR_GP_PIN(2, 21), /* TPU0TO0 */
4170 [22] = RCAR_GP_PIN(2, 22), /* TPU0TO1 */
4171 [23] = RCAR_GP_PIN(2, 23), /* TCLK1_A */
4172 [24] = RCAR_GP_PIN(2, 24), /* TCLK2_A */
4173 [25] = SH_PFC_PIN_NONE,
4174 [26] = SH_PFC_PIN_NONE,
4175 [27] = SH_PFC_PIN_NONE,
4176 [28] = SH_PFC_PIN_NONE,
4177 [29] = SH_PFC_PIN_NONE,
4178 [30] = SH_PFC_PIN_NONE,
4179 [31] = SH_PFC_PIN_NONE,
4181 { PINMUX_BIAS_REG("PUEN3", 0xe60588c0, "PUD3", 0xe60588e0) {
4182 [ 0] = RCAR_GP_PIN(3, 0), /* CAN_CLK */
4183 [ 1] = RCAR_GP_PIN(3, 1), /* CANFD0_TX */
4184 [ 2] = RCAR_GP_PIN(3, 2), /* CANFD0_RX */
4185 [ 3] = RCAR_GP_PIN(3, 3), /* CANFD1_TX */
4186 [ 4] = RCAR_GP_PIN(3, 4), /* CANFD1_RX */
4187 [ 5] = RCAR_GP_PIN(3, 5), /* CANFD2_TX */
4188 [ 6] = RCAR_GP_PIN(3, 6), /* CANFD2_RX */
4189 [ 7] = RCAR_GP_PIN(3, 7), /* CANFD3_TX */
4190 [ 8] = RCAR_GP_PIN(3, 8), /* CANFD3_RX */
4191 [ 9] = RCAR_GP_PIN(3, 9), /* CANFD4_TX */
4192 [10] = RCAR_GP_PIN(3, 10), /* CANFD4_RX */
4193 [11] = RCAR_GP_PIN(3, 11), /* CANFD5_TX */
4194 [12] = RCAR_GP_PIN(3, 12), /* CANFD5_RX */
4195 [13] = RCAR_GP_PIN(3, 13), /* CANFD6_TX */
4196 [14] = RCAR_GP_PIN(3, 14), /* CANFD6_RX */
4197 [15] = RCAR_GP_PIN(3, 15), /* CANFD7_TX */
4198 [16] = RCAR_GP_PIN(3, 16), /* CANFD7_RX */
4199 [17] = SH_PFC_PIN_NONE,
4200 [18] = SH_PFC_PIN_NONE,
4201 [19] = SH_PFC_PIN_NONE,
4202 [20] = SH_PFC_PIN_NONE,
4203 [21] = SH_PFC_PIN_NONE,
4204 [22] = SH_PFC_PIN_NONE,
4205 [23] = SH_PFC_PIN_NONE,
4206 [24] = SH_PFC_PIN_NONE,
4207 [25] = SH_PFC_PIN_NONE,
4208 [26] = SH_PFC_PIN_NONE,
4209 [27] = SH_PFC_PIN_NONE,
4210 [28] = SH_PFC_PIN_NONE,
4211 [29] = SH_PFC_PIN_NONE,
4212 [30] = SH_PFC_PIN_NONE,
4213 [31] = SH_PFC_PIN_NONE,
4215 { PINMUX_BIAS_REG("PUEN4", 0xe60600c0, "PUD4", 0xe60600e0) {
4216 [ 0] = RCAR_GP_PIN(4, 0), /* AVB0_RX_CTL */
4217 [ 1] = RCAR_GP_PIN(4, 1), /* AVB0_RXC */
4218 [ 2] = RCAR_GP_PIN(4, 2), /* AVB0_RD0 */
4219 [ 3] = RCAR_GP_PIN(4, 3), /* AVB0_RD1 */
4220 [ 4] = RCAR_GP_PIN(4, 4), /* AVB0_RD2 */
4221 [ 5] = RCAR_GP_PIN(4, 5), /* AVB0_RD3 */
4222 [ 6] = RCAR_GP_PIN(4, 6), /* AVB0_TX_CTL */
4223 [ 7] = RCAR_GP_PIN(4, 7), /* AVB0_TXC */
4224 [ 8] = RCAR_GP_PIN(4, 8), /* AVB0_TD0 */
4225 [ 9] = RCAR_GP_PIN(4, 9), /* AVB0_TD1 */
4226 [10] = RCAR_GP_PIN(4, 10), /* AVB0_TD2 */
4227 [11] = RCAR_GP_PIN(4, 11), /* AVB0_TD3 */
4228 [12] = RCAR_GP_PIN(4, 12), /* AVB0_TXREFCLK */
4229 [13] = RCAR_GP_PIN(4, 13), /* AVB0_MDIO */
4230 [14] = RCAR_GP_PIN(4, 14), /* AVB0_MDC */
4231 [15] = RCAR_GP_PIN(4, 15), /* AVB0_MAGIC */
4232 [16] = RCAR_GP_PIN(4, 16), /* AVB0_PHY_INT */
4233 [17] = RCAR_GP_PIN(4, 17), /* AVB0_LINK */
4234 [18] = RCAR_GP_PIN(4, 18), /* AVB0_AVTP_MATCH */
4235 [19] = RCAR_GP_PIN(4, 19), /* AVB0_AVTP_CAPTURE */
4236 [20] = RCAR_GP_PIN(4, 20), /* AVB0_AVTP_PPS */
4237 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
4238 [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */
4239 [23] = RCAR_GP_PIN(4, 23), /* PCIE2_CLKREQ_N */
4240 [24] = RCAR_GP_PIN(4, 24), /* PCIE3_CLKREQ_N */
4241 [25] = RCAR_GP_PIN(4, 25), /* AVS0 */
4242 [26] = RCAR_GP_PIN(4, 26), /* AVS1 */
4243 [27] = SH_PFC_PIN_NONE,
4244 [28] = SH_PFC_PIN_NONE,
4245 [29] = SH_PFC_PIN_NONE,
4246 [30] = SH_PFC_PIN_NONE,
4247 [31] = SH_PFC_PIN_NONE,
4249 { PINMUX_BIAS_REG("PUEN5", 0xe60608c0, "PUD5", 0xe60608e0) {
4250 [ 0] = RCAR_GP_PIN(5, 0), /* AVB1_RX_CTL */
4251 [ 1] = RCAR_GP_PIN(5, 1), /* AVB1_RXC */
4252 [ 2] = RCAR_GP_PIN(5, 2), /* AVB1_RD0 */
4253 [ 3] = RCAR_GP_PIN(5, 3), /* AVB1_RD1 */
4254 [ 4] = RCAR_GP_PIN(5, 4), /* AVB1_RD2 */
4255 [ 5] = RCAR_GP_PIN(5, 5), /* AVB1_RD3 */
4256 [ 6] = RCAR_GP_PIN(5, 6), /* AVB1_TX_CTL */
4257 [ 7] = RCAR_GP_PIN(5, 7), /* AVB1_TXC */
4258 [ 8] = RCAR_GP_PIN(5, 8), /* AVB1_TD0 */
4259 [ 9] = RCAR_GP_PIN(5, 9), /* AVB1_TD1 */
4260 [10] = RCAR_GP_PIN(5, 10), /* AVB1_TD2 */
4261 [11] = RCAR_GP_PIN(5, 11), /* AVB1_TD3 */
4262 [12] = RCAR_GP_PIN(5, 12), /* AVB1_TXCREFCLK */
4263 [13] = RCAR_GP_PIN(5, 13), /* AVB1_MDIO */
4264 [14] = RCAR_GP_PIN(5, 14), /* AVB1_MDC */
4265 [15] = RCAR_GP_PIN(5, 15), /* AVB1_MAGIC */
4266 [16] = RCAR_GP_PIN(5, 16), /* AVB1_PHY_INT */
4267 [17] = RCAR_GP_PIN(5, 17), /* AVB1_LINK */
4268 [18] = RCAR_GP_PIN(5, 18), /* AVB1_AVTP_MATCH */
4269 [19] = RCAR_GP_PIN(5, 19), /* AVB1_AVTP_CAPTURE */
4270 [20] = RCAR_GP_PIN(5, 20), /* AVB1_AVTP_PPS */
4271 [21] = SH_PFC_PIN_NONE,
4272 [22] = SH_PFC_PIN_NONE,
4273 [23] = SH_PFC_PIN_NONE,
4274 [24] = SH_PFC_PIN_NONE,
4275 [25] = SH_PFC_PIN_NONE,
4276 [26] = SH_PFC_PIN_NONE,
4277 [27] = SH_PFC_PIN_NONE,
4278 [28] = SH_PFC_PIN_NONE,
4279 [29] = SH_PFC_PIN_NONE,
4280 [30] = SH_PFC_PIN_NONE,
4281 [31] = SH_PFC_PIN_NONE,
4283 { PINMUX_BIAS_REG("PUEN6", 0xe60680c0, "PUD6", 0xe60680e0) {
4284 [ 0] = RCAR_GP_PIN(6, 0), /* AVB2_RX_CTL */
4285 [ 1] = RCAR_GP_PIN(6, 1), /* AVB2_RXC */
4286 [ 2] = RCAR_GP_PIN(6, 2), /* AVB2_RD0 */
4287 [ 3] = RCAR_GP_PIN(6, 3), /* AVB2_RD1 */
4288 [ 4] = RCAR_GP_PIN(6, 4), /* AVB2_RD2 */
4289 [ 5] = RCAR_GP_PIN(6, 5), /* AVB2_RD3 */
4290 [ 6] = RCAR_GP_PIN(6, 6), /* AVB2_TX_CTL */
4291 [ 7] = RCAR_GP_PIN(6, 7), /* AVB2_TXC */
4292 [ 8] = RCAR_GP_PIN(6, 8), /* AVB2_TD0 */
4293 [ 9] = RCAR_GP_PIN(6, 9), /* AVB2_TD1 */
4294 [10] = RCAR_GP_PIN(6, 10), /* AVB2_TD2 */
4295 [11] = RCAR_GP_PIN(6, 11), /* AVB2_TD3 */
4296 [12] = RCAR_GP_PIN(6, 12), /* AVB2_TXCREFCLK */
4297 [13] = RCAR_GP_PIN(6, 13), /* AVB2_MDIO */
4298 [14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC */
4299 [15] = RCAR_GP_PIN(6, 15), /* AVB2_MAGIC */
4300 [16] = RCAR_GP_PIN(6, 16), /* AVB2_PHY_INT */
4301 [17] = RCAR_GP_PIN(6, 17), /* AVB2_LINK */
4302 [18] = RCAR_GP_PIN(6, 18), /* AVB2_AVTP_MATCH */
4303 [19] = RCAR_GP_PIN(6, 19), /* AVB2_AVTP_CAPTURE */
4304 [20] = RCAR_GP_PIN(6, 20), /* AVB2_AVTP_PPS */
4305 [21] = SH_PFC_PIN_NONE,
4306 [22] = SH_PFC_PIN_NONE,
4307 [23] = SH_PFC_PIN_NONE,
4308 [24] = SH_PFC_PIN_NONE,
4309 [25] = SH_PFC_PIN_NONE,
4310 [26] = SH_PFC_PIN_NONE,
4311 [27] = SH_PFC_PIN_NONE,
4312 [28] = SH_PFC_PIN_NONE,
4313 [29] = SH_PFC_PIN_NONE,
4314 [30] = SH_PFC_PIN_NONE,
4315 [31] = SH_PFC_PIN_NONE,
4317 { PINMUX_BIAS_REG("PUEN7", 0xe60688c0, "PUD7", 0xe60688e0) {
4318 [ 0] = RCAR_GP_PIN(7, 0), /* AVB3_RX_CTL */
4319 [ 1] = RCAR_GP_PIN(7, 1), /* AVB3_RXC */
4320 [ 2] = RCAR_GP_PIN(7, 2), /* AVB3_RD0 */
4321 [ 3] = RCAR_GP_PIN(7, 3), /* AVB3_RD1 */
4322 [ 4] = RCAR_GP_PIN(7, 4), /* AVB3_RD2 */
4323 [ 5] = RCAR_GP_PIN(7, 5), /* AVB3_RD3 */
4324 [ 6] = RCAR_GP_PIN(7, 6), /* AVB3_TX_CTL */
4325 [ 7] = RCAR_GP_PIN(7, 7), /* AVB3_TXC */
4326 [ 8] = RCAR_GP_PIN(7, 8), /* AVB3_TD0 */
4327 [ 9] = RCAR_GP_PIN(7, 9), /* AVB3_TD1 */
4328 [10] = RCAR_GP_PIN(7, 10), /* AVB3_TD2 */
4329 [11] = RCAR_GP_PIN(7, 11), /* AVB3_TD3 */
4330 [12] = RCAR_GP_PIN(7, 12), /* AVB3_TXCREFCLK */
4331 [13] = RCAR_GP_PIN(7, 13), /* AVB3_MDIO */
4332 [14] = RCAR_GP_PIN(7, 14), /* AVB3_MDC */
4333 [15] = RCAR_GP_PIN(7, 15), /* AVB3_MAGIC */
4334 [16] = RCAR_GP_PIN(7, 16), /* AVB3_PHY_INT */
4335 [17] = RCAR_GP_PIN(7, 17), /* AVB3_LINK */
4336 [18] = RCAR_GP_PIN(7, 18), /* AVB3_AVTP_MATCH */
4337 [19] = RCAR_GP_PIN(7, 19), /* AVB3_AVTP_CAPTURE */
4338 [20] = RCAR_GP_PIN(7, 20), /* AVB3_AVTP_PPS */
4339 [21] = SH_PFC_PIN_NONE,
4340 [22] = SH_PFC_PIN_NONE,
4341 [23] = SH_PFC_PIN_NONE,
4342 [24] = SH_PFC_PIN_NONE,
4343 [25] = SH_PFC_PIN_NONE,
4344 [26] = SH_PFC_PIN_NONE,
4345 [27] = SH_PFC_PIN_NONE,
4346 [28] = SH_PFC_PIN_NONE,
4347 [29] = SH_PFC_PIN_NONE,
4348 [30] = SH_PFC_PIN_NONE,
4349 [31] = SH_PFC_PIN_NONE,
4351 { PINMUX_BIAS_REG("PUEN8", 0xe60690c0, "PUD8", 0xe60690e0) {
4352 [ 0] = RCAR_GP_PIN(8, 0), /* AVB4_RX_CTL */
4353 [ 1] = RCAR_GP_PIN(8, 1), /* AVB4_RXC */
4354 [ 2] = RCAR_GP_PIN(8, 2), /* AVB4_RD0 */
4355 [ 3] = RCAR_GP_PIN(8, 3), /* AVB4_RD1 */
4356 [ 4] = RCAR_GP_PIN(8, 4), /* AVB4_RD2 */
4357 [ 5] = RCAR_GP_PIN(8, 5), /* AVB4_RD3 */
4358 [ 6] = RCAR_GP_PIN(8, 6), /* AVB4_TX_CTL */
4359 [ 7] = RCAR_GP_PIN(8, 7), /* AVB4_TXC */
4360 [ 8] = RCAR_GP_PIN(8, 8), /* AVB4_TD0 */
4361 [ 9] = RCAR_GP_PIN(8, 9), /* AVB4_TD1 */
4362 [10] = RCAR_GP_PIN(8, 10), /* AVB4_TD2 */
4363 [11] = RCAR_GP_PIN(8, 11), /* AVB4_TD3 */
4364 [12] = RCAR_GP_PIN(8, 12), /* AVB4_TXCREFCLK */
4365 [13] = RCAR_GP_PIN(8, 13), /* AVB4_MDIO */
4366 [14] = RCAR_GP_PIN(8, 14), /* AVB4_MDC */
4367 [15] = RCAR_GP_PIN(8, 15), /* AVB4_MAGIC */
4368 [16] = RCAR_GP_PIN(8, 16), /* AVB4_PHY_INT */
4369 [17] = RCAR_GP_PIN(8, 17), /* AVB4_LINK */
4370 [18] = RCAR_GP_PIN(8, 18), /* AVB4_AVTP_MATCH */
4371 [19] = RCAR_GP_PIN(8, 19), /* AVB4_AVTP_CAPTURE */
4372 [20] = RCAR_GP_PIN(8, 20), /* AVB4_AVTP_PPS */
4373 [21] = SH_PFC_PIN_NONE,
4374 [22] = SH_PFC_PIN_NONE,
4375 [23] = SH_PFC_PIN_NONE,
4376 [24] = SH_PFC_PIN_NONE,
4377 [25] = SH_PFC_PIN_NONE,
4378 [26] = SH_PFC_PIN_NONE,
4379 [27] = SH_PFC_PIN_NONE,
4380 [28] = SH_PFC_PIN_NONE,
4381 [29] = SH_PFC_PIN_NONE,
4382 [30] = SH_PFC_PIN_NONE,
4383 [31] = SH_PFC_PIN_NONE,
4385 { PINMUX_BIAS_REG("PUEN9", 0xe60698c0, "PUD9", 0xe60698e0) {
4386 [ 0] = RCAR_GP_PIN(9, 0), /* AVB5_RX_CTL */
4387 [ 1] = RCAR_GP_PIN(9, 1), /* AVB5_RXC */
4388 [ 2] = RCAR_GP_PIN(9, 2), /* AVB5_RD0 */
4389 [ 3] = RCAR_GP_PIN(9, 3), /* AVB5_RD1 */
4390 [ 4] = RCAR_GP_PIN(9, 4), /* AVB5_RD2 */
4391 [ 5] = RCAR_GP_PIN(9, 5), /* AVB5_RD3 */
4392 [ 6] = RCAR_GP_PIN(9, 6), /* AVB5_TX_CTL */
4393 [ 7] = RCAR_GP_PIN(9, 7), /* AVB5_TXC */
4394 [ 8] = RCAR_GP_PIN(9, 8), /* AVB5_TD0 */
4395 [ 9] = RCAR_GP_PIN(9, 9), /* AVB5_TD1 */
4396 [10] = RCAR_GP_PIN(9, 10), /* AVB5_TD2 */
4397 [11] = RCAR_GP_PIN(9, 11), /* AVB5_TD3 */
4398 [12] = RCAR_GP_PIN(9, 12), /* AVB5_TXCREFCLK */
4399 [13] = RCAR_GP_PIN(9, 13), /* AVB5_MDIO */
4400 [14] = RCAR_GP_PIN(9, 14), /* AVB5_MDC */
4401 [15] = RCAR_GP_PIN(9, 15), /* AVB5_MAGIC */
4402 [16] = RCAR_GP_PIN(9, 16), /* AVB5_PHY_INT */
4403 [17] = RCAR_GP_PIN(9, 17), /* AVB5_LINK */
4404 [18] = RCAR_GP_PIN(9, 18), /* AVB5_AVTP_MATCH */
4405 [19] = RCAR_GP_PIN(9, 19), /* AVB5_AVTP_CAPTURE */
4406 [20] = RCAR_GP_PIN(9, 20), /* AVB5_AVTP_PPS */
4407 [21] = SH_PFC_PIN_NONE,
4408 [22] = SH_PFC_PIN_NONE,
4409 [23] = SH_PFC_PIN_NONE,
4410 [24] = SH_PFC_PIN_NONE,
4411 [25] = SH_PFC_PIN_NONE,
4412 [26] = SH_PFC_PIN_NONE,
4413 [27] = SH_PFC_PIN_NONE,
4414 [28] = SH_PFC_PIN_NONE,
4415 [29] = SH_PFC_PIN_NONE,
4416 [30] = SH_PFC_PIN_NONE,
4417 [31] = SH_PFC_PIN_NONE,
4422 static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = {
4423 .pin_to_pocctrl = r8a779a0_pin_to_pocctrl,
4424 .get_bias = rcar_pinmux_get_bias,
4425 .set_bias = rcar_pinmux_set_bias,
4428 const struct sh_pfc_soc_info r8a779a0_pinmux_info = {
4429 .name = "r8a779a0_pfc",
4430 .ops = &r8a779a0_pfc_ops,
4431 .unlock_reg = 0x1ff, /* PMMRn mask */
4433 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4435 .pins = pinmux_pins,
4436 .nr_pins = ARRAY_SIZE(pinmux_pins),
4437 .groups = pinmux_groups,
4438 .nr_groups = ARRAY_SIZE(pinmux_groups),
4439 .functions = pinmux_functions,
4440 .nr_functions = ARRAY_SIZE(pinmux_functions),
4442 .cfg_regs = pinmux_config_regs,
4443 .drive_regs = pinmux_drive_regs,
4444 .bias_regs = pinmux_bias_regs,
4445 .ioctrl_regs = pinmux_ioctrl_regs,
4447 .pinmux_data = pinmux_data,
4448 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
projects / platform / kernel / linux-starfive.git / blob