drivers/pinctrl/renesas/pfc-r8a7796.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
   4  *
   5  * Copyright (C) 2016-2019 Renesas Electronics Corp.
   6  *
   7  * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
   8  *
   9  * R-Car Gen3 processor support - PFC hardware block.
  10  *
  11  * Copyright (C) 2015  Renesas Electronics Corporation
  12  */
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <dm/pinctrl.h>
  18 #include <linux/kernel.h>
  19
  20 #include "sh_pfc.h"
  21
  22 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
  23
  24 #define CPU_ALL_GP(fn, sfx)                                             \
  25         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  26         PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
  27         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  28         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  29         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  30         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  31         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  32         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  33         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  34         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  35         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  36         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  37
  38 #define CPU_ALL_NOGP(fn)                                                \
  39         PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS),                  \
  40         PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS),              \
  41         PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS),                \
  42         PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS),                \
  43         PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS),                \
  44         PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS),                \
  45         PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS),                \
  46         PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS),          \
  47         PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS),                \
  48         PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS),                \
  49         PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS),                \
  50         PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS),                \
  51         PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS),                \
  52         PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS),    \
  53         PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),          \
  54         PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS),      \
  55         PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS),      \
  56         PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS),      \
  57         PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
  58         PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS),                \
  59         PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),                \
  60         PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS),         \
  61         PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS),            \
  62         PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS),            \
  63         PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS),  \
  64         PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS),  \
  65         PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS),        \
  66         PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS),            \
  67         PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS),            \
  68         PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS),            \
  69         PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS),  \
  70         PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS),  \
  71         PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS),        \
  72         PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS),            \
  73         PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\
  74         PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS),             \
  75         PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS),         \
  76         PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS),               \
  77         PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),      \
  78         PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),      \
  79         PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH),    \
  80         PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS),                        \
  81         PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
  82
  83 /*
  84  * F_() : just information
  85  * FM() : macro for FN_xxx / xxx_MARK
  86  */
  87
  88 /* GPSR0 */
  89 #define GPSR0_15        F_(D15,                 IP7_11_8)
  90 #define GPSR0_14        F_(D14,                 IP7_7_4)
  91 #define GPSR0_13        F_(D13,                 IP7_3_0)
  92 #define GPSR0_12        F_(D12,                 IP6_31_28)
  93 #define GPSR0_11        F_(D11,                 IP6_27_24)
  94 #define GPSR0_10        F_(D10,                 IP6_23_20)
  95 #define GPSR0_9         F_(D9,                  IP6_19_16)
  96 #define GPSR0_8         F_(D8,                  IP6_15_12)
  97 #define GPSR0_7         F_(D7,                  IP6_11_8)
  98 #define GPSR0_6         F_(D6,                  IP6_7_4)
  99 #define GPSR0_5         F_(D5,                  IP6_3_0)
 100 #define GPSR0_4         F_(D4,                  IP5_31_28)
 101 #define GPSR0_3         F_(D3,                  IP5_27_24)
 102 #define GPSR0_2         F_(D2,                  IP5_23_20)
 103 #define GPSR0_1         F_(D1,                  IP5_19_16)
 104 #define GPSR0_0         F_(D0,                  IP5_15_12)
 105
 106 /* GPSR1 */
 107 #define GPSR1_28        FM(CLKOUT)
 108 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
 109 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
 110 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
 111 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
 112 #define GPSR1_23        F_(RD_N,                IP4_27_24)
 113 #define GPSR1_22        F_(BS_N,                IP4_23_20)
 114 #define GPSR1_21        F_(CS1_N,               IP4_19_16)
 115 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
 116 #define GPSR1_19        F_(A19,                 IP4_11_8)
 117 #define GPSR1_18        F_(A18,                 IP4_7_4)
 118 #define GPSR1_17        F_(A17,                 IP4_3_0)
 119 #define GPSR1_16        F_(A16,                 IP3_31_28)
 120 #define GPSR1_15        F_(A15,                 IP3_27_24)
 121 #define GPSR1_14        F_(A14,                 IP3_23_20)
 122 #define GPSR1_13        F_(A13,                 IP3_19_16)
 123 #define GPSR1_12        F_(A12,                 IP3_15_12)
 124 #define GPSR1_11        F_(A11,                 IP3_11_8)
 125 #define GPSR1_10        F_(A10,                 IP3_7_4)
 126 #define GPSR1_9         F_(A9,                  IP3_3_0)
 127 #define GPSR1_8         F_(A8,                  IP2_31_28)
 128 #define GPSR1_7         F_(A7,                  IP2_27_24)
 129 #define GPSR1_6         F_(A6,                  IP2_23_20)
 130 #define GPSR1_5         F_(A5,                  IP2_19_16)
 131 #define GPSR1_4         F_(A4,                  IP2_15_12)
 132 #define GPSR1_3         F_(A3,                  IP2_11_8)
 133 #define GPSR1_2         F_(A2,                  IP2_7_4)
 134 #define GPSR1_1         F_(A1,                  IP2_3_0)
 135 #define GPSR1_0         F_(A0,                  IP1_31_28)
 136
 137 /* GPSR2 */
 138 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
 139 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
 140 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
 141 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
 142 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
 143 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
 144 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
 145 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
 146 #define GPSR2_6         F_(PWM0,                IP1_19_16)
 147 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
 148 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
 149 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
 150 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
 151 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
 152 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
 153
 154 /* GPSR3 */
 155 #define GPSR3_15        F_(SD1_WP,              IP11_23_20)
 156 #define GPSR3_14        F_(SD1_CD,              IP11_19_16)
 157 #define GPSR3_13        F_(SD0_WP,              IP11_15_12)
 158 #define GPSR3_12        F_(SD0_CD,              IP11_11_8)
 159 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 160 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 161 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 162 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 163 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 164 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 165 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 166 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 167 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 168 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 169 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 170 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 171
 172 /* GPSR4 */
 173 #define GPSR4_17        F_(SD3_DS,              IP11_7_4)
 174 #define GPSR4_16        F_(SD3_DAT7,            IP11_3_0)
 175 #define GPSR4_15        F_(SD3_DAT6,            IP10_31_28)
 176 #define GPSR4_14        F_(SD3_DAT5,            IP10_27_24)
 177 #define GPSR4_13        F_(SD3_DAT4,            IP10_23_20)
 178 #define GPSR4_12        F_(SD3_DAT3,            IP10_19_16)
 179 #define GPSR4_11        F_(SD3_DAT2,            IP10_15_12)
 180 #define GPSR4_10        F_(SD3_DAT1,            IP10_11_8)
 181 #define GPSR4_9         F_(SD3_DAT0,            IP10_7_4)
 182 #define GPSR4_8         F_(SD3_CMD,             IP10_3_0)
 183 #define GPSR4_7         F_(SD3_CLK,             IP9_31_28)
 184 #define GPSR4_6         F_(SD2_DS,              IP9_27_24)
 185 #define GPSR4_5         F_(SD2_DAT3,            IP9_23_20)
 186 #define GPSR4_4         F_(SD2_DAT2,            IP9_19_16)
 187 #define GPSR4_3         F_(SD2_DAT1,            IP9_15_12)
 188 #define GPSR4_2         F_(SD2_DAT0,            IP9_11_8)
 189 #define GPSR4_1         F_(SD2_CMD,             IP9_7_4)
 190 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 191
 192 /* GPSR5 */
 193 #define GPSR5_25        F_(MLB_DAT,             IP14_19_16)
 194 #define GPSR5_24        F_(MLB_SIG,             IP14_15_12)
 195 #define GPSR5_23        F_(MLB_CLK,             IP14_11_8)
 196 #define GPSR5_22        FM(MSIOF0_RXD)
 197 #define GPSR5_21        F_(MSIOF0_SS2,          IP14_7_4)
 198 #define GPSR5_20        FM(MSIOF0_TXD)
 199 #define GPSR5_19        F_(MSIOF0_SS1,          IP14_3_0)
 200 #define GPSR5_18        F_(MSIOF0_SYNC,         IP13_31_28)
 201 #define GPSR5_17        FM(MSIOF0_SCK)
 202 #define GPSR5_16        F_(HRTS0_N,             IP13_27_24)
 203 #define GPSR5_15        F_(HCTS0_N,             IP13_23_20)
 204 #define GPSR5_14        F_(HTX0,                IP13_19_16)
 205 #define GPSR5_13        F_(HRX0,                IP13_15_12)
 206 #define GPSR5_12        F_(HSCK0,               IP13_11_8)
 207 #define GPSR5_11        F_(RX2_A,               IP13_7_4)
 208 #define GPSR5_10        F_(TX2_A,               IP13_3_0)
 209 #define GPSR5_9         F_(SCK2,                IP12_31_28)
 210 #define GPSR5_8         F_(RTS1_N,              IP12_27_24)
 211 #define GPSR5_7         F_(CTS1_N,              IP12_23_20)
 212 #define GPSR5_6         F_(TX1_A,               IP12_19_16)
 213 #define GPSR5_5         F_(RX1_A,               IP12_15_12)
 214 #define GPSR5_4         F_(RTS0_N,              IP12_11_8)
 215 #define GPSR5_3         F_(CTS0_N,              IP12_7_4)
 216 #define GPSR5_2         F_(TX0,                 IP12_3_0)
 217 #define GPSR5_1         F_(RX0,                 IP11_31_28)
 218 #define GPSR5_0         F_(SCK0,                IP11_27_24)
 219
 220 /* GPSR6 */
 221 #define GPSR6_31        F_(GP6_31,              IP18_7_4)
 222 #define GPSR6_30        F_(GP6_30,              IP18_3_0)
 223 #define GPSR6_29        F_(USB30_OVC,           IP17_31_28)
 224 #define GPSR6_28        F_(USB30_PWEN,          IP17_27_24)
 225 #define GPSR6_27        F_(USB1_OVC,            IP17_23_20)
 226 #define GPSR6_26        F_(USB1_PWEN,           IP17_19_16)
 227 #define GPSR6_25        F_(USB0_OVC,            IP17_15_12)
 228 #define GPSR6_24        F_(USB0_PWEN,           IP17_11_8)
 229 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP17_7_4)
 230 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP17_3_0)
 231 #define GPSR6_21        F_(SSI_SDATA9_A,        IP16_31_28)
 232 #define GPSR6_20        F_(SSI_SDATA8,          IP16_27_24)
 233 #define GPSR6_19        F_(SSI_SDATA7,          IP16_23_20)
 234 #define GPSR6_18        F_(SSI_WS78,            IP16_19_16)
 235 #define GPSR6_17        F_(SSI_SCK78,           IP16_15_12)
 236 #define GPSR6_16        F_(SSI_SDATA6,          IP16_11_8)
 237 #define GPSR6_15        F_(SSI_WS6,             IP16_7_4)
 238 #define GPSR6_14        F_(SSI_SCK6,            IP16_3_0)
 239 #define GPSR6_13        FM(SSI_SDATA5)
 240 #define GPSR6_12        FM(SSI_WS5)
 241 #define GPSR6_11        FM(SSI_SCK5)
 242 #define GPSR6_10        F_(SSI_SDATA4,          IP15_31_28)
 243 #define GPSR6_9         F_(SSI_WS4,             IP15_27_24)
 244 #define GPSR6_8         F_(SSI_SCK4,            IP15_23_20)
 245 #define GPSR6_7         F_(SSI_SDATA3,          IP15_19_16)
 246 #define GPSR6_6         F_(SSI_WS349,           IP15_15_12)
 247 #define GPSR6_5         F_(SSI_SCK349,          IP15_11_8)
 248 #define GPSR6_4         F_(SSI_SDATA2_A,        IP15_7_4)
 249 #define GPSR6_3         F_(SSI_SDATA1_A,        IP15_3_0)
 250 #define GPSR6_2         F_(SSI_SDATA0,          IP14_31_28)
 251 #define GPSR6_1         F_(SSI_WS01239,         IP14_27_24)
 252 #define GPSR6_0         F_(SSI_SCK01239,        IP14_23_20)
 253
 254 /* GPSR7 */
 255 #define GPSR7_3         FM(GP7_03)
 256 #define GPSR7_2         FM(GP7_02)
 257 #define GPSR7_1         FM(AVS2)
 258 #define GPSR7_0         FM(AVS1)
 259
 260
 261 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 262 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         FM(MSIOF3_SS2_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         FM(MSIOF3_SS1_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SYNC_E) F_(0, 0)              FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   F_(0, 0)                FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SCK_E) F_(0, 0)               FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    F_(0, 0)                FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_RXD_E) F_(0, 0)               FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    F_(0, 0)                FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_TXD_E) F_(0, 0)               FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 275 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        F_(0, 0)                FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 276 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        F_(0, 0)                FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 277 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 278 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_B)                    F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289
 290 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 291 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP4_19_16       FM(CS1_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N)                      FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 313 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 314 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_C)    FM(DU_DR3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320
 321 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 322 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       FM(NFCE_N_B)                    F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        FM(NFWP_N_B)                    F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        FM(NFDATA14_B)                  F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 335 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        FM(NFDATA15_B)                  F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        FM(NFRB_N_B)                    F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        FM(NFDATA8)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP9_7_4         FM(SD2_CMD)             F_(0, 0)        FM(NFDATA9)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP9_11_8        FM(SD2_DAT0)            F_(0, 0)        FM(NFDATA10)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340 #define IP9_15_12       FM(SD2_DAT1)            F_(0, 0)        FM(NFDATA11)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341 #define IP9_19_16       FM(SD2_DAT2)            F_(0, 0)        FM(NFDATA12)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342 #define IP9_23_20       FM(SD2_DAT3)            F_(0, 0)        FM(NFDATA13)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 343 #define IP9_27_24       FM(SD2_DS)              F_(0, 0)        FM(NFALE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 344 #define IP9_31_28       FM(SD3_CLK)             F_(0, 0)        FM(NFWE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP10_3_0        FM(SD3_CMD)             F_(0, 0)        FM(NFRE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP10_7_4        FM(SD3_DAT0)            F_(0, 0)        FM(NFDATA0)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP10_11_8       FM(SD3_DAT1)            F_(0, 0)        FM(NFDATA1)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP10_15_12      FM(SD3_DAT2)            F_(0, 0)        FM(NFDATA2)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP10_19_16      FM(SD3_DAT3)            F_(0, 0)        FM(NFDATA3)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP10_23_20      FM(SD3_DAT4)            FM(SD2_CD_A)    FM(NFDATA4)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP10_27_24      FM(SD3_DAT5)            FM(SD2_WP_A)    FM(NFDATA5)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352 #define IP10_31_28      FM(SD3_DAT6)            FM(SD3_CD)      FM(NFDATA6)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353 #define IP11_3_0        FM(SD3_DAT7)            FM(SD3_WP)      FM(NFDATA7)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354 #define IP11_7_4        FM(SD3_DS)              F_(0, 0)        FM(NFCLE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355 #define IP11_11_8       FM(SD0_CD)              F_(0, 0)        FM(NFDATA14_A)          F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 356
 357 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 358 #define IP11_15_12      FM(SD0_WP)              F_(0, 0)        FM(NFDATA15_A)          F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 359 #define IP11_19_16      FM(SD1_CD)              F_(0, 0)        FM(NFRB_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 360 #define IP11_23_20      FM(SD1_WP)              F_(0, 0)        FM(NFCE_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 361 #define IP11_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     FM(SCK5_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 362 #define IP11_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 363 #define IP12_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 364 #define IP12_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 365 #define IP12_11_8       FM(RTS0_N)              FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 366 #define IP12_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 367 #define IP12_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 368 #define IP12_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 369 #define IP12_27_24      FM(RTS1_N)              FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 370 #define IP12_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 371 #define IP13_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 372 #define IP13_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 373 #define IP13_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        FM(RX5_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 374 #define IP13_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 375 #define IP13_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 376 #define IP13_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 377 #define IP13_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 378 #define IP13_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        FM(TX5_B)       F_(0, 0)        F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
 379 #define IP14_3_0        FM(MSIOF0_SS1)          FM(RX5_A)       FM(NFWP_N_A)            FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 380 #define IP14_7_4        FM(MSIOF0_SS2)          FM(TX5_A)       FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 381 #define IP14_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 382 #define IP14_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 383 #define IP14_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 384 #define IP14_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 385 #define IP14_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 386
 387 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 388 #define IP14_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 389 #define IP15_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 390 #define IP15_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 391 #define IP15_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 392 #define IP15_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 393 #define IP15_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 394 #define IP15_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 395 #define IP15_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 396 #define IP15_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 397 #define IP16_3_0        FM(SSI_SCK6)            F_(0, 0)        F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 398 #define IP16_7_4        FM(SSI_WS6)             F_(0, 0)        F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 399 #define IP16_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 400 #define IP16_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 401 #define IP16_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 402 #define IP16_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 403 #define IP16_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 404 #define IP16_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5_A)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 405 #define IP17_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 406 #define IP17_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 407 #define IP17_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
 408 #define IP17_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
 409 #define IP17_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
 410 #define IP17_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
 411 #define IP17_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 412 #define IP17_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_N)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 413 #define IP18_3_0        FM(GP6_30)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
 414 #define IP18_7_4        FM(GP6_31)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
 415
 416 #define PINMUX_GPSR     \
 417 \
 418                                                                                                 GPSR6_31 \
 419                                                                                                 GPSR6_30 \
 420                                                                                                 GPSR6_29 \
 421                 GPSR1_28                                                                        GPSR6_28 \
 422                 GPSR1_27                                                                        GPSR6_27 \
 423                 GPSR1_26                                                                        GPSR6_26 \
 424                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 425                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 426                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 427                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 428                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 429                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 430                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 431                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 432                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 433                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 434 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 435 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 436 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 437 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 438 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 439 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 440 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 441 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 442 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 443 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 444 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 445 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 446 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 447 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 448 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 449 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 450
 451 #define PINMUX_IPSR                             \
 452 \
 453 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 454 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 455 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 456 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 457 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 458 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 459 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 460 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 461 \
 462 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 463 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 464 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 465 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12 \
 466 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 467 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 468 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 469 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 470 \
 471 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 472 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 473 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 474 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 475 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 476 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 477 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 478 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 479 \
 480 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 481 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 482 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 483 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 484 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 485 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 486 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 487 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 488 \
 489 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0        FM(IP18_3_0)    IP18_3_0 \
 490 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4        FM(IP18_7_4)    IP18_7_4 \
 491 FM(IP16_11_8)   IP16_11_8       FM(IP17_11_8)   IP17_11_8 \
 492 FM(IP16_15_12)  IP16_15_12      FM(IP17_15_12)  IP17_15_12 \
 493 FM(IP16_19_16)  IP16_19_16      FM(IP17_19_16)  IP17_19_16 \
 494 FM(IP16_23_20)  IP16_23_20      FM(IP17_23_20)  IP17_23_20 \
 495 FM(IP16_27_24)  IP16_27_24      FM(IP17_27_24)  IP17_27_24 \
 496 FM(IP16_31_28)  IP16_31_28      FM(IP17_31_28)  IP17_31_28
 497
 498 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 499 #define MOD_SEL0_31_30_29       FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)        FM(SEL_MSIOF3_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 500 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 501 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 502 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 503 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 504 #define MOD_SEL0_21             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 505 #define MOD_SEL0_20             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 506 #define MOD_SEL0_19             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 507 #define MOD_SEL0_18_17          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 508 #define MOD_SEL0_16             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 509 #define MOD_SEL0_14_13          FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)        FM(SEL_HSCIF2_2)        F_(0, 0)
 510 #define MOD_SEL0_12             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 511 #define MOD_SEL0_11             FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 512 #define MOD_SEL0_10             FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 513 #define MOD_SEL0_9_8            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 514 #define MOD_SEL0_7_6            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 515 #define MOD_SEL0_5              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 516 #define MOD_SEL0_4_3            FM(SEL_ADGA_0)          FM(SEL_ADGA_1)          FM(SEL_ADGA_2)          FM(SEL_ADGA_3)
 517
 518 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 519 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 520 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 521 #define MOD_SEL1_26             FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
 522 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 523 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 524 #define MOD_SEL1_20             FM(SEL_SSI1_0)          FM(SEL_SSI1_1)
 525 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 526 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 527 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 528 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 529 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 530 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 531 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 532 #define MOD_SEL1_10             FM(SEL_SCIF_0)          FM(SEL_SCIF_1)
 533 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 534 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 535 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 536 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 537 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 538 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 539 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 540 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 541
 542 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 543 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 544 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 545 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 546 #define MOD_SEL2_28_27          FM(SEL_FM_0)            FM(SEL_FM_1)            FM(SEL_FM_2)            FM(SEL_FM_3)
 547 #define MOD_SEL2_26             FM(SEL_SCIF5_0)         FM(SEL_SCIF5_1)
 548 #define MOD_SEL2_25_24_23       FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)
 549 #define MOD_SEL2_22             FM(SEL_NDF_0)           FM(SEL_NDF_1)
 550 #define MOD_SEL2_21             FM(SEL_SSI2_0)          FM(SEL_SSI2_1)
 551 #define MOD_SEL2_20             FM(SEL_SSI9_0)          FM(SEL_SSI9_1)
 552 #define MOD_SEL2_19             FM(SEL_TIMER_TMU2_0)    FM(SEL_TIMER_TMU2_1)
 553 #define MOD_SEL2_18             FM(SEL_ADGB_0)          FM(SEL_ADGB_1)
 554 #define MOD_SEL2_17             FM(SEL_ADGC_0)          FM(SEL_ADGC_1)
 555 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 556
 557 #define PINMUX_MOD_SELS \
 558 \
 559 MOD_SEL0_31_30_29       MOD_SEL1_31_30          MOD_SEL2_31 \
 560                                                 MOD_SEL2_30 \
 561                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 562 MOD_SEL0_28_27                                  MOD_SEL2_28_27 \
 563 MOD_SEL0_26_25_24       MOD_SEL1_26             MOD_SEL2_26 \
 564                         MOD_SEL1_25_24          MOD_SEL2_25_24_23 \
 565 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 566 MOD_SEL0_22                                     MOD_SEL2_22 \
 567 MOD_SEL0_21                                     MOD_SEL2_21 \
 568 MOD_SEL0_20             MOD_SEL1_20             MOD_SEL2_20 \
 569 MOD_SEL0_19             MOD_SEL1_19             MOD_SEL2_19 \
 570 MOD_SEL0_18_17          MOD_SEL1_18_17          MOD_SEL2_18 \
 571                                                 MOD_SEL2_17 \
 572 MOD_SEL0_16             MOD_SEL1_16 \
 573                         MOD_SEL1_15_14 \
 574 MOD_SEL0_14_13 \
 575                         MOD_SEL1_13 \
 576 MOD_SEL0_12             MOD_SEL1_12 \
 577 MOD_SEL0_11             MOD_SEL1_11 \
 578 MOD_SEL0_10             MOD_SEL1_10 \
 579 MOD_SEL0_9_8            MOD_SEL1_9 \
 580 MOD_SEL0_7_6 \
 581                         MOD_SEL1_6 \
 582 MOD_SEL0_5              MOD_SEL1_5 \
 583 MOD_SEL0_4_3            MOD_SEL1_4 \
 584                         MOD_SEL1_3 \
 585                         MOD_SEL1_2 \
 586                         MOD_SEL1_1 \
 587                         MOD_SEL1_0              MOD_SEL2_0
 588
 589 /*
 590  * These pins are not able to be muxed but have other properties
 591  * that can be set, such as drive-strength or pull-up/pull-down enable.
 592  */
 593 #define PINMUX_STATIC \
 594         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 595         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 596         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 597         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 598         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 599         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 600         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 601         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 602         FM(PRESETOUT) \
 603         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
 604         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 605
 606 #define PINMUX_PHYS \
 607         FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
 608
 609 enum {
 610         PINMUX_RESERVED = 0,
 611
 612         PINMUX_DATA_BEGIN,
 613         GP_ALL(DATA),
 614         PINMUX_DATA_END,
 615
 616 #define F_(x, y)
 617 #define FM(x)   FN_##x,
 618         PINMUX_FUNCTION_BEGIN,
 619         GP_ALL(FN),
 620         PINMUX_GPSR
 621         PINMUX_IPSR
 622         PINMUX_MOD_SELS
 623         PINMUX_FUNCTION_END,
 624 #undef F_
 625 #undef FM
 626
 627 #define F_(x, y)
 628 #define FM(x)   x##_MARK,
 629         PINMUX_MARK_BEGIN,
 630         PINMUX_GPSR
 631         PINMUX_IPSR
 632         PINMUX_MOD_SELS
 633         PINMUX_STATIC
 634         PINMUX_PHYS
 635         PINMUX_MARK_END,
 636 #undef F_
 637 #undef FM
 638 };
 639
 640 static const u16 pinmux_data[] = {
 641         PINMUX_DATA_GP_ALL(),
 642
 643         PINMUX_SINGLE(AVS1),
 644         PINMUX_SINGLE(AVS2),
 645         PINMUX_SINGLE(CLKOUT),
 646         PINMUX_SINGLE(GP7_03),
 647         PINMUX_SINGLE(GP7_02),
 648         PINMUX_SINGLE(MSIOF0_RXD),
 649         PINMUX_SINGLE(MSIOF0_SCK),
 650         PINMUX_SINGLE(MSIOF0_TXD),
 651         PINMUX_SINGLE(SSI_SCK5),
 652         PINMUX_SINGLE(SSI_SDATA5),
 653         PINMUX_SINGLE(SSI_WS5),
 654
 655         /* IPSR0 */
 656         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 657         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 658
 659         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 660         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 661         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 662
 663         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 664         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 665         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 666
 667         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 668         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 669         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 670
 671         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,      I2C_SEL_5_0,    SEL_ETHERAVB_0),
 672         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,          I2C_SEL_5_0,    SEL_MSIOF2_2),
 673         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,              I2C_SEL_5_0,    SEL_SCIF4_0),
 674         PINMUX_IPSR_PHYS(IP0_19_16,     SCL5,                   I2C_SEL_5_1),
 675
 676         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,    I2C_SEL_5_0,    SEL_ETHERAVB_0),
 677         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,          I2C_SEL_5_0,    SEL_MSIOF2_2),
 678         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A,              I2C_SEL_5_0,    SEL_SCIF4_0),
 679         PINMUX_IPSR_PHYS(IP0_23_20,     SDA5,                   I2C_SEL_5_1),
 680
 681         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 682         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 683         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 684         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 685         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 686         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 687         PINMUX_IPSR_MSEL(IP0_27_24,     MSIOF3_SS2_E,           SEL_MSIOF3_4),
 688
 689         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 690         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 691         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 692         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 693         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 694         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 695         PINMUX_IPSR_MSEL(IP0_31_28,     MSIOF3_SS1_E,           SEL_MSIOF3_4),
 696
 697         /* IPSR1 */
 698         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 699         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 700         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 701         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 702         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 703         PINMUX_IPSR_MSEL(IP1_3_0,       MSIOF3_SYNC_E,          SEL_MSIOF3_4),
 704
 705         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 706         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 707         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 708         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 709         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 710         PINMUX_IPSR_MSEL(IP1_7_4,       MSIOF3_SCK_E,           SEL_MSIOF3_4),
 711
 712         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 713         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 714         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 715         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 716         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 717         PINMUX_IPSR_MSEL(IP1_11_8,      MSIOF3_RXD_E,           SEL_MSIOF3_4),
 718
 719         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 720         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 721         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 722         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 723         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 724         PINMUX_IPSR_MSEL(IP1_15_12,     MSIOF3_TXD_E,           SEL_MSIOF3_4),
 725
 726         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 727         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 728         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 729         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 730
 731         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,                I2C_SEL_3_0,    SEL_PWM1_0),
 732         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,                I2C_SEL_3_0,    SEL_HSCIF3_3),
 733         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,           I2C_SEL_3_0,    SEL_VIN4_1),
 734         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,                I2C_SEL_3_0,    SEL_IEBUS_1),
 735         PINMUX_IPSR_PHYS(IP1_23_20,     SCL3,                   I2C_SEL_3_1),
 736
 737         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,                I2C_SEL_3_0,    SEL_PWM2_0),
 738         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,                I2C_SEL_3_0,    SEL_HSCIF3_3),
 739         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,                I2C_SEL_3_0,    SEL_IEBUS_1),
 740         PINMUX_IPSR_PHYS(IP1_27_24,     SDA3,                   I2C_SEL_3_1),
 741
 742         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 743         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 744         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 745         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 746         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 747         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 748
 749         /* IPSR2 */
 750         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 751         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 752         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 753         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 754         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 755         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 756
 757         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 758         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 759         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 760         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 761         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 762         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 763
 764         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 765         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 766         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 767         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 768         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 769         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 770
 771         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 772         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 773         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 774         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 775         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 776         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 777
 778         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 779         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 780         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 781         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 782         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 783         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 784         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 785
 786         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 787         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 788         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 789         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 790         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 791         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 792         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 793
 794         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 795         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 796         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 797         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 798         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 799         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 800         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 801
 802         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 803         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 804         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 805         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 806         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 807         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 808         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 809
 810         /* IPSR3 */
 811         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 812         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 813         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 814         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 815
 816         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 817         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 818         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_B,               SEL_SCIF4_1),
 819         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 820
 821         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 822         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 823         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 824         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 825         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 826         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 827         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 828         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 829         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 830
 831         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 832         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 833         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 834         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 835         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 836         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 837
 838         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 839         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 840         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 841         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 842         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 843         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 844
 845         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 846         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 847         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 848         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 849         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 850         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 851
 852         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 853         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 854         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 855         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 856         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 857         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 858
 859         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 860         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 861         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 862         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 863
 864         /* IPSR4 */
 865         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 866         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 867         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 868         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 869
 870         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 871         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 872         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 873         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 874
 875         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 876         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 877         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 878         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 879
 880         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 881         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 882
 883         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N),
 884         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 885         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 886
 887         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 888         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 889         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 890         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 891         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 892         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 893         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 894         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 895
 896         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 897         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 898         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 899         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 900         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 901         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 902
 903         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 904         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 905         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 906         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 907         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 908         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 909
 910         /* IPSR5 */
 911         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 912         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 913         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 914         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 915         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 916         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 917         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 918
 919         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 920         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 921         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N),
 922         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 923         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 924         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 925         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 926         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 927
 928         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 929         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 930         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 931         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 932
 933         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 934         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 935         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 936         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 937         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 938
 939         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 940         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 941         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 942         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 943         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 944
 945         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 946         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 947         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 948         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 949
 950         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 951         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 952         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 953         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 954
 955         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 956         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 957         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 958         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 959
 960         /* IPSR6 */
 961         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 962         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 963         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 964         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 965
 966         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 967         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 968         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 969         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 970
 971         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 972         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 973         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 974         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 975
 976         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 977         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 978         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 979         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 980         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 981         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 982
 983         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 984         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 985         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 986         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 987         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 988
 989         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 990         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 991         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 992         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 993         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 994         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 995         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 996
 997         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 998         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 999         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
1000         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
1001         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
1002         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_C,               SEL_SCIF4_2),
1003         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
1004
1005         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
1006         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
1007         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
1008         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
1009         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
1010         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
1011
1012         /* IPSR7 */
1013         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
1014         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
1015         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
1016         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
1017         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
1018         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
1019
1020         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
1021         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
1022         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
1023         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
1024         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
1025         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
1026         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
1027
1028         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
1029         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
1030         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
1031         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
1032         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
1033         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
1034         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
1035
1036         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
1037         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
1038         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
1039
1040         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
1041         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
1042         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
1043
1044         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
1045         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
1046         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
1047         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
1048
1049         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
1050         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
1051         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
1052         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
1053
1054         /* IPSR8 */
1055         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
1056         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
1057         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
1058         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1059
1060         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1061         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1062         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1063         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1064
1065         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1066         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1067         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1068
1069         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1070         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1071         PINMUX_IPSR_MSEL(IP8_15_12,     NFCE_N_B,               SEL_NDF_1),
1072         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1073         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1074
1075         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1076         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1077         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1078         PINMUX_IPSR_MSEL(IP8_19_16,     NFWP_N_B,               SEL_NDF_1),
1079         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1080         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1081
1082         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1083         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1084         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1085         PINMUX_IPSR_MSEL(IP8_23_20,     NFDATA14_B,             SEL_NDF_1),
1086         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1087         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1088
1089         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1090         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1091         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1092         PINMUX_IPSR_MSEL(IP8_27_24,     NFDATA15_B,             SEL_NDF_1),
1093         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1094         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1095
1096         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1097         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1098         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1099         PINMUX_IPSR_MSEL(IP8_31_28,     NFRB_N_B,               SEL_NDF_1),
1100         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1101         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1102
1103         /* IPSR9 */
1104         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1105         PINMUX_IPSR_GPSR(IP9_3_0,       NFDATA8),
1106
1107         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_CMD),
1108         PINMUX_IPSR_GPSR(IP9_7_4,       NFDATA9),
1109
1110         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT0),
1111         PINMUX_IPSR_GPSR(IP9_11_8,      NFDATA10),
1112
1113         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT1),
1114         PINMUX_IPSR_GPSR(IP9_15_12,     NFDATA11),
1115
1116         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT2),
1117         PINMUX_IPSR_GPSR(IP9_19_16,     NFDATA12),
1118
1119         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DAT3),
1120         PINMUX_IPSR_GPSR(IP9_23_20,     NFDATA13),
1121
1122         PINMUX_IPSR_GPSR(IP9_27_24,     SD2_DS),
1123         PINMUX_IPSR_GPSR(IP9_27_24,     NFALE),
1124
1125         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_CLK),
1126         PINMUX_IPSR_GPSR(IP9_31_28,     NFWE_N),
1127
1128         /* IPSR10 */
1129         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CMD),
1130         PINMUX_IPSR_GPSR(IP10_3_0,      NFRE_N),
1131
1132         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT0),
1133         PINMUX_IPSR_GPSR(IP10_7_4,      NFDATA0),
1134
1135         PINMUX_IPSR_GPSR(IP10_11_8,     SD3_DAT1),
1136         PINMUX_IPSR_GPSR(IP10_11_8,     NFDATA1),
1137
1138         PINMUX_IPSR_GPSR(IP10_15_12,    SD3_DAT2),
1139         PINMUX_IPSR_GPSR(IP10_15_12,    NFDATA2),
1140
1141         PINMUX_IPSR_GPSR(IP10_19_16,    SD3_DAT3),
1142         PINMUX_IPSR_GPSR(IP10_19_16,    NFDATA3),
1143
1144         PINMUX_IPSR_GPSR(IP10_23_20,    SD3_DAT4),
1145         PINMUX_IPSR_MSEL(IP10_23_20,    SD2_CD_A,               SEL_SDHI2_0),
1146         PINMUX_IPSR_GPSR(IP10_23_20,    NFDATA4),
1147
1148         PINMUX_IPSR_GPSR(IP10_27_24,    SD3_DAT5),
1149         PINMUX_IPSR_MSEL(IP10_27_24,    SD2_WP_A,               SEL_SDHI2_0),
1150         PINMUX_IPSR_GPSR(IP10_27_24,    NFDATA5),
1151
1152         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_DAT6),
1153         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_CD),
1154         PINMUX_IPSR_GPSR(IP10_31_28,    NFDATA6),
1155
1156         /* IPSR11 */
1157         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_DAT7),
1158         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_WP),
1159         PINMUX_IPSR_GPSR(IP11_3_0,      NFDATA7),
1160
1161         PINMUX_IPSR_GPSR(IP11_7_4,      SD3_DS),
1162         PINMUX_IPSR_GPSR(IP11_7_4,      NFCLE),
1163
1164         PINMUX_IPSR_GPSR(IP11_11_8,     SD0_CD),
1165         PINMUX_IPSR_MSEL(IP11_11_8,     NFDATA14_A,             SEL_NDF_0),
1166         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_B,                 SEL_I2C2_1),
1167         PINMUX_IPSR_MSEL(IP11_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1168
1169         PINMUX_IPSR_GPSR(IP11_15_12,    SD0_WP),
1170         PINMUX_IPSR_MSEL(IP11_15_12,    NFDATA15_A,             SEL_NDF_0),
1171         PINMUX_IPSR_MSEL(IP11_15_12,    SDA2_B,                 SEL_I2C2_1),
1172
1173         PINMUX_IPSR_MSEL(IP11_19_16,    SD1_CD,                 I2C_SEL_0_0),
1174         PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A,             I2C_SEL_0_0,    SEL_NDF_0),
1175         PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B,           I2C_SEL_0_0,    SEL_SIMCARD_1),
1176         PINMUX_IPSR_PHYS(IP11_19_16,    SCL0,                   I2C_SEL_0_1),
1177
1178         PINMUX_IPSR_MSEL(IP11_23_20,    SD1_WP,                 I2C_SEL_0_0),
1179         PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A,             I2C_SEL_0_0,    SEL_NDF_0),
1180         PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B,             I2C_SEL_0_0,    SEL_SIMCARD_1),
1181         PINMUX_IPSR_PHYS(IP11_23_20,    SDA0,                   I2C_SEL_0_1),
1182
1183         PINMUX_IPSR_GPSR(IP11_27_24,    SCK0),
1184         PINMUX_IPSR_MSEL(IP11_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1185         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1186         PINMUX_IPSR_MSEL(IP11_27_24,    AUDIO_CLKC_B,           SEL_ADGC_1),
1187         PINMUX_IPSR_MSEL(IP11_27_24,    SDA2_A,                 SEL_I2C2_0),
1188         PINMUX_IPSR_MSEL(IP11_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1189         PINMUX_IPSR_MSEL(IP11_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1190         PINMUX_IPSR_MSEL(IP11_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1191         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS2),
1192         PINMUX_IPSR_MSEL(IP11_27_24,    SCK5_B,                 SEL_SCIF5_1),
1193
1194         PINMUX_IPSR_GPSR(IP11_31_28,    RX0),
1195         PINMUX_IPSR_MSEL(IP11_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1196         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1197         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1198         PINMUX_IPSR_MSEL(IP11_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1199
1200         /* IPSR12 */
1201         PINMUX_IPSR_GPSR(IP12_3_0,      TX0),
1202         PINMUX_IPSR_MSEL(IP12_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1203         PINMUX_IPSR_MSEL(IP12_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1204         PINMUX_IPSR_MSEL(IP12_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1205         PINMUX_IPSR_MSEL(IP12_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1206
1207         PINMUX_IPSR_GPSR(IP12_7_4,      CTS0_N),
1208         PINMUX_IPSR_MSEL(IP12_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1209         PINMUX_IPSR_MSEL(IP12_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1210         PINMUX_IPSR_MSEL(IP12_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1211         PINMUX_IPSR_MSEL(IP12_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1212         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1213         PINMUX_IPSR_GPSR(IP12_7_4,      AUDIO_CLKOUT_C),
1214         PINMUX_IPSR_GPSR(IP12_7_4,      ADICS_SAMP),
1215
1216         PINMUX_IPSR_GPSR(IP12_11_8,     RTS0_N),
1217         PINMUX_IPSR_MSEL(IP12_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1218         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1219         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKA_B,           SEL_ADGA_1),
1220         PINMUX_IPSR_MSEL(IP12_11_8,     SCL2_A,                 SEL_I2C2_0),
1221         PINMUX_IPSR_MSEL(IP12_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1222         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1223         PINMUX_IPSR_GPSR(IP12_11_8,     ADICHS1),
1224
1225         PINMUX_IPSR_MSEL(IP12_15_12,    RX1_A,                  SEL_SCIF1_0),
1226         PINMUX_IPSR_MSEL(IP12_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1227         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1228         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1229         PINMUX_IPSR_MSEL(IP12_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1230
1231         PINMUX_IPSR_MSEL(IP12_19_16,    TX1_A,                  SEL_SCIF1_0),
1232         PINMUX_IPSR_MSEL(IP12_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1233         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1234         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1235         PINMUX_IPSR_MSEL(IP12_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1236
1237         PINMUX_IPSR_GPSR(IP12_23_20,    CTS1_N),
1238         PINMUX_IPSR_MSEL(IP12_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1239         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1240         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1241         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1242         PINMUX_IPSR_MSEL(IP12_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1243         PINMUX_IPSR_GPSR(IP12_23_20,    ADIDATA),
1244
1245         PINMUX_IPSR_GPSR(IP12_27_24,    RTS1_N),
1246         PINMUX_IPSR_MSEL(IP12_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1247         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1248         PINMUX_IPSR_MSEL(IP12_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1249         PINMUX_IPSR_MSEL(IP12_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1250         PINMUX_IPSR_MSEL(IP12_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1251         PINMUX_IPSR_GPSR(IP12_27_24,    ADICHS0),
1252
1253         PINMUX_IPSR_GPSR(IP12_31_28,    SCK2),
1254         PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,             SEL_SCIF_1),
1255         PINMUX_IPSR_MSEL(IP12_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1256         PINMUX_IPSR_MSEL(IP12_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1257         PINMUX_IPSR_MSEL(IP12_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1258         PINMUX_IPSR_MSEL(IP12_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1259         PINMUX_IPSR_GPSR(IP12_31_28,    ADICLK),
1260
1261         /* IPSR13 */
1262         PINMUX_IPSR_MSEL(IP13_3_0,      TX2_A,                  SEL_SCIF2_0),
1263         PINMUX_IPSR_MSEL(IP13_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1264         PINMUX_IPSR_MSEL(IP13_3_0,      SCL1_A,                 SEL_I2C1_0),
1265         PINMUX_IPSR_MSEL(IP13_3_0,      FMCLK_A,                SEL_FM_0),
1266         PINMUX_IPSR_MSEL(IP13_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1267         PINMUX_IPSR_GPSR(IP13_3_0,      FSO_CFE_0_N),
1268
1269         PINMUX_IPSR_MSEL(IP13_7_4,      RX2_A,                  SEL_SCIF2_0),
1270         PINMUX_IPSR_MSEL(IP13_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1271         PINMUX_IPSR_MSEL(IP13_7_4,      SDA1_A,                 SEL_I2C1_0),
1272         PINMUX_IPSR_MSEL(IP13_7_4,      FMIN_A,                 SEL_FM_0),
1273         PINMUX_IPSR_MSEL(IP13_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1274         PINMUX_IPSR_GPSR(IP13_7_4,      FSO_CFE_1_N),
1275
1276         PINMUX_IPSR_GPSR(IP13_11_8,     HSCK0),
1277         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1278         PINMUX_IPSR_MSEL(IP13_11_8,     AUDIO_CLKB_A,           SEL_ADGB_0),
1279         PINMUX_IPSR_MSEL(IP13_11_8,     SSI_SDATA1_B,           SEL_SSI1_1),
1280         PINMUX_IPSR_MSEL(IP13_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1281         PINMUX_IPSR_MSEL(IP13_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1282         PINMUX_IPSR_MSEL(IP13_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1283         PINMUX_IPSR_MSEL(IP13_11_8,     RX5_B,                  SEL_SCIF5_1),
1284
1285         PINMUX_IPSR_GPSR(IP13_15_12,    HRX0),
1286         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1287         PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,           SEL_SSI2_1),
1288         PINMUX_IPSR_MSEL(IP13_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1289         PINMUX_IPSR_MSEL(IP13_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1290         PINMUX_IPSR_MSEL(IP13_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1291
1292         PINMUX_IPSR_GPSR(IP13_19_16,    HTX0),
1293         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1294         PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,           SEL_SSI9_1),
1295         PINMUX_IPSR_MSEL(IP13_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1296         PINMUX_IPSR_MSEL(IP13_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1297         PINMUX_IPSR_MSEL(IP13_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1298
1299         PINMUX_IPSR_GPSR(IP13_23_20,    HCTS0_N),
1300         PINMUX_IPSR_MSEL(IP13_23_20,    RX2_B,                  SEL_SCIF2_1),
1301         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1302         PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,             SEL_SSI9_0),
1303         PINMUX_IPSR_MSEL(IP13_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1304         PINMUX_IPSR_MSEL(IP13_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1305         PINMUX_IPSR_MSEL(IP13_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1306         PINMUX_IPSR_GPSR(IP13_23_20,    AUDIO_CLKOUT1_A),
1307
1308         PINMUX_IPSR_GPSR(IP13_27_24,    HRTS0_N),
1309         PINMUX_IPSR_MSEL(IP13_27_24,    TX2_B,                  SEL_SCIF2_1),
1310         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1311         PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,              SEL_SSI9_0),
1312         PINMUX_IPSR_MSEL(IP13_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1313         PINMUX_IPSR_MSEL(IP13_27_24,    BPFCLK_A,               SEL_FM_0),
1314         PINMUX_IPSR_GPSR(IP13_27_24,    AUDIO_CLKOUT2_A),
1315
1316         PINMUX_IPSR_GPSR(IP13_31_28,    MSIOF0_SYNC),
1317         PINMUX_IPSR_GPSR(IP13_31_28,    AUDIO_CLKOUT_A),
1318         PINMUX_IPSR_MSEL(IP13_31_28,    TX5_B,                  SEL_SCIF5_1),
1319         PINMUX_IPSR_MSEL(IP13_31_28,    BPFCLK_D,               SEL_FM_3),
1320
1321         /* IPSR14 */
1322         PINMUX_IPSR_GPSR(IP14_3_0,      MSIOF0_SS1),
1323         PINMUX_IPSR_MSEL(IP14_3_0,      RX5_A,                  SEL_SCIF5_0),
1324         PINMUX_IPSR_MSEL(IP14_3_0,      NFWP_N_A,               SEL_NDF_0),
1325         PINMUX_IPSR_MSEL(IP14_3_0,      AUDIO_CLKA_C,           SEL_ADGA_2),
1326         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SCK2_A,             SEL_SSI2_0),
1327         PINMUX_IPSR_MSEL(IP14_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1328         PINMUX_IPSR_GPSR(IP14_3_0,      AUDIO_CLKOUT3_A),
1329         PINMUX_IPSR_MSEL(IP14_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
1330
1331         PINMUX_IPSR_GPSR(IP14_7_4,      MSIOF0_SS2),
1332         PINMUX_IPSR_MSEL(IP14_7_4,      TX5_A,                  SEL_SCIF5_0),
1333         PINMUX_IPSR_MSEL(IP14_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1334         PINMUX_IPSR_MSEL(IP14_7_4,      AUDIO_CLKC_A,           SEL_ADGC_0),
1335         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_WS2_A,              SEL_SSI2_0),
1336         PINMUX_IPSR_MSEL(IP14_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1337         PINMUX_IPSR_GPSR(IP14_7_4,      AUDIO_CLKOUT_D),
1338         PINMUX_IPSR_MSEL(IP14_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1339
1340         PINMUX_IPSR_GPSR(IP14_11_8,     MLB_CLK),
1341         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1342         PINMUX_IPSR_MSEL(IP14_11_8,     SCL1_B,                 SEL_I2C1_1),
1343
1344         PINMUX_IPSR_GPSR(IP14_15_12,    MLB_SIG),
1345         PINMUX_IPSR_MSEL(IP14_15_12,    RX1_B,                  SEL_SCIF1_1),
1346         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1347         PINMUX_IPSR_MSEL(IP14_15_12,    SDA1_B,                 SEL_I2C1_1),
1348
1349         PINMUX_IPSR_GPSR(IP14_19_16,    MLB_DAT),
1350         PINMUX_IPSR_MSEL(IP14_19_16,    TX1_B,                  SEL_SCIF1_1),
1351         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1352
1353         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK01239),
1354         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1355
1356         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS01239),
1357         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1358
1359         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA0),
1360         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1361
1362         /* IPSR15 */
1363         PINMUX_IPSR_MSEL(IP15_3_0,      SSI_SDATA1_A,           SEL_SSI1_0),
1364
1365         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SDATA2_A,           SEL_SSI2_0),
1366         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SCK1_B,             SEL_SSI1_1),
1367
1368         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SCK349),
1369         PINMUX_IPSR_MSEL(IP15_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1370         PINMUX_IPSR_MSEL(IP15_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1371
1372         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_WS349),
1373         PINMUX_IPSR_MSEL(IP15_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1374         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1375         PINMUX_IPSR_MSEL(IP15_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1376
1377         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_SDATA3),
1378         PINMUX_IPSR_MSEL(IP15_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1379         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1380         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1381         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1382         PINMUX_IPSR_MSEL(IP15_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1383         PINMUX_IPSR_MSEL(IP15_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1384
1385         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SCK4),
1386         PINMUX_IPSR_MSEL(IP15_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1387         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1388         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1389         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1390         PINMUX_IPSR_MSEL(IP15_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1391         PINMUX_IPSR_MSEL(IP15_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1392
1393         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_WS4),
1394         PINMUX_IPSR_MSEL(IP15_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1395         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1396         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1397         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1398         PINMUX_IPSR_MSEL(IP15_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1399         PINMUX_IPSR_MSEL(IP15_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1400
1401         PINMUX_IPSR_GPSR(IP15_31_28,    SSI_SDATA4),
1402         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1403         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1404         PINMUX_IPSR_MSEL(IP15_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1405         PINMUX_IPSR_MSEL(IP15_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1406         PINMUX_IPSR_MSEL(IP15_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1407         PINMUX_IPSR_MSEL(IP15_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1408
1409         /* IPSR16 */
1410         PINMUX_IPSR_GPSR(IP16_3_0,      SSI_SCK6),
1411         PINMUX_IPSR_MSEL(IP16_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1412
1413         PINMUX_IPSR_GPSR(IP16_7_4,      SSI_WS6),
1414         PINMUX_IPSR_MSEL(IP16_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1415
1416         PINMUX_IPSR_GPSR(IP16_11_8,     SSI_SDATA6),
1417         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1418
1419         PINMUX_IPSR_GPSR(IP16_15_12,    SSI_SCK78),
1420         PINMUX_IPSR_MSEL(IP16_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1421         PINMUX_IPSR_MSEL(IP16_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1422         PINMUX_IPSR_MSEL(IP16_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1423         PINMUX_IPSR_MSEL(IP16_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1424         PINMUX_IPSR_MSEL(IP16_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1425         PINMUX_IPSR_MSEL(IP16_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1426
1427         PINMUX_IPSR_GPSR(IP16_19_16,    SSI_WS78),
1428         PINMUX_IPSR_MSEL(IP16_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1429         PINMUX_IPSR_MSEL(IP16_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1430         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1431         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1432         PINMUX_IPSR_MSEL(IP16_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1433         PINMUX_IPSR_MSEL(IP16_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1434
1435         PINMUX_IPSR_GPSR(IP16_23_20,    SSI_SDATA7),
1436         PINMUX_IPSR_MSEL(IP16_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1437         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1438         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1439         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1440         PINMUX_IPSR_MSEL(IP16_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1441         PINMUX_IPSR_MSEL(IP16_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1442         PINMUX_IPSR_MSEL(IP16_23_20,    TCLK2_A,                SEL_TIMER_TMU2_0),
1443
1444         PINMUX_IPSR_GPSR(IP16_27_24,    SSI_SDATA8),
1445         PINMUX_IPSR_MSEL(IP16_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1446         PINMUX_IPSR_MSEL(IP16_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1447         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1448         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1449         PINMUX_IPSR_MSEL(IP16_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1450         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1451
1452         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,           SEL_SSI9_0),
1453         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1454         PINMUX_IPSR_MSEL(IP16_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1455         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1456         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,              SEL_SSI1_1),
1457         PINMUX_IPSR_GPSR(IP16_31_28,    SCK1),
1458         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1459         PINMUX_IPSR_MSEL(IP16_31_28,    SCK5_A,                 SEL_SCIF5_0),
1460
1461         /* IPSR17 */
1462         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKA_A,           SEL_ADGA_0),
1463
1464         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKB_B,           SEL_ADGB_1),
1465         PINMUX_IPSR_MSEL(IP17_7_4,      SCIF_CLK_A,             SEL_SCIF_0),
1466         PINMUX_IPSR_MSEL(IP17_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1467         PINMUX_IPSR_MSEL(IP17_7_4,      REMOCON_A,              SEL_REMOCON_0),
1468         PINMUX_IPSR_MSEL(IP17_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
1469
1470         PINMUX_IPSR_GPSR(IP17_11_8,     USB0_PWEN),
1471         PINMUX_IPSR_MSEL(IP17_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1472         PINMUX_IPSR_MSEL(IP17_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1473         PINMUX_IPSR_MSEL(IP17_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1474         PINMUX_IPSR_MSEL(IP17_11_8,     BPFCLK_B,               SEL_FM_1),
1475         PINMUX_IPSR_MSEL(IP17_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1476         PINMUX_IPSR_MSEL(IP17_11_8,     HSCK2_C,                SEL_HSCIF2_2),
1477
1478         PINMUX_IPSR_GPSR(IP17_15_12,    USB0_OVC),
1479         PINMUX_IPSR_MSEL(IP17_15_12,    SIM0_D_C,               SEL_SIMCARD_2),
1480         PINMUX_IPSR_MSEL(IP17_15_12,    TS_SDAT1_D,             SEL_TSIF1_3),
1481         PINMUX_IPSR_MSEL(IP17_15_12,    STP_ISD_1_D,            SEL_SSP1_1_3),
1482         PINMUX_IPSR_MSEL(IP17_15_12,    RIF3_SYNC_B,            SEL_DRIF3_1),
1483         PINMUX_IPSR_MSEL(IP17_15_12,    HRX2_C,                 SEL_HSCIF2_2),
1484
1485         PINMUX_IPSR_GPSR(IP17_19_16,    USB1_PWEN),
1486         PINMUX_IPSR_MSEL(IP17_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1487         PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,             SEL_SSI1_0),
1488         PINMUX_IPSR_MSEL(IP17_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1489         PINMUX_IPSR_MSEL(IP17_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1490         PINMUX_IPSR_MSEL(IP17_19_16,    FMCLK_B,                SEL_FM_1),
1491         PINMUX_IPSR_MSEL(IP17_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1492         PINMUX_IPSR_MSEL(IP17_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1493         PINMUX_IPSR_MSEL(IP17_19_16,    HTX2_C,                 SEL_HSCIF2_2),
1494
1495         PINMUX_IPSR_GPSR(IP17_23_20,    USB1_OVC),
1496         PINMUX_IPSR_MSEL(IP17_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1497         PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,              SEL_SSI1_0),
1498         PINMUX_IPSR_MSEL(IP17_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1499         PINMUX_IPSR_MSEL(IP17_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1500         PINMUX_IPSR_MSEL(IP17_23_20,    FMIN_B,                 SEL_FM_1),
1501         PINMUX_IPSR_MSEL(IP17_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1502         PINMUX_IPSR_MSEL(IP17_23_20,    REMOCON_B,              SEL_REMOCON_1),
1503         PINMUX_IPSR_MSEL(IP17_23_20,    HCTS2_N_C,              SEL_HSCIF2_2),
1504
1505         PINMUX_IPSR_GPSR(IP17_27_24,    USB30_PWEN),
1506         PINMUX_IPSR_GPSR(IP17_27_24,    AUDIO_CLKOUT_B),
1507         PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,             SEL_SSI2_1),
1508         PINMUX_IPSR_MSEL(IP17_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1509         PINMUX_IPSR_MSEL(IP17_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1510         PINMUX_IPSR_MSEL(IP17_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1511         PINMUX_IPSR_MSEL(IP17_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1512         PINMUX_IPSR_MSEL(IP17_27_24,    TCLK2_B,                SEL_TIMER_TMU2_1),
1513         PINMUX_IPSR_GPSR(IP17_27_24,    TPU0TO0),
1514         PINMUX_IPSR_MSEL(IP17_27_24,    BPFCLK_C,               SEL_FM_2),
1515         PINMUX_IPSR_MSEL(IP17_27_24,    HRTS2_N_C,              SEL_HSCIF2_2),
1516
1517         PINMUX_IPSR_GPSR(IP17_31_28,    USB30_OVC),
1518         PINMUX_IPSR_GPSR(IP17_31_28,    AUDIO_CLKOUT1_B),
1519         PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,              SEL_SSI2_1),
1520         PINMUX_IPSR_MSEL(IP17_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1521         PINMUX_IPSR_MSEL(IP17_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1522         PINMUX_IPSR_MSEL(IP17_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1523         PINMUX_IPSR_MSEL(IP17_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1524         PINMUX_IPSR_GPSR(IP17_31_28,    FSO_TOE_N),
1525         PINMUX_IPSR_GPSR(IP17_31_28,    TPU0TO1),
1526
1527         /* IPSR18 */
1528         PINMUX_IPSR_GPSR(IP18_3_0,      GP6_30),
1529         PINMUX_IPSR_GPSR(IP18_3_0,      AUDIO_CLKOUT2_B),
1530         PINMUX_IPSR_MSEL(IP18_3_0,      SSI_SCK9_B,             SEL_SSI9_1),
1531         PINMUX_IPSR_MSEL(IP18_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1532         PINMUX_IPSR_MSEL(IP18_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1533         PINMUX_IPSR_MSEL(IP18_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1534         PINMUX_IPSR_GPSR(IP18_3_0,      TPU0TO2),
1535         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_C,                SEL_FM_2),
1536         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_D,                SEL_FM_3),
1537
1538         PINMUX_IPSR_GPSR(IP18_7_4,      GP6_31),
1539         PINMUX_IPSR_GPSR(IP18_7_4,      AUDIO_CLKOUT3_B),
1540         PINMUX_IPSR_MSEL(IP18_7_4,      SSI_WS9_B,              SEL_SSI9_1),
1541         PINMUX_IPSR_MSEL(IP18_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1542         PINMUX_IPSR_MSEL(IP18_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1543         PINMUX_IPSR_MSEL(IP18_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1544         PINMUX_IPSR_GPSR(IP18_7_4,      TPU0TO3),
1545         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_C,                 SEL_FM_2),
1546         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_D,                 SEL_FM_3),
1547
1548 /*
1549  * Static pins can not be muxed between different functions but
1550  * still need mark entries in the pinmux list. Add each static
1551  * pin to the list without an associated function. The sh-pfc
1552  * core will do the right thing and skip trying to mux the pin
1553  * while still applying configuration to it.
1554  */
1555 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1556         PINMUX_STATIC
1557 #undef FM
1558 };
1559
1560 /*
1561  * Pins not associated with a GPIO port.
1562  */
1563 enum {
1564         GP_ASSIGN_LAST(),
1565         NOGP_ALL(),
1566 };
1567
1568 static const struct sh_pfc_pin pinmux_pins[] = {
1569         PINMUX_GPIO_GP_ALL(),
1570         PINMUX_NOGP_ALL(),
1571 };
1572
1573 /* - AUDIO CLOCK ------------------------------------------------------------ */
1574 static const unsigned int audio_clk_a_a_pins[] = {
1575         /* CLK A */
1576         RCAR_GP_PIN(6, 22),
1577 };
1578 static const unsigned int audio_clk_a_a_mux[] = {
1579         AUDIO_CLKA_A_MARK,
1580 };
1581 static const unsigned int audio_clk_a_b_pins[] = {
1582         /* CLK A */
1583         RCAR_GP_PIN(5, 4),
1584 };
1585 static const unsigned int audio_clk_a_b_mux[] = {
1586         AUDIO_CLKA_B_MARK,
1587 };
1588 static const unsigned int audio_clk_a_c_pins[] = {
1589         /* CLK A */
1590         RCAR_GP_PIN(5, 19),
1591 };
1592 static const unsigned int audio_clk_a_c_mux[] = {
1593         AUDIO_CLKA_C_MARK,
1594 };
1595 static const unsigned int audio_clk_b_a_pins[] = {
1596         /* CLK B */
1597         RCAR_GP_PIN(5, 12),
1598 };
1599 static const unsigned int audio_clk_b_a_mux[] = {
1600         AUDIO_CLKB_A_MARK,
1601 };
1602 static const unsigned int audio_clk_b_b_pins[] = {
1603         /* CLK B */
1604         RCAR_GP_PIN(6, 23),
1605 };
1606 static const unsigned int audio_clk_b_b_mux[] = {
1607         AUDIO_CLKB_B_MARK,
1608 };
1609 static const unsigned int audio_clk_c_a_pins[] = {
1610         /* CLK C */
1611         RCAR_GP_PIN(5, 21),
1612 };
1613 static const unsigned int audio_clk_c_a_mux[] = {
1614         AUDIO_CLKC_A_MARK,
1615 };
1616 static const unsigned int audio_clk_c_b_pins[] = {
1617         /* CLK C */
1618         RCAR_GP_PIN(5, 0),
1619 };
1620 static const unsigned int audio_clk_c_b_mux[] = {
1621         AUDIO_CLKC_B_MARK,
1622 };
1623 static const unsigned int audio_clkout_a_pins[] = {
1624         /* CLKOUT */
1625         RCAR_GP_PIN(5, 18),
1626 };
1627 static const unsigned int audio_clkout_a_mux[] = {
1628         AUDIO_CLKOUT_A_MARK,
1629 };
1630 static const unsigned int audio_clkout_b_pins[] = {
1631         /* CLKOUT */
1632         RCAR_GP_PIN(6, 28),
1633 };
1634 static const unsigned int audio_clkout_b_mux[] = {
1635         AUDIO_CLKOUT_B_MARK,
1636 };
1637 static const unsigned int audio_clkout_c_pins[] = {
1638         /* CLKOUT */
1639         RCAR_GP_PIN(5, 3),
1640 };
1641 static const unsigned int audio_clkout_c_mux[] = {
1642         AUDIO_CLKOUT_C_MARK,
1643 };
1644 static const unsigned int audio_clkout_d_pins[] = {
1645         /* CLKOUT */
1646         RCAR_GP_PIN(5, 21),
1647 };
1648 static const unsigned int audio_clkout_d_mux[] = {
1649         AUDIO_CLKOUT_D_MARK,
1650 };
1651 static const unsigned int audio_clkout1_a_pins[] = {
1652         /* CLKOUT1 */
1653         RCAR_GP_PIN(5, 15),
1654 };
1655 static const unsigned int audio_clkout1_a_mux[] = {
1656         AUDIO_CLKOUT1_A_MARK,
1657 };
1658 static const unsigned int audio_clkout1_b_pins[] = {
1659         /* CLKOUT1 */
1660         RCAR_GP_PIN(6, 29),
1661 };
1662 static const unsigned int audio_clkout1_b_mux[] = {
1663         AUDIO_CLKOUT1_B_MARK,
1664 };
1665 static const unsigned int audio_clkout2_a_pins[] = {
1666         /* CLKOUT2 */
1667         RCAR_GP_PIN(5, 16),
1668 };
1669 static const unsigned int audio_clkout2_a_mux[] = {
1670         AUDIO_CLKOUT2_A_MARK,
1671 };
1672 static const unsigned int audio_clkout2_b_pins[] = {
1673         /* CLKOUT2 */
1674         RCAR_GP_PIN(6, 30),
1675 };
1676 static const unsigned int audio_clkout2_b_mux[] = {
1677         AUDIO_CLKOUT2_B_MARK,
1678 };
1679
1680 static const unsigned int audio_clkout3_a_pins[] = {
1681         /* CLKOUT3 */
1682         RCAR_GP_PIN(5, 19),
1683 };
1684 static const unsigned int audio_clkout3_a_mux[] = {
1685         AUDIO_CLKOUT3_A_MARK,
1686 };
1687 static const unsigned int audio_clkout3_b_pins[] = {
1688         /* CLKOUT3 */
1689         RCAR_GP_PIN(6, 31),
1690 };
1691 static const unsigned int audio_clkout3_b_mux[] = {
1692         AUDIO_CLKOUT3_B_MARK,
1693 };
1694
1695 /* - EtherAVB --------------------------------------------------------------- */
1696 static const unsigned int avb_link_pins[] = {
1697         /* AVB_LINK */
1698         RCAR_GP_PIN(2, 12),
1699 };
1700 static const unsigned int avb_link_mux[] = {
1701         AVB_LINK_MARK,
1702 };
1703 static const unsigned int avb_magic_pins[] = {
1704         /* AVB_MAGIC_ */
1705         RCAR_GP_PIN(2, 10),
1706 };
1707 static const unsigned int avb_magic_mux[] = {
1708         AVB_MAGIC_MARK,
1709 };
1710 static const unsigned int avb_phy_int_pins[] = {
1711         /* AVB_PHY_INT */
1712         RCAR_GP_PIN(2, 11),
1713 };
1714 static const unsigned int avb_phy_int_mux[] = {
1715         AVB_PHY_INT_MARK,
1716 };
1717 static const unsigned int avb_mdio_pins[] = {
1718         /* AVB_MDC, AVB_MDIO */
1719         RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1720 };
1721 static const unsigned int avb_mdio_mux[] = {
1722         AVB_MDC_MARK, AVB_MDIO_MARK,
1723 };
1724 static const unsigned int avb_mii_pins[] = {
1725         /*
1726          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1727          * AVB_TD1, AVB_TD2, AVB_TD3,
1728          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1729          * AVB_RD1, AVB_RD2, AVB_RD3,
1730          * AVB_TXCREFCLK
1731          */
1732         PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1733         PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1734         PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1735         PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1736         PIN_AVB_TXCREFCLK,
1737 };
1738 static const unsigned int avb_mii_mux[] = {
1739         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1740         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1741         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1742         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1743         AVB_TXCREFCLK_MARK,
1744 };
1745 static const unsigned int avb_avtp_pps_pins[] = {
1746         /* AVB_AVTP_PPS */
1747         RCAR_GP_PIN(2, 6),
1748 };
1749 static const unsigned int avb_avtp_pps_mux[] = {
1750         AVB_AVTP_PPS_MARK,
1751 };
1752 static const unsigned int avb_avtp_match_a_pins[] = {
1753         /* AVB_AVTP_MATCH_A */
1754         RCAR_GP_PIN(2, 13),
1755 };
1756 static const unsigned int avb_avtp_match_a_mux[] = {
1757         AVB_AVTP_MATCH_A_MARK,
1758 };
1759 static const unsigned int avb_avtp_capture_a_pins[] = {
1760         /* AVB_AVTP_CAPTURE_A */
1761         RCAR_GP_PIN(2, 14),
1762 };
1763 static const unsigned int avb_avtp_capture_a_mux[] = {
1764         AVB_AVTP_CAPTURE_A_MARK,
1765 };
1766 static const unsigned int avb_avtp_match_b_pins[] = {
1767         /*  AVB_AVTP_MATCH_B */
1768         RCAR_GP_PIN(1, 8),
1769 };
1770 static const unsigned int avb_avtp_match_b_mux[] = {
1771         AVB_AVTP_MATCH_B_MARK,
1772 };
1773 static const unsigned int avb_avtp_capture_b_pins[] = {
1774         /* AVB_AVTP_CAPTURE_B */
1775         RCAR_GP_PIN(1, 11),
1776 };
1777 static const unsigned int avb_avtp_capture_b_mux[] = {
1778         AVB_AVTP_CAPTURE_B_MARK,
1779 };
1780
1781 /* - CAN ------------------------------------------------------------------ */
1782 static const unsigned int can0_data_a_pins[] = {
1783         /* TX, RX */
1784         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1785 };
1786 static const unsigned int can0_data_a_mux[] = {
1787         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1788 };
1789 static const unsigned int can0_data_b_pins[] = {
1790         /* TX, RX */
1791         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1792 };
1793 static const unsigned int can0_data_b_mux[] = {
1794         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1795 };
1796 static const unsigned int can1_data_pins[] = {
1797         /* TX, RX */
1798         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1799 };
1800 static const unsigned int can1_data_mux[] = {
1801         CAN1_TX_MARK,           CAN1_RX_MARK,
1802 };
1803
1804 /* - CAN Clock -------------------------------------------------------------- */
1805 static const unsigned int can_clk_pins[] = {
1806         /* CLK */
1807         RCAR_GP_PIN(1, 25),
1808 };
1809 static const unsigned int can_clk_mux[] = {
1810         CAN_CLK_MARK,
1811 };
1812
1813 /* - CAN FD --------------------------------------------------------------- */
1814 static const unsigned int canfd0_data_a_pins[] = {
1815         /* TX, RX */
1816         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1817 };
1818 static const unsigned int canfd0_data_a_mux[] = {
1819         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1820 };
1821 static const unsigned int canfd0_data_b_pins[] = {
1822         /* TX, RX */
1823         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1824 };
1825 static const unsigned int canfd0_data_b_mux[] = {
1826         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1827 };
1828 static const unsigned int canfd1_data_pins[] = {
1829         /* TX, RX */
1830         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1831 };
1832 static const unsigned int canfd1_data_mux[] = {
1833         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1834 };
1835
1836 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
1837 /* - DRIF0 --------------------------------------------------------------- */
1838 static const unsigned int drif0_ctrl_a_pins[] = {
1839         /* CLK, SYNC */
1840         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1841 };
1842 static const unsigned int drif0_ctrl_a_mux[] = {
1843         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1844 };
1845 static const unsigned int drif0_data0_a_pins[] = {
1846         /* D0 */
1847         RCAR_GP_PIN(6, 10),
1848 };
1849 static const unsigned int drif0_data0_a_mux[] = {
1850         RIF0_D0_A_MARK,
1851 };
1852 static const unsigned int drif0_data1_a_pins[] = {
1853         /* D1 */
1854         RCAR_GP_PIN(6, 7),
1855 };
1856 static const unsigned int drif0_data1_a_mux[] = {
1857         RIF0_D1_A_MARK,
1858 };
1859 static const unsigned int drif0_ctrl_b_pins[] = {
1860         /* CLK, SYNC */
1861         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1862 };
1863 static const unsigned int drif0_ctrl_b_mux[] = {
1864         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1865 };
1866 static const unsigned int drif0_data0_b_pins[] = {
1867         /* D0 */
1868         RCAR_GP_PIN(5, 1),
1869 };
1870 static const unsigned int drif0_data0_b_mux[] = {
1871         RIF0_D0_B_MARK,
1872 };
1873 static const unsigned int drif0_data1_b_pins[] = {
1874         /* D1 */
1875         RCAR_GP_PIN(5, 2),
1876 };
1877 static const unsigned int drif0_data1_b_mux[] = {
1878         RIF0_D1_B_MARK,
1879 };
1880 static const unsigned int drif0_ctrl_c_pins[] = {
1881         /* CLK, SYNC */
1882         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1883 };
1884 static const unsigned int drif0_ctrl_c_mux[] = {
1885         RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1886 };
1887 static const unsigned int drif0_data0_c_pins[] = {
1888         /* D0 */
1889         RCAR_GP_PIN(5, 13),
1890 };
1891 static const unsigned int drif0_data0_c_mux[] = {
1892         RIF0_D0_C_MARK,
1893 };
1894 static const unsigned int drif0_data1_c_pins[] = {
1895         /* D1 */
1896         RCAR_GP_PIN(5, 14),
1897 };
1898 static const unsigned int drif0_data1_c_mux[] = {
1899         RIF0_D1_C_MARK,
1900 };
1901 /* - DRIF1 --------------------------------------------------------------- */
1902 static const unsigned int drif1_ctrl_a_pins[] = {
1903         /* CLK, SYNC */
1904         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1905 };
1906 static const unsigned int drif1_ctrl_a_mux[] = {
1907         RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1908 };
1909 static const unsigned int drif1_data0_a_pins[] = {
1910         /* D0 */
1911         RCAR_GP_PIN(6, 19),
1912 };
1913 static const unsigned int drif1_data0_a_mux[] = {
1914         RIF1_D0_A_MARK,
1915 };
1916 static const unsigned int drif1_data1_a_pins[] = {
1917         /* D1 */
1918         RCAR_GP_PIN(6, 20),
1919 };
1920 static const unsigned int drif1_data1_a_mux[] = {
1921         RIF1_D1_A_MARK,
1922 };
1923 static const unsigned int drif1_ctrl_b_pins[] = {
1924         /* CLK, SYNC */
1925         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1926 };
1927 static const unsigned int drif1_ctrl_b_mux[] = {
1928         RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1929 };
1930 static const unsigned int drif1_data0_b_pins[] = {
1931         /* D0 */
1932         RCAR_GP_PIN(5, 7),
1933 };
1934 static const unsigned int drif1_data0_b_mux[] = {
1935         RIF1_D0_B_MARK,
1936 };
1937 static const unsigned int drif1_data1_b_pins[] = {
1938         /* D1 */
1939         RCAR_GP_PIN(5, 8),
1940 };
1941 static const unsigned int drif1_data1_b_mux[] = {
1942         RIF1_D1_B_MARK,
1943 };
1944 static const unsigned int drif1_ctrl_c_pins[] = {
1945         /* CLK, SYNC */
1946         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1947 };
1948 static const unsigned int drif1_ctrl_c_mux[] = {
1949         RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1950 };
1951 static const unsigned int drif1_data0_c_pins[] = {
1952         /* D0 */
1953         RCAR_GP_PIN(5, 6),
1954 };
1955 static const unsigned int drif1_data0_c_mux[] = {
1956         RIF1_D0_C_MARK,
1957 };
1958 static const unsigned int drif1_data1_c_pins[] = {
1959         /* D1 */
1960         RCAR_GP_PIN(5, 10),
1961 };
1962 static const unsigned int drif1_data1_c_mux[] = {
1963         RIF1_D1_C_MARK,
1964 };
1965 /* - DRIF2 --------------------------------------------------------------- */
1966 static const unsigned int drif2_ctrl_a_pins[] = {
1967         /* CLK, SYNC */
1968         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1969 };
1970 static const unsigned int drif2_ctrl_a_mux[] = {
1971         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1972 };
1973 static const unsigned int drif2_data0_a_pins[] = {
1974         /* D0 */
1975         RCAR_GP_PIN(6, 7),
1976 };
1977 static const unsigned int drif2_data0_a_mux[] = {
1978         RIF2_D0_A_MARK,
1979 };
1980 static const unsigned int drif2_data1_a_pins[] = {
1981         /* D1 */
1982         RCAR_GP_PIN(6, 10),
1983 };
1984 static const unsigned int drif2_data1_a_mux[] = {
1985         RIF2_D1_A_MARK,
1986 };
1987 static const unsigned int drif2_ctrl_b_pins[] = {
1988         /* CLK, SYNC */
1989         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1990 };
1991 static const unsigned int drif2_ctrl_b_mux[] = {
1992         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1993 };
1994 static const unsigned int drif2_data0_b_pins[] = {
1995         /* D0 */
1996         RCAR_GP_PIN(6, 30),
1997 };
1998 static const unsigned int drif2_data0_b_mux[] = {
1999         RIF2_D0_B_MARK,
2000 };
2001 static const unsigned int drif2_data1_b_pins[] = {
2002         /* D1 */
2003         RCAR_GP_PIN(6, 31),
2004 };
2005 static const unsigned int drif2_data1_b_mux[] = {
2006         RIF2_D1_B_MARK,
2007 };
2008 /* - DRIF3 --------------------------------------------------------------- */
2009 static const unsigned int drif3_ctrl_a_pins[] = {
2010         /* CLK, SYNC */
2011         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2012 };
2013 static const unsigned int drif3_ctrl_a_mux[] = {
2014         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2015 };
2016 static const unsigned int drif3_data0_a_pins[] = {
2017         /* D0 */
2018         RCAR_GP_PIN(6, 19),
2019 };
2020 static const unsigned int drif3_data0_a_mux[] = {
2021         RIF3_D0_A_MARK,
2022 };
2023 static const unsigned int drif3_data1_a_pins[] = {
2024         /* D1 */
2025         RCAR_GP_PIN(6, 20),
2026 };
2027 static const unsigned int drif3_data1_a_mux[] = {
2028         RIF3_D1_A_MARK,
2029 };
2030 static const unsigned int drif3_ctrl_b_pins[] = {
2031         /* CLK, SYNC */
2032         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2033 };
2034 static const unsigned int drif3_ctrl_b_mux[] = {
2035         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2036 };
2037 static const unsigned int drif3_data0_b_pins[] = {
2038         /* D0 */
2039         RCAR_GP_PIN(6, 28),
2040 };
2041 static const unsigned int drif3_data0_b_mux[] = {
2042         RIF3_D0_B_MARK,
2043 };
2044 static const unsigned int drif3_data1_b_pins[] = {
2045         /* D1 */
2046         RCAR_GP_PIN(6, 29),
2047 };
2048 static const unsigned int drif3_data1_b_mux[] = {
2049         RIF3_D1_B_MARK,
2050 };
2051 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
2052
2053 /* - DU --------------------------------------------------------------------- */
2054 static const unsigned int du_rgb666_pins[] = {
2055         /* R[7:2], G[7:2], B[7:2] */
2056         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2057         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2058         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2059         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2060         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2061         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2062 };
2063 static const unsigned int du_rgb666_mux[] = {
2064         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2065         DU_DR3_MARK, DU_DR2_MARK,
2066         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2067         DU_DG3_MARK, DU_DG2_MARK,
2068         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2069         DU_DB3_MARK, DU_DB2_MARK,
2070 };
2071 static const unsigned int du_rgb888_pins[] = {
2072         /* R[7:0], G[7:0], B[7:0] */
2073         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2074         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2075         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2076         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2077         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2078         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2079         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2080         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2081         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2082 };
2083 static const unsigned int du_rgb888_mux[] = {
2084         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2085         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2086         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2087         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2088         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2089         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2090 };
2091 static const unsigned int du_clk_out_0_pins[] = {
2092         /* CLKOUT */
2093         RCAR_GP_PIN(1, 27),
2094 };
2095 static const unsigned int du_clk_out_0_mux[] = {
2096         DU_DOTCLKOUT0_MARK
2097 };
2098 static const unsigned int du_clk_out_1_pins[] = {
2099         /* CLKOUT */
2100         RCAR_GP_PIN(2, 3),
2101 };
2102 static const unsigned int du_clk_out_1_mux[] = {
2103         DU_DOTCLKOUT1_MARK
2104 };
2105 static const unsigned int du_sync_pins[] = {
2106         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2107         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2108 };
2109 static const unsigned int du_sync_mux[] = {
2110         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2111 };
2112 static const unsigned int du_oddf_pins[] = {
2113         /* EXDISP/EXODDF/EXCDE */
2114         RCAR_GP_PIN(2, 2),
2115 };
2116 static const unsigned int du_oddf_mux[] = {
2117         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2118 };
2119 static const unsigned int du_cde_pins[] = {
2120         /* CDE */
2121         RCAR_GP_PIN(2, 0),
2122 };
2123 static const unsigned int du_cde_mux[] = {
2124         DU_CDE_MARK,
2125 };
2126 static const unsigned int du_disp_pins[] = {
2127         /* DISP */
2128         RCAR_GP_PIN(2, 1),
2129 };
2130 static const unsigned int du_disp_mux[] = {
2131         DU_DISP_MARK,
2132 };
2133
2134 /* - HSCIF0 ----------------------------------------------------------------- */
2135 static const unsigned int hscif0_data_pins[] = {
2136         /* RX, TX */
2137         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2138 };
2139 static const unsigned int hscif0_data_mux[] = {
2140         HRX0_MARK, HTX0_MARK,
2141 };
2142 static const unsigned int hscif0_clk_pins[] = {
2143         /* SCK */
2144         RCAR_GP_PIN(5, 12),
2145 };
2146 static const unsigned int hscif0_clk_mux[] = {
2147         HSCK0_MARK,
2148 };
2149 static const unsigned int hscif0_ctrl_pins[] = {
2150         /* RTS, CTS */
2151         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2152 };
2153 static const unsigned int hscif0_ctrl_mux[] = {
2154         HRTS0_N_MARK, HCTS0_N_MARK,
2155 };
2156 /* - HSCIF1 ----------------------------------------------------------------- */
2157 static const unsigned int hscif1_data_a_pins[] = {
2158         /* RX, TX */
2159         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2160 };
2161 static const unsigned int hscif1_data_a_mux[] = {
2162         HRX1_A_MARK, HTX1_A_MARK,
2163 };
2164 static const unsigned int hscif1_clk_a_pins[] = {
2165         /* SCK */
2166         RCAR_GP_PIN(6, 21),
2167 };
2168 static const unsigned int hscif1_clk_a_mux[] = {
2169         HSCK1_A_MARK,
2170 };
2171 static const unsigned int hscif1_ctrl_a_pins[] = {
2172         /* RTS, CTS */
2173         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2174 };
2175 static const unsigned int hscif1_ctrl_a_mux[] = {
2176         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2177 };
2178
2179 static const unsigned int hscif1_data_b_pins[] = {
2180         /* RX, TX */
2181         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2182 };
2183 static const unsigned int hscif1_data_b_mux[] = {
2184         HRX1_B_MARK, HTX1_B_MARK,
2185 };
2186 static const unsigned int hscif1_clk_b_pins[] = {
2187         /* SCK */
2188         RCAR_GP_PIN(5, 0),
2189 };
2190 static const unsigned int hscif1_clk_b_mux[] = {
2191         HSCK1_B_MARK,
2192 };
2193 static const unsigned int hscif1_ctrl_b_pins[] = {
2194         /* RTS, CTS */
2195         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2196 };
2197 static const unsigned int hscif1_ctrl_b_mux[] = {
2198         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2199 };
2200 /* - HSCIF2 ----------------------------------------------------------------- */
2201 static const unsigned int hscif2_data_a_pins[] = {
2202         /* RX, TX */
2203         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2204 };
2205 static const unsigned int hscif2_data_a_mux[] = {
2206         HRX2_A_MARK, HTX2_A_MARK,
2207 };
2208 static const unsigned int hscif2_clk_a_pins[] = {
2209         /* SCK */
2210         RCAR_GP_PIN(6, 10),
2211 };
2212 static const unsigned int hscif2_clk_a_mux[] = {
2213         HSCK2_A_MARK,
2214 };
2215 static const unsigned int hscif2_ctrl_a_pins[] = {
2216         /* RTS, CTS */
2217         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2218 };
2219 static const unsigned int hscif2_ctrl_a_mux[] = {
2220         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2221 };
2222
2223 static const unsigned int hscif2_data_b_pins[] = {
2224         /* RX, TX */
2225         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2226 };
2227 static const unsigned int hscif2_data_b_mux[] = {
2228         HRX2_B_MARK, HTX2_B_MARK,
2229 };
2230 static const unsigned int hscif2_clk_b_pins[] = {
2231         /* SCK */
2232         RCAR_GP_PIN(6, 21),
2233 };
2234 static const unsigned int hscif2_clk_b_mux[] = {
2235         HSCK2_B_MARK,
2236 };
2237 static const unsigned int hscif2_ctrl_b_pins[] = {
2238         /* RTS, CTS */
2239         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2240 };
2241 static const unsigned int hscif2_ctrl_b_mux[] = {
2242         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2243 };
2244
2245 static const unsigned int hscif2_data_c_pins[] = {
2246         /* RX, TX */
2247         RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2248 };
2249 static const unsigned int hscif2_data_c_mux[] = {
2250         HRX2_C_MARK, HTX2_C_MARK,
2251 };
2252 static const unsigned int hscif2_clk_c_pins[] = {
2253         /* SCK */
2254         RCAR_GP_PIN(6, 24),
2255 };
2256 static const unsigned int hscif2_clk_c_mux[] = {
2257         HSCK2_C_MARK,
2258 };
2259 static const unsigned int hscif2_ctrl_c_pins[] = {
2260         /* RTS, CTS */
2261         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2262 };
2263 static const unsigned int hscif2_ctrl_c_mux[] = {
2264         HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2265 };
2266 /* - HSCIF3 ----------------------------------------------------------------- */
2267 static const unsigned int hscif3_data_a_pins[] = {
2268         /* RX, TX */
2269         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2270 };
2271 static const unsigned int hscif3_data_a_mux[] = {
2272         HRX3_A_MARK, HTX3_A_MARK,
2273 };
2274 static const unsigned int hscif3_clk_pins[] = {
2275         /* SCK */
2276         RCAR_GP_PIN(1, 22),
2277 };
2278 static const unsigned int hscif3_clk_mux[] = {
2279         HSCK3_MARK,
2280 };
2281 static const unsigned int hscif3_ctrl_pins[] = {
2282         /* RTS, CTS */
2283         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2284 };
2285 static const unsigned int hscif3_ctrl_mux[] = {
2286         HRTS3_N_MARK, HCTS3_N_MARK,
2287 };
2288
2289 static const unsigned int hscif3_data_b_pins[] = {
2290         /* RX, TX */
2291         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2292 };
2293 static const unsigned int hscif3_data_b_mux[] = {
2294         HRX3_B_MARK, HTX3_B_MARK,
2295 };
2296 static const unsigned int hscif3_data_c_pins[] = {
2297         /* RX, TX */
2298         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2299 };
2300 static const unsigned int hscif3_data_c_mux[] = {
2301         HRX3_C_MARK, HTX3_C_MARK,
2302 };
2303 static const unsigned int hscif3_data_d_pins[] = {
2304         /* RX, TX */
2305         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2306 };
2307 static const unsigned int hscif3_data_d_mux[] = {
2308         HRX3_D_MARK, HTX3_D_MARK,
2309 };
2310 /* - HSCIF4 ----------------------------------------------------------------- */
2311 static const unsigned int hscif4_data_a_pins[] = {
2312         /* RX, TX */
2313         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2314 };
2315 static const unsigned int hscif4_data_a_mux[] = {
2316         HRX4_A_MARK, HTX4_A_MARK,
2317 };
2318 static const unsigned int hscif4_clk_pins[] = {
2319         /* SCK */
2320         RCAR_GP_PIN(1, 11),
2321 };
2322 static const unsigned int hscif4_clk_mux[] = {
2323         HSCK4_MARK,
2324 };
2325 static const unsigned int hscif4_ctrl_pins[] = {
2326         /* RTS, CTS */
2327         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2328 };
2329 static const unsigned int hscif4_ctrl_mux[] = {
2330         HRTS4_N_MARK, HCTS4_N_MARK,
2331 };
2332
2333 static const unsigned int hscif4_data_b_pins[] = {
2334         /* RX, TX */
2335         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2336 };
2337 static const unsigned int hscif4_data_b_mux[] = {
2338         HRX4_B_MARK, HTX4_B_MARK,
2339 };
2340
2341 /* - I2C -------------------------------------------------------------------- */
2342 static const unsigned int i2c0_pins[] = {
2343         /* SCL, SDA */
2344         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2345 };
2346
2347 static const unsigned int i2c0_mux[] = {
2348         SCL0_MARK, SDA0_MARK,
2349 };
2350
2351 static const unsigned int i2c1_a_pins[] = {
2352         /* SDA, SCL */
2353         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2354 };
2355 static const unsigned int i2c1_a_mux[] = {
2356         SDA1_A_MARK, SCL1_A_MARK,
2357 };
2358 static const unsigned int i2c1_b_pins[] = {
2359         /* SDA, SCL */
2360         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2361 };
2362 static const unsigned int i2c1_b_mux[] = {
2363         SDA1_B_MARK, SCL1_B_MARK,
2364 };
2365 static const unsigned int i2c2_a_pins[] = {
2366         /* SDA, SCL */
2367         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2368 };
2369 static const unsigned int i2c2_a_mux[] = {
2370         SDA2_A_MARK, SCL2_A_MARK,
2371 };
2372 static const unsigned int i2c2_b_pins[] = {
2373         /* SDA, SCL */
2374         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2375 };
2376 static const unsigned int i2c2_b_mux[] = {
2377         SDA2_B_MARK, SCL2_B_MARK,
2378 };
2379
2380 static const unsigned int i2c3_pins[] = {
2381         /* SCL, SDA */
2382         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2383 };
2384
2385 static const unsigned int i2c3_mux[] = {
2386         SCL3_MARK, SDA3_MARK,
2387 };
2388
2389 static const unsigned int i2c5_pins[] = {
2390         /* SCL, SDA */
2391         RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2392 };
2393
2394 static const unsigned int i2c5_mux[] = {
2395         SCL5_MARK, SDA5_MARK,
2396 };
2397
2398 static const unsigned int i2c6_a_pins[] = {
2399         /* SDA, SCL */
2400         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2401 };
2402 static const unsigned int i2c6_a_mux[] = {
2403         SDA6_A_MARK, SCL6_A_MARK,
2404 };
2405 static const unsigned int i2c6_b_pins[] = {
2406         /* SDA, SCL */
2407         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2408 };
2409 static const unsigned int i2c6_b_mux[] = {
2410         SDA6_B_MARK, SCL6_B_MARK,
2411 };
2412 static const unsigned int i2c6_c_pins[] = {
2413         /* SDA, SCL */
2414         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2415 };
2416 static const unsigned int i2c6_c_mux[] = {
2417         SDA6_C_MARK, SCL6_C_MARK,
2418 };
2419
2420 /* - INTC-EX ---------------------------------------------------------------- */
2421 static const unsigned int intc_ex_irq0_pins[] = {
2422         /* IRQ0 */
2423         RCAR_GP_PIN(2, 0),
2424 };
2425 static const unsigned int intc_ex_irq0_mux[] = {
2426         IRQ0_MARK,
2427 };
2428 static const unsigned int intc_ex_irq1_pins[] = {
2429         /* IRQ1 */
2430         RCAR_GP_PIN(2, 1),
2431 };
2432 static const unsigned int intc_ex_irq1_mux[] = {
2433         IRQ1_MARK,
2434 };
2435 static const unsigned int intc_ex_irq2_pins[] = {
2436         /* IRQ2 */
2437         RCAR_GP_PIN(2, 2),
2438 };
2439 static const unsigned int intc_ex_irq2_mux[] = {
2440         IRQ2_MARK,
2441 };
2442 static const unsigned int intc_ex_irq3_pins[] = {
2443         /* IRQ3 */
2444         RCAR_GP_PIN(2, 3),
2445 };
2446 static const unsigned int intc_ex_irq3_mux[] = {
2447         IRQ3_MARK,
2448 };
2449 static const unsigned int intc_ex_irq4_pins[] = {
2450         /* IRQ4 */
2451         RCAR_GP_PIN(2, 4),
2452 };
2453 static const unsigned int intc_ex_irq4_mux[] = {
2454         IRQ4_MARK,
2455 };
2456 static const unsigned int intc_ex_irq5_pins[] = {
2457         /* IRQ5 */
2458         RCAR_GP_PIN(2, 5),
2459 };
2460 static const unsigned int intc_ex_irq5_mux[] = {
2461         IRQ5_MARK,
2462 };
2463
2464 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
2465 /* - MLB+ ------------------------------------------------------------------- */
2466 static const unsigned int mlb_3pin_pins[] = {
2467         RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2468 };
2469 static const unsigned int mlb_3pin_mux[] = {
2470         MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2471 };
2472 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
2473
2474 /* - MSIOF0 ----------------------------------------------------------------- */
2475 static const unsigned int msiof0_clk_pins[] = {
2476         /* SCK */
2477         RCAR_GP_PIN(5, 17),
2478 };
2479 static const unsigned int msiof0_clk_mux[] = {
2480         MSIOF0_SCK_MARK,
2481 };
2482 static const unsigned int msiof0_sync_pins[] = {
2483         /* SYNC */
2484         RCAR_GP_PIN(5, 18),
2485 };
2486 static const unsigned int msiof0_sync_mux[] = {
2487         MSIOF0_SYNC_MARK,
2488 };
2489 static const unsigned int msiof0_ss1_pins[] = {
2490         /* SS1 */
2491         RCAR_GP_PIN(5, 19),
2492 };
2493 static const unsigned int msiof0_ss1_mux[] = {
2494         MSIOF0_SS1_MARK,
2495 };
2496 static const unsigned int msiof0_ss2_pins[] = {
2497         /* SS2 */
2498         RCAR_GP_PIN(5, 21),
2499 };
2500 static const unsigned int msiof0_ss2_mux[] = {
2501         MSIOF0_SS2_MARK,
2502 };
2503 static const unsigned int msiof0_txd_pins[] = {
2504         /* TXD */
2505         RCAR_GP_PIN(5, 20),
2506 };
2507 static const unsigned int msiof0_txd_mux[] = {
2508         MSIOF0_TXD_MARK,
2509 };
2510 static const unsigned int msiof0_rxd_pins[] = {
2511         /* RXD */
2512         RCAR_GP_PIN(5, 22),
2513 };
2514 static const unsigned int msiof0_rxd_mux[] = {
2515         MSIOF0_RXD_MARK,
2516 };
2517 /* - MSIOF1 ----------------------------------------------------------------- */
2518 static const unsigned int msiof1_clk_a_pins[] = {
2519         /* SCK */
2520         RCAR_GP_PIN(6, 8),
2521 };
2522 static const unsigned int msiof1_clk_a_mux[] = {
2523         MSIOF1_SCK_A_MARK,
2524 };
2525 static const unsigned int msiof1_sync_a_pins[] = {
2526         /* SYNC */
2527         RCAR_GP_PIN(6, 9),
2528 };
2529 static const unsigned int msiof1_sync_a_mux[] = {
2530         MSIOF1_SYNC_A_MARK,
2531 };
2532 static const unsigned int msiof1_ss1_a_pins[] = {
2533         /* SS1 */
2534         RCAR_GP_PIN(6, 5),
2535 };
2536 static const unsigned int msiof1_ss1_a_mux[] = {
2537         MSIOF1_SS1_A_MARK,
2538 };
2539 static const unsigned int msiof1_ss2_a_pins[] = {
2540         /* SS2 */
2541         RCAR_GP_PIN(6, 6),
2542 };
2543 static const unsigned int msiof1_ss2_a_mux[] = {
2544         MSIOF1_SS2_A_MARK,
2545 };
2546 static const unsigned int msiof1_txd_a_pins[] = {
2547         /* TXD */
2548         RCAR_GP_PIN(6, 7),
2549 };
2550 static const unsigned int msiof1_txd_a_mux[] = {
2551         MSIOF1_TXD_A_MARK,
2552 };
2553 static const unsigned int msiof1_rxd_a_pins[] = {
2554         /* RXD */
2555         RCAR_GP_PIN(6, 10),
2556 };
2557 static const unsigned int msiof1_rxd_a_mux[] = {
2558         MSIOF1_RXD_A_MARK,
2559 };
2560 static const unsigned int msiof1_clk_b_pins[] = {
2561         /* SCK */
2562         RCAR_GP_PIN(5, 9),
2563 };
2564 static const unsigned int msiof1_clk_b_mux[] = {
2565         MSIOF1_SCK_B_MARK,
2566 };
2567 static const unsigned int msiof1_sync_b_pins[] = {
2568         /* SYNC */
2569         RCAR_GP_PIN(5, 3),
2570 };
2571 static const unsigned int msiof1_sync_b_mux[] = {
2572         MSIOF1_SYNC_B_MARK,
2573 };
2574 static const unsigned int msiof1_ss1_b_pins[] = {
2575         /* SS1 */
2576         RCAR_GP_PIN(5, 4),
2577 };
2578 static const unsigned int msiof1_ss1_b_mux[] = {
2579         MSIOF1_SS1_B_MARK,
2580 };
2581 static const unsigned int msiof1_ss2_b_pins[] = {
2582         /* SS2 */
2583         RCAR_GP_PIN(5, 0),
2584 };
2585 static const unsigned int msiof1_ss2_b_mux[] = {
2586         MSIOF1_SS2_B_MARK,
2587 };
2588 static const unsigned int msiof1_txd_b_pins[] = {
2589         /* TXD */
2590         RCAR_GP_PIN(5, 8),
2591 };
2592 static const unsigned int msiof1_txd_b_mux[] = {
2593         MSIOF1_TXD_B_MARK,
2594 };
2595 static const unsigned int msiof1_rxd_b_pins[] = {
2596         /* RXD */
2597         RCAR_GP_PIN(5, 7),
2598 };
2599 static const unsigned int msiof1_rxd_b_mux[] = {
2600         MSIOF1_RXD_B_MARK,
2601 };
2602 static const unsigned int msiof1_clk_c_pins[] = {
2603         /* SCK */
2604         RCAR_GP_PIN(6, 17),
2605 };
2606 static const unsigned int msiof1_clk_c_mux[] = {
2607         MSIOF1_SCK_C_MARK,
2608 };
2609 static const unsigned int msiof1_sync_c_pins[] = {
2610         /* SYNC */
2611         RCAR_GP_PIN(6, 18),
2612 };
2613 static const unsigned int msiof1_sync_c_mux[] = {
2614         MSIOF1_SYNC_C_MARK,
2615 };
2616 static const unsigned int msiof1_ss1_c_pins[] = {
2617         /* SS1 */
2618         RCAR_GP_PIN(6, 21),
2619 };
2620 static const unsigned int msiof1_ss1_c_mux[] = {
2621         MSIOF1_SS1_C_MARK,
2622 };
2623 static const unsigned int msiof1_ss2_c_pins[] = {
2624         /* SS2 */
2625         RCAR_GP_PIN(6, 27),
2626 };
2627 static const unsigned int msiof1_ss2_c_mux[] = {
2628         MSIOF1_SS2_C_MARK,
2629 };
2630 static const unsigned int msiof1_txd_c_pins[] = {
2631         /* TXD */
2632         RCAR_GP_PIN(6, 20),
2633 };
2634 static const unsigned int msiof1_txd_c_mux[] = {
2635         MSIOF1_TXD_C_MARK,
2636 };
2637 static const unsigned int msiof1_rxd_c_pins[] = {
2638         /* RXD */
2639         RCAR_GP_PIN(6, 19),
2640 };
2641 static const unsigned int msiof1_rxd_c_mux[] = {
2642         MSIOF1_RXD_C_MARK,
2643 };
2644 static const unsigned int msiof1_clk_d_pins[] = {
2645         /* SCK */
2646         RCAR_GP_PIN(5, 12),
2647 };
2648 static const unsigned int msiof1_clk_d_mux[] = {
2649         MSIOF1_SCK_D_MARK,
2650 };
2651 static const unsigned int msiof1_sync_d_pins[] = {
2652         /* SYNC */
2653         RCAR_GP_PIN(5, 15),
2654 };
2655 static const unsigned int msiof1_sync_d_mux[] = {
2656         MSIOF1_SYNC_D_MARK,
2657 };
2658 static const unsigned int msiof1_ss1_d_pins[] = {
2659         /* SS1 */
2660         RCAR_GP_PIN(5, 16),
2661 };
2662 static const unsigned int msiof1_ss1_d_mux[] = {
2663         MSIOF1_SS1_D_MARK,
2664 };
2665 static const unsigned int msiof1_ss2_d_pins[] = {
2666         /* SS2 */
2667         RCAR_GP_PIN(5, 21),
2668 };
2669 static const unsigned int msiof1_ss2_d_mux[] = {
2670         MSIOF1_SS2_D_MARK,
2671 };
2672 static const unsigned int msiof1_txd_d_pins[] = {
2673         /* TXD */
2674         RCAR_GP_PIN(5, 14),
2675 };
2676 static const unsigned int msiof1_txd_d_mux[] = {
2677         MSIOF1_TXD_D_MARK,
2678 };
2679 static const unsigned int msiof1_rxd_d_pins[] = {
2680         /* RXD */
2681         RCAR_GP_PIN(5, 13),
2682 };
2683 static const unsigned int msiof1_rxd_d_mux[] = {
2684         MSIOF1_RXD_D_MARK,
2685 };
2686 static const unsigned int msiof1_clk_e_pins[] = {
2687         /* SCK */
2688         RCAR_GP_PIN(3, 0),
2689 };
2690 static const unsigned int msiof1_clk_e_mux[] = {
2691         MSIOF1_SCK_E_MARK,
2692 };
2693 static const unsigned int msiof1_sync_e_pins[] = {
2694         /* SYNC */
2695         RCAR_GP_PIN(3, 1),
2696 };
2697 static const unsigned int msiof1_sync_e_mux[] = {
2698         MSIOF1_SYNC_E_MARK,
2699 };
2700 static const unsigned int msiof1_ss1_e_pins[] = {
2701         /* SS1 */
2702         RCAR_GP_PIN(3, 4),
2703 };
2704 static const unsigned int msiof1_ss1_e_mux[] = {
2705         MSIOF1_SS1_E_MARK,
2706 };
2707 static const unsigned int msiof1_ss2_e_pins[] = {
2708         /* SS2 */
2709         RCAR_GP_PIN(3, 5),
2710 };
2711 static const unsigned int msiof1_ss2_e_mux[] = {
2712         MSIOF1_SS2_E_MARK,
2713 };
2714 static const unsigned int msiof1_txd_e_pins[] = {
2715         /* TXD */
2716         RCAR_GP_PIN(3, 3),
2717 };
2718 static const unsigned int msiof1_txd_e_mux[] = {
2719         MSIOF1_TXD_E_MARK,
2720 };
2721 static const unsigned int msiof1_rxd_e_pins[] = {
2722         /* RXD */
2723         RCAR_GP_PIN(3, 2),
2724 };
2725 static const unsigned int msiof1_rxd_e_mux[] = {
2726         MSIOF1_RXD_E_MARK,
2727 };
2728 static const unsigned int msiof1_clk_f_pins[] = {
2729         /* SCK */
2730         RCAR_GP_PIN(5, 23),
2731 };
2732 static const unsigned int msiof1_clk_f_mux[] = {
2733         MSIOF1_SCK_F_MARK,
2734 };
2735 static const unsigned int msiof1_sync_f_pins[] = {
2736         /* SYNC */
2737         RCAR_GP_PIN(5, 24),
2738 };
2739 static const unsigned int msiof1_sync_f_mux[] = {
2740         MSIOF1_SYNC_F_MARK,
2741 };
2742 static const unsigned int msiof1_ss1_f_pins[] = {
2743         /* SS1 */
2744         RCAR_GP_PIN(6, 1),
2745 };
2746 static const unsigned int msiof1_ss1_f_mux[] = {
2747         MSIOF1_SS1_F_MARK,
2748 };
2749 static const unsigned int msiof1_ss2_f_pins[] = {
2750         /* SS2 */
2751         RCAR_GP_PIN(6, 2),
2752 };
2753 static const unsigned int msiof1_ss2_f_mux[] = {
2754         MSIOF1_SS2_F_MARK,
2755 };
2756 static const unsigned int msiof1_txd_f_pins[] = {
2757         /* TXD */
2758         RCAR_GP_PIN(6, 0),
2759 };
2760 static const unsigned int msiof1_txd_f_mux[] = {
2761         MSIOF1_TXD_F_MARK,
2762 };
2763 static const unsigned int msiof1_rxd_f_pins[] = {
2764         /* RXD */
2765         RCAR_GP_PIN(5, 25),
2766 };
2767 static const unsigned int msiof1_rxd_f_mux[] = {
2768         MSIOF1_RXD_F_MARK,
2769 };
2770 static const unsigned int msiof1_clk_g_pins[] = {
2771         /* SCK */
2772         RCAR_GP_PIN(3, 6),
2773 };
2774 static const unsigned int msiof1_clk_g_mux[] = {
2775         MSIOF1_SCK_G_MARK,
2776 };
2777 static const unsigned int msiof1_sync_g_pins[] = {
2778         /* SYNC */
2779         RCAR_GP_PIN(3, 7),
2780 };
2781 static const unsigned int msiof1_sync_g_mux[] = {
2782         MSIOF1_SYNC_G_MARK,
2783 };
2784 static const unsigned int msiof1_ss1_g_pins[] = {
2785         /* SS1 */
2786         RCAR_GP_PIN(3, 10),
2787 };
2788 static const unsigned int msiof1_ss1_g_mux[] = {
2789         MSIOF1_SS1_G_MARK,
2790 };
2791 static const unsigned int msiof1_ss2_g_pins[] = {
2792         /* SS2 */
2793         RCAR_GP_PIN(3, 11),
2794 };
2795 static const unsigned int msiof1_ss2_g_mux[] = {
2796         MSIOF1_SS2_G_MARK,
2797 };
2798 static const unsigned int msiof1_txd_g_pins[] = {
2799         /* TXD */
2800         RCAR_GP_PIN(3, 9),
2801 };
2802 static const unsigned int msiof1_txd_g_mux[] = {
2803         MSIOF1_TXD_G_MARK,
2804 };
2805 static const unsigned int msiof1_rxd_g_pins[] = {
2806         /* RXD */
2807         RCAR_GP_PIN(3, 8),
2808 };
2809 static const unsigned int msiof1_rxd_g_mux[] = {
2810         MSIOF1_RXD_G_MARK,
2811 };
2812 /* - MSIOF2 ----------------------------------------------------------------- */
2813 static const unsigned int msiof2_clk_a_pins[] = {
2814         /* SCK */
2815         RCAR_GP_PIN(1, 9),
2816 };
2817 static const unsigned int msiof2_clk_a_mux[] = {
2818         MSIOF2_SCK_A_MARK,
2819 };
2820 static const unsigned int msiof2_sync_a_pins[] = {
2821         /* SYNC */
2822         RCAR_GP_PIN(1, 8),
2823 };
2824 static const unsigned int msiof2_sync_a_mux[] = {
2825         MSIOF2_SYNC_A_MARK,
2826 };
2827 static const unsigned int msiof2_ss1_a_pins[] = {
2828         /* SS1 */
2829         RCAR_GP_PIN(1, 6),
2830 };
2831 static const unsigned int msiof2_ss1_a_mux[] = {
2832         MSIOF2_SS1_A_MARK,
2833 };
2834 static const unsigned int msiof2_ss2_a_pins[] = {
2835         /* SS2 */
2836         RCAR_GP_PIN(1, 7),
2837 };
2838 static const unsigned int msiof2_ss2_a_mux[] = {
2839         MSIOF2_SS2_A_MARK,
2840 };
2841 static const unsigned int msiof2_txd_a_pins[] = {
2842         /* TXD */
2843         RCAR_GP_PIN(1, 11),
2844 };
2845 static const unsigned int msiof2_txd_a_mux[] = {
2846         MSIOF2_TXD_A_MARK,
2847 };
2848 static const unsigned int msiof2_rxd_a_pins[] = {
2849         /* RXD */
2850         RCAR_GP_PIN(1, 10),
2851 };
2852 static const unsigned int msiof2_rxd_a_mux[] = {
2853         MSIOF2_RXD_A_MARK,
2854 };
2855 static const unsigned int msiof2_clk_b_pins[] = {
2856         /* SCK */
2857         RCAR_GP_PIN(0, 4),
2858 };
2859 static const unsigned int msiof2_clk_b_mux[] = {
2860         MSIOF2_SCK_B_MARK,
2861 };
2862 static const unsigned int msiof2_sync_b_pins[] = {
2863         /* SYNC */
2864         RCAR_GP_PIN(0, 5),
2865 };
2866 static const unsigned int msiof2_sync_b_mux[] = {
2867         MSIOF2_SYNC_B_MARK,
2868 };
2869 static const unsigned int msiof2_ss1_b_pins[] = {
2870         /* SS1 */
2871         RCAR_GP_PIN(0, 0),
2872 };
2873 static const unsigned int msiof2_ss1_b_mux[] = {
2874         MSIOF2_SS1_B_MARK,
2875 };
2876 static const unsigned int msiof2_ss2_b_pins[] = {
2877         /* SS2 */
2878         RCAR_GP_PIN(0, 1),
2879 };
2880 static const unsigned int msiof2_ss2_b_mux[] = {
2881         MSIOF2_SS2_B_MARK,
2882 };
2883 static const unsigned int msiof2_txd_b_pins[] = {
2884         /* TXD */
2885         RCAR_GP_PIN(0, 7),
2886 };
2887 static const unsigned int msiof2_txd_b_mux[] = {
2888         MSIOF2_TXD_B_MARK,
2889 };
2890 static const unsigned int msiof2_rxd_b_pins[] = {
2891         /* RXD */
2892         RCAR_GP_PIN(0, 6),
2893 };
2894 static const unsigned int msiof2_rxd_b_mux[] = {
2895         MSIOF2_RXD_B_MARK,
2896 };
2897 static const unsigned int msiof2_clk_c_pins[] = {
2898         /* SCK */
2899         RCAR_GP_PIN(2, 12),
2900 };
2901 static const unsigned int msiof2_clk_c_mux[] = {
2902         MSIOF2_SCK_C_MARK,
2903 };
2904 static const unsigned int msiof2_sync_c_pins[] = {
2905         /* SYNC */
2906         RCAR_GP_PIN(2, 11),
2907 };
2908 static const unsigned int msiof2_sync_c_mux[] = {
2909         MSIOF2_SYNC_C_MARK,
2910 };
2911 static const unsigned int msiof2_ss1_c_pins[] = {
2912         /* SS1 */
2913         RCAR_GP_PIN(2, 10),
2914 };
2915 static const unsigned int msiof2_ss1_c_mux[] = {
2916         MSIOF2_SS1_C_MARK,
2917 };
2918 static const unsigned int msiof2_ss2_c_pins[] = {
2919         /* SS2 */
2920         RCAR_GP_PIN(2, 9),
2921 };
2922 static const unsigned int msiof2_ss2_c_mux[] = {
2923         MSIOF2_SS2_C_MARK,
2924 };
2925 static const unsigned int msiof2_txd_c_pins[] = {
2926         /* TXD */
2927         RCAR_GP_PIN(2, 14),
2928 };
2929 static const unsigned int msiof2_txd_c_mux[] = {
2930         MSIOF2_TXD_C_MARK,
2931 };
2932 static const unsigned int msiof2_rxd_c_pins[] = {
2933         /* RXD */
2934         RCAR_GP_PIN(2, 13),
2935 };
2936 static const unsigned int msiof2_rxd_c_mux[] = {
2937         MSIOF2_RXD_C_MARK,
2938 };
2939 static const unsigned int msiof2_clk_d_pins[] = {
2940         /* SCK */
2941         RCAR_GP_PIN(0, 8),
2942 };
2943 static const unsigned int msiof2_clk_d_mux[] = {
2944         MSIOF2_SCK_D_MARK,
2945 };
2946 static const unsigned int msiof2_sync_d_pins[] = {
2947         /* SYNC */
2948         RCAR_GP_PIN(0, 9),
2949 };
2950 static const unsigned int msiof2_sync_d_mux[] = {
2951         MSIOF2_SYNC_D_MARK,
2952 };
2953 static const unsigned int msiof2_ss1_d_pins[] = {
2954         /* SS1 */
2955         RCAR_GP_PIN(0, 12),
2956 };
2957 static const unsigned int msiof2_ss1_d_mux[] = {
2958         MSIOF2_SS1_D_MARK,
2959 };
2960 static const unsigned int msiof2_ss2_d_pins[] = {
2961         /* SS2 */
2962         RCAR_GP_PIN(0, 13),
2963 };
2964 static const unsigned int msiof2_ss2_d_mux[] = {
2965         MSIOF2_SS2_D_MARK,
2966 };
2967 static const unsigned int msiof2_txd_d_pins[] = {
2968         /* TXD */
2969         RCAR_GP_PIN(0, 11),
2970 };
2971 static const unsigned int msiof2_txd_d_mux[] = {
2972         MSIOF2_TXD_D_MARK,
2973 };
2974 static const unsigned int msiof2_rxd_d_pins[] = {
2975         /* RXD */
2976         RCAR_GP_PIN(0, 10),
2977 };
2978 static const unsigned int msiof2_rxd_d_mux[] = {
2979         MSIOF2_RXD_D_MARK,
2980 };
2981 /* - MSIOF3 ----------------------------------------------------------------- */
2982 static const unsigned int msiof3_clk_a_pins[] = {
2983         /* SCK */
2984         RCAR_GP_PIN(0, 0),
2985 };
2986 static const unsigned int msiof3_clk_a_mux[] = {
2987         MSIOF3_SCK_A_MARK,
2988 };
2989 static const unsigned int msiof3_sync_a_pins[] = {
2990         /* SYNC */
2991         RCAR_GP_PIN(0, 1),
2992 };
2993 static const unsigned int msiof3_sync_a_mux[] = {
2994         MSIOF3_SYNC_A_MARK,
2995 };
2996 static const unsigned int msiof3_ss1_a_pins[] = {
2997         /* SS1 */
2998         RCAR_GP_PIN(0, 14),
2999 };
3000 static const unsigned int msiof3_ss1_a_mux[] = {
3001         MSIOF3_SS1_A_MARK,
3002 };
3003 static const unsigned int msiof3_ss2_a_pins[] = {
3004         /* SS2 */
3005         RCAR_GP_PIN(0, 15),
3006 };
3007 static const unsigned int msiof3_ss2_a_mux[] = {
3008         MSIOF3_SS2_A_MARK,
3009 };
3010 static const unsigned int msiof3_txd_a_pins[] = {
3011         /* TXD */
3012         RCAR_GP_PIN(0, 3),
3013 };
3014 static const unsigned int msiof3_txd_a_mux[] = {
3015         MSIOF3_TXD_A_MARK,
3016 };
3017 static const unsigned int msiof3_rxd_a_pins[] = {
3018         /* RXD */
3019         RCAR_GP_PIN(0, 2),
3020 };
3021 static const unsigned int msiof3_rxd_a_mux[] = {
3022         MSIOF3_RXD_A_MARK,
3023 };
3024 static const unsigned int msiof3_clk_b_pins[] = {
3025         /* SCK */
3026         RCAR_GP_PIN(1, 2),
3027 };
3028 static const unsigned int msiof3_clk_b_mux[] = {
3029         MSIOF3_SCK_B_MARK,
3030 };
3031 static const unsigned int msiof3_sync_b_pins[] = {
3032         /* SYNC */
3033         RCAR_GP_PIN(1, 0),
3034 };
3035 static const unsigned int msiof3_sync_b_mux[] = {
3036         MSIOF3_SYNC_B_MARK,
3037 };
3038 static const unsigned int msiof3_ss1_b_pins[] = {
3039         /* SS1 */
3040         RCAR_GP_PIN(1, 4),
3041 };
3042 static const unsigned int msiof3_ss1_b_mux[] = {
3043         MSIOF3_SS1_B_MARK,
3044 };
3045 static const unsigned int msiof3_ss2_b_pins[] = {
3046         /* SS2 */
3047         RCAR_GP_PIN(1, 5),
3048 };
3049 static const unsigned int msiof3_ss2_b_mux[] = {
3050         MSIOF3_SS2_B_MARK,
3051 };
3052 static const unsigned int msiof3_txd_b_pins[] = {
3053         /* TXD */
3054         RCAR_GP_PIN(1, 1),
3055 };
3056 static const unsigned int msiof3_txd_b_mux[] = {
3057         MSIOF3_TXD_B_MARK,
3058 };
3059 static const unsigned int msiof3_rxd_b_pins[] = {
3060         /* RXD */
3061         RCAR_GP_PIN(1, 3),
3062 };
3063 static const unsigned int msiof3_rxd_b_mux[] = {
3064         MSIOF3_RXD_B_MARK,
3065 };
3066 static const unsigned int msiof3_clk_c_pins[] = {
3067         /* SCK */
3068         RCAR_GP_PIN(1, 12),
3069 };
3070 static const unsigned int msiof3_clk_c_mux[] = {
3071         MSIOF3_SCK_C_MARK,
3072 };
3073 static const unsigned int msiof3_sync_c_pins[] = {
3074         /* SYNC */
3075         RCAR_GP_PIN(1, 13),
3076 };
3077 static const unsigned int msiof3_sync_c_mux[] = {
3078         MSIOF3_SYNC_C_MARK,
3079 };
3080 static const unsigned int msiof3_txd_c_pins[] = {
3081         /* TXD */
3082         RCAR_GP_PIN(1, 15),
3083 };
3084 static const unsigned int msiof3_txd_c_mux[] = {
3085         MSIOF3_TXD_C_MARK,
3086 };
3087 static const unsigned int msiof3_rxd_c_pins[] = {
3088         /* RXD */
3089         RCAR_GP_PIN(1, 14),
3090 };
3091 static const unsigned int msiof3_rxd_c_mux[] = {
3092         MSIOF3_RXD_C_MARK,
3093 };
3094 static const unsigned int msiof3_clk_d_pins[] = {
3095         /* SCK */
3096         RCAR_GP_PIN(1, 22),
3097 };
3098 static const unsigned int msiof3_clk_d_mux[] = {
3099         MSIOF3_SCK_D_MARK,
3100 };
3101 static const unsigned int msiof3_sync_d_pins[] = {
3102         /* SYNC */
3103         RCAR_GP_PIN(1, 23),
3104 };
3105 static const unsigned int msiof3_sync_d_mux[] = {
3106         MSIOF3_SYNC_D_MARK,
3107 };
3108 static const unsigned int msiof3_ss1_d_pins[] = {
3109         /* SS1 */
3110         RCAR_GP_PIN(1, 26),
3111 };
3112 static const unsigned int msiof3_ss1_d_mux[] = {
3113         MSIOF3_SS1_D_MARK,
3114 };
3115 static const unsigned int msiof3_txd_d_pins[] = {
3116         /* TXD */
3117         RCAR_GP_PIN(1, 25),
3118 };
3119 static const unsigned int msiof3_txd_d_mux[] = {
3120         MSIOF3_TXD_D_MARK,
3121 };
3122 static const unsigned int msiof3_rxd_d_pins[] = {
3123         /* RXD */
3124         RCAR_GP_PIN(1, 24),
3125 };
3126 static const unsigned int msiof3_rxd_d_mux[] = {
3127         MSIOF3_RXD_D_MARK,
3128 };
3129
3130 static const unsigned int msiof3_clk_e_pins[] = {
3131         /* SCK */
3132         RCAR_GP_PIN(2, 3),
3133 };
3134 static const unsigned int msiof3_clk_e_mux[] = {
3135         MSIOF3_SCK_E_MARK,
3136 };
3137 static const unsigned int msiof3_sync_e_pins[] = {
3138         /* SYNC */
3139         RCAR_GP_PIN(2, 2),
3140 };
3141 static const unsigned int msiof3_sync_e_mux[] = {
3142         MSIOF3_SYNC_E_MARK,
3143 };
3144 static const unsigned int msiof3_ss1_e_pins[] = {
3145         /* SS1 */
3146         RCAR_GP_PIN(2, 1),
3147 };
3148 static const unsigned int msiof3_ss1_e_mux[] = {
3149         MSIOF3_SS1_E_MARK,
3150 };
3151 static const unsigned int msiof3_ss2_e_pins[] = {
3152         /* SS2 */
3153         RCAR_GP_PIN(2, 0),
3154 };
3155 static const unsigned int msiof3_ss2_e_mux[] = {
3156         MSIOF3_SS2_E_MARK,
3157 };
3158 static const unsigned int msiof3_txd_e_pins[] = {
3159         /* TXD */
3160         RCAR_GP_PIN(2, 5),
3161 };
3162 static const unsigned int msiof3_txd_e_mux[] = {
3163         MSIOF3_TXD_E_MARK,
3164 };
3165 static const unsigned int msiof3_rxd_e_pins[] = {
3166         /* RXD */
3167         RCAR_GP_PIN(2, 4),
3168 };
3169 static const unsigned int msiof3_rxd_e_mux[] = {
3170         MSIOF3_RXD_E_MARK,
3171 };
3172
3173 /* - PWM0 --------------------------------------------------------------------*/
3174 static const unsigned int pwm0_pins[] = {
3175         /* PWM */
3176         RCAR_GP_PIN(2, 6),
3177 };
3178 static const unsigned int pwm0_mux[] = {
3179         PWM0_MARK,
3180 };
3181 /* - PWM1 --------------------------------------------------------------------*/
3182 static const unsigned int pwm1_a_pins[] = {
3183         /* PWM */
3184         RCAR_GP_PIN(2, 7),
3185 };
3186 static const unsigned int pwm1_a_mux[] = {
3187         PWM1_A_MARK,
3188 };
3189 static const unsigned int pwm1_b_pins[] = {
3190         /* PWM */
3191         RCAR_GP_PIN(1, 8),
3192 };
3193 static const unsigned int pwm1_b_mux[] = {
3194         PWM1_B_MARK,
3195 };
3196 /* - PWM2 --------------------------------------------------------------------*/
3197 static const unsigned int pwm2_a_pins[] = {
3198         /* PWM */
3199         RCAR_GP_PIN(2, 8),
3200 };
3201 static const unsigned int pwm2_a_mux[] = {
3202         PWM2_A_MARK,
3203 };
3204 static const unsigned int pwm2_b_pins[] = {
3205         /* PWM */
3206         RCAR_GP_PIN(1, 11),
3207 };
3208 static const unsigned int pwm2_b_mux[] = {
3209         PWM2_B_MARK,
3210 };
3211 /* - PWM3 --------------------------------------------------------------------*/
3212 static const unsigned int pwm3_a_pins[] = {
3213         /* PWM */
3214         RCAR_GP_PIN(1, 0),
3215 };
3216 static const unsigned int pwm3_a_mux[] = {
3217         PWM3_A_MARK,
3218 };
3219 static const unsigned int pwm3_b_pins[] = {
3220         /* PWM */
3221         RCAR_GP_PIN(2, 2),
3222 };
3223 static const unsigned int pwm3_b_mux[] = {
3224         PWM3_B_MARK,
3225 };
3226 /* - PWM4 --------------------------------------------------------------------*/
3227 static const unsigned int pwm4_a_pins[] = {
3228         /* PWM */
3229         RCAR_GP_PIN(1, 1),
3230 };
3231 static const unsigned int pwm4_a_mux[] = {
3232         PWM4_A_MARK,
3233 };
3234 static const unsigned int pwm4_b_pins[] = {
3235         /* PWM */
3236         RCAR_GP_PIN(2, 3),
3237 };
3238 static const unsigned int pwm4_b_mux[] = {
3239         PWM4_B_MARK,
3240 };
3241 /* - PWM5 --------------------------------------------------------------------*/
3242 static const unsigned int pwm5_a_pins[] = {
3243         /* PWM */
3244         RCAR_GP_PIN(1, 2),
3245 };
3246 static const unsigned int pwm5_a_mux[] = {
3247         PWM5_A_MARK,
3248 };
3249 static const unsigned int pwm5_b_pins[] = {
3250         /* PWM */
3251         RCAR_GP_PIN(2, 4),
3252 };
3253 static const unsigned int pwm5_b_mux[] = {
3254         PWM5_B_MARK,
3255 };
3256 /* - PWM6 --------------------------------------------------------------------*/
3257 static const unsigned int pwm6_a_pins[] = {
3258         /* PWM */
3259         RCAR_GP_PIN(1, 3),
3260 };
3261 static const unsigned int pwm6_a_mux[] = {
3262         PWM6_A_MARK,
3263 };
3264 static const unsigned int pwm6_b_pins[] = {
3265         /* PWM */
3266         RCAR_GP_PIN(2, 5),
3267 };
3268 static const unsigned int pwm6_b_mux[] = {
3269         PWM6_B_MARK,
3270 };
3271
3272 /* - QSPI0 ------------------------------------------------------------------ */
3273 static const unsigned int qspi0_ctrl_pins[] = {
3274         /* QSPI0_SPCLK, QSPI0_SSL */
3275         PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3276 };
3277 static const unsigned int qspi0_ctrl_mux[] = {
3278         QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3279 };
3280 static const unsigned int qspi0_data_pins[] = {
3281         /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3282         PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3283         /* QSPI0_IO2, QSPI0_IO3 */
3284         PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3285 };
3286 static const unsigned int qspi0_data_mux[] = {
3287         QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3288         QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3289 };
3290 /* - QSPI1 ------------------------------------------------------------------ */
3291 static const unsigned int qspi1_ctrl_pins[] = {
3292         /* QSPI1_SPCLK, QSPI1_SSL */
3293         PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3294 };
3295 static const unsigned int qspi1_ctrl_mux[] = {
3296         QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3297 };
3298 static const unsigned int qspi1_data_pins[] = {
3299         /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3300         PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3301         /* QSPI1_IO2, QSPI1_IO3 */
3302         PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3303 };
3304 static const unsigned int qspi1_data_mux[] = {
3305         QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3306         QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3307 };
3308
3309 /* - SCIF0 ------------------------------------------------------------------ */
3310 static const unsigned int scif0_data_pins[] = {
3311         /* RX, TX */
3312         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3313 };
3314 static const unsigned int scif0_data_mux[] = {
3315         RX0_MARK, TX0_MARK,
3316 };
3317 static const unsigned int scif0_clk_pins[] = {
3318         /* SCK */
3319         RCAR_GP_PIN(5, 0),
3320 };
3321 static const unsigned int scif0_clk_mux[] = {
3322         SCK0_MARK,
3323 };
3324 static const unsigned int scif0_ctrl_pins[] = {
3325         /* RTS, CTS */
3326         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3327 };
3328 static const unsigned int scif0_ctrl_mux[] = {
3329         RTS0_N_MARK, CTS0_N_MARK,
3330 };
3331 /* - SCIF1 ------------------------------------------------------------------ */
3332 static const unsigned int scif1_data_a_pins[] = {
3333         /* RX, TX */
3334         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3335 };
3336 static const unsigned int scif1_data_a_mux[] = {
3337         RX1_A_MARK, TX1_A_MARK,
3338 };
3339 static const unsigned int scif1_clk_pins[] = {
3340         /* SCK */
3341         RCAR_GP_PIN(6, 21),
3342 };
3343 static const unsigned int scif1_clk_mux[] = {
3344         SCK1_MARK,
3345 };
3346 static const unsigned int scif1_ctrl_pins[] = {
3347         /* RTS, CTS */
3348         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3349 };
3350 static const unsigned int scif1_ctrl_mux[] = {
3351         RTS1_N_MARK, CTS1_N_MARK,
3352 };
3353
3354 static const unsigned int scif1_data_b_pins[] = {
3355         /* RX, TX */
3356         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3357 };
3358 static const unsigned int scif1_data_b_mux[] = {
3359         RX1_B_MARK, TX1_B_MARK,
3360 };
3361 /* - SCIF2 ------------------------------------------------------------------ */
3362 static const unsigned int scif2_data_a_pins[] = {
3363         /* RX, TX */
3364         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3365 };
3366 static const unsigned int scif2_data_a_mux[] = {
3367         RX2_A_MARK, TX2_A_MARK,
3368 };
3369 static const unsigned int scif2_clk_pins[] = {
3370         /* SCK */
3371         RCAR_GP_PIN(5, 9),
3372 };
3373 static const unsigned int scif2_clk_mux[] = {
3374         SCK2_MARK,
3375 };
3376 static const unsigned int scif2_data_b_pins[] = {
3377         /* RX, TX */
3378         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3379 };
3380 static const unsigned int scif2_data_b_mux[] = {
3381         RX2_B_MARK, TX2_B_MARK,
3382 };
3383 /* - SCIF3 ------------------------------------------------------------------ */
3384 static const unsigned int scif3_data_a_pins[] = {
3385         /* RX, TX */
3386         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3387 };
3388 static const unsigned int scif3_data_a_mux[] = {
3389         RX3_A_MARK, TX3_A_MARK,
3390 };
3391 static const unsigned int scif3_clk_pins[] = {
3392         /* SCK */
3393         RCAR_GP_PIN(1, 22),
3394 };
3395 static const unsigned int scif3_clk_mux[] = {
3396         SCK3_MARK,
3397 };
3398 static const unsigned int scif3_ctrl_pins[] = {
3399         /* RTS, CTS */
3400         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3401 };
3402 static const unsigned int scif3_ctrl_mux[] = {
3403         RTS3_N_MARK, CTS3_N_MARK,
3404 };
3405 static const unsigned int scif3_data_b_pins[] = {
3406         /* RX, TX */
3407         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3408 };
3409 static const unsigned int scif3_data_b_mux[] = {
3410         RX3_B_MARK, TX3_B_MARK,
3411 };
3412 /* - SCIF4 ------------------------------------------------------------------ */
3413 static const unsigned int scif4_data_a_pins[] = {
3414         /* RX, TX */
3415         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3416 };
3417 static const unsigned int scif4_data_a_mux[] = {
3418         RX4_A_MARK, TX4_A_MARK,
3419 };
3420 static const unsigned int scif4_clk_a_pins[] = {
3421         /* SCK */
3422         RCAR_GP_PIN(2, 10),
3423 };
3424 static const unsigned int scif4_clk_a_mux[] = {
3425         SCK4_A_MARK,
3426 };
3427 static const unsigned int scif4_ctrl_a_pins[] = {
3428         /* RTS, CTS */
3429         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3430 };
3431 static const unsigned int scif4_ctrl_a_mux[] = {
3432         RTS4_N_A_MARK, CTS4_N_A_MARK,
3433 };
3434 static const unsigned int scif4_data_b_pins[] = {
3435         /* RX, TX */
3436         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3437 };
3438 static const unsigned int scif4_data_b_mux[] = {
3439         RX4_B_MARK, TX4_B_MARK,
3440 };
3441 static const unsigned int scif4_clk_b_pins[] = {
3442         /* SCK */
3443         RCAR_GP_PIN(1, 5),
3444 };
3445 static const unsigned int scif4_clk_b_mux[] = {
3446         SCK4_B_MARK,
3447 };
3448 static const unsigned int scif4_ctrl_b_pins[] = {
3449         /* RTS, CTS */
3450         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3451 };
3452 static const unsigned int scif4_ctrl_b_mux[] = {
3453         RTS4_N_B_MARK, CTS4_N_B_MARK,
3454 };
3455 static const unsigned int scif4_data_c_pins[] = {
3456         /* RX, TX */
3457         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3458 };
3459 static const unsigned int scif4_data_c_mux[] = {
3460         RX4_C_MARK, TX4_C_MARK,
3461 };
3462 static const unsigned int scif4_clk_c_pins[] = {
3463         /* SCK */
3464         RCAR_GP_PIN(0, 8),
3465 };
3466 static const unsigned int scif4_clk_c_mux[] = {
3467         SCK4_C_MARK,
3468 };
3469 static const unsigned int scif4_ctrl_c_pins[] = {
3470         /* RTS, CTS */
3471         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3472 };
3473 static const unsigned int scif4_ctrl_c_mux[] = {
3474         RTS4_N_C_MARK, CTS4_N_C_MARK,
3475 };
3476 /* - SCIF5 ------------------------------------------------------------------ */
3477 static const unsigned int scif5_data_a_pins[] = {
3478         /* RX, TX */
3479         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3480 };
3481 static const unsigned int scif5_data_a_mux[] = {
3482         RX5_A_MARK, TX5_A_MARK,
3483 };
3484 static const unsigned int scif5_clk_a_pins[] = {
3485         /* SCK */
3486         RCAR_GP_PIN(6, 21),
3487 };
3488 static const unsigned int scif5_clk_a_mux[] = {
3489         SCK5_A_MARK,
3490 };
3491
3492 static const unsigned int scif5_data_b_pins[] = {
3493         /* RX, TX */
3494         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3495 };
3496 static const unsigned int scif5_data_b_mux[] = {
3497         RX5_B_MARK, TX5_B_MARK,
3498 };
3499 static const unsigned int scif5_clk_b_pins[] = {
3500         /* SCK */
3501         RCAR_GP_PIN(5, 0),
3502 };
3503 static const unsigned int scif5_clk_b_mux[] = {
3504         SCK5_B_MARK,
3505 };
3506
3507 /* - SCIF Clock ------------------------------------------------------------- */
3508 static const unsigned int scif_clk_a_pins[] = {
3509         /* SCIF_CLK */
3510         RCAR_GP_PIN(6, 23),
3511 };
3512 static const unsigned int scif_clk_a_mux[] = {
3513         SCIF_CLK_A_MARK,
3514 };
3515 static const unsigned int scif_clk_b_pins[] = {
3516         /* SCIF_CLK */
3517         RCAR_GP_PIN(5, 9),
3518 };
3519 static const unsigned int scif_clk_b_mux[] = {
3520         SCIF_CLK_B_MARK,
3521 };
3522
3523 /* - SDHI0 ------------------------------------------------------------------ */
3524 static const unsigned int sdhi0_data_pins[] = {
3525         /* D[0:3] */
3526         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3527         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3528 };
3529 static const unsigned int sdhi0_data_mux[] = {
3530         SD0_DAT0_MARK, SD0_DAT1_MARK,
3531         SD0_DAT2_MARK, SD0_DAT3_MARK,
3532 };
3533 static const unsigned int sdhi0_ctrl_pins[] = {
3534         /* CLK, CMD */
3535         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3536 };
3537 static const unsigned int sdhi0_ctrl_mux[] = {
3538         SD0_CLK_MARK, SD0_CMD_MARK,
3539 };
3540 static const unsigned int sdhi0_cd_pins[] = {
3541         /* CD */
3542         RCAR_GP_PIN(3, 12),
3543 };
3544 static const unsigned int sdhi0_cd_mux[] = {
3545         SD0_CD_MARK,
3546 };
3547 static const unsigned int sdhi0_wp_pins[] = {
3548         /* WP */
3549         RCAR_GP_PIN(3, 13),
3550 };
3551 static const unsigned int sdhi0_wp_mux[] = {
3552         SD0_WP_MARK,
3553 };
3554 /* - SDHI1 ------------------------------------------------------------------ */
3555 static const unsigned int sdhi1_data_pins[] = {
3556         /* D[0:3] */
3557         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3558         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3559 };
3560 static const unsigned int sdhi1_data_mux[] = {
3561         SD1_DAT0_MARK, SD1_DAT1_MARK,
3562         SD1_DAT2_MARK, SD1_DAT3_MARK,
3563 };
3564 static const unsigned int sdhi1_ctrl_pins[] = {
3565         /* CLK, CMD */
3566         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3567 };
3568 static const unsigned int sdhi1_ctrl_mux[] = {
3569         SD1_CLK_MARK, SD1_CMD_MARK,
3570 };
3571 static const unsigned int sdhi1_cd_pins[] = {
3572         /* CD */
3573         RCAR_GP_PIN(3, 14),
3574 };
3575 static const unsigned int sdhi1_cd_mux[] = {
3576         SD1_CD_MARK,
3577 };
3578 static const unsigned int sdhi1_wp_pins[] = {
3579         /* WP */
3580         RCAR_GP_PIN(3, 15),
3581 };
3582 static const unsigned int sdhi1_wp_mux[] = {
3583         SD1_WP_MARK,
3584 };
3585 /* - SDHI2 ------------------------------------------------------------------ */
3586 static const unsigned int sdhi2_data_pins[] = {
3587         /* D[0:7] */
3588         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3589         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3590         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3591         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3592 };
3593 static const unsigned int sdhi2_data_mux[] = {
3594         SD2_DAT0_MARK, SD2_DAT1_MARK,
3595         SD2_DAT2_MARK, SD2_DAT3_MARK,
3596         SD2_DAT4_MARK, SD2_DAT5_MARK,
3597         SD2_DAT6_MARK, SD2_DAT7_MARK,
3598 };
3599 static const unsigned int sdhi2_ctrl_pins[] = {
3600         /* CLK, CMD */
3601         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3602 };
3603 static const unsigned int sdhi2_ctrl_mux[] = {
3604         SD2_CLK_MARK, SD2_CMD_MARK,
3605 };
3606 static const unsigned int sdhi2_cd_a_pins[] = {
3607         /* CD */
3608         RCAR_GP_PIN(4, 13),
3609 };
3610 static const unsigned int sdhi2_cd_a_mux[] = {
3611         SD2_CD_A_MARK,
3612 };
3613 static const unsigned int sdhi2_cd_b_pins[] = {
3614         /* CD */
3615         RCAR_GP_PIN(5, 10),
3616 };
3617 static const unsigned int sdhi2_cd_b_mux[] = {
3618         SD2_CD_B_MARK,
3619 };
3620 static const unsigned int sdhi2_wp_a_pins[] = {
3621         /* WP */
3622         RCAR_GP_PIN(4, 14),
3623 };
3624 static const unsigned int sdhi2_wp_a_mux[] = {
3625         SD2_WP_A_MARK,
3626 };
3627 static const unsigned int sdhi2_wp_b_pins[] = {
3628         /* WP */
3629         RCAR_GP_PIN(5, 11),
3630 };
3631 static const unsigned int sdhi2_wp_b_mux[] = {
3632         SD2_WP_B_MARK,
3633 };
3634 static const unsigned int sdhi2_ds_pins[] = {
3635         /* DS */
3636         RCAR_GP_PIN(4, 6),
3637 };
3638 static const unsigned int sdhi2_ds_mux[] = {
3639         SD2_DS_MARK,
3640 };
3641 /* - SDHI3 ------------------------------------------------------------------ */
3642 static const unsigned int sdhi3_data_pins[] = {
3643         /* D[0:7] */
3644         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3645         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3646         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3647         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3648 };
3649 static const unsigned int sdhi3_data_mux[] = {
3650         SD3_DAT0_MARK, SD3_DAT1_MARK,
3651         SD3_DAT2_MARK, SD3_DAT3_MARK,
3652         SD3_DAT4_MARK, SD3_DAT5_MARK,
3653         SD3_DAT6_MARK, SD3_DAT7_MARK,
3654 };
3655 static const unsigned int sdhi3_ctrl_pins[] = {
3656         /* CLK, CMD */
3657         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3658 };
3659 static const unsigned int sdhi3_ctrl_mux[] = {
3660         SD3_CLK_MARK, SD3_CMD_MARK,
3661 };
3662 static const unsigned int sdhi3_cd_pins[] = {
3663         /* CD */
3664         RCAR_GP_PIN(4, 15),
3665 };
3666 static const unsigned int sdhi3_cd_mux[] = {
3667         SD3_CD_MARK,
3668 };
3669 static const unsigned int sdhi3_wp_pins[] = {
3670         /* WP */
3671         RCAR_GP_PIN(4, 16),
3672 };
3673 static const unsigned int sdhi3_wp_mux[] = {
3674         SD3_WP_MARK,
3675 };
3676 static const unsigned int sdhi3_ds_pins[] = {
3677         /* DS */
3678         RCAR_GP_PIN(4, 17),
3679 };
3680 static const unsigned int sdhi3_ds_mux[] = {
3681         SD3_DS_MARK,
3682 };
3683
3684 /* - SSI -------------------------------------------------------------------- */
3685 static const unsigned int ssi0_data_pins[] = {
3686         /* SDATA */
3687         RCAR_GP_PIN(6, 2),
3688 };
3689 static const unsigned int ssi0_data_mux[] = {
3690         SSI_SDATA0_MARK,
3691 };
3692 static const unsigned int ssi01239_ctrl_pins[] = {
3693         /* SCK, WS */
3694         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3695 };
3696 static const unsigned int ssi01239_ctrl_mux[] = {
3697         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3698 };
3699 static const unsigned int ssi1_data_a_pins[] = {
3700         /* SDATA */
3701         RCAR_GP_PIN(6, 3),
3702 };
3703 static const unsigned int ssi1_data_a_mux[] = {
3704         SSI_SDATA1_A_MARK,
3705 };
3706 static const unsigned int ssi1_data_b_pins[] = {
3707         /* SDATA */
3708         RCAR_GP_PIN(5, 12),
3709 };
3710 static const unsigned int ssi1_data_b_mux[] = {
3711         SSI_SDATA1_B_MARK,
3712 };
3713 static const unsigned int ssi1_ctrl_a_pins[] = {
3714         /* SCK, WS */
3715         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3716 };
3717 static const unsigned int ssi1_ctrl_a_mux[] = {
3718         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3719 };
3720 static const unsigned int ssi1_ctrl_b_pins[] = {
3721         /* SCK, WS */
3722         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3723 };
3724 static const unsigned int ssi1_ctrl_b_mux[] = {
3725         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3726 };
3727 static const unsigned int ssi2_data_a_pins[] = {
3728         /* SDATA */
3729         RCAR_GP_PIN(6, 4),
3730 };
3731 static const unsigned int ssi2_data_a_mux[] = {
3732         SSI_SDATA2_A_MARK,
3733 };
3734 static const unsigned int ssi2_data_b_pins[] = {
3735         /* SDATA */
3736         RCAR_GP_PIN(5, 13),
3737 };
3738 static const unsigned int ssi2_data_b_mux[] = {
3739         SSI_SDATA2_B_MARK,
3740 };
3741 static const unsigned int ssi2_ctrl_a_pins[] = {
3742         /* SCK, WS */
3743         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3744 };
3745 static const unsigned int ssi2_ctrl_a_mux[] = {
3746         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3747 };
3748 static const unsigned int ssi2_ctrl_b_pins[] = {
3749         /* SCK, WS */
3750         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3751 };
3752 static const unsigned int ssi2_ctrl_b_mux[] = {
3753         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3754 };
3755 static const unsigned int ssi3_data_pins[] = {
3756         /* SDATA */
3757         RCAR_GP_PIN(6, 7),
3758 };
3759 static const unsigned int ssi3_data_mux[] = {
3760         SSI_SDATA3_MARK,
3761 };
3762 static const unsigned int ssi349_ctrl_pins[] = {
3763         /* SCK, WS */
3764         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3765 };
3766 static const unsigned int ssi349_ctrl_mux[] = {
3767         SSI_SCK349_MARK, SSI_WS349_MARK,
3768 };
3769 static const unsigned int ssi4_data_pins[] = {
3770         /* SDATA */
3771         RCAR_GP_PIN(6, 10),
3772 };
3773 static const unsigned int ssi4_data_mux[] = {
3774         SSI_SDATA4_MARK,
3775 };
3776 static const unsigned int ssi4_ctrl_pins[] = {
3777         /* SCK, WS */
3778         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3779 };
3780 static const unsigned int ssi4_ctrl_mux[] = {
3781         SSI_SCK4_MARK, SSI_WS4_MARK,
3782 };
3783 static const unsigned int ssi5_data_pins[] = {
3784         /* SDATA */
3785         RCAR_GP_PIN(6, 13),
3786 };
3787 static const unsigned int ssi5_data_mux[] = {
3788         SSI_SDATA5_MARK,
3789 };
3790 static const unsigned int ssi5_ctrl_pins[] = {
3791         /* SCK, WS */
3792         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3793 };
3794 static const unsigned int ssi5_ctrl_mux[] = {
3795         SSI_SCK5_MARK, SSI_WS5_MARK,
3796 };
3797 static const unsigned int ssi6_data_pins[] = {
3798         /* SDATA */
3799         RCAR_GP_PIN(6, 16),
3800 };
3801 static const unsigned int ssi6_data_mux[] = {
3802         SSI_SDATA6_MARK,
3803 };
3804 static const unsigned int ssi6_ctrl_pins[] = {
3805         /* SCK, WS */
3806         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3807 };
3808 static const unsigned int ssi6_ctrl_mux[] = {
3809         SSI_SCK6_MARK, SSI_WS6_MARK,
3810 };
3811 static const unsigned int ssi7_data_pins[] = {
3812         /* SDATA */
3813         RCAR_GP_PIN(6, 19),
3814 };
3815 static const unsigned int ssi7_data_mux[] = {
3816         SSI_SDATA7_MARK,
3817 };
3818 static const unsigned int ssi78_ctrl_pins[] = {
3819         /* SCK, WS */
3820         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3821 };
3822 static const unsigned int ssi78_ctrl_mux[] = {
3823         SSI_SCK78_MARK, SSI_WS78_MARK,
3824 };
3825 static const unsigned int ssi8_data_pins[] = {
3826         /* SDATA */
3827         RCAR_GP_PIN(6, 20),
3828 };
3829 static const unsigned int ssi8_data_mux[] = {
3830         SSI_SDATA8_MARK,
3831 };
3832 static const unsigned int ssi9_data_a_pins[] = {
3833         /* SDATA */
3834         RCAR_GP_PIN(6, 21),
3835 };
3836 static const unsigned int ssi9_data_a_mux[] = {
3837         SSI_SDATA9_A_MARK,
3838 };
3839 static const unsigned int ssi9_data_b_pins[] = {
3840         /* SDATA */
3841         RCAR_GP_PIN(5, 14),
3842 };
3843 static const unsigned int ssi9_data_b_mux[] = {
3844         SSI_SDATA9_B_MARK,
3845 };
3846 static const unsigned int ssi9_ctrl_a_pins[] = {
3847         /* SCK, WS */
3848         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3849 };
3850 static const unsigned int ssi9_ctrl_a_mux[] = {
3851         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3852 };
3853 static const unsigned int ssi9_ctrl_b_pins[] = {
3854         /* SCK, WS */
3855         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3856 };
3857 static const unsigned int ssi9_ctrl_b_mux[] = {
3858         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3859 };
3860
3861 /* - TMU -------------------------------------------------------------------- */
3862 static const unsigned int tmu_tclk1_a_pins[] = {
3863         /* TCLK */
3864         RCAR_GP_PIN(6, 23),
3865 };
3866 static const unsigned int tmu_tclk1_a_mux[] = {
3867         TCLK1_A_MARK,
3868 };
3869 static const unsigned int tmu_tclk1_b_pins[] = {
3870         /* TCLK */
3871         RCAR_GP_PIN(5, 19),
3872 };
3873 static const unsigned int tmu_tclk1_b_mux[] = {
3874         TCLK1_B_MARK,
3875 };
3876 static const unsigned int tmu_tclk2_a_pins[] = {
3877         /* TCLK */
3878         RCAR_GP_PIN(6, 19),
3879 };
3880 static const unsigned int tmu_tclk2_a_mux[] = {
3881         TCLK2_A_MARK,
3882 };
3883 static const unsigned int tmu_tclk2_b_pins[] = {
3884         /* TCLK */
3885         RCAR_GP_PIN(6, 28),
3886 };
3887 static const unsigned int tmu_tclk2_b_mux[] = {
3888         TCLK2_B_MARK,
3889 };
3890
3891 /* - TPU ------------------------------------------------------------------- */
3892 static const unsigned int tpu_to0_pins[] = {
3893         /* TPU0TO0 */
3894         RCAR_GP_PIN(6, 28),
3895 };
3896 static const unsigned int tpu_to0_mux[] = {
3897         TPU0TO0_MARK,
3898 };
3899 static const unsigned int tpu_to1_pins[] = {
3900         /* TPU0TO1 */
3901         RCAR_GP_PIN(6, 29),
3902 };
3903 static const unsigned int tpu_to1_mux[] = {
3904         TPU0TO1_MARK,
3905 };
3906 static const unsigned int tpu_to2_pins[] = {
3907         /* TPU0TO2 */
3908         RCAR_GP_PIN(6, 30),
3909 };
3910 static const unsigned int tpu_to2_mux[] = {
3911         TPU0TO2_MARK,
3912 };
3913 static const unsigned int tpu_to3_pins[] = {
3914         /* TPU0TO3 */
3915         RCAR_GP_PIN(6, 31),
3916 };
3917 static const unsigned int tpu_to3_mux[] = {
3918         TPU0TO3_MARK,
3919 };
3920
3921 /* - USB0 ------------------------------------------------------------------- */
3922 static const unsigned int usb0_pins[] = {
3923         /* PWEN, OVC */
3924         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3925 };
3926 static const unsigned int usb0_mux[] = {
3927         USB0_PWEN_MARK, USB0_OVC_MARK,
3928 };
3929 /* - USB1 ------------------------------------------------------------------- */
3930 static const unsigned int usb1_pins[] = {
3931         /* PWEN, OVC */
3932         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3933 };
3934 static const unsigned int usb1_mux[] = {
3935         USB1_PWEN_MARK, USB1_OVC_MARK,
3936 };
3937
3938 /* - USB30 ------------------------------------------------------------------ */
3939 static const unsigned int usb30_pins[] = {
3940         /* PWEN, OVC */
3941         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3942 };
3943 static const unsigned int usb30_mux[] = {
3944         USB30_PWEN_MARK, USB30_OVC_MARK,
3945 };
3946
3947 /* - VIN4 ------------------------------------------------------------------- */
3948 static const unsigned int vin4_data18_a_pins[] = {
3949         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3950         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3951         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3952         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3953         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3954         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3955         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3956         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3957         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3958 };
3959 static const unsigned int vin4_data18_a_mux[] = {
3960         VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3961         VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3962         VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3963         VI4_DATA10_MARK, VI4_DATA11_MARK,
3964         VI4_DATA12_MARK, VI4_DATA13_MARK,
3965         VI4_DATA14_MARK, VI4_DATA15_MARK,
3966         VI4_DATA18_MARK, VI4_DATA19_MARK,
3967         VI4_DATA20_MARK, VI4_DATA21_MARK,
3968         VI4_DATA22_MARK, VI4_DATA23_MARK,
3969 };
3970 static const unsigned int vin4_data18_b_pins[] = {
3971         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3972         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3973         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3974         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3975         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3976         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3977         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3978         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3979         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3980 };
3981 static const unsigned int vin4_data18_b_mux[] = {
3982         VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3983         VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3984         VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3985         VI4_DATA10_MARK, VI4_DATA11_MARK,
3986         VI4_DATA12_MARK, VI4_DATA13_MARK,
3987         VI4_DATA14_MARK, VI4_DATA15_MARK,
3988         VI4_DATA18_MARK, VI4_DATA19_MARK,
3989         VI4_DATA20_MARK, VI4_DATA21_MARK,
3990         VI4_DATA22_MARK, VI4_DATA23_MARK,
3991 };
3992 static const unsigned int vin4_data_a_pins[] = {
3993         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3994         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3995         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3996         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3997         RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3998         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3999         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4000         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4001         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4002         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4003         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4004         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4005 };
4006 static const unsigned int vin4_data_a_mux[] = {
4007         VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4008         VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4009         VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4010         VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4011         VI4_DATA8_MARK,  VI4_DATA9_MARK,
4012         VI4_DATA10_MARK, VI4_DATA11_MARK,
4013         VI4_DATA12_MARK, VI4_DATA13_MARK,
4014         VI4_DATA14_MARK, VI4_DATA15_MARK,
4015         VI4_DATA16_MARK, VI4_DATA17_MARK,
4016         VI4_DATA18_MARK, VI4_DATA19_MARK,
4017         VI4_DATA20_MARK, VI4_DATA21_MARK,
4018         VI4_DATA22_MARK, VI4_DATA23_MARK,
4019 };
4020 static const unsigned int vin4_data_b_pins[] = {
4021         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4022         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4023         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4024         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4025         RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4026         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4027         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4028         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4029         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4030         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4031         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4032         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4033 };
4034 static const unsigned int vin4_data_b_mux[] = {
4035         VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4036         VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4037         VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4038         VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4039         VI4_DATA8_MARK,  VI4_DATA9_MARK,
4040         VI4_DATA10_MARK, VI4_DATA11_MARK,
4041         VI4_DATA12_MARK, VI4_DATA13_MARK,
4042         VI4_DATA14_MARK, VI4_DATA15_MARK,
4043         VI4_DATA16_MARK, VI4_DATA17_MARK,
4044         VI4_DATA18_MARK, VI4_DATA19_MARK,
4045         VI4_DATA20_MARK, VI4_DATA21_MARK,
4046         VI4_DATA22_MARK, VI4_DATA23_MARK,
4047 };
4048 static const unsigned int vin4_sync_pins[] = {
4049         /* HSYNC#, VSYNC# */
4050         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4051 };
4052 static const unsigned int vin4_sync_mux[] = {
4053         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4054 };
4055 static const unsigned int vin4_field_pins[] = {
4056         /* FIELD */
4057         RCAR_GP_PIN(1, 16),
4058 };
4059 static const unsigned int vin4_field_mux[] = {
4060         VI4_FIELD_MARK,
4061 };
4062 static const unsigned int vin4_clkenb_pins[] = {
4063         /* CLKENB */
4064         RCAR_GP_PIN(1, 19),
4065 };
4066 static const unsigned int vin4_clkenb_mux[] = {
4067         VI4_CLKENB_MARK,
4068 };
4069 static const unsigned int vin4_clk_pins[] = {
4070         /* CLK */
4071         RCAR_GP_PIN(1, 27),
4072 };
4073 static const unsigned int vin4_clk_mux[] = {
4074         VI4_CLK_MARK,
4075 };
4076
4077 /* - VIN5 ------------------------------------------------------------------- */
4078 static const unsigned int vin5_data_pins[] = {
4079         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4080         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4081         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4082         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4083         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4084         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4085         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4086         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4087 };
4088 static const unsigned int vin5_data_mux[] = {
4089         VI5_DATA0_MARK, VI5_DATA1_MARK,
4090         VI5_DATA2_MARK, VI5_DATA3_MARK,
4091         VI5_DATA4_MARK, VI5_DATA5_MARK,
4092         VI5_DATA6_MARK, VI5_DATA7_MARK,
4093         VI5_DATA8_MARK,  VI5_DATA9_MARK,
4094         VI5_DATA10_MARK, VI5_DATA11_MARK,
4095         VI5_DATA12_MARK, VI5_DATA13_MARK,
4096         VI5_DATA14_MARK, VI5_DATA15_MARK,
4097 };
4098 static const unsigned int vin5_sync_pins[] = {
4099         /* HSYNC#, VSYNC# */
4100         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4101 };
4102 static const unsigned int vin5_sync_mux[] = {
4103         VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4104 };
4105 static const unsigned int vin5_field_pins[] = {
4106         RCAR_GP_PIN(1, 11),
4107 };
4108 static const unsigned int vin5_field_mux[] = {
4109         /* FIELD */
4110         VI5_FIELD_MARK,
4111 };
4112 static const unsigned int vin5_clkenb_pins[] = {
4113         RCAR_GP_PIN(1, 20),
4114 };
4115 static const unsigned int vin5_clkenb_mux[] = {
4116         /* CLKENB */
4117         VI5_CLKENB_MARK,
4118 };
4119 static const unsigned int vin5_clk_pins[] = {
4120         RCAR_GP_PIN(1, 21),
4121 };
4122 static const unsigned int vin5_clk_mux[] = {
4123         /* CLK */
4124         VI5_CLK_MARK,
4125 };
4126
4127 static const struct {
4128         struct sh_pfc_pin_group common[324];
4129 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4130         struct sh_pfc_pin_group automotive[31];
4131 #endif
4132 } pinmux_groups = {
4133         .common = {
4134                 SH_PFC_PIN_GROUP(audio_clk_a_a),
4135                 SH_PFC_PIN_GROUP(audio_clk_a_b),
4136                 SH_PFC_PIN_GROUP(audio_clk_a_c),
4137                 SH_PFC_PIN_GROUP(audio_clk_b_a),
4138                 SH_PFC_PIN_GROUP(audio_clk_b_b),
4139                 SH_PFC_PIN_GROUP(audio_clk_c_a),
4140                 SH_PFC_PIN_GROUP(audio_clk_c_b),
4141                 SH_PFC_PIN_GROUP(audio_clkout_a),
4142                 SH_PFC_PIN_GROUP(audio_clkout_b),
4143                 SH_PFC_PIN_GROUP(audio_clkout_c),
4144                 SH_PFC_PIN_GROUP(audio_clkout_d),
4145                 SH_PFC_PIN_GROUP(audio_clkout1_a),
4146                 SH_PFC_PIN_GROUP(audio_clkout1_b),
4147                 SH_PFC_PIN_GROUP(audio_clkout2_a),
4148                 SH_PFC_PIN_GROUP(audio_clkout2_b),
4149                 SH_PFC_PIN_GROUP(audio_clkout3_a),
4150                 SH_PFC_PIN_GROUP(audio_clkout3_b),
4151                 SH_PFC_PIN_GROUP(avb_link),
4152                 SH_PFC_PIN_GROUP(avb_magic),
4153                 SH_PFC_PIN_GROUP(avb_phy_int),
4154                 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),      /* Deprecated */
4155                 SH_PFC_PIN_GROUP(avb_mdio),
4156                 SH_PFC_PIN_GROUP(avb_mii),
4157                 SH_PFC_PIN_GROUP(avb_avtp_pps),
4158                 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4159                 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4160                 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4161                 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4162                 SH_PFC_PIN_GROUP(can0_data_a),
4163                 SH_PFC_PIN_GROUP(can0_data_b),
4164                 SH_PFC_PIN_GROUP(can1_data),
4165                 SH_PFC_PIN_GROUP(can_clk),
4166                 SH_PFC_PIN_GROUP(canfd0_data_a),
4167                 SH_PFC_PIN_GROUP(canfd0_data_b),
4168                 SH_PFC_PIN_GROUP(canfd1_data),
4169                 SH_PFC_PIN_GROUP(du_rgb666),
4170                 SH_PFC_PIN_GROUP(du_rgb888),
4171                 SH_PFC_PIN_GROUP(du_clk_out_0),
4172                 SH_PFC_PIN_GROUP(du_clk_out_1),
4173                 SH_PFC_PIN_GROUP(du_sync),
4174                 SH_PFC_PIN_GROUP(du_oddf),
4175                 SH_PFC_PIN_GROUP(du_cde),
4176                 SH_PFC_PIN_GROUP(du_disp),
4177                 SH_PFC_PIN_GROUP(hscif0_data),
4178                 SH_PFC_PIN_GROUP(hscif0_clk),
4179                 SH_PFC_PIN_GROUP(hscif0_ctrl),
4180                 SH_PFC_PIN_GROUP(hscif1_data_a),
4181                 SH_PFC_PIN_GROUP(hscif1_clk_a),
4182                 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4183                 SH_PFC_PIN_GROUP(hscif1_data_b),
4184                 SH_PFC_PIN_GROUP(hscif1_clk_b),
4185                 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4186                 SH_PFC_PIN_GROUP(hscif2_data_a),
4187                 SH_PFC_PIN_GROUP(hscif2_clk_a),
4188                 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4189                 SH_PFC_PIN_GROUP(hscif2_data_b),
4190                 SH_PFC_PIN_GROUP(hscif2_clk_b),
4191                 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4192                 SH_PFC_PIN_GROUP(hscif2_data_c),
4193                 SH_PFC_PIN_GROUP(hscif2_clk_c),
4194                 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4195                 SH_PFC_PIN_GROUP(hscif3_data_a),
4196                 SH_PFC_PIN_GROUP(hscif3_clk),
4197                 SH_PFC_PIN_GROUP(hscif3_ctrl),
4198                 SH_PFC_PIN_GROUP(hscif3_data_b),
4199                 SH_PFC_PIN_GROUP(hscif3_data_c),
4200                 SH_PFC_PIN_GROUP(hscif3_data_d),
4201                 SH_PFC_PIN_GROUP(hscif4_data_a),
4202                 SH_PFC_PIN_GROUP(hscif4_clk),
4203                 SH_PFC_PIN_GROUP(hscif4_ctrl),
4204                 SH_PFC_PIN_GROUP(hscif4_data_b),
4205                 SH_PFC_PIN_GROUP(i2c0),
4206                 SH_PFC_PIN_GROUP(i2c1_a),
4207                 SH_PFC_PIN_GROUP(i2c1_b),
4208                 SH_PFC_PIN_GROUP(i2c2_a),
4209                 SH_PFC_PIN_GROUP(i2c2_b),
4210                 SH_PFC_PIN_GROUP(i2c3),
4211                 SH_PFC_PIN_GROUP(i2c5),
4212                 SH_PFC_PIN_GROUP(i2c6_a),
4213                 SH_PFC_PIN_GROUP(i2c6_b),
4214                 SH_PFC_PIN_GROUP(i2c6_c),
4215                 SH_PFC_PIN_GROUP(intc_ex_irq0),
4216                 SH_PFC_PIN_GROUP(intc_ex_irq1),
4217                 SH_PFC_PIN_GROUP(intc_ex_irq2),
4218                 SH_PFC_PIN_GROUP(intc_ex_irq3),
4219                 SH_PFC_PIN_GROUP(intc_ex_irq4),
4220                 SH_PFC_PIN_GROUP(intc_ex_irq5),
4221                 SH_PFC_PIN_GROUP(msiof0_clk),
4222                 SH_PFC_PIN_GROUP(msiof0_sync),
4223                 SH_PFC_PIN_GROUP(msiof0_ss1),
4224                 SH_PFC_PIN_GROUP(msiof0_ss2),
4225                 SH_PFC_PIN_GROUP(msiof0_txd),
4226                 SH_PFC_PIN_GROUP(msiof0_rxd),
4227                 SH_PFC_PIN_GROUP(msiof1_clk_a),
4228                 SH_PFC_PIN_GROUP(msiof1_sync_a),
4229                 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4230                 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4231                 SH_PFC_PIN_GROUP(msiof1_txd_a),
4232                 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4233                 SH_PFC_PIN_GROUP(msiof1_clk_b),
4234                 SH_PFC_PIN_GROUP(msiof1_sync_b),
4235                 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4236                 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4237                 SH_PFC_PIN_GROUP(msiof1_txd_b),
4238                 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4239                 SH_PFC_PIN_GROUP(msiof1_clk_c),
4240                 SH_PFC_PIN_GROUP(msiof1_sync_c),
4241                 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4242                 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4243                 SH_PFC_PIN_GROUP(msiof1_txd_c),
4244                 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4245                 SH_PFC_PIN_GROUP(msiof1_clk_d),
4246                 SH_PFC_PIN_GROUP(msiof1_sync_d),
4247                 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4248                 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4249                 SH_PFC_PIN_GROUP(msiof1_txd_d),
4250                 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4251                 SH_PFC_PIN_GROUP(msiof1_clk_e),
4252                 SH_PFC_PIN_GROUP(msiof1_sync_e),
4253                 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4254                 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4255                 SH_PFC_PIN_GROUP(msiof1_txd_e),
4256                 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4257                 SH_PFC_PIN_GROUP(msiof1_clk_f),
4258                 SH_PFC_PIN_GROUP(msiof1_sync_f),
4259                 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4260                 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4261                 SH_PFC_PIN_GROUP(msiof1_txd_f),
4262                 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4263                 SH_PFC_PIN_GROUP(msiof1_clk_g),
4264                 SH_PFC_PIN_GROUP(msiof1_sync_g),
4265                 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4266                 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4267                 SH_PFC_PIN_GROUP(msiof1_txd_g),
4268                 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4269                 SH_PFC_PIN_GROUP(msiof2_clk_a),
4270                 SH_PFC_PIN_GROUP(msiof2_sync_a),
4271                 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4272                 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4273                 SH_PFC_PIN_GROUP(msiof2_txd_a),
4274                 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4275                 SH_PFC_PIN_GROUP(msiof2_clk_b),
4276                 SH_PFC_PIN_GROUP(msiof2_sync_b),
4277                 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4278                 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4279                 SH_PFC_PIN_GROUP(msiof2_txd_b),
4280                 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4281                 SH_PFC_PIN_GROUP(msiof2_clk_c),
4282                 SH_PFC_PIN_GROUP(msiof2_sync_c),
4283                 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4284                 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4285                 SH_PFC_PIN_GROUP(msiof2_txd_c),
4286                 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4287                 SH_PFC_PIN_GROUP(msiof2_clk_d),
4288                 SH_PFC_PIN_GROUP(msiof2_sync_d),
4289                 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4290                 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4291                 SH_PFC_PIN_GROUP(msiof2_txd_d),
4292                 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4293                 SH_PFC_PIN_GROUP(msiof3_clk_a),
4294                 SH_PFC_PIN_GROUP(msiof3_sync_a),
4295                 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4296                 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4297                 SH_PFC_PIN_GROUP(msiof3_txd_a),
4298                 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4299                 SH_PFC_PIN_GROUP(msiof3_clk_b),
4300                 SH_PFC_PIN_GROUP(msiof3_sync_b),
4301                 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4302                 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4303                 SH_PFC_PIN_GROUP(msiof3_txd_b),
4304                 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4305                 SH_PFC_PIN_GROUP(msiof3_clk_c),
4306                 SH_PFC_PIN_GROUP(msiof3_sync_c),
4307                 SH_PFC_PIN_GROUP(msiof3_txd_c),
4308                 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4309                 SH_PFC_PIN_GROUP(msiof3_clk_d),
4310                 SH_PFC_PIN_GROUP(msiof3_sync_d),
4311                 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4312                 SH_PFC_PIN_GROUP(msiof3_txd_d),
4313                 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4314                 SH_PFC_PIN_GROUP(msiof3_clk_e),
4315                 SH_PFC_PIN_GROUP(msiof3_sync_e),
4316                 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4317                 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4318                 SH_PFC_PIN_GROUP(msiof3_txd_e),
4319                 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4320                 SH_PFC_PIN_GROUP(pwm0),
4321                 SH_PFC_PIN_GROUP(pwm1_a),
4322                 SH_PFC_PIN_GROUP(pwm1_b),
4323                 SH_PFC_PIN_GROUP(pwm2_a),
4324                 SH_PFC_PIN_GROUP(pwm2_b),
4325                 SH_PFC_PIN_GROUP(pwm3_a),
4326                 SH_PFC_PIN_GROUP(pwm3_b),
4327                 SH_PFC_PIN_GROUP(pwm4_a),
4328                 SH_PFC_PIN_GROUP(pwm4_b),
4329                 SH_PFC_PIN_GROUP(pwm5_a),
4330                 SH_PFC_PIN_GROUP(pwm5_b),
4331                 SH_PFC_PIN_GROUP(pwm6_a),
4332                 SH_PFC_PIN_GROUP(pwm6_b),
4333                 SH_PFC_PIN_GROUP(qspi0_ctrl),
4334                 BUS_DATA_PIN_GROUP(qspi0_data, 2),
4335                 BUS_DATA_PIN_GROUP(qspi0_data, 4),
4336                 SH_PFC_PIN_GROUP(qspi1_ctrl),
4337                 BUS_DATA_PIN_GROUP(qspi1_data, 2),
4338                 BUS_DATA_PIN_GROUP(qspi1_data, 4),
4339                 SH_PFC_PIN_GROUP(scif0_data),
4340                 SH_PFC_PIN_GROUP(scif0_clk),
4341                 SH_PFC_PIN_GROUP(scif0_ctrl),
4342                 SH_PFC_PIN_GROUP(scif1_data_a),
4343                 SH_PFC_PIN_GROUP(scif1_clk),
4344                 SH_PFC_PIN_GROUP(scif1_ctrl),
4345                 SH_PFC_PIN_GROUP(scif1_data_b),
4346                 SH_PFC_PIN_GROUP(scif2_data_a),
4347                 SH_PFC_PIN_GROUP(scif2_clk),
4348                 SH_PFC_PIN_GROUP(scif2_data_b),
4349                 SH_PFC_PIN_GROUP(scif3_data_a),
4350                 SH_PFC_PIN_GROUP(scif3_clk),
4351                 SH_PFC_PIN_GROUP(scif3_ctrl),
4352                 SH_PFC_PIN_GROUP(scif3_data_b),
4353                 SH_PFC_PIN_GROUP(scif4_data_a),
4354                 SH_PFC_PIN_GROUP(scif4_clk_a),
4355                 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4356                 SH_PFC_PIN_GROUP(scif4_data_b),
4357                 SH_PFC_PIN_GROUP(scif4_clk_b),
4358                 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4359                 SH_PFC_PIN_GROUP(scif4_data_c),
4360                 SH_PFC_PIN_GROUP(scif4_clk_c),
4361                 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4362                 SH_PFC_PIN_GROUP(scif5_data_a),
4363                 SH_PFC_PIN_GROUP(scif5_clk_a),
4364                 SH_PFC_PIN_GROUP(scif5_data_b),
4365                 SH_PFC_PIN_GROUP(scif5_clk_b),
4366                 SH_PFC_PIN_GROUP(scif_clk_a),
4367                 SH_PFC_PIN_GROUP(scif_clk_b),
4368                 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4369                 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
4370                 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4371                 SH_PFC_PIN_GROUP(sdhi0_cd),
4372                 SH_PFC_PIN_GROUP(sdhi0_wp),
4373                 BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4374                 BUS_DATA_PIN_GROUP(sdhi1_data, 4),
4375                 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4376                 SH_PFC_PIN_GROUP(sdhi1_cd),
4377                 SH_PFC_PIN_GROUP(sdhi1_wp),
4378                 BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4379                 BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4380                 BUS_DATA_PIN_GROUP(sdhi2_data, 8),
4381                 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4382                 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4383                 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4384                 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4385                 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4386                 SH_PFC_PIN_GROUP(sdhi2_ds),
4387                 BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4388                 BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4389                 BUS_DATA_PIN_GROUP(sdhi3_data, 8),
4390                 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4391                 SH_PFC_PIN_GROUP(sdhi3_cd),
4392                 SH_PFC_PIN_GROUP(sdhi3_wp),
4393                 SH_PFC_PIN_GROUP(sdhi3_ds),
4394                 SH_PFC_PIN_GROUP(ssi0_data),
4395                 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4396                 SH_PFC_PIN_GROUP(ssi1_data_a),
4397                 SH_PFC_PIN_GROUP(ssi1_data_b),
4398                 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4399                 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4400                 SH_PFC_PIN_GROUP(ssi2_data_a),
4401                 SH_PFC_PIN_GROUP(ssi2_data_b),
4402                 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4403                 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4404                 SH_PFC_PIN_GROUP(ssi3_data),
4405                 SH_PFC_PIN_GROUP(ssi349_ctrl),
4406                 SH_PFC_PIN_GROUP(ssi4_data),
4407                 SH_PFC_PIN_GROUP(ssi4_ctrl),
4408                 SH_PFC_PIN_GROUP(ssi5_data),
4409                 SH_PFC_PIN_GROUP(ssi5_ctrl),
4410                 SH_PFC_PIN_GROUP(ssi6_data),
4411                 SH_PFC_PIN_GROUP(ssi6_ctrl),
4412                 SH_PFC_PIN_GROUP(ssi7_data),
4413                 SH_PFC_PIN_GROUP(ssi78_ctrl),
4414                 SH_PFC_PIN_GROUP(ssi8_data),
4415                 SH_PFC_PIN_GROUP(ssi9_data_a),
4416                 SH_PFC_PIN_GROUP(ssi9_data_b),
4417                 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4418                 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4419                 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4420                 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4421                 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4422                 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4423                 SH_PFC_PIN_GROUP(tpu_to0),
4424                 SH_PFC_PIN_GROUP(tpu_to1),
4425                 SH_PFC_PIN_GROUP(tpu_to2),
4426                 SH_PFC_PIN_GROUP(tpu_to3),
4427                 SH_PFC_PIN_GROUP(usb0),
4428                 SH_PFC_PIN_GROUP(usb1),
4429                 SH_PFC_PIN_GROUP(usb30),
4430                 BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4431                 BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4432                 BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4433                 BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
4434                 SH_PFC_PIN_GROUP(vin4_data18_a),
4435                 BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4436                 BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4437                 BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4438                 BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4439                 BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4440                 BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
4441                 SH_PFC_PIN_GROUP(vin4_data18_b),
4442                 BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4443                 BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4444                 SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
4445                 SH_PFC_PIN_GROUP(vin4_sync),
4446                 SH_PFC_PIN_GROUP(vin4_field),
4447                 SH_PFC_PIN_GROUP(vin4_clkenb),
4448                 SH_PFC_PIN_GROUP(vin4_clk),
4449                 BUS_DATA_PIN_GROUP(vin5_data, 8),
4450                 BUS_DATA_PIN_GROUP(vin5_data, 10),
4451                 BUS_DATA_PIN_GROUP(vin5_data, 12),
4452                 BUS_DATA_PIN_GROUP(vin5_data, 16),
4453                 SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
4454                 SH_PFC_PIN_GROUP(vin5_sync),
4455                 SH_PFC_PIN_GROUP(vin5_field),
4456                 SH_PFC_PIN_GROUP(vin5_clkenb),
4457                 SH_PFC_PIN_GROUP(vin5_clk),
4458         },
4459 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4460         .automotive = {
4461                 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4462                 SH_PFC_PIN_GROUP(drif0_data0_a),
4463                 SH_PFC_PIN_GROUP(drif0_data1_a),
4464                 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4465                 SH_PFC_PIN_GROUP(drif0_data0_b),
4466                 SH_PFC_PIN_GROUP(drif0_data1_b),
4467                 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4468                 SH_PFC_PIN_GROUP(drif0_data0_c),
4469                 SH_PFC_PIN_GROUP(drif0_data1_c),
4470                 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4471                 SH_PFC_PIN_GROUP(drif1_data0_a),
4472                 SH_PFC_PIN_GROUP(drif1_data1_a),
4473                 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4474                 SH_PFC_PIN_GROUP(drif1_data0_b),
4475                 SH_PFC_PIN_GROUP(drif1_data1_b),
4476                 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4477                 SH_PFC_PIN_GROUP(drif1_data0_c),
4478                 SH_PFC_PIN_GROUP(drif1_data1_c),
4479                 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4480                 SH_PFC_PIN_GROUP(drif2_data0_a),
4481                 SH_PFC_PIN_GROUP(drif2_data1_a),
4482                 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4483                 SH_PFC_PIN_GROUP(drif2_data0_b),
4484                 SH_PFC_PIN_GROUP(drif2_data1_b),
4485                 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4486                 SH_PFC_PIN_GROUP(drif3_data0_a),
4487                 SH_PFC_PIN_GROUP(drif3_data1_a),
4488                 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4489                 SH_PFC_PIN_GROUP(drif3_data0_b),
4490                 SH_PFC_PIN_GROUP(drif3_data1_b),
4491                 SH_PFC_PIN_GROUP(mlb_3pin),
4492         }
4493 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4494 };
4495
4496 static const char * const audio_clk_groups[] = {
4497         "audio_clk_a_a",
4498         "audio_clk_a_b",
4499         "audio_clk_a_c",
4500         "audio_clk_b_a",
4501         "audio_clk_b_b",
4502         "audio_clk_c_a",
4503         "audio_clk_c_b",
4504         "audio_clkout_a",
4505         "audio_clkout_b",
4506         "audio_clkout_c",
4507         "audio_clkout_d",
4508         "audio_clkout1_a",
4509         "audio_clkout1_b",
4510         "audio_clkout2_a",
4511         "audio_clkout2_b",
4512         "audio_clkout3_a",
4513         "audio_clkout3_b",
4514 };
4515
4516 static const char * const avb_groups[] = {
4517         "avb_link",
4518         "avb_magic",
4519         "avb_phy_int",
4520         "avb_mdc",      /* Deprecated, please use "avb_mdio" instead */
4521         "avb_mdio",
4522         "avb_mii",
4523         "avb_avtp_pps",
4524         "avb_avtp_match_a",
4525         "avb_avtp_capture_a",
4526         "avb_avtp_match_b",
4527         "avb_avtp_capture_b",
4528 };
4529
4530 static const char * const can0_groups[] = {
4531         "can0_data_a",
4532         "can0_data_b",
4533 };
4534
4535 static const char * const can1_groups[] = {
4536         "can1_data",
4537 };
4538
4539 static const char * const can_clk_groups[] = {
4540         "can_clk",
4541 };
4542
4543 static const char * const canfd0_groups[] = {
4544         "canfd0_data_a",
4545         "canfd0_data_b",
4546 };
4547
4548 static const char * const canfd1_groups[] = {
4549         "canfd1_data",
4550 };
4551
4552 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4553 static const char * const drif0_groups[] = {
4554         "drif0_ctrl_a",
4555         "drif0_data0_a",
4556         "drif0_data1_a",
4557         "drif0_ctrl_b",
4558         "drif0_data0_b",
4559         "drif0_data1_b",
4560         "drif0_ctrl_c",
4561         "drif0_data0_c",
4562         "drif0_data1_c",
4563 };
4564
4565 static const char * const drif1_groups[] = {
4566         "drif1_ctrl_a",
4567         "drif1_data0_a",
4568         "drif1_data1_a",
4569         "drif1_ctrl_b",
4570         "drif1_data0_b",
4571         "drif1_data1_b",
4572         "drif1_ctrl_c",
4573         "drif1_data0_c",
4574         "drif1_data1_c",
4575 };
4576
4577 static const char * const drif2_groups[] = {
4578         "drif2_ctrl_a",
4579         "drif2_data0_a",
4580         "drif2_data1_a",
4581         "drif2_ctrl_b",
4582         "drif2_data0_b",
4583         "drif2_data1_b",
4584 };
4585
4586 static const char * const drif3_groups[] = {
4587         "drif3_ctrl_a",
4588         "drif3_data0_a",
4589         "drif3_data1_a",
4590         "drif3_ctrl_b",
4591         "drif3_data0_b",
4592         "drif3_data1_b",
4593 };
4594 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4595
4596 static const char * const du_groups[] = {
4597         "du_rgb666",
4598         "du_rgb888",
4599         "du_clk_out_0",
4600         "du_clk_out_1",
4601         "du_sync",
4602         "du_oddf",
4603         "du_cde",
4604         "du_disp",
4605 };
4606
4607 static const char * const hscif0_groups[] = {
4608         "hscif0_data",
4609         "hscif0_clk",
4610         "hscif0_ctrl",
4611 };
4612
4613 static const char * const hscif1_groups[] = {
4614         "hscif1_data_a",
4615         "hscif1_clk_a",
4616         "hscif1_ctrl_a",
4617         "hscif1_data_b",
4618         "hscif1_clk_b",
4619         "hscif1_ctrl_b",
4620 };
4621
4622 static const char * const hscif2_groups[] = {
4623         "hscif2_data_a",
4624         "hscif2_clk_a",
4625         "hscif2_ctrl_a",
4626         "hscif2_data_b",
4627         "hscif2_clk_b",
4628         "hscif2_ctrl_b",
4629         "hscif2_data_c",
4630         "hscif2_clk_c",
4631         "hscif2_ctrl_c",
4632 };
4633
4634 static const char * const hscif3_groups[] = {
4635         "hscif3_data_a",
4636         "hscif3_clk",
4637         "hscif3_ctrl",
4638         "hscif3_data_b",
4639         "hscif3_data_c",
4640         "hscif3_data_d",
4641 };
4642
4643 static const char * const hscif4_groups[] = {
4644         "hscif4_data_a",
4645         "hscif4_clk",
4646         "hscif4_ctrl",
4647         "hscif4_data_b",
4648 };
4649
4650 static const char * const i2c0_groups[] = {
4651         "i2c0",
4652 };
4653
4654 static const char * const i2c1_groups[] = {
4655         "i2c1_a",
4656         "i2c1_b",
4657 };
4658
4659 static const char * const i2c2_groups[] = {
4660         "i2c2_a",
4661         "i2c2_b",
4662 };
4663
4664 static const char * const i2c3_groups[] = {
4665         "i2c3",
4666 };
4667
4668 static const char * const i2c5_groups[] = {
4669         "i2c5",
4670 };
4671
4672 static const char * const i2c6_groups[] = {
4673         "i2c6_a",
4674         "i2c6_b",
4675         "i2c6_c",
4676 };
4677
4678 static const char * const intc_ex_groups[] = {
4679         "intc_ex_irq0",
4680         "intc_ex_irq1",
4681         "intc_ex_irq2",
4682         "intc_ex_irq3",
4683         "intc_ex_irq4",
4684         "intc_ex_irq5",
4685 };
4686
4687 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4688 static const char * const mlb_3pin_groups[] = {
4689         "mlb_3pin",
4690 };
4691 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4692
4693 static const char * const msiof0_groups[] = {
4694         "msiof0_clk",
4695         "msiof0_sync",
4696         "msiof0_ss1",
4697         "msiof0_ss2",
4698         "msiof0_txd",
4699         "msiof0_rxd",
4700 };
4701
4702 static const char * const msiof1_groups[] = {
4703         "msiof1_clk_a",
4704         "msiof1_sync_a",
4705         "msiof1_ss1_a",
4706         "msiof1_ss2_a",
4707         "msiof1_txd_a",
4708         "msiof1_rxd_a",
4709         "msiof1_clk_b",
4710         "msiof1_sync_b",
4711         "msiof1_ss1_b",
4712         "msiof1_ss2_b",
4713         "msiof1_txd_b",
4714         "msiof1_rxd_b",
4715         "msiof1_clk_c",
4716         "msiof1_sync_c",
4717         "msiof1_ss1_c",
4718         "msiof1_ss2_c",
4719         "msiof1_txd_c",
4720         "msiof1_rxd_c",
4721         "msiof1_clk_d",
4722         "msiof1_sync_d",
4723         "msiof1_ss1_d",
4724         "msiof1_ss2_d",
4725         "msiof1_txd_d",
4726         "msiof1_rxd_d",
4727         "msiof1_clk_e",
4728         "msiof1_sync_e",
4729         "msiof1_ss1_e",
4730         "msiof1_ss2_e",
4731         "msiof1_txd_e",
4732         "msiof1_rxd_e",
4733         "msiof1_clk_f",
4734         "msiof1_sync_f",
4735         "msiof1_ss1_f",
4736         "msiof1_ss2_f",
4737         "msiof1_txd_f",
4738         "msiof1_rxd_f",
4739         "msiof1_clk_g",
4740         "msiof1_sync_g",
4741         "msiof1_ss1_g",
4742         "msiof1_ss2_g",
4743         "msiof1_txd_g",
4744         "msiof1_rxd_g",
4745 };
4746
4747 static const char * const msiof2_groups[] = {
4748         "msiof2_clk_a",
4749         "msiof2_sync_a",
4750         "msiof2_ss1_a",
4751         "msiof2_ss2_a",
4752         "msiof2_txd_a",
4753         "msiof2_rxd_a",
4754         "msiof2_clk_b",
4755         "msiof2_sync_b",
4756         "msiof2_ss1_b",
4757         "msiof2_ss2_b",
4758         "msiof2_txd_b",
4759         "msiof2_rxd_b",
4760         "msiof2_clk_c",
4761         "msiof2_sync_c",
4762         "msiof2_ss1_c",
4763         "msiof2_ss2_c",
4764         "msiof2_txd_c",
4765         "msiof2_rxd_c",
4766         "msiof2_clk_d",
4767         "msiof2_sync_d",
4768         "msiof2_ss1_d",
4769         "msiof2_ss2_d",
4770         "msiof2_txd_d",
4771         "msiof2_rxd_d",
4772 };
4773
4774 static const char * const msiof3_groups[] = {
4775         "msiof3_clk_a",
4776         "msiof3_sync_a",
4777         "msiof3_ss1_a",
4778         "msiof3_ss2_a",
4779         "msiof3_txd_a",
4780         "msiof3_rxd_a",
4781         "msiof3_clk_b",
4782         "msiof3_sync_b",
4783         "msiof3_ss1_b",
4784         "msiof3_ss2_b",
4785         "msiof3_txd_b",
4786         "msiof3_rxd_b",
4787         "msiof3_clk_c",
4788         "msiof3_sync_c",
4789         "msiof3_txd_c",
4790         "msiof3_rxd_c",
4791         "msiof3_clk_d",
4792         "msiof3_sync_d",
4793         "msiof3_ss1_d",
4794         "msiof3_txd_d",
4795         "msiof3_rxd_d",
4796         "msiof3_clk_e",
4797         "msiof3_sync_e",
4798         "msiof3_ss1_e",
4799         "msiof3_ss2_e",
4800         "msiof3_txd_e",
4801         "msiof3_rxd_e",
4802 };
4803
4804 static const char * const pwm0_groups[] = {
4805         "pwm0",
4806 };
4807
4808 static const char * const pwm1_groups[] = {
4809         "pwm1_a",
4810         "pwm1_b",
4811 };
4812
4813 static const char * const pwm2_groups[] = {
4814         "pwm2_a",
4815         "pwm2_b",
4816 };
4817
4818 static const char * const pwm3_groups[] = {
4819         "pwm3_a",
4820         "pwm3_b",
4821 };
4822
4823 static const char * const pwm4_groups[] = {
4824         "pwm4_a",
4825         "pwm4_b",
4826 };
4827
4828 static const char * const pwm5_groups[] = {
4829         "pwm5_a",
4830         "pwm5_b",
4831 };
4832
4833 static const char * const pwm6_groups[] = {
4834         "pwm6_a",
4835         "pwm6_b",
4836 };
4837
4838 static const char * const qspi0_groups[] = {
4839         "qspi0_ctrl",
4840         "qspi0_data2",
4841         "qspi0_data4",
4842 };
4843
4844 static const char * const qspi1_groups[] = {
4845         "qspi1_ctrl",
4846         "qspi1_data2",
4847         "qspi1_data4",
4848 };
4849
4850 static const char * const scif0_groups[] = {
4851         "scif0_data",
4852         "scif0_clk",
4853         "scif0_ctrl",
4854 };
4855
4856 static const char * const scif1_groups[] = {
4857         "scif1_data_a",
4858         "scif1_clk",
4859         "scif1_ctrl",
4860         "scif1_data_b",
4861 };
4862
4863 static const char * const scif2_groups[] = {
4864         "scif2_data_a",
4865         "scif2_clk",
4866         "scif2_data_b",
4867 };
4868
4869 static const char * const scif3_groups[] = {
4870         "scif3_data_a",
4871         "scif3_clk",
4872         "scif3_ctrl",
4873         "scif3_data_b",
4874 };
4875
4876 static const char * const scif4_groups[] = {
4877         "scif4_data_a",
4878         "scif4_clk_a",
4879         "scif4_ctrl_a",
4880         "scif4_data_b",
4881         "scif4_clk_b",
4882         "scif4_ctrl_b",
4883         "scif4_data_c",
4884         "scif4_clk_c",
4885         "scif4_ctrl_c",
4886 };
4887
4888 static const char * const scif5_groups[] = {
4889         "scif5_data_a",
4890         "scif5_clk_a",
4891         "scif5_data_b",
4892         "scif5_clk_b",
4893 };
4894
4895 static const char * const scif_clk_groups[] = {
4896         "scif_clk_a",
4897         "scif_clk_b",
4898 };
4899
4900 static const char * const sdhi0_groups[] = {
4901         "sdhi0_data1",
4902         "sdhi0_data4",
4903         "sdhi0_ctrl",
4904         "sdhi0_cd",
4905         "sdhi0_wp",
4906 };
4907
4908 static const char * const sdhi1_groups[] = {
4909         "sdhi1_data1",
4910         "sdhi1_data4",
4911         "sdhi1_ctrl",
4912         "sdhi1_cd",
4913         "sdhi1_wp",
4914 };
4915
4916 static const char * const sdhi2_groups[] = {
4917         "sdhi2_data1",
4918         "sdhi2_data4",
4919         "sdhi2_data8",
4920         "sdhi2_ctrl",
4921         "sdhi2_cd_a",
4922         "sdhi2_wp_a",
4923         "sdhi2_cd_b",
4924         "sdhi2_wp_b",
4925         "sdhi2_ds",
4926 };
4927
4928 static const char * const sdhi3_groups[] = {
4929         "sdhi3_data1",
4930         "sdhi3_data4",
4931         "sdhi3_data8",
4932         "sdhi3_ctrl",
4933         "sdhi3_cd",
4934         "sdhi3_wp",
4935         "sdhi3_ds",
4936 };
4937
4938 static const char * const ssi_groups[] = {
4939         "ssi0_data",
4940         "ssi01239_ctrl",
4941         "ssi1_data_a",
4942         "ssi1_data_b",
4943         "ssi1_ctrl_a",
4944         "ssi1_ctrl_b",
4945         "ssi2_data_a",
4946         "ssi2_data_b",
4947         "ssi2_ctrl_a",
4948         "ssi2_ctrl_b",
4949         "ssi3_data",
4950         "ssi349_ctrl",
4951         "ssi4_data",
4952         "ssi4_ctrl",
4953         "ssi5_data",
4954         "ssi5_ctrl",
4955         "ssi6_data",
4956         "ssi6_ctrl",
4957         "ssi7_data",
4958         "ssi78_ctrl",
4959         "ssi8_data",
4960         "ssi9_data_a",
4961         "ssi9_data_b",
4962         "ssi9_ctrl_a",
4963         "ssi9_ctrl_b",
4964 };
4965
4966 static const char * const tmu_groups[] = {
4967         "tmu_tclk1_a",
4968         "tmu_tclk1_b",
4969         "tmu_tclk2_a",
4970         "tmu_tclk2_b",
4971 };
4972
4973 static const char * const tpu_groups[] = {
4974         "tpu_to0",
4975         "tpu_to1",
4976         "tpu_to2",
4977         "tpu_to3",
4978 };
4979
4980 static const char * const usb0_groups[] = {
4981         "usb0",
4982 };
4983
4984 static const char * const usb1_groups[] = {
4985         "usb1",
4986 };
4987
4988 static const char * const usb30_groups[] = {
4989         "usb30",
4990 };
4991
4992 static const char * const vin4_groups[] = {
4993         "vin4_data8_a",
4994         "vin4_data10_a",
4995         "vin4_data12_a",
4996         "vin4_data16_a",
4997         "vin4_data18_a",
4998         "vin4_data20_a",
4999         "vin4_data24_a",
5000         "vin4_data8_b",
5001         "vin4_data10_b",
5002         "vin4_data12_b",
5003         "vin4_data16_b",
5004         "vin4_data18_b",
5005         "vin4_data20_b",
5006         "vin4_data24_b",
5007         "vin4_g8",
5008         "vin4_sync",
5009         "vin4_field",
5010         "vin4_clkenb",
5011         "vin4_clk",
5012 };
5013
5014 static const char * const vin5_groups[] = {
5015         "vin5_data8",
5016         "vin5_data10",
5017         "vin5_data12",
5018         "vin5_data16",
5019         "vin5_high8",
5020         "vin5_sync",
5021         "vin5_field",
5022         "vin5_clkenb",
5023         "vin5_clk",
5024 };
5025
5026 static const struct {
5027         struct sh_pfc_function common[52];
5028 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5029         struct sh_pfc_function automotive[5];
5030 #endif
5031 } pinmux_functions = {
5032         .common = {
5033                 SH_PFC_FUNCTION(audio_clk),
5034                 SH_PFC_FUNCTION(avb),
5035                 SH_PFC_FUNCTION(can0),
5036                 SH_PFC_FUNCTION(can1),
5037                 SH_PFC_FUNCTION(can_clk),
5038                 SH_PFC_FUNCTION(canfd0),
5039                 SH_PFC_FUNCTION(canfd1),
5040                 SH_PFC_FUNCTION(du),
5041                 SH_PFC_FUNCTION(hscif0),
5042                 SH_PFC_FUNCTION(hscif1),
5043                 SH_PFC_FUNCTION(hscif2),
5044                 SH_PFC_FUNCTION(hscif3),
5045                 SH_PFC_FUNCTION(hscif4),
5046                 SH_PFC_FUNCTION(i2c0),
5047                 SH_PFC_FUNCTION(i2c1),
5048                 SH_PFC_FUNCTION(i2c2),
5049                 SH_PFC_FUNCTION(i2c3),
5050                 SH_PFC_FUNCTION(i2c5),
5051                 SH_PFC_FUNCTION(i2c6),
5052                 SH_PFC_FUNCTION(intc_ex),
5053                 SH_PFC_FUNCTION(msiof0),
5054                 SH_PFC_FUNCTION(msiof1),
5055                 SH_PFC_FUNCTION(msiof2),
5056                 SH_PFC_FUNCTION(msiof3),
5057                 SH_PFC_FUNCTION(pwm0),
5058                 SH_PFC_FUNCTION(pwm1),
5059                 SH_PFC_FUNCTION(pwm2),
5060                 SH_PFC_FUNCTION(pwm3),
5061                 SH_PFC_FUNCTION(pwm4),
5062                 SH_PFC_FUNCTION(pwm5),
5063                 SH_PFC_FUNCTION(pwm6),
5064                 SH_PFC_FUNCTION(qspi0),
5065                 SH_PFC_FUNCTION(qspi1),
5066                 SH_PFC_FUNCTION(scif0),
5067                 SH_PFC_FUNCTION(scif1),
5068                 SH_PFC_FUNCTION(scif2),
5069                 SH_PFC_FUNCTION(scif3),
5070                 SH_PFC_FUNCTION(scif4),
5071                 SH_PFC_FUNCTION(scif5),
5072                 SH_PFC_FUNCTION(scif_clk),
5073                 SH_PFC_FUNCTION(sdhi0),
5074                 SH_PFC_FUNCTION(sdhi1),
5075                 SH_PFC_FUNCTION(sdhi2),
5076                 SH_PFC_FUNCTION(sdhi3),
5077                 SH_PFC_FUNCTION(ssi),
5078                 SH_PFC_FUNCTION(tmu),
5079                 SH_PFC_FUNCTION(tpu),
5080                 SH_PFC_FUNCTION(usb0),
5081                 SH_PFC_FUNCTION(usb1),
5082                 SH_PFC_FUNCTION(usb30),
5083                 SH_PFC_FUNCTION(vin4),
5084                 SH_PFC_FUNCTION(vin5),
5085         },
5086 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5087         .automotive = {
5088                 SH_PFC_FUNCTION(drif0),
5089                 SH_PFC_FUNCTION(drif1),
5090                 SH_PFC_FUNCTION(drif2),
5091                 SH_PFC_FUNCTION(drif3),
5092                 SH_PFC_FUNCTION(mlb_3pin),
5093         }
5094 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
5095 };
5096
5097 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5098 #define F_(x, y)        FN_##y
5099 #define FM(x)           FN_##x
5100         { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
5101                              GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5102                                    1, 1, 1, 1, 1),
5103                              GROUP(
5104                 /* GP0_31_16 RESERVED */
5105                 GP_0_15_FN,     GPSR0_15,
5106                 GP_0_14_FN,     GPSR0_14,
5107                 GP_0_13_FN,     GPSR0_13,
5108                 GP_0_12_FN,     GPSR0_12,
5109                 GP_0_11_FN,     GPSR0_11,
5110                 GP_0_10_FN,     GPSR0_10,
5111                 GP_0_9_FN,      GPSR0_9,
5112                 GP_0_8_FN,      GPSR0_8,
5113                 GP_0_7_FN,      GPSR0_7,
5114                 GP_0_6_FN,      GPSR0_6,
5115                 GP_0_5_FN,      GPSR0_5,
5116                 GP_0_4_FN,      GPSR0_4,
5117                 GP_0_3_FN,      GPSR0_3,
5118                 GP_0_2_FN,      GPSR0_2,
5119                 GP_0_1_FN,      GPSR0_1,
5120                 GP_0_0_FN,      GPSR0_0, ))
5121         },
5122         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5123                 0, 0,
5124                 0, 0,
5125                 0, 0,
5126                 GP_1_28_FN,     GPSR1_28,
5127                 GP_1_27_FN,     GPSR1_27,
5128                 GP_1_26_FN,     GPSR1_26,
5129                 GP_1_25_FN,     GPSR1_25,
5130                 GP_1_24_FN,     GPSR1_24,
5131                 GP_1_23_FN,     GPSR1_23,
5132                 GP_1_22_FN,     GPSR1_22,
5133                 GP_1_21_FN,     GPSR1_21,
5134                 GP_1_20_FN,     GPSR1_20,
5135                 GP_1_19_FN,     GPSR1_19,
5136                 GP_1_18_FN,     GPSR1_18,
5137                 GP_1_17_FN,     GPSR1_17,
5138                 GP_1_16_FN,     GPSR1_16,
5139                 GP_1_15_FN,     GPSR1_15,
5140                 GP_1_14_FN,     GPSR1_14,
5141                 GP_1_13_FN,     GPSR1_13,
5142                 GP_1_12_FN,     GPSR1_12,
5143                 GP_1_11_FN,     GPSR1_11,
5144                 GP_1_10_FN,     GPSR1_10,
5145                 GP_1_9_FN,      GPSR1_9,
5146                 GP_1_8_FN,      GPSR1_8,
5147                 GP_1_7_FN,      GPSR1_7,
5148                 GP_1_6_FN,      GPSR1_6,
5149                 GP_1_5_FN,      GPSR1_5,
5150                 GP_1_4_FN,      GPSR1_4,
5151                 GP_1_3_FN,      GPSR1_3,
5152                 GP_1_2_FN,      GPSR1_2,
5153                 GP_1_1_FN,      GPSR1_1,
5154                 GP_1_0_FN,      GPSR1_0, ))
5155         },
5156         { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
5157                              GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5158                                    1, 1, 1, 1),
5159                              GROUP(
5160                 /* GP2_31_15 RESERVED */
5161                 GP_2_14_FN,     GPSR2_14,
5162                 GP_2_13_FN,     GPSR2_13,
5163                 GP_2_12_FN,     GPSR2_12,
5164                 GP_2_11_FN,     GPSR2_11,
5165                 GP_2_10_FN,     GPSR2_10,
5166                 GP_2_9_FN,      GPSR2_9,
5167                 GP_2_8_FN,      GPSR2_8,
5168                 GP_2_7_FN,      GPSR2_7,
5169                 GP_2_6_FN,      GPSR2_6,
5170                 GP_2_5_FN,      GPSR2_5,
5171                 GP_2_4_FN,      GPSR2_4,
5172                 GP_2_3_FN,      GPSR2_3,
5173                 GP_2_2_FN,      GPSR2_2,
5174                 GP_2_1_FN,      GPSR2_1,
5175                 GP_2_0_FN,      GPSR2_0, ))
5176         },
5177         { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
5178                              GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5179                                    1, 1, 1, 1, 1),
5180                              GROUP(
5181                 /* GP3_31_16 RESERVED */
5182                 GP_3_15_FN,     GPSR3_15,
5183                 GP_3_14_FN,     GPSR3_14,
5184                 GP_3_13_FN,     GPSR3_13,
5185                 GP_3_12_FN,     GPSR3_12,
5186                 GP_3_11_FN,     GPSR3_11,
5187                 GP_3_10_FN,     GPSR3_10,
5188                 GP_3_9_FN,      GPSR3_9,
5189                 GP_3_8_FN,      GPSR3_8,
5190                 GP_3_7_FN,      GPSR3_7,
5191                 GP_3_6_FN,      GPSR3_6,
5192                 GP_3_5_FN,      GPSR3_5,
5193                 GP_3_4_FN,      GPSR3_4,
5194                 GP_3_3_FN,      GPSR3_3,
5195                 GP_3_2_FN,      GPSR3_2,
5196                 GP_3_1_FN,      GPSR3_1,
5197                 GP_3_0_FN,      GPSR3_0, ))
5198         },
5199         { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
5200                              GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5201                                    1, 1, 1, 1, 1, 1, 1),
5202                              GROUP(
5203                 /* GP4_31_18 RESERVED */
5204                 GP_4_17_FN,     GPSR4_17,
5205                 GP_4_16_FN,     GPSR4_16,
5206                 GP_4_15_FN,     GPSR4_15,
5207                 GP_4_14_FN,     GPSR4_14,
5208                 GP_4_13_FN,     GPSR4_13,
5209                 GP_4_12_FN,     GPSR4_12,
5210                 GP_4_11_FN,     GPSR4_11,
5211                 GP_4_10_FN,     GPSR4_10,
5212                 GP_4_9_FN,      GPSR4_9,
5213                 GP_4_8_FN,      GPSR4_8,
5214                 GP_4_7_FN,      GPSR4_7,
5215                 GP_4_6_FN,      GPSR4_6,
5216                 GP_4_5_FN,      GPSR4_5,
5217                 GP_4_4_FN,      GPSR4_4,
5218                 GP_4_3_FN,      GPSR4_3,
5219                 GP_4_2_FN,      GPSR4_2,
5220                 GP_4_1_FN,      GPSR4_1,
5221                 GP_4_0_FN,      GPSR4_0, ))
5222         },
5223         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5224                 0, 0,
5225                 0, 0,
5226                 0, 0,
5227                 0, 0,
5228                 0, 0,
5229                 0, 0,
5230                 GP_5_25_FN,     GPSR5_25,
5231                 GP_5_24_FN,     GPSR5_24,
5232                 GP_5_23_FN,     GPSR5_23,
5233                 GP_5_22_FN,     GPSR5_22,
5234                 GP_5_21_FN,     GPSR5_21,
5235                 GP_5_20_FN,     GPSR5_20,
5236                 GP_5_19_FN,     GPSR5_19,
5237                 GP_5_18_FN,     GPSR5_18,
5238                 GP_5_17_FN,     GPSR5_17,
5239                 GP_5_16_FN,     GPSR5_16,
5240                 GP_5_15_FN,     GPSR5_15,
5241                 GP_5_14_FN,     GPSR5_14,
5242                 GP_5_13_FN,     GPSR5_13,
5243                 GP_5_12_FN,     GPSR5_12,
5244                 GP_5_11_FN,     GPSR5_11,
5245                 GP_5_10_FN,     GPSR5_10,
5246                 GP_5_9_FN,      GPSR5_9,
5247                 GP_5_8_FN,      GPSR5_8,
5248                 GP_5_7_FN,      GPSR5_7,
5249                 GP_5_6_FN,      GPSR5_6,
5250                 GP_5_5_FN,      GPSR5_5,
5251                 GP_5_4_FN,      GPSR5_4,
5252                 GP_5_3_FN,      GPSR5_3,
5253                 GP_5_2_FN,      GPSR5_2,
5254                 GP_5_1_FN,      GPSR5_1,
5255                 GP_5_0_FN,      GPSR5_0, ))
5256         },
5257         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5258                 GP_6_31_FN,     GPSR6_31,
5259                 GP_6_30_FN,     GPSR6_30,
5260                 GP_6_29_FN,     GPSR6_29,
5261                 GP_6_28_FN,     GPSR6_28,
5262                 GP_6_27_FN,     GPSR6_27,
5263                 GP_6_26_FN,     GPSR6_26,
5264                 GP_6_25_FN,     GPSR6_25,
5265                 GP_6_24_FN,     GPSR6_24,
5266                 GP_6_23_FN,     GPSR6_23,
5267                 GP_6_22_FN,     GPSR6_22,
5268                 GP_6_21_FN,     GPSR6_21,
5269                 GP_6_20_FN,     GPSR6_20,
5270                 GP_6_19_FN,     GPSR6_19,
5271                 GP_6_18_FN,     GPSR6_18,
5272                 GP_6_17_FN,     GPSR6_17,
5273                 GP_6_16_FN,     GPSR6_16,
5274                 GP_6_15_FN,     GPSR6_15,
5275                 GP_6_14_FN,     GPSR6_14,
5276                 GP_6_13_FN,     GPSR6_13,
5277                 GP_6_12_FN,     GPSR6_12,
5278                 GP_6_11_FN,     GPSR6_11,
5279                 GP_6_10_FN,     GPSR6_10,
5280                 GP_6_9_FN,      GPSR6_9,
5281                 GP_6_8_FN,      GPSR6_8,
5282                 GP_6_7_FN,      GPSR6_7,
5283                 GP_6_6_FN,      GPSR6_6,
5284                 GP_6_5_FN,      GPSR6_5,
5285                 GP_6_4_FN,      GPSR6_4,
5286                 GP_6_3_FN,      GPSR6_3,
5287                 GP_6_2_FN,      GPSR6_2,
5288                 GP_6_1_FN,      GPSR6_1,
5289                 GP_6_0_FN,      GPSR6_0, ))
5290         },
5291         { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
5292                              GROUP(-28, 1, 1, 1, 1),
5293                              GROUP(
5294                 /* GP7_31_4 RESERVED */
5295                 GP_7_3_FN, GPSR7_3,
5296                 GP_7_2_FN, GPSR7_2,
5297                 GP_7_1_FN, GPSR7_1,
5298                 GP_7_0_FN, GPSR7_0, ))
5299         },
5300 #undef F_
5301 #undef FM
5302
5303 #define F_(x, y)        x,
5304 #define FM(x)           FN_##x,
5305         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5306                 IP0_31_28
5307                 IP0_27_24
5308                 IP0_23_20
5309                 IP0_19_16
5310                 IP0_15_12
5311                 IP0_11_8
5312                 IP0_7_4
5313                 IP0_3_0 ))
5314         },
5315         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5316                 IP1_31_28
5317                 IP1_27_24
5318                 IP1_23_20
5319                 IP1_19_16
5320                 IP1_15_12
5321                 IP1_11_8
5322                 IP1_7_4
5323                 IP1_3_0 ))
5324         },
5325         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5326                 IP2_31_28
5327                 IP2_27_24
5328                 IP2_23_20
5329                 IP2_19_16
5330                 IP2_15_12
5331                 IP2_11_8
5332                 IP2_7_4
5333                 IP2_3_0 ))
5334         },
5335         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5336                 IP3_31_28
5337                 IP3_27_24
5338                 IP3_23_20
5339                 IP3_19_16
5340                 IP3_15_12
5341                 IP3_11_8
5342                 IP3_7_4
5343                 IP3_3_0 ))
5344         },
5345         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5346                 IP4_31_28
5347                 IP4_27_24
5348                 IP4_23_20
5349                 IP4_19_16
5350                 IP4_15_12
5351                 IP4_11_8
5352                 IP4_7_4
5353                 IP4_3_0 ))
5354         },
5355         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5356                 IP5_31_28
5357                 IP5_27_24
5358                 IP5_23_20
5359                 IP5_19_16
5360                 IP5_15_12
5361                 IP5_11_8
5362                 IP5_7_4
5363                 IP5_3_0 ))
5364         },
5365         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5366                 IP6_31_28
5367                 IP6_27_24
5368                 IP6_23_20
5369                 IP6_19_16
5370                 IP6_15_12
5371                 IP6_11_8
5372                 IP6_7_4
5373                 IP6_3_0 ))
5374         },
5375         { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
5376                              GROUP(4, 4, 4, 4, -4, 4, 4, 4),
5377                              GROUP(
5378                 IP7_31_28
5379                 IP7_27_24
5380                 IP7_23_20
5381                 IP7_19_16
5382                 /* IP7_15_12 RESERVED */
5383                 IP7_11_8
5384                 IP7_7_4
5385                 IP7_3_0 ))
5386         },
5387         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5388                 IP8_31_28
5389                 IP8_27_24
5390                 IP8_23_20
5391                 IP8_19_16
5392                 IP8_15_12
5393                 IP8_11_8
5394                 IP8_7_4
5395                 IP8_3_0 ))
5396         },
5397         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5398                 IP9_31_28
5399                 IP9_27_24
5400                 IP9_23_20
5401                 IP9_19_16
5402                 IP9_15_12
5403                 IP9_11_8
5404                 IP9_7_4
5405                 IP9_3_0 ))
5406         },
5407         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5408                 IP10_31_28
5409                 IP10_27_24
5410                 IP10_23_20
5411                 IP10_19_16
5412                 IP10_15_12
5413                 IP10_11_8
5414                 IP10_7_4
5415                 IP10_3_0 ))
5416         },
5417         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5418                 IP11_31_28
5419                 IP11_27_24
5420                 IP11_23_20
5421                 IP11_19_16
5422                 IP11_15_12
5423                 IP11_11_8
5424                 IP11_7_4
5425                 IP11_3_0 ))
5426         },
5427         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5428                 IP12_31_28
5429                 IP12_27_24
5430                 IP12_23_20
5431                 IP12_19_16
5432                 IP12_15_12
5433                 IP12_11_8
5434                 IP12_7_4
5435                 IP12_3_0 ))
5436         },
5437         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5438                 IP13_31_28
5439                 IP13_27_24
5440                 IP13_23_20
5441                 IP13_19_16
5442                 IP13_15_12
5443                 IP13_11_8
5444                 IP13_7_4
5445                 IP13_3_0 ))
5446         },
5447         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5448                 IP14_31_28
5449                 IP14_27_24
5450                 IP14_23_20
5451                 IP14_19_16
5452                 IP14_15_12
5453                 IP14_11_8
5454                 IP14_7_4
5455                 IP14_3_0 ))
5456         },
5457         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5458                 IP15_31_28
5459                 IP15_27_24
5460                 IP15_23_20
5461                 IP15_19_16
5462                 IP15_15_12
5463                 IP15_11_8
5464                 IP15_7_4
5465                 IP15_3_0 ))
5466         },
5467         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5468                 IP16_31_28
5469                 IP16_27_24
5470                 IP16_23_20
5471                 IP16_19_16
5472                 IP16_15_12
5473                 IP16_11_8
5474                 IP16_7_4
5475                 IP16_3_0 ))
5476         },
5477         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5478                 IP17_31_28
5479                 IP17_27_24
5480                 IP17_23_20
5481                 IP17_19_16
5482                 IP17_15_12
5483                 IP17_11_8
5484                 IP17_7_4
5485                 IP17_3_0 ))
5486         },
5487         { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
5488                              GROUP(-24, 4, 4),
5489                              GROUP(
5490                 /* IP18_31_8 RESERVED */
5491                 IP18_7_4
5492                 IP18_3_0 ))
5493         },
5494 #undef F_
5495 #undef FM
5496
5497 #define F_(x, y)        x,
5498 #define FM(x)           FN_##x,
5499         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5500                              GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
5501                                    1, 1, 1, 2, 2, 1, 2, -3),
5502                              GROUP(
5503                 MOD_SEL0_31_30_29
5504                 MOD_SEL0_28_27
5505                 MOD_SEL0_26_25_24
5506                 MOD_SEL0_23
5507                 MOD_SEL0_22
5508                 MOD_SEL0_21
5509                 MOD_SEL0_20
5510                 MOD_SEL0_19
5511                 MOD_SEL0_18_17
5512                 MOD_SEL0_16
5513                 /* RESERVED 15 */
5514                 MOD_SEL0_14_13
5515                 MOD_SEL0_12
5516                 MOD_SEL0_11
5517                 MOD_SEL0_10
5518                 MOD_SEL0_9_8
5519                 MOD_SEL0_7_6
5520                 MOD_SEL0_5
5521                 MOD_SEL0_4_3
5522                 /* RESERVED 2, 1, 0 */ ))
5523         },
5524         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5525                              GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5526                                    1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
5527                              GROUP(
5528                 MOD_SEL1_31_30
5529                 MOD_SEL1_29_28_27
5530                 MOD_SEL1_26
5531                 MOD_SEL1_25_24
5532                 MOD_SEL1_23_22_21
5533                 MOD_SEL1_20
5534                 MOD_SEL1_19
5535                 MOD_SEL1_18_17
5536                 MOD_SEL1_16
5537                 MOD_SEL1_15_14
5538                 MOD_SEL1_13
5539                 MOD_SEL1_12
5540                 MOD_SEL1_11
5541                 MOD_SEL1_10
5542                 MOD_SEL1_9
5543                 /* RESERVED 8, 7 */
5544                 MOD_SEL1_6
5545                 MOD_SEL1_5
5546                 MOD_SEL1_4
5547                 MOD_SEL1_3
5548                 MOD_SEL1_2
5549                 MOD_SEL1_1
5550                 MOD_SEL1_0 ))
5551         },
5552         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5553                              GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5554                                    -16, 1),
5555                              GROUP(
5556                 MOD_SEL2_31
5557                 MOD_SEL2_30
5558                 MOD_SEL2_29
5559                 MOD_SEL2_28_27
5560                 MOD_SEL2_26
5561                 MOD_SEL2_25_24_23
5562                 MOD_SEL2_22
5563                 MOD_SEL2_21
5564                 MOD_SEL2_20
5565                 MOD_SEL2_19
5566                 MOD_SEL2_18
5567                 MOD_SEL2_17
5568                 /* RESERVED 16-1 */
5569                 MOD_SEL2_0 ))
5570         },
5571         { },
5572 };
5573
5574 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5575         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5576                 { PIN_QSPI0_SPCLK,    28, 2 },  /* QSPI0_SPCLK */
5577                 { PIN_QSPI0_MOSI_IO0, 24, 2 },  /* QSPI0_MOSI_IO0 */
5578                 { PIN_QSPI0_MISO_IO1, 20, 2 },  /* QSPI0_MISO_IO1 */
5579                 { PIN_QSPI0_IO2,      16, 2 },  /* QSPI0_IO2 */
5580                 { PIN_QSPI0_IO3,      12, 2 },  /* QSPI0_IO3 */
5581                 { PIN_QSPI0_SSL,       8, 2 },  /* QSPI0_SSL */
5582                 { PIN_QSPI1_SPCLK,     4, 2 },  /* QSPI1_SPCLK */
5583                 { PIN_QSPI1_MOSI_IO0,  0, 2 },  /* QSPI1_MOSI_IO0 */
5584         } },
5585         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5586                 { PIN_QSPI1_MISO_IO1, 28, 2 },  /* QSPI1_MISO_IO1 */
5587                 { PIN_QSPI1_IO2,      24, 2 },  /* QSPI1_IO2 */
5588                 { PIN_QSPI1_IO3,      20, 2 },  /* QSPI1_IO3 */
5589                 { PIN_QSPI1_SSL,      16, 2 },  /* QSPI1_SSL */
5590                 { PIN_RPC_INT_N,      12, 2 },  /* RPC_INT# */
5591                 { PIN_RPC_WP_N,        8, 2 },  /* RPC_WP# */
5592                 { PIN_RPC_RESET_N,     4, 2 },  /* RPC_RESET# */
5593                 { PIN_AVB_RX_CTL,      0, 3 },  /* AVB_RX_CTL */
5594         } },
5595         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5596                 { PIN_AVB_RXC,        28, 3 },  /* AVB_RXC */
5597                 { PIN_AVB_RD0,        24, 3 },  /* AVB_RD0 */
5598                 { PIN_AVB_RD1,        20, 3 },  /* AVB_RD1 */
5599                 { PIN_AVB_RD2,        16, 3 },  /* AVB_RD2 */
5600                 { PIN_AVB_RD3,        12, 3 },  /* AVB_RD3 */
5601                 { PIN_AVB_TX_CTL,      8, 3 },  /* AVB_TX_CTL */
5602                 { PIN_AVB_TXC,         4, 3 },  /* AVB_TXC */
5603                 { PIN_AVB_TD0,         0, 3 },  /* AVB_TD0 */
5604         } },
5605         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5606                 { PIN_AVB_TD1,        28, 3 },  /* AVB_TD1 */
5607                 { PIN_AVB_TD2,        24, 3 },  /* AVB_TD2 */
5608                 { PIN_AVB_TD3,        20, 3 },  /* AVB_TD3 */
5609                 { PIN_AVB_TXCREFCLK,  16, 3 },  /* AVB_TXCREFCLK */
5610                 { PIN_AVB_MDIO,       12, 3 },  /* AVB_MDIO */
5611                 { RCAR_GP_PIN(2,  9),  8, 3 },  /* AVB_MDC */
5612                 { RCAR_GP_PIN(2, 10),  4, 3 },  /* AVB_MAGIC */
5613                 { RCAR_GP_PIN(2, 11),  0, 3 },  /* AVB_PHY_INT */
5614         } },
5615         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5616                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5617                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5618                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5619                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5620                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5621                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5622                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5623                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5624         } },
5625         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5626                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5627                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5628                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5629                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5630                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5631                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5632                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5633                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5634         } },
5635         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5636                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5637                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5638                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5639                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5640                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5641                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5642                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5643                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5644         } },
5645         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5646                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5647                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5648                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5649                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5650                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5651                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5652                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5653                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5654         } },
5655         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5656                 { RCAR_GP_PIN(1, 28), 28, 3 },  /* CLKOUT */
5657                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5658                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5659                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5660                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5661                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5662                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5663                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5664         } },
5665         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5666                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5667                 { PIN_PRESETOUT_N,    24, 3 },  /* PRESETOUT# */
5668                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5669                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5670                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5671                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5672                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5673                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5674         } },
5675         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5676                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5677                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5678                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5679                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5680                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5681                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5682                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5683                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5684         } },
5685         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5686                 { RCAR_GP_PIN(0, 14), 28, 3 },  /* D14 */
5687                 { RCAR_GP_PIN(0, 15), 24, 3 },  /* D15 */
5688                 { RCAR_GP_PIN(7,  0), 20, 3 },  /* AVS1 */
5689                 { RCAR_GP_PIN(7,  1), 16, 3 },  /* AVS2 */
5690                 { RCAR_GP_PIN(7,  2), 12, 3 },  /* GP7_02 */
5691                 { RCAR_GP_PIN(7,  3),  8, 3 },  /* GP7_03 */
5692                 { PIN_DU_DOTCLKIN0,    4, 2 },  /* DU_DOTCLKIN0 */
5693                 { PIN_DU_DOTCLKIN1,    0, 2 },  /* DU_DOTCLKIN1 */
5694         } },
5695         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5696                 { PIN_DU_DOTCLKIN2,   28, 2 },  /* DU_DOTCLKIN2 */
5697                 { PIN_FSCLKST,        20, 2 },  /* FSCLKST */
5698                 { PIN_TMS,             4, 2 },  /* TMS */
5699         } },
5700         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5701                 { PIN_TDO,            28, 2 },  /* TDO */
5702                 { PIN_ASEBRK,         24, 2 },  /* ASEBRK */
5703                 { RCAR_GP_PIN(3,  0), 20, 3 },  /* SD0_CLK */
5704                 { RCAR_GP_PIN(3,  1), 16, 3 },  /* SD0_CMD */
5705                 { RCAR_GP_PIN(3,  2), 12, 3 },  /* SD0_DAT0 */
5706                 { RCAR_GP_PIN(3,  3),  8, 3 },  /* SD0_DAT1 */
5707                 { RCAR_GP_PIN(3,  4),  4, 3 },  /* SD0_DAT2 */
5708                 { RCAR_GP_PIN(3,  5),  0, 3 },  /* SD0_DAT3 */
5709         } },
5710         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5711                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5712                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5713                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5714                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5715                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5716                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5717                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5718                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5719         } },
5720         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5721                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5722                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5723                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5724                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5725                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5726                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5727                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5728                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5729         } },
5730         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5731                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5732                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5733                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5734                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5735                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5736                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5737                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5738                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5739         } },
5740         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5741                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5742                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5743                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5744                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5745                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5746                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5747                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5748                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5749         } },
5750         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5751                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0 */
5752                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5753                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5754                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5755                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1 */
5756                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5757                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5758                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5759         } },
5760         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5761                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5762                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5763                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5764                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5765                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5766                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5767                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5768                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5769         } },
5770         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5771                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5772                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5773                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5774                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5775                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5776                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5777                 { PIN_MLB_REF,         4, 3 },  /* MLB_REF */
5778                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5779         } },
5780         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5781                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5782                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5783                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5784                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5785                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5786                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5787                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5788                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5789         } },
5790         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5791                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5792                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5793                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5794                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5795                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5796                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5797                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5798                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5799         } },
5800         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5801                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5802                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5803                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5804                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5805                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5806                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5807                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5808                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5809         } },
5810         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5811                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5812                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5813                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5814                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5815                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5816                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* GP6_30 */
5817                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* GP6_31 */
5818         } },
5819         { },
5820 };
5821
5822 enum ioctrl_regs {
5823         POCCTRL,
5824         TDSELCTRL,
5825 };
5826
5827 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5828         [POCCTRL] = { 0xe6060380, },
5829         [TDSELCTRL] = { 0xe60603c0, },
5830         { /* sentinel */ },
5831 };
5832
5833 static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
5834 {
5835         int bit = -EINVAL;
5836
5837         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5838
5839         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5840                 bit = pin & 0x1f;
5841
5842         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5843                 bit = (pin & 0x1f) + 12;
5844
5845         return bit;
5846 }
5847
5848 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5849         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5850                 [ 0] = PIN_QSPI0_SPCLK,         /* QSPI0_SPCLK */
5851                 [ 1] = PIN_QSPI0_MOSI_IO0,      /* QSPI0_MOSI_IO0 */
5852                 [ 2] = PIN_QSPI0_MISO_IO1,      /* QSPI0_MISO_IO1 */
5853                 [ 3] = PIN_QSPI0_IO2,           /* QSPI0_IO2 */
5854                 [ 4] = PIN_QSPI0_IO3,           /* QSPI0_IO3 */
5855                 [ 5] = PIN_QSPI0_SSL,           /* QSPI0_SSL */
5856                 [ 6] = PIN_QSPI1_SPCLK,         /* QSPI1_SPCLK */
5857                 [ 7] = PIN_QSPI1_MOSI_IO0,      /* QSPI1_MOSI_IO0 */
5858                 [ 8] = PIN_QSPI1_MISO_IO1,      /* QSPI1_MISO_IO1 */
5859                 [ 9] = PIN_QSPI1_IO2,           /* QSPI1_IO2 */
5860                 [10] = PIN_QSPI1_IO3,           /* QSPI1_IO3 */
5861                 [11] = PIN_QSPI1_SSL,           /* QSPI1_SSL */
5862                 [12] = PIN_RPC_INT_N,           /* RPC_INT# */
5863                 [13] = PIN_RPC_WP_N,            /* RPC_WP# */
5864                 [14] = PIN_RPC_RESET_N,         /* RPC_RESET# */
5865                 [15] = PIN_AVB_RX_CTL,          /* AVB_RX_CTL */
5866                 [16] = PIN_AVB_RXC,             /* AVB_RXC */
5867                 [17] = PIN_AVB_RD0,             /* AVB_RD0 */
5868                 [18] = PIN_AVB_RD1,             /* AVB_RD1 */
5869                 [19] = PIN_AVB_RD2,             /* AVB_RD2 */
5870                 [20] = PIN_AVB_RD3,             /* AVB_RD3 */
5871                 [21] = PIN_AVB_TX_CTL,          /* AVB_TX_CTL */
5872                 [22] = PIN_AVB_TXC,             /* AVB_TXC */
5873                 [23] = PIN_AVB_TD0,             /* AVB_TD0 */
5874                 [24] = PIN_AVB_TD1,             /* AVB_TD1 */
5875                 [25] = PIN_AVB_TD2,             /* AVB_TD2 */
5876                 [26] = PIN_AVB_TD3,             /* AVB_TD3 */
5877                 [27] = PIN_AVB_TXCREFCLK,       /* AVB_TXCREFCLK */
5878                 [28] = PIN_AVB_MDIO,            /* AVB_MDIO */
5879                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
5880                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
5881                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
5882         } },
5883         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5884                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
5885                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
5886                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
5887                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
5888                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
5889                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
5890                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
5891                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
5892                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
5893                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
5894                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
5895                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
5896                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
5897                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
5898                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
5899                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
5900                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
5901                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
5902                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
5903                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
5904                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
5905                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
5906                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
5907                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
5908                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
5909                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
5910                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
5911                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
5912                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
5913                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
5914                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
5915                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
5916         } },
5917         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5918                 [ 0] = RCAR_GP_PIN(1, 28),      /* CLKOUT */
5919                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
5920                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N */
5921                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
5922                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
5923                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
5924                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
5925                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
5926                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
5927                 [ 9] = PIN_PRESETOUT_N,         /* PRESETOUT# */
5928                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
5929                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
5930                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
5931                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
5932                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
5933                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
5934                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
5935                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
5936                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
5937                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
5938                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
5939                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
5940                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
5941                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
5942                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
5943                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
5944                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
5945                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
5946                 [28] = RCAR_GP_PIN(7,  2),      /* GP7_02 */
5947                 [29] = RCAR_GP_PIN(7,  3),      /* GP7_03 */
5948                 [30] = PIN_DU_DOTCLKIN0,        /* DU_DOTCLKIN0 */
5949                 [31] = PIN_DU_DOTCLKIN1,        /* DU_DOTCLKIN1 */
5950         } },
5951         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5952                 [ 0] = PIN_DU_DOTCLKIN2,        /* DU_DOTCLKIN2 */
5953                 [ 1] = SH_PFC_PIN_NONE,
5954                 [ 2] = PIN_FSCLKST,             /* FSCLKST */
5955                 [ 3] = PIN_EXTALR,              /* EXTALR*/
5956                 [ 4] = PIN_TRST_N,              /* TRST# */
5957                 [ 5] = PIN_TCK,                 /* TCK */
5958                 [ 6] = PIN_TMS,                 /* TMS */
5959                 [ 7] = PIN_TDI,                 /* TDI */
5960                 [ 8] = SH_PFC_PIN_NONE,
5961                 [ 9] = PIN_ASEBRK,              /* ASEBRK */
5962                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
5963                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
5964                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
5965                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
5966                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
5967                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
5968                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
5969                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
5970                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
5971                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
5972                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
5973                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
5974                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
5975                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
5976                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
5977                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
5978                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
5979                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
5980                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
5981                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
5982                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
5983                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
5984         } },
5985         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5986                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
5987                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
5988                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
5989                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
5990                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
5991                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
5992                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
5993                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
5994                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
5995                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
5996                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
5997                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
5998                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
5999                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
6000                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
6001                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
6002                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N */
6003                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
6004                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
6005                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
6006                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N */
6007                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
6008                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
6009                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
6010                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
6011                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
6012                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
6013                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
6014                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
6015                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
6016                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
6017                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
6018         } },
6019         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6020                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
6021                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
6022                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
6023                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
6024                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
6025                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
6026                 [ 6] = PIN_MLB_REF,             /* MLB_REF */
6027                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
6028                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
6029                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
6030                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
6031                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
6032                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
6033                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
6034                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
6035                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
6036                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
6037                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
6038                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
6039                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
6040                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
6041                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
6042                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
6043                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
6044                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
6045                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
6046                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
6047                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
6048                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
6049                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
6050                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
6051                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
6052         } },
6053         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6054                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
6055                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
6056                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
6057                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
6058                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
6059                 [ 5] = RCAR_GP_PIN(6, 30),      /* GP6_30 */
6060                 [ 6] = RCAR_GP_PIN(6, 31),      /* GP6_31 */
6061                 [ 7] = PIN_PRESET_N,            /* PRESET# */
6062                 [ 8] = SH_PFC_PIN_NONE,
6063                 [ 9] = SH_PFC_PIN_NONE,
6064                 [10] = SH_PFC_PIN_NONE,
6065                 [11] = SH_PFC_PIN_NONE,
6066                 [12] = SH_PFC_PIN_NONE,
6067                 [13] = SH_PFC_PIN_NONE,
6068                 [14] = SH_PFC_PIN_NONE,
6069                 [15] = SH_PFC_PIN_NONE,
6070                 [16] = SH_PFC_PIN_NONE,
6071                 [17] = SH_PFC_PIN_NONE,
6072                 [18] = SH_PFC_PIN_NONE,
6073                 [19] = SH_PFC_PIN_NONE,
6074                 [20] = SH_PFC_PIN_NONE,
6075                 [21] = SH_PFC_PIN_NONE,
6076                 [22] = SH_PFC_PIN_NONE,
6077                 [23] = SH_PFC_PIN_NONE,
6078                 [24] = SH_PFC_PIN_NONE,
6079                 [25] = SH_PFC_PIN_NONE,
6080                 [26] = SH_PFC_PIN_NONE,
6081                 [27] = SH_PFC_PIN_NONE,
6082                 [28] = SH_PFC_PIN_NONE,
6083                 [29] = SH_PFC_PIN_NONE,
6084                 [30] = SH_PFC_PIN_NONE,
6085                 [31] = SH_PFC_PIN_NONE,
6086         } },
6087         { /* sentinel */ },
6088 };
6089
6090 static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
6091         .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
6092         .get_bias = rcar_pinmux_get_bias,
6093         .set_bias = rcar_pinmux_set_bias,
6094 };
6095
6096 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
6097 const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
6098         .name = "r8a774a1_pfc",
6099         .ops = &r8a7796_pfc_ops,
6100         .unlock_reg = 0xe6060000, /* PMMR */
6101
6102         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6103
6104         .pins = pinmux_pins,
6105         .nr_pins = ARRAY_SIZE(pinmux_pins),
6106         .groups = pinmux_groups.common,
6107         .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6108         .functions = pinmux_functions.common,
6109         .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6110
6111         .cfg_regs = pinmux_config_regs,
6112         .drive_regs = pinmux_drive_regs,
6113         .bias_regs = pinmux_bias_regs,
6114         .ioctrl_regs = pinmux_ioctrl_regs,
6115
6116         .pinmux_data = pinmux_data,
6117         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6118 };
6119 #endif
6120
6121 #ifdef CONFIG_PINCTRL_PFC_R8A77960
6122 const struct sh_pfc_soc_info r8a77960_pinmux_info = {
6123         .name = "r8a77960_pfc",
6124         .ops = &r8a7796_pfc_ops,
6125         .unlock_reg = 0xe6060000, /* PMMR */
6126
6127         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6128
6129         .pins = pinmux_pins,
6130         .nr_pins = ARRAY_SIZE(pinmux_pins),
6131         .groups = pinmux_groups.common,
6132         .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6133                 ARRAY_SIZE(pinmux_groups.automotive),
6134         .functions = pinmux_functions.common,
6135         .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6136                 ARRAY_SIZE(pinmux_functions.automotive),
6137
6138         .cfg_regs = pinmux_config_regs,
6139         .drive_regs = pinmux_drive_regs,
6140         .bias_regs = pinmux_bias_regs,
6141         .ioctrl_regs = pinmux_ioctrl_regs,
6142
6143         .pinmux_data = pinmux_data,
6144         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6145 };
6146 #endif
6147
6148 #ifdef CONFIG_PINCTRL_PFC_R8A77961
6149 const struct sh_pfc_soc_info r8a77961_pinmux_info = {
6150         .name = "r8a77961_pfc",
6151         .ops = &r8a7796_pfc_ops,
6152         .unlock_reg = 0xe6060000, /* PMMR */
6153
6154         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6155
6156         .pins = pinmux_pins,
6157         .nr_pins = ARRAY_SIZE(pinmux_pins),
6158         .groups = pinmux_groups.common,
6159         .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6160                 ARRAY_SIZE(pinmux_groups.automotive),
6161         .functions = pinmux_functions.common,
6162         .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6163                 ARRAY_SIZE(pinmux_functions.automotive),
6164
6165         .cfg_regs = pinmux_config_regs,
6166         .drive_regs = pinmux_drive_regs,
6167         .bias_regs = pinmux_bias_regs,
6168         .ioctrl_regs = pinmux_ioctrl_regs,
6169
6170         .pinmux_data = pinmux_data,
6171         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6172 };
6173 #endif