drivers/pinctrl/renesas/pfc-r8a7796.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A7796 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2016-2019 Renesas Electronics Corp.
   6  *
   7  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
   8  *
   9  * R-Car Gen3 processor support - PFC hardware block.
  10  *
  11  * Copyright (C) 2015  Renesas Electronics Corporation
  12  */
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <dm/pinctrl.h>
  18 #include <linux/kernel.h>
  19
  20 #include "sh_pfc.h"
  21
  22 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  23                    SH_PFC_PIN_CFG_PULL_UP | \
  24                    SH_PFC_PIN_CFG_PULL_DOWN)
  25
  26 #define CPU_ALL_PORT(fn, sfx)                                           \
  27         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  28         PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
  29         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  30         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  31         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  32         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  33         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  34         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  35         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  36         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  37         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  38         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  39 /*
  40  * F_() : just information
  41  * FM() : macro for FN_xxx / xxx_MARK
  42  */
  43
  44 /* GPSR0 */
  45 #define GPSR0_15        F_(D15,                 IP7_11_8)
  46 #define GPSR0_14        F_(D14,                 IP7_7_4)
  47 #define GPSR0_13        F_(D13,                 IP7_3_0)
  48 #define GPSR0_12        F_(D12,                 IP6_31_28)
  49 #define GPSR0_11        F_(D11,                 IP6_27_24)
  50 #define GPSR0_10        F_(D10,                 IP6_23_20)
  51 #define GPSR0_9         F_(D9,                  IP6_19_16)
  52 #define GPSR0_8         F_(D8,                  IP6_15_12)
  53 #define GPSR0_7         F_(D7,                  IP6_11_8)
  54 #define GPSR0_6         F_(D6,                  IP6_7_4)
  55 #define GPSR0_5         F_(D5,                  IP6_3_0)
  56 #define GPSR0_4         F_(D4,                  IP5_31_28)
  57 #define GPSR0_3         F_(D3,                  IP5_27_24)
  58 #define GPSR0_2         F_(D2,                  IP5_23_20)
  59 #define GPSR0_1         F_(D1,                  IP5_19_16)
  60 #define GPSR0_0         F_(D0,                  IP5_15_12)
  61
  62 /* GPSR1 */
  63 #define GPSR1_28        FM(CLKOUT)
  64 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  65 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  66 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  67 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  68 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  69 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  70 #define GPSR1_21        F_(CS1_N,               IP4_19_16)
  71 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  72 #define GPSR1_19        F_(A19,                 IP4_11_8)
  73 #define GPSR1_18        F_(A18,                 IP4_7_4)
  74 #define GPSR1_17        F_(A17,                 IP4_3_0)
  75 #define GPSR1_16        F_(A16,                 IP3_31_28)
  76 #define GPSR1_15        F_(A15,                 IP3_27_24)
  77 #define GPSR1_14        F_(A14,                 IP3_23_20)
  78 #define GPSR1_13        F_(A13,                 IP3_19_16)
  79 #define GPSR1_12        F_(A12,                 IP3_15_12)
  80 #define GPSR1_11        F_(A11,                 IP3_11_8)
  81 #define GPSR1_10        F_(A10,                 IP3_7_4)
  82 #define GPSR1_9         F_(A9,                  IP3_3_0)
  83 #define GPSR1_8         F_(A8,                  IP2_31_28)
  84 #define GPSR1_7         F_(A7,                  IP2_27_24)
  85 #define GPSR1_6         F_(A6,                  IP2_23_20)
  86 #define GPSR1_5         F_(A5,                  IP2_19_16)
  87 #define GPSR1_4         F_(A4,                  IP2_15_12)
  88 #define GPSR1_3         F_(A3,                  IP2_11_8)
  89 #define GPSR1_2         F_(A2,                  IP2_7_4)
  90 #define GPSR1_1         F_(A1,                  IP2_3_0)
  91 #define GPSR1_0         F_(A0,                  IP1_31_28)
  92
  93 /* GPSR2 */
  94 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  95 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  96 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  97 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  98 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
  99 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
 100 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
 101 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
 102 #define GPSR2_6         F_(PWM0,                IP1_19_16)
 103 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
 104 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
 105 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
 106 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
 107 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
 108 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
 109
 110 /* GPSR3 */
 111 #define GPSR3_15        F_(SD1_WP,              IP11_23_20)
 112 #define GPSR3_14        F_(SD1_CD,              IP11_19_16)
 113 #define GPSR3_13        F_(SD0_WP,              IP11_15_12)
 114 #define GPSR3_12        F_(SD0_CD,              IP11_11_8)
 115 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 116 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 117 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 118 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 119 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 120 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 121 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 122 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 123 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 124 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 125 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 126 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 127
 128 /* GPSR4 */
 129 #define GPSR4_17        F_(SD3_DS,              IP11_7_4)
 130 #define GPSR4_16        F_(SD3_DAT7,            IP11_3_0)
 131 #define GPSR4_15        F_(SD3_DAT6,            IP10_31_28)
 132 #define GPSR4_14        F_(SD3_DAT5,            IP10_27_24)
 133 #define GPSR4_13        F_(SD3_DAT4,            IP10_23_20)
 134 #define GPSR4_12        F_(SD3_DAT3,            IP10_19_16)
 135 #define GPSR4_11        F_(SD3_DAT2,            IP10_15_12)
 136 #define GPSR4_10        F_(SD3_DAT1,            IP10_11_8)
 137 #define GPSR4_9         F_(SD3_DAT0,            IP10_7_4)
 138 #define GPSR4_8         F_(SD3_CMD,             IP10_3_0)
 139 #define GPSR4_7         F_(SD3_CLK,             IP9_31_28)
 140 #define GPSR4_6         F_(SD2_DS,              IP9_27_24)
 141 #define GPSR4_5         F_(SD2_DAT3,            IP9_23_20)
 142 #define GPSR4_4         F_(SD2_DAT2,            IP9_19_16)
 143 #define GPSR4_3         F_(SD2_DAT1,            IP9_15_12)
 144 #define GPSR4_2         F_(SD2_DAT0,            IP9_11_8)
 145 #define GPSR4_1         F_(SD2_CMD,             IP9_7_4)
 146 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 147
 148 /* GPSR5 */
 149 #define GPSR5_25        F_(MLB_DAT,             IP14_19_16)
 150 #define GPSR5_24        F_(MLB_SIG,             IP14_15_12)
 151 #define GPSR5_23        F_(MLB_CLK,             IP14_11_8)
 152 #define GPSR5_22        FM(MSIOF0_RXD)
 153 #define GPSR5_21        F_(MSIOF0_SS2,          IP14_7_4)
 154 #define GPSR5_20        FM(MSIOF0_TXD)
 155 #define GPSR5_19        F_(MSIOF0_SS1,          IP14_3_0)
 156 #define GPSR5_18        F_(MSIOF0_SYNC,         IP13_31_28)
 157 #define GPSR5_17        FM(MSIOF0_SCK)
 158 #define GPSR5_16        F_(HRTS0_N,             IP13_27_24)
 159 #define GPSR5_15        F_(HCTS0_N,             IP13_23_20)
 160 #define GPSR5_14        F_(HTX0,                IP13_19_16)
 161 #define GPSR5_13        F_(HRX0,                IP13_15_12)
 162 #define GPSR5_12        F_(HSCK0,               IP13_11_8)
 163 #define GPSR5_11        F_(RX2_A,               IP13_7_4)
 164 #define GPSR5_10        F_(TX2_A,               IP13_3_0)
 165 #define GPSR5_9         F_(SCK2,                IP12_31_28)
 166 #define GPSR5_8         F_(RTS1_N,              IP12_27_24)
 167 #define GPSR5_7         F_(CTS1_N,              IP12_23_20)
 168 #define GPSR5_6         F_(TX1_A,               IP12_19_16)
 169 #define GPSR5_5         F_(RX1_A,               IP12_15_12)
 170 #define GPSR5_4         F_(RTS0_N,              IP12_11_8)
 171 #define GPSR5_3         F_(CTS0_N,              IP12_7_4)
 172 #define GPSR5_2         F_(TX0,                 IP12_3_0)
 173 #define GPSR5_1         F_(RX0,                 IP11_31_28)
 174 #define GPSR5_0         F_(SCK0,                IP11_27_24)
 175
 176 /* GPSR6 */
 177 #define GPSR6_31        F_(GP6_31,              IP18_7_4)
 178 #define GPSR6_30        F_(GP6_30,              IP18_3_0)
 179 #define GPSR6_29        F_(USB30_OVC,           IP17_31_28)
 180 #define GPSR6_28        F_(USB30_PWEN,          IP17_27_24)
 181 #define GPSR6_27        F_(USB1_OVC,            IP17_23_20)
 182 #define GPSR6_26        F_(USB1_PWEN,           IP17_19_16)
 183 #define GPSR6_25        F_(USB0_OVC,            IP17_15_12)
 184 #define GPSR6_24        F_(USB0_PWEN,           IP17_11_8)
 185 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP17_7_4)
 186 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP17_3_0)
 187 #define GPSR6_21        F_(SSI_SDATA9_A,        IP16_31_28)
 188 #define GPSR6_20        F_(SSI_SDATA8,          IP16_27_24)
 189 #define GPSR6_19        F_(SSI_SDATA7,          IP16_23_20)
 190 #define GPSR6_18        F_(SSI_WS78,            IP16_19_16)
 191 #define GPSR6_17        F_(SSI_SCK78,           IP16_15_12)
 192 #define GPSR6_16        F_(SSI_SDATA6,          IP16_11_8)
 193 #define GPSR6_15        F_(SSI_WS6,             IP16_7_4)
 194 #define GPSR6_14        F_(SSI_SCK6,            IP16_3_0)
 195 #define GPSR6_13        FM(SSI_SDATA5)
 196 #define GPSR6_12        FM(SSI_WS5)
 197 #define GPSR6_11        FM(SSI_SCK5)
 198 #define GPSR6_10        F_(SSI_SDATA4,          IP15_31_28)
 199 #define GPSR6_9         F_(SSI_WS4,             IP15_27_24)
 200 #define GPSR6_8         F_(SSI_SCK4,            IP15_23_20)
 201 #define GPSR6_7         F_(SSI_SDATA3,          IP15_19_16)
 202 #define GPSR6_6         F_(SSI_WS349,           IP15_15_12)
 203 #define GPSR6_5         F_(SSI_SCK349,          IP15_11_8)
 204 #define GPSR6_4         F_(SSI_SDATA2_A,        IP15_7_4)
 205 #define GPSR6_3         F_(SSI_SDATA1_A,        IP15_3_0)
 206 #define GPSR6_2         F_(SSI_SDATA0,          IP14_31_28)
 207 #define GPSR6_1         F_(SSI_WS01239,         IP14_27_24)
 208 #define GPSR6_0         F_(SSI_SCK01239,        IP14_23_20)
 209
 210 /* GPSR7 */
 211 #define GPSR7_3         FM(GP7_03)
 212 #define GPSR7_2         FM(GP7_02)
 213 #define GPSR7_1         FM(AVS2)
 214 #define GPSR7_0         FM(AVS1)
 215
 216
 217 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 218 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         FM(MSIOF3_SS2_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         FM(MSIOF3_SS1_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SYNC_E) F_(0, 0)              FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   F_(0, 0)                FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SCK_E) F_(0, 0)               FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    F_(0, 0)                FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_RXD_E) F_(0, 0)               FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 229 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    F_(0, 0)                FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_TXD_E) F_(0, 0)               FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 231 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        F_(0, 0)                FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 232 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        F_(0, 0)                FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_B)                    F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 244 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 245
 246 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 247 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP4_19_16       FM(CS1_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N)                      FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_C)    FM(DU_DR3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 275 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 276
 277 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 278 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       FM(NFCE_N_B)                    F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        FM(NFWP_N_B)                    F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        FM(NFDATA14_B)                  F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        FM(NFDATA15_B)                  F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        FM(NFRB_N_B)                    F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        FM(NFDATA8)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP9_7_4         FM(SD2_CMD)             F_(0, 0)        FM(NFDATA9)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP9_11_8        FM(SD2_DAT0)            F_(0, 0)        FM(NFDATA10)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP9_15_12       FM(SD2_DAT1)            F_(0, 0)        FM(NFDATA11)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP9_19_16       FM(SD2_DAT2)            F_(0, 0)        FM(NFDATA12)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP9_23_20       FM(SD2_DAT3)            F_(0, 0)        FM(NFDATA13)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP9_27_24       FM(SD2_DS)              F_(0, 0)        FM(NFALE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP9_31_28       FM(SD3_CLK)             F_(0, 0)        FM(NFWE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP10_3_0        FM(SD3_CMD)             F_(0, 0)        FM(NFRE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP10_7_4        FM(SD3_DAT0)            F_(0, 0)        FM(NFDATA0)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP10_11_8       FM(SD3_DAT1)            F_(0, 0)        FM(NFDATA1)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP10_15_12      FM(SD3_DAT2)            F_(0, 0)        FM(NFDATA2)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP10_19_16      FM(SD3_DAT3)            F_(0, 0)        FM(NFDATA3)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306 #define IP10_23_20      FM(SD3_DAT4)            FM(SD2_CD_A)    FM(NFDATA4)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP10_27_24      FM(SD3_DAT5)            FM(SD2_WP_A)    FM(NFDATA5)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP10_31_28      FM(SD3_DAT6)            FM(SD3_CD)      FM(NFDATA6)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP11_3_0        FM(SD3_DAT7)            FM(SD3_WP)      FM(NFDATA7)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310 #define IP11_7_4        FM(SD3_DS)              F_(0, 0)        FM(NFCLE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311 #define IP11_11_8       FM(SD0_CD)              F_(0, 0)        FM(NFDATA14_A)          F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312
 313 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 314 #define IP11_15_12      FM(SD0_WP)              F_(0, 0)        FM(NFDATA15_A)          F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315 #define IP11_19_16      FM(SD1_CD)              F_(0, 0)        FM(NFRB_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316 #define IP11_23_20      FM(SD1_WP)              F_(0, 0)        FM(NFCE_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317 #define IP11_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     FM(SCK5_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318 #define IP11_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319 #define IP12_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320 #define IP12_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP12_11_8       FM(RTS0_N)              FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP12_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP12_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP12_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP12_27_24      FM(RTS1_N)              FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP12_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP13_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP13_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP13_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        FM(RX5_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP13_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP13_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP13_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333 #define IP13_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334 #define IP13_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        FM(TX5_B)       F_(0, 0)        F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
 335 #define IP14_3_0        FM(MSIOF0_SS1)          FM(RX5_A)       FM(NFWP_N_A)            FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336 #define IP14_7_4        FM(MSIOF0_SS2)          FM(TX5_A)       FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP14_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP14_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP14_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340 #define IP14_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341 #define IP14_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342
 343 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 344 #define IP14_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP15_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP15_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP15_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP15_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP15_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP15_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP15_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352 #define IP15_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353 #define IP16_3_0        FM(SSI_SCK6)            F_(0, 0)        F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354 #define IP16_7_4        FM(SSI_WS6)             F_(0, 0)        F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355 #define IP16_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 356 #define IP16_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 357 #define IP16_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 358 #define IP16_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 359 #define IP16_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 360 #define IP16_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5_A)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 361 #define IP17_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 362 #define IP17_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 363 #define IP17_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
 364 #define IP17_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
 365 #define IP17_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
 366 #define IP17_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
 367 #define IP17_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 368 #define IP17_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_N)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 369 #define IP18_3_0        FM(GP6_30)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
 370 #define IP18_7_4        FM(GP6_31)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
 371
 372 #define PINMUX_GPSR     \
 373 \
 374                                                                                                 GPSR6_31 \
 375                                                                                                 GPSR6_30 \
 376                                                                                                 GPSR6_29 \
 377                 GPSR1_28                                                                        GPSR6_28 \
 378                 GPSR1_27                                                                        GPSR6_27 \
 379                 GPSR1_26                                                                        GPSR6_26 \
 380                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 381                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 382                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 383                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 384                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 385                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 386                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 387                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 388                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 389                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 390 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 391 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 392 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 393 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 394 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 395 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 396 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 397 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 398 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 399 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 400 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 401 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 402 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 403 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 404 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 405 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 406
 407 #define PINMUX_IPSR                             \
 408 \
 409 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 410 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 411 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 412 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 413 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 414 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 415 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 416 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 417 \
 418 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 419 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 420 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 421 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12 \
 422 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 423 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 424 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 425 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 426 \
 427 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 428 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 429 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 430 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 431 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 432 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 433 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 434 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 435 \
 436 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 437 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 438 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 439 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 440 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 441 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 442 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 443 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 444 \
 445 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0        FM(IP18_3_0)    IP18_3_0 \
 446 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4        FM(IP18_7_4)    IP18_7_4 \
 447 FM(IP16_11_8)   IP16_11_8       FM(IP17_11_8)   IP17_11_8 \
 448 FM(IP16_15_12)  IP16_15_12      FM(IP17_15_12)  IP17_15_12 \
 449 FM(IP16_19_16)  IP16_19_16      FM(IP17_19_16)  IP17_19_16 \
 450 FM(IP16_23_20)  IP16_23_20      FM(IP17_23_20)  IP17_23_20 \
 451 FM(IP16_27_24)  IP16_27_24      FM(IP17_27_24)  IP17_27_24 \
 452 FM(IP16_31_28)  IP16_31_28      FM(IP17_31_28)  IP17_31_28
 453
 454 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 455 #define MOD_SEL0_31_30_29       FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)        FM(SEL_MSIOF3_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 456 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 457 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 458 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 459 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 460 #define MOD_SEL0_21             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 461 #define MOD_SEL0_20             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 462 #define MOD_SEL0_19             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 463 #define MOD_SEL0_18_17          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 464 #define MOD_SEL0_16             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 465 #define MOD_SEL0_14_13          FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)        FM(SEL_HSCIF2_2)        F_(0, 0)
 466 #define MOD_SEL0_12             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 467 #define MOD_SEL0_11             FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 468 #define MOD_SEL0_10             FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 469 #define MOD_SEL0_9_8            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 470 #define MOD_SEL0_7_6            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 471 #define MOD_SEL0_5              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 472 #define MOD_SEL0_4_3            FM(SEL_ADGA_0)          FM(SEL_ADGA_1)          FM(SEL_ADGA_2)          FM(SEL_ADGA_3)
 473
 474 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 475 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 476 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 477 #define MOD_SEL1_26             FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
 478 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 479 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 480 #define MOD_SEL1_20             FM(SEL_SSI1_0)          FM(SEL_SSI1_1)
 481 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 482 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 483 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 484 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 485 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 486 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 487 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 488 #define MOD_SEL1_10             FM(SEL_SCIF_0)          FM(SEL_SCIF_1)
 489 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 490 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 491 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 492 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 493 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 494 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 495 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 496 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 497
 498 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 499 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 500 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 501 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 502 #define MOD_SEL2_28_27          FM(SEL_FM_0)            FM(SEL_FM_1)            FM(SEL_FM_2)            FM(SEL_FM_3)
 503 #define MOD_SEL2_26             FM(SEL_SCIF5_0)         FM(SEL_SCIF5_1)
 504 #define MOD_SEL2_25_24_23       FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)
 505 #define MOD_SEL2_22             FM(SEL_NDF_0)           FM(SEL_NDF_1)
 506 #define MOD_SEL2_21             FM(SEL_SSI2_0)          FM(SEL_SSI2_1)
 507 #define MOD_SEL2_20             FM(SEL_SSI9_0)          FM(SEL_SSI9_1)
 508 #define MOD_SEL2_19             FM(SEL_TIMER_TMU2_0)    FM(SEL_TIMER_TMU2_1)
 509 #define MOD_SEL2_18             FM(SEL_ADGB_0)          FM(SEL_ADGB_1)
 510 #define MOD_SEL2_17             FM(SEL_ADGC_0)          FM(SEL_ADGC_1)
 511 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 512
 513 #define PINMUX_MOD_SELS \
 514 \
 515 MOD_SEL0_31_30_29       MOD_SEL1_31_30          MOD_SEL2_31 \
 516                                                 MOD_SEL2_30 \
 517                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 518 MOD_SEL0_28_27                                  MOD_SEL2_28_27 \
 519 MOD_SEL0_26_25_24       MOD_SEL1_26             MOD_SEL2_26 \
 520                         MOD_SEL1_25_24          MOD_SEL2_25_24_23 \
 521 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 522 MOD_SEL0_22                                     MOD_SEL2_22 \
 523 MOD_SEL0_21                                     MOD_SEL2_21 \
 524 MOD_SEL0_20             MOD_SEL1_20             MOD_SEL2_20 \
 525 MOD_SEL0_19             MOD_SEL1_19             MOD_SEL2_19 \
 526 MOD_SEL0_18_17          MOD_SEL1_18_17          MOD_SEL2_18 \
 527                                                 MOD_SEL2_17 \
 528 MOD_SEL0_16             MOD_SEL1_16 \
 529                         MOD_SEL1_15_14 \
 530 MOD_SEL0_14_13 \
 531                         MOD_SEL1_13 \
 532 MOD_SEL0_12             MOD_SEL1_12 \
 533 MOD_SEL0_11             MOD_SEL1_11 \
 534 MOD_SEL0_10             MOD_SEL1_10 \
 535 MOD_SEL0_9_8            MOD_SEL1_9 \
 536 MOD_SEL0_7_6 \
 537                         MOD_SEL1_6 \
 538 MOD_SEL0_5              MOD_SEL1_5 \
 539 MOD_SEL0_4_3            MOD_SEL1_4 \
 540                         MOD_SEL1_3 \
 541                         MOD_SEL1_2 \
 542                         MOD_SEL1_1 \
 543                         MOD_SEL1_0              MOD_SEL2_0
 544
 545 /*
 546  * These pins are not able to be muxed but have other properties
 547  * that can be set, such as drive-strength or pull-up/pull-down enable.
 548  */
 549 #define PINMUX_STATIC \
 550         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 551         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 552         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 553         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 554         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 555         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 556         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 557         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 558         FM(PRESETOUT) \
 559         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
 560         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 561
 562 #define PINMUX_PHYS \
 563         FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
 564
 565 enum {
 566         PINMUX_RESERVED = 0,
 567
 568         PINMUX_DATA_BEGIN,
 569         GP_ALL(DATA),
 570         PINMUX_DATA_END,
 571
 572 #define F_(x, y)
 573 #define FM(x)   FN_##x,
 574         PINMUX_FUNCTION_BEGIN,
 575         GP_ALL(FN),
 576         PINMUX_GPSR
 577         PINMUX_IPSR
 578         PINMUX_MOD_SELS
 579         PINMUX_FUNCTION_END,
 580 #undef F_
 581 #undef FM
 582
 583 #define F_(x, y)
 584 #define FM(x)   x##_MARK,
 585         PINMUX_MARK_BEGIN,
 586         PINMUX_GPSR
 587         PINMUX_IPSR
 588         PINMUX_MOD_SELS
 589         PINMUX_STATIC
 590         PINMUX_PHYS
 591         PINMUX_MARK_END,
 592 #undef F_
 593 #undef FM
 594 };
 595
 596 static const u16 pinmux_data[] = {
 597         PINMUX_DATA_GP_ALL(),
 598
 599         PINMUX_SINGLE(AVS1),
 600         PINMUX_SINGLE(AVS2),
 601         PINMUX_SINGLE(CLKOUT),
 602         PINMUX_SINGLE(GP7_03),
 603         PINMUX_SINGLE(GP7_02),
 604         PINMUX_SINGLE(MSIOF0_RXD),
 605         PINMUX_SINGLE(MSIOF0_SCK),
 606         PINMUX_SINGLE(MSIOF0_TXD),
 607         PINMUX_SINGLE(SSI_SCK5),
 608         PINMUX_SINGLE(SSI_SDATA5),
 609         PINMUX_SINGLE(SSI_WS5),
 610
 611         /* IPSR0 */
 612         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 613         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 614
 615         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 616         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 617         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 618
 619         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 620         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 621         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 622
 623         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 624         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 625         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 626
 627         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,      I2C_SEL_5_0,    SEL_ETHERAVB_0),
 628         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,          I2C_SEL_5_0,    SEL_MSIOF2_2),
 629         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,              I2C_SEL_5_0,    SEL_SCIF4_0),
 630         PINMUX_IPSR_PHYS(IP0_19_16,     SCL5,                   I2C_SEL_5_1),
 631
 632         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,    I2C_SEL_5_0,    SEL_ETHERAVB_0),
 633         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,          I2C_SEL_5_0,    SEL_MSIOF2_2),
 634         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A,              I2C_SEL_5_0,    SEL_SCIF4_0),
 635         PINMUX_IPSR_PHYS(IP0_23_20,     SDA5,                   I2C_SEL_5_1),
 636
 637         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 638         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 639         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 640         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 641         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 642         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 643         PINMUX_IPSR_MSEL(IP0_27_24,     MSIOF3_SS2_E,           SEL_MSIOF3_4),
 644
 645         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 646         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 647         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 648         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 649         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 650         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 651         PINMUX_IPSR_MSEL(IP0_31_28,     MSIOF3_SS1_E,           SEL_MSIOF3_4),
 652
 653         /* IPSR1 */
 654         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 655         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 656         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 657         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 658         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 659         PINMUX_IPSR_MSEL(IP1_3_0,       MSIOF3_SYNC_E,          SEL_MSIOF3_4),
 660
 661         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 662         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 663         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 664         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 665         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 666         PINMUX_IPSR_MSEL(IP1_7_4,       MSIOF3_SCK_E,           SEL_MSIOF3_4),
 667
 668         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 669         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 670         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 671         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 672         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 673         PINMUX_IPSR_MSEL(IP1_11_8,      MSIOF3_RXD_E,           SEL_MSIOF3_4),
 674
 675         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 676         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 677         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 678         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 679         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 680         PINMUX_IPSR_MSEL(IP1_15_12,     MSIOF3_TXD_E,           SEL_MSIOF3_4),
 681
 682         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 683         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 684         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 685         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 686
 687         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,                I2C_SEL_3_0,    SEL_PWM1_0),
 688         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,                I2C_SEL_3_0,    SEL_HSCIF3_3),
 689         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,           I2C_SEL_3_0,    SEL_VIN4_1),
 690         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,                I2C_SEL_3_0,    SEL_IEBUS_1),
 691         PINMUX_IPSR_PHYS(IP0_23_20,     SCL3,                   I2C_SEL_3_1),
 692
 693         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,                I2C_SEL_3_0,    SEL_PWM2_0),
 694         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,                I2C_SEL_3_0,    SEL_HSCIF3_3),
 695         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,                I2C_SEL_3_0,    SEL_IEBUS_1),
 696         PINMUX_IPSR_PHYS(IP1_27_24,     SDA3,                   I2C_SEL_3_1),
 697
 698         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 699         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 700         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 701         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 702         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 703         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 704
 705         /* IPSR2 */
 706         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 707         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 708         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 709         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 710         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 711         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 712
 713         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 714         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 715         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 716         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 717         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 718         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 719
 720         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 721         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 722         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 723         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 724         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 725         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 726
 727         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 728         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 729         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 730         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 731         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 732         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 733
 734         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 735         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 736         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 737         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 738         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 739         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 740         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 741
 742         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 743         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 744         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 745         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 746         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 747         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 748         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 749
 750         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 751         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 752         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 753         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 754         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 755         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 756         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 757
 758         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 759         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 760         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 761         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 762         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 763         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 764         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 765
 766         /* IPSR3 */
 767         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 768         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 769         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 770         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 771
 772         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 773         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 774         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_B,               SEL_SCIF4_1),
 775         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 776
 777         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 778         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 779         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 780         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 781         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 782         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 783         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 784         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 785         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 786
 787         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 788         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 789         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 790         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 791         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 792         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 793
 794         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 795         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 796         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 797         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 798         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 799         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 800
 801         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 802         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 803         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 804         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 805         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 806         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 807
 808         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 809         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 810         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 811         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 812         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 813         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 814
 815         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 816         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 817         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 818         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 819
 820         /* IPSR4 */
 821         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 822         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 823         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 824         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 825
 826         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 827         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 828         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 829         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 830
 831         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 832         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 833         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 834         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 835
 836         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 837         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 838
 839         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N),
 840         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 841         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 842
 843         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 844         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 845         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 846         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 847         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 848         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 849         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 850         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 851
 852         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 853         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 854         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 855         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 856         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 857         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 858
 859         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 860         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 861         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 862         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 863         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 864         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 865
 866         /* IPSR5 */
 867         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 868         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 869         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 870         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 871         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 872         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 873         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 874
 875         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 876         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 877         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N),
 878         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 879         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 880         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 881         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 882         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 883
 884         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 885         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 886         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 887         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 888
 889         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 890         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 891         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 892         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 893         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 894
 895         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 896         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 897         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 898         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 899         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 900
 901         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 902         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 903         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 904         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 905
 906         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 907         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 908         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 909         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 910
 911         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 912         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 913         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 914         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 915
 916         /* IPSR6 */
 917         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 918         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 919         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 920         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 921
 922         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 923         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 924         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 925         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 926
 927         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 928         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 929         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 930         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 931
 932         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 933         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 934         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 935         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 936         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 937         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 938
 939         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 940         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 941         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 942         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 943         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 944
 945         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 946         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 947         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 948         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 949         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 950         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 951         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 952
 953         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 954         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 955         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 956         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 957         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 958         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_C,               SEL_SCIF4_2),
 959         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 960
 961         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 962         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 963         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 964         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 965         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 966         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 967
 968         /* IPSR7 */
 969         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 970         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 971         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 972         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 973         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 974         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 975
 976         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 977         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 978         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 979         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 980         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 981         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 982         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 983
 984         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 985         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 986         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 987         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 988         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 989         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 990         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 991
 992         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 993         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 994         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 995
 996         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 997         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 998         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 999
1000         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
1001         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
1002         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
1003         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
1004
1005         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
1006         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
1007         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
1008         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
1009
1010         /* IPSR8 */
1011         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
1012         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
1013         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
1014         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1015
1016         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1017         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1018         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1019         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1020
1021         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1022         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1023         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1024
1025         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1026         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1027         PINMUX_IPSR_MSEL(IP8_15_12,     NFCE_N_B,               SEL_NDF_1),
1028         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1029         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1030
1031         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1032         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1033         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1034         PINMUX_IPSR_MSEL(IP8_19_16,     NFWP_N_B,               SEL_NDF_1),
1035         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1036         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1037
1038         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1039         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1040         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1041         PINMUX_IPSR_MSEL(IP8_23_20,     NFDATA14_B,             SEL_NDF_1),
1042         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1043         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1044
1045         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1046         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1047         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1048         PINMUX_IPSR_MSEL(IP8_27_24,     NFDATA15_B,             SEL_NDF_1),
1049         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1050         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1051
1052         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1053         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1054         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1055         PINMUX_IPSR_MSEL(IP8_31_28,     NFRB_N_B,               SEL_NDF_1),
1056         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1057         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1058
1059         /* IPSR9 */
1060         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1061         PINMUX_IPSR_GPSR(IP9_3_0,       NFDATA8),
1062
1063         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_CMD),
1064         PINMUX_IPSR_GPSR(IP9_7_4,       NFDATA9),
1065
1066         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT0),
1067         PINMUX_IPSR_GPSR(IP9_11_8,      NFDATA10),
1068
1069         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT1),
1070         PINMUX_IPSR_GPSR(IP9_15_12,     NFDATA11),
1071
1072         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT2),
1073         PINMUX_IPSR_GPSR(IP9_19_16,     NFDATA12),
1074
1075         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DAT3),
1076         PINMUX_IPSR_GPSR(IP9_23_20,     NFDATA13),
1077
1078         PINMUX_IPSR_GPSR(IP9_27_24,     SD2_DS),
1079         PINMUX_IPSR_GPSR(IP9_27_24,     NFALE),
1080
1081         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_CLK),
1082         PINMUX_IPSR_GPSR(IP9_31_28,     NFWE_N),
1083
1084         /* IPSR10 */
1085         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CMD),
1086         PINMUX_IPSR_GPSR(IP10_3_0,      NFRE_N),
1087
1088         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT0),
1089         PINMUX_IPSR_GPSR(IP10_7_4,      NFDATA0),
1090
1091         PINMUX_IPSR_GPSR(IP10_11_8,     SD3_DAT1),
1092         PINMUX_IPSR_GPSR(IP10_11_8,     NFDATA1),
1093
1094         PINMUX_IPSR_GPSR(IP10_15_12,    SD3_DAT2),
1095         PINMUX_IPSR_GPSR(IP10_15_12,    NFDATA2),
1096
1097         PINMUX_IPSR_GPSR(IP10_19_16,    SD3_DAT3),
1098         PINMUX_IPSR_GPSR(IP10_19_16,    NFDATA3),
1099
1100         PINMUX_IPSR_GPSR(IP10_23_20,    SD3_DAT4),
1101         PINMUX_IPSR_MSEL(IP10_23_20,    SD2_CD_A,               SEL_SDHI2_0),
1102         PINMUX_IPSR_GPSR(IP10_23_20,    NFDATA4),
1103
1104         PINMUX_IPSR_GPSR(IP10_27_24,    SD3_DAT5),
1105         PINMUX_IPSR_MSEL(IP10_27_24,    SD2_WP_A,               SEL_SDHI2_0),
1106         PINMUX_IPSR_GPSR(IP10_27_24,    NFDATA5),
1107
1108         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_DAT6),
1109         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_CD),
1110         PINMUX_IPSR_GPSR(IP10_31_28,    NFDATA6),
1111
1112         /* IPSR11 */
1113         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_DAT7),
1114         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_WP),
1115         PINMUX_IPSR_GPSR(IP11_3_0,      NFDATA7),
1116
1117         PINMUX_IPSR_GPSR(IP11_7_4,      SD3_DS),
1118         PINMUX_IPSR_GPSR(IP11_7_4,      NFCLE),
1119
1120         PINMUX_IPSR_GPSR(IP11_11_8,     SD0_CD),
1121         PINMUX_IPSR_MSEL(IP11_11_8,     NFDATA14_A,             SEL_NDF_0),
1122         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_B,                 SEL_I2C2_1),
1123         PINMUX_IPSR_MSEL(IP11_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1124
1125         PINMUX_IPSR_GPSR(IP11_15_12,    SD0_WP),
1126         PINMUX_IPSR_MSEL(IP11_15_12,    NFDATA15_A,             SEL_NDF_0),
1127         PINMUX_IPSR_MSEL(IP11_15_12,    SDA2_B,                 SEL_I2C2_1),
1128
1129         PINMUX_IPSR_MSEL(IP11_19_16,    SD1_CD,                 I2C_SEL_0_0),
1130         PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A,             I2C_SEL_0_0,    SEL_NDF_0),
1131         PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B,           I2C_SEL_0_0,    SEL_SIMCARD_1),
1132         PINMUX_IPSR_PHYS(IP11_19_16,    SCL0,                   I2C_SEL_0_1),
1133
1134         PINMUX_IPSR_MSEL(IP11_23_20,    SD1_WP,                 I2C_SEL_0_0),
1135         PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A,             I2C_SEL_0_0,    SEL_NDF_0),
1136         PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B,             I2C_SEL_0_0,    SEL_SIMCARD_1),
1137         PINMUX_IPSR_PHYS(IP11_23_20,    SDA0,                   I2C_SEL_0_1),
1138
1139         PINMUX_IPSR_GPSR(IP11_27_24,    SCK0),
1140         PINMUX_IPSR_MSEL(IP11_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1141         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1142         PINMUX_IPSR_MSEL(IP11_27_24,    AUDIO_CLKC_B,           SEL_ADGC_1),
1143         PINMUX_IPSR_MSEL(IP11_27_24,    SDA2_A,                 SEL_I2C2_0),
1144         PINMUX_IPSR_MSEL(IP11_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1145         PINMUX_IPSR_MSEL(IP11_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1146         PINMUX_IPSR_MSEL(IP11_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1147         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS2),
1148         PINMUX_IPSR_MSEL(IP11_27_24,    SCK5_B,                 SEL_SCIF5_1),
1149
1150         PINMUX_IPSR_GPSR(IP11_31_28,    RX0),
1151         PINMUX_IPSR_MSEL(IP11_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1152         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1153         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1154         PINMUX_IPSR_MSEL(IP11_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1155
1156         /* IPSR12 */
1157         PINMUX_IPSR_GPSR(IP12_3_0,      TX0),
1158         PINMUX_IPSR_MSEL(IP12_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1159         PINMUX_IPSR_MSEL(IP12_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1160         PINMUX_IPSR_MSEL(IP12_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1161         PINMUX_IPSR_MSEL(IP12_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1162
1163         PINMUX_IPSR_GPSR(IP12_7_4,      CTS0_N),
1164         PINMUX_IPSR_MSEL(IP12_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1165         PINMUX_IPSR_MSEL(IP12_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1166         PINMUX_IPSR_MSEL(IP12_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1167         PINMUX_IPSR_MSEL(IP12_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1168         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1169         PINMUX_IPSR_GPSR(IP12_7_4,      AUDIO_CLKOUT_C),
1170         PINMUX_IPSR_GPSR(IP12_7_4,      ADICS_SAMP),
1171
1172         PINMUX_IPSR_GPSR(IP12_11_8,     RTS0_N),
1173         PINMUX_IPSR_MSEL(IP12_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1174         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1175         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKA_B,           SEL_ADGA_1),
1176         PINMUX_IPSR_MSEL(IP12_11_8,     SCL2_A,                 SEL_I2C2_0),
1177         PINMUX_IPSR_MSEL(IP12_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1178         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1179         PINMUX_IPSR_GPSR(IP12_11_8,     ADICHS1),
1180
1181         PINMUX_IPSR_MSEL(IP12_15_12,    RX1_A,                  SEL_SCIF1_0),
1182         PINMUX_IPSR_MSEL(IP12_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1183         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1184         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1185         PINMUX_IPSR_MSEL(IP12_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1186
1187         PINMUX_IPSR_MSEL(IP12_19_16,    TX1_A,                  SEL_SCIF1_0),
1188         PINMUX_IPSR_MSEL(IP12_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1189         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1190         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1191         PINMUX_IPSR_MSEL(IP12_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1192
1193         PINMUX_IPSR_GPSR(IP12_23_20,    CTS1_N),
1194         PINMUX_IPSR_MSEL(IP12_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1195         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1196         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1197         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1198         PINMUX_IPSR_MSEL(IP12_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1199         PINMUX_IPSR_GPSR(IP12_23_20,    ADIDATA),
1200
1201         PINMUX_IPSR_GPSR(IP12_27_24,    RTS1_N),
1202         PINMUX_IPSR_MSEL(IP12_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1203         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1204         PINMUX_IPSR_MSEL(IP12_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1205         PINMUX_IPSR_MSEL(IP12_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1206         PINMUX_IPSR_MSEL(IP12_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1207         PINMUX_IPSR_GPSR(IP12_27_24,    ADICHS0),
1208
1209         PINMUX_IPSR_GPSR(IP12_31_28,    SCK2),
1210         PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,             SEL_SCIF_1),
1211         PINMUX_IPSR_MSEL(IP12_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1212         PINMUX_IPSR_MSEL(IP12_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1213         PINMUX_IPSR_MSEL(IP12_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1214         PINMUX_IPSR_MSEL(IP12_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1215         PINMUX_IPSR_GPSR(IP12_31_28,    ADICLK),
1216
1217         /* IPSR13 */
1218         PINMUX_IPSR_MSEL(IP13_3_0,      TX2_A,                  SEL_SCIF2_0),
1219         PINMUX_IPSR_MSEL(IP13_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1220         PINMUX_IPSR_MSEL(IP13_3_0,      SCL1_A,                 SEL_I2C1_0),
1221         PINMUX_IPSR_MSEL(IP13_3_0,      FMCLK_A,                SEL_FM_0),
1222         PINMUX_IPSR_MSEL(IP13_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1223         PINMUX_IPSR_GPSR(IP13_3_0,      FSO_CFE_0_N),
1224
1225         PINMUX_IPSR_MSEL(IP13_7_4,      RX2_A,                  SEL_SCIF2_0),
1226         PINMUX_IPSR_MSEL(IP13_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1227         PINMUX_IPSR_MSEL(IP13_7_4,      SDA1_A,                 SEL_I2C1_0),
1228         PINMUX_IPSR_MSEL(IP13_7_4,      FMIN_A,                 SEL_FM_0),
1229         PINMUX_IPSR_MSEL(IP13_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1230         PINMUX_IPSR_GPSR(IP13_7_4,      FSO_CFE_1_N),
1231
1232         PINMUX_IPSR_GPSR(IP13_11_8,     HSCK0),
1233         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1234         PINMUX_IPSR_MSEL(IP13_11_8,     AUDIO_CLKB_A,           SEL_ADGB_0),
1235         PINMUX_IPSR_MSEL(IP13_11_8,     SSI_SDATA1_B,           SEL_SSI1_1),
1236         PINMUX_IPSR_MSEL(IP13_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1237         PINMUX_IPSR_MSEL(IP13_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1238         PINMUX_IPSR_MSEL(IP13_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1239         PINMUX_IPSR_MSEL(IP13_11_8,     RX5_B,                  SEL_SCIF5_1),
1240
1241         PINMUX_IPSR_GPSR(IP13_15_12,    HRX0),
1242         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1243         PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,           SEL_SSI2_1),
1244         PINMUX_IPSR_MSEL(IP13_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1245         PINMUX_IPSR_MSEL(IP13_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1246         PINMUX_IPSR_MSEL(IP13_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1247
1248         PINMUX_IPSR_GPSR(IP13_19_16,    HTX0),
1249         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1250         PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,           SEL_SSI9_1),
1251         PINMUX_IPSR_MSEL(IP13_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1252         PINMUX_IPSR_MSEL(IP13_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1253         PINMUX_IPSR_MSEL(IP13_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1254
1255         PINMUX_IPSR_GPSR(IP13_23_20,    HCTS0_N),
1256         PINMUX_IPSR_MSEL(IP13_23_20,    RX2_B,                  SEL_SCIF2_1),
1257         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1258         PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,             SEL_SSI9_0),
1259         PINMUX_IPSR_MSEL(IP13_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1260         PINMUX_IPSR_MSEL(IP13_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1261         PINMUX_IPSR_MSEL(IP13_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1262         PINMUX_IPSR_GPSR(IP13_23_20,    AUDIO_CLKOUT1_A),
1263
1264         PINMUX_IPSR_GPSR(IP13_27_24,    HRTS0_N),
1265         PINMUX_IPSR_MSEL(IP13_27_24,    TX2_B,                  SEL_SCIF2_1),
1266         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1267         PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,              SEL_SSI9_0),
1268         PINMUX_IPSR_MSEL(IP13_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1269         PINMUX_IPSR_MSEL(IP13_27_24,    BPFCLK_A,               SEL_FM_0),
1270         PINMUX_IPSR_GPSR(IP13_27_24,    AUDIO_CLKOUT2_A),
1271
1272         PINMUX_IPSR_GPSR(IP13_31_28,    MSIOF0_SYNC),
1273         PINMUX_IPSR_GPSR(IP13_31_28,    AUDIO_CLKOUT_A),
1274         PINMUX_IPSR_MSEL(IP13_31_28,    TX5_B,                  SEL_SCIF5_1),
1275         PINMUX_IPSR_MSEL(IP13_31_28,    BPFCLK_D,               SEL_FM_3),
1276
1277         /* IPSR14 */
1278         PINMUX_IPSR_GPSR(IP14_3_0,      MSIOF0_SS1),
1279         PINMUX_IPSR_MSEL(IP14_3_0,      RX5_A,                  SEL_SCIF5_0),
1280         PINMUX_IPSR_MSEL(IP14_3_0,      NFWP_N_A,               SEL_NDF_0),
1281         PINMUX_IPSR_MSEL(IP14_3_0,      AUDIO_CLKA_C,           SEL_ADGA_2),
1282         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SCK2_A,             SEL_SSI2_0),
1283         PINMUX_IPSR_MSEL(IP14_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1284         PINMUX_IPSR_GPSR(IP14_3_0,      AUDIO_CLKOUT3_A),
1285         PINMUX_IPSR_MSEL(IP14_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
1286
1287         PINMUX_IPSR_GPSR(IP14_7_4,      MSIOF0_SS2),
1288         PINMUX_IPSR_MSEL(IP14_7_4,      TX5_A,                  SEL_SCIF5_0),
1289         PINMUX_IPSR_MSEL(IP14_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1290         PINMUX_IPSR_MSEL(IP14_7_4,      AUDIO_CLKC_A,           SEL_ADGC_0),
1291         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_WS2_A,              SEL_SSI2_0),
1292         PINMUX_IPSR_MSEL(IP14_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1293         PINMUX_IPSR_GPSR(IP14_7_4,      AUDIO_CLKOUT_D),
1294         PINMUX_IPSR_MSEL(IP14_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1295
1296         PINMUX_IPSR_GPSR(IP14_11_8,     MLB_CLK),
1297         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1298         PINMUX_IPSR_MSEL(IP14_11_8,     SCL1_B,                 SEL_I2C1_1),
1299
1300         PINMUX_IPSR_GPSR(IP14_15_12,    MLB_SIG),
1301         PINMUX_IPSR_MSEL(IP14_15_12,    RX1_B,                  SEL_SCIF1_1),
1302         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1303         PINMUX_IPSR_MSEL(IP14_15_12,    SDA1_B,                 SEL_I2C1_1),
1304
1305         PINMUX_IPSR_GPSR(IP14_19_16,    MLB_DAT),
1306         PINMUX_IPSR_MSEL(IP14_19_16,    TX1_B,                  SEL_SCIF1_1),
1307         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1308
1309         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK01239),
1310         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1311
1312         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS01239),
1313         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1314
1315         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA0),
1316         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1317
1318         /* IPSR15 */
1319         PINMUX_IPSR_MSEL(IP15_3_0,      SSI_SDATA1_A,           SEL_SSI1_0),
1320
1321         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SDATA2_A,           SEL_SSI2_0),
1322         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SCK1_B,             SEL_SSI1_1),
1323
1324         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SCK349),
1325         PINMUX_IPSR_MSEL(IP15_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1326         PINMUX_IPSR_MSEL(IP15_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1327
1328         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_WS349),
1329         PINMUX_IPSR_MSEL(IP15_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1330         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1331         PINMUX_IPSR_MSEL(IP15_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1332
1333         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_SDATA3),
1334         PINMUX_IPSR_MSEL(IP15_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1335         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1336         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1337         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1338         PINMUX_IPSR_MSEL(IP15_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1339         PINMUX_IPSR_MSEL(IP15_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1340
1341         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SCK4),
1342         PINMUX_IPSR_MSEL(IP15_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1343         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1344         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1345         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1346         PINMUX_IPSR_MSEL(IP15_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1347         PINMUX_IPSR_MSEL(IP15_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1348
1349         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_WS4),
1350         PINMUX_IPSR_MSEL(IP15_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1351         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1352         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1353         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1354         PINMUX_IPSR_MSEL(IP15_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1355         PINMUX_IPSR_MSEL(IP15_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1356
1357         PINMUX_IPSR_GPSR(IP15_31_28,    SSI_SDATA4),
1358         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1359         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1360         PINMUX_IPSR_MSEL(IP15_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1361         PINMUX_IPSR_MSEL(IP15_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1362         PINMUX_IPSR_MSEL(IP15_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1363         PINMUX_IPSR_MSEL(IP15_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1364
1365         /* IPSR16 */
1366         PINMUX_IPSR_GPSR(IP16_3_0,      SSI_SCK6),
1367         PINMUX_IPSR_MSEL(IP16_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1368
1369         PINMUX_IPSR_GPSR(IP16_7_4,      SSI_WS6),
1370         PINMUX_IPSR_MSEL(IP16_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1371
1372         PINMUX_IPSR_GPSR(IP16_11_8,     SSI_SDATA6),
1373         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1374
1375         PINMUX_IPSR_GPSR(IP16_15_12,    SSI_SCK78),
1376         PINMUX_IPSR_MSEL(IP16_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1377         PINMUX_IPSR_MSEL(IP16_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1378         PINMUX_IPSR_MSEL(IP16_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1379         PINMUX_IPSR_MSEL(IP16_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1380         PINMUX_IPSR_MSEL(IP16_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1381         PINMUX_IPSR_MSEL(IP16_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1382
1383         PINMUX_IPSR_GPSR(IP16_19_16,    SSI_WS78),
1384         PINMUX_IPSR_MSEL(IP16_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1385         PINMUX_IPSR_MSEL(IP16_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1386         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1387         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1388         PINMUX_IPSR_MSEL(IP16_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1389         PINMUX_IPSR_MSEL(IP16_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1390
1391         PINMUX_IPSR_GPSR(IP16_23_20,    SSI_SDATA7),
1392         PINMUX_IPSR_MSEL(IP16_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1393         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1394         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1395         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1396         PINMUX_IPSR_MSEL(IP16_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1397         PINMUX_IPSR_MSEL(IP16_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1398         PINMUX_IPSR_MSEL(IP16_23_20,    TCLK2_A,                SEL_TIMER_TMU2_0),
1399
1400         PINMUX_IPSR_GPSR(IP16_27_24,    SSI_SDATA8),
1401         PINMUX_IPSR_MSEL(IP16_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1402         PINMUX_IPSR_MSEL(IP16_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1403         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1404         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1405         PINMUX_IPSR_MSEL(IP16_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1406         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1407
1408         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,           SEL_SSI9_0),
1409         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1410         PINMUX_IPSR_MSEL(IP16_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1411         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1412         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,              SEL_SSI1_1),
1413         PINMUX_IPSR_GPSR(IP16_31_28,    SCK1),
1414         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1415         PINMUX_IPSR_MSEL(IP16_31_28,    SCK5_A,                 SEL_SCIF5_0),
1416
1417         /* IPSR17 */
1418         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKA_A,           SEL_ADGA_0),
1419
1420         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKB_B,           SEL_ADGB_1),
1421         PINMUX_IPSR_MSEL(IP17_7_4,      SCIF_CLK_A,             SEL_SCIF_0),
1422         PINMUX_IPSR_MSEL(IP17_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1423         PINMUX_IPSR_MSEL(IP17_7_4,      REMOCON_A,              SEL_REMOCON_0),
1424         PINMUX_IPSR_MSEL(IP17_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
1425
1426         PINMUX_IPSR_GPSR(IP17_11_8,     USB0_PWEN),
1427         PINMUX_IPSR_MSEL(IP17_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1428         PINMUX_IPSR_MSEL(IP17_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1429         PINMUX_IPSR_MSEL(IP17_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1430         PINMUX_IPSR_MSEL(IP17_11_8,     BPFCLK_B,               SEL_FM_1),
1431         PINMUX_IPSR_MSEL(IP17_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1432         PINMUX_IPSR_MSEL(IP17_11_8,     HSCK2_C,                SEL_HSCIF2_2),
1433
1434         PINMUX_IPSR_GPSR(IP17_15_12,    USB0_OVC),
1435         PINMUX_IPSR_MSEL(IP17_15_12,    SIM0_D_C,               SEL_SIMCARD_2),
1436         PINMUX_IPSR_MSEL(IP17_15_12,    TS_SDAT1_D,             SEL_TSIF1_3),
1437         PINMUX_IPSR_MSEL(IP17_15_12,    STP_ISD_1_D,            SEL_SSP1_1_3),
1438         PINMUX_IPSR_MSEL(IP17_15_12,    RIF3_SYNC_B,            SEL_DRIF3_1),
1439         PINMUX_IPSR_MSEL(IP17_15_12,    HRX2_C,                 SEL_HSCIF2_2),
1440
1441         PINMUX_IPSR_GPSR(IP17_19_16,    USB1_PWEN),
1442         PINMUX_IPSR_MSEL(IP17_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1443         PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,             SEL_SSI1_0),
1444         PINMUX_IPSR_MSEL(IP17_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1445         PINMUX_IPSR_MSEL(IP17_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1446         PINMUX_IPSR_MSEL(IP17_19_16,    FMCLK_B,                SEL_FM_1),
1447         PINMUX_IPSR_MSEL(IP17_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1448         PINMUX_IPSR_MSEL(IP17_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1449         PINMUX_IPSR_MSEL(IP17_19_16,    HTX2_C,                 SEL_HSCIF2_2),
1450
1451         PINMUX_IPSR_GPSR(IP17_23_20,    USB1_OVC),
1452         PINMUX_IPSR_MSEL(IP17_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1453         PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,              SEL_SSI1_0),
1454         PINMUX_IPSR_MSEL(IP17_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1455         PINMUX_IPSR_MSEL(IP17_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1456         PINMUX_IPSR_MSEL(IP17_23_20,    FMIN_B,                 SEL_FM_1),
1457         PINMUX_IPSR_MSEL(IP17_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1458         PINMUX_IPSR_MSEL(IP17_23_20,    REMOCON_B,              SEL_REMOCON_1),
1459         PINMUX_IPSR_MSEL(IP17_23_20,    HCTS2_N_C,              SEL_HSCIF2_2),
1460
1461         PINMUX_IPSR_GPSR(IP17_27_24,    USB30_PWEN),
1462         PINMUX_IPSR_GPSR(IP17_27_24,    AUDIO_CLKOUT_B),
1463         PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,             SEL_SSI2_1),
1464         PINMUX_IPSR_MSEL(IP17_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1465         PINMUX_IPSR_MSEL(IP17_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1466         PINMUX_IPSR_MSEL(IP17_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1467         PINMUX_IPSR_MSEL(IP17_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1468         PINMUX_IPSR_MSEL(IP17_27_24,    TCLK2_B,                SEL_TIMER_TMU2_1),
1469         PINMUX_IPSR_GPSR(IP17_27_24,    TPU0TO0),
1470         PINMUX_IPSR_MSEL(IP17_27_24,    BPFCLK_C,               SEL_FM_2),
1471         PINMUX_IPSR_MSEL(IP17_27_24,    HRTS2_N_C,              SEL_HSCIF2_2),
1472
1473         PINMUX_IPSR_GPSR(IP17_31_28,    USB30_OVC),
1474         PINMUX_IPSR_GPSR(IP17_31_28,    AUDIO_CLKOUT1_B),
1475         PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,              SEL_SSI2_1),
1476         PINMUX_IPSR_MSEL(IP17_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1477         PINMUX_IPSR_MSEL(IP17_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1478         PINMUX_IPSR_MSEL(IP17_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1479         PINMUX_IPSR_MSEL(IP17_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1480         PINMUX_IPSR_GPSR(IP17_31_28,    FSO_TOE_N),
1481         PINMUX_IPSR_GPSR(IP17_31_28,    TPU0TO1),
1482
1483         /* IPSR18 */
1484         PINMUX_IPSR_GPSR(IP18_3_0,      GP6_30),
1485         PINMUX_IPSR_GPSR(IP18_3_0,      AUDIO_CLKOUT2_B),
1486         PINMUX_IPSR_MSEL(IP18_3_0,      SSI_SCK9_B,             SEL_SSI9_1),
1487         PINMUX_IPSR_MSEL(IP18_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1488         PINMUX_IPSR_MSEL(IP18_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1489         PINMUX_IPSR_MSEL(IP18_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1490         PINMUX_IPSR_GPSR(IP18_3_0,      TPU0TO2),
1491         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_C,                SEL_FM_2),
1492         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_D,                SEL_FM_3),
1493
1494         PINMUX_IPSR_GPSR(IP18_7_4,      GP6_31),
1495         PINMUX_IPSR_GPSR(IP18_7_4,      AUDIO_CLKOUT3_B),
1496         PINMUX_IPSR_MSEL(IP18_7_4,      SSI_WS9_B,              SEL_SSI9_1),
1497         PINMUX_IPSR_MSEL(IP18_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1498         PINMUX_IPSR_MSEL(IP18_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1499         PINMUX_IPSR_MSEL(IP18_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1500         PINMUX_IPSR_GPSR(IP18_7_4,      TPU0TO3),
1501         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_C,                 SEL_FM_2),
1502         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_D,                 SEL_FM_3),
1503
1504 /*
1505  * Static pins can not be muxed between different functions but
1506  * still need mark entries in the pinmux list. Add each static
1507  * pin to the list without an associated function. The sh-pfc
1508  * core will do the right thing and skip trying to mux the pin
1509  * while still applying configuration to it.
1510  */
1511 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1512         PINMUX_STATIC
1513 #undef FM
1514 };
1515
1516 /*
1517  * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1518  * Physical layout rows: A - AW, cols: 1 - 39.
1519  */
1520 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1521 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1522 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1523 #define PIN_NONE U16_MAX
1524
1525 static const struct sh_pfc_pin pinmux_pins[] = {
1526         PINMUX_GPIO_GP_ALL(),
1527
1528         /*
1529          * Pins not associated with a GPIO port.
1530          *
1531          * The pin positions are different between different r8a7796
1532          * packages, all that is needed for the pfc driver is a unique
1533          * number for each pin. To this end use the pin layout from
1534          * R-Car M3SiP to calculate a unique number for each pin.
1535          */
1536         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1537         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1538         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1539         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1540         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1541         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1542         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1543         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1544         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1545         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1546         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1547         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1548         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1549         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1550         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1551         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1552         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1553         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1554         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1555         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1556         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1557         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1558         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1559         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1560         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1561         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1562         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1563         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1564         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1565         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1566         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1567         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1568         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1569         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1570         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1571         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN2, CFG_FLAGS),
1572         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1573         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1575         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1576         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1577         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1578 };
1579
1580 /* - AUDIO CLOCK ------------------------------------------------------------ */
1581 static const unsigned int audio_clk_a_a_pins[] = {
1582         /* CLK A */
1583         RCAR_GP_PIN(6, 22),
1584 };
1585 static const unsigned int audio_clk_a_a_mux[] = {
1586         AUDIO_CLKA_A_MARK,
1587 };
1588 static const unsigned int audio_clk_a_b_pins[] = {
1589         /* CLK A */
1590         RCAR_GP_PIN(5, 4),
1591 };
1592 static const unsigned int audio_clk_a_b_mux[] = {
1593         AUDIO_CLKA_B_MARK,
1594 };
1595 static const unsigned int audio_clk_a_c_pins[] = {
1596         /* CLK A */
1597         RCAR_GP_PIN(5, 19),
1598 };
1599 static const unsigned int audio_clk_a_c_mux[] = {
1600         AUDIO_CLKA_C_MARK,
1601 };
1602 static const unsigned int audio_clk_b_a_pins[] = {
1603         /* CLK B */
1604         RCAR_GP_PIN(5, 12),
1605 };
1606 static const unsigned int audio_clk_b_a_mux[] = {
1607         AUDIO_CLKB_A_MARK,
1608 };
1609 static const unsigned int audio_clk_b_b_pins[] = {
1610         /* CLK B */
1611         RCAR_GP_PIN(6, 23),
1612 };
1613 static const unsigned int audio_clk_b_b_mux[] = {
1614         AUDIO_CLKB_B_MARK,
1615 };
1616 static const unsigned int audio_clk_c_a_pins[] = {
1617         /* CLK C */
1618         RCAR_GP_PIN(5, 21),
1619 };
1620 static const unsigned int audio_clk_c_a_mux[] = {
1621         AUDIO_CLKC_A_MARK,
1622 };
1623 static const unsigned int audio_clk_c_b_pins[] = {
1624         /* CLK C */
1625         RCAR_GP_PIN(5, 0),
1626 };
1627 static const unsigned int audio_clk_c_b_mux[] = {
1628         AUDIO_CLKC_B_MARK,
1629 };
1630 static const unsigned int audio_clkout_a_pins[] = {
1631         /* CLKOUT */
1632         RCAR_GP_PIN(5, 18),
1633 };
1634 static const unsigned int audio_clkout_a_mux[] = {
1635         AUDIO_CLKOUT_A_MARK,
1636 };
1637 static const unsigned int audio_clkout_b_pins[] = {
1638         /* CLKOUT */
1639         RCAR_GP_PIN(6, 28),
1640 };
1641 static const unsigned int audio_clkout_b_mux[] = {
1642         AUDIO_CLKOUT_B_MARK,
1643 };
1644 static const unsigned int audio_clkout_c_pins[] = {
1645         /* CLKOUT */
1646         RCAR_GP_PIN(5, 3),
1647 };
1648 static const unsigned int audio_clkout_c_mux[] = {
1649         AUDIO_CLKOUT_C_MARK,
1650 };
1651 static const unsigned int audio_clkout_d_pins[] = {
1652         /* CLKOUT */
1653         RCAR_GP_PIN(5, 21),
1654 };
1655 static const unsigned int audio_clkout_d_mux[] = {
1656         AUDIO_CLKOUT_D_MARK,
1657 };
1658 static const unsigned int audio_clkout1_a_pins[] = {
1659         /* CLKOUT1 */
1660         RCAR_GP_PIN(5, 15),
1661 };
1662 static const unsigned int audio_clkout1_a_mux[] = {
1663         AUDIO_CLKOUT1_A_MARK,
1664 };
1665 static const unsigned int audio_clkout1_b_pins[] = {
1666         /* CLKOUT1 */
1667         RCAR_GP_PIN(6, 29),
1668 };
1669 static const unsigned int audio_clkout1_b_mux[] = {
1670         AUDIO_CLKOUT1_B_MARK,
1671 };
1672 static const unsigned int audio_clkout2_a_pins[] = {
1673         /* CLKOUT2 */
1674         RCAR_GP_PIN(5, 16),
1675 };
1676 static const unsigned int audio_clkout2_a_mux[] = {
1677         AUDIO_CLKOUT2_A_MARK,
1678 };
1679 static const unsigned int audio_clkout2_b_pins[] = {
1680         /* CLKOUT2 */
1681         RCAR_GP_PIN(6, 30),
1682 };
1683 static const unsigned int audio_clkout2_b_mux[] = {
1684         AUDIO_CLKOUT2_B_MARK,
1685 };
1686
1687 static const unsigned int audio_clkout3_a_pins[] = {
1688         /* CLKOUT3 */
1689         RCAR_GP_PIN(5, 19),
1690 };
1691 static const unsigned int audio_clkout3_a_mux[] = {
1692         AUDIO_CLKOUT3_A_MARK,
1693 };
1694 static const unsigned int audio_clkout3_b_pins[] = {
1695         /* CLKOUT3 */
1696         RCAR_GP_PIN(6, 31),
1697 };
1698 static const unsigned int audio_clkout3_b_mux[] = {
1699         AUDIO_CLKOUT3_B_MARK,
1700 };
1701
1702 /* - EtherAVB --------------------------------------------------------------- */
1703 static const unsigned int avb_link_pins[] = {
1704         /* AVB_LINK */
1705         RCAR_GP_PIN(2, 12),
1706 };
1707 static const unsigned int avb_link_mux[] = {
1708         AVB_LINK_MARK,
1709 };
1710 static const unsigned int avb_magic_pins[] = {
1711         /* AVB_MAGIC_ */
1712         RCAR_GP_PIN(2, 10),
1713 };
1714 static const unsigned int avb_magic_mux[] = {
1715         AVB_MAGIC_MARK,
1716 };
1717 static const unsigned int avb_phy_int_pins[] = {
1718         /* AVB_PHY_INT */
1719         RCAR_GP_PIN(2, 11),
1720 };
1721 static const unsigned int avb_phy_int_mux[] = {
1722         AVB_PHY_INT_MARK,
1723 };
1724 static const unsigned int avb_mdio_pins[] = {
1725         /* AVB_MDC, AVB_MDIO */
1726         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1727 };
1728 static const unsigned int avb_mdio_mux[] = {
1729         AVB_MDC_MARK, AVB_MDIO_MARK,
1730 };
1731 static const unsigned int avb_mii_pins[] = {
1732         /*
1733          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1734          * AVB_TD1, AVB_TD2, AVB_TD3,
1735          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1736          * AVB_RD1, AVB_RD2, AVB_RD3,
1737          * AVB_TXCREFCLK
1738          */
1739         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1740         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1741         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1742         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1743         PIN_NUMBER('A', 12),
1744
1745 };
1746 static const unsigned int avb_mii_mux[] = {
1747         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1748         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1749         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1750         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1751         AVB_TXCREFCLK_MARK,
1752 };
1753 static const unsigned int avb_avtp_pps_pins[] = {
1754         /* AVB_AVTP_PPS */
1755         RCAR_GP_PIN(2, 6),
1756 };
1757 static const unsigned int avb_avtp_pps_mux[] = {
1758         AVB_AVTP_PPS_MARK,
1759 };
1760 static const unsigned int avb_avtp_match_a_pins[] = {
1761         /* AVB_AVTP_MATCH_A */
1762         RCAR_GP_PIN(2, 13),
1763 };
1764 static const unsigned int avb_avtp_match_a_mux[] = {
1765         AVB_AVTP_MATCH_A_MARK,
1766 };
1767 static const unsigned int avb_avtp_capture_a_pins[] = {
1768         /* AVB_AVTP_CAPTURE_A */
1769         RCAR_GP_PIN(2, 14),
1770 };
1771 static const unsigned int avb_avtp_capture_a_mux[] = {
1772         AVB_AVTP_CAPTURE_A_MARK,
1773 };
1774 static const unsigned int avb_avtp_match_b_pins[] = {
1775         /*  AVB_AVTP_MATCH_B */
1776         RCAR_GP_PIN(1, 8),
1777 };
1778 static const unsigned int avb_avtp_match_b_mux[] = {
1779         AVB_AVTP_MATCH_B_MARK,
1780 };
1781 static const unsigned int avb_avtp_capture_b_pins[] = {
1782         /* AVB_AVTP_CAPTURE_B */
1783         RCAR_GP_PIN(1, 11),
1784 };
1785 static const unsigned int avb_avtp_capture_b_mux[] = {
1786         AVB_AVTP_CAPTURE_B_MARK,
1787 };
1788
1789 /* - CAN ------------------------------------------------------------------ */
1790 static const unsigned int can0_data_a_pins[] = {
1791         /* TX, RX */
1792         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1793 };
1794 static const unsigned int can0_data_a_mux[] = {
1795         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1796 };
1797 static const unsigned int can0_data_b_pins[] = {
1798         /* TX, RX */
1799         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1800 };
1801 static const unsigned int can0_data_b_mux[] = {
1802         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1803 };
1804 static const unsigned int can1_data_pins[] = {
1805         /* TX, RX */
1806         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1807 };
1808 static const unsigned int can1_data_mux[] = {
1809         CAN1_TX_MARK,           CAN1_RX_MARK,
1810 };
1811
1812 /* - CAN Clock -------------------------------------------------------------- */
1813 static const unsigned int can_clk_pins[] = {
1814         /* CLK */
1815         RCAR_GP_PIN(1, 25),
1816 };
1817 static const unsigned int can_clk_mux[] = {
1818         CAN_CLK_MARK,
1819 };
1820
1821 /* - CAN FD --------------------------------------------------------------- */
1822 static const unsigned int canfd0_data_a_pins[] = {
1823         /* TX, RX */
1824         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1825 };
1826 static const unsigned int canfd0_data_a_mux[] = {
1827         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1828 };
1829 static const unsigned int canfd0_data_b_pins[] = {
1830         /* TX, RX */
1831         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1832 };
1833 static const unsigned int canfd0_data_b_mux[] = {
1834         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1835 };
1836 static const unsigned int canfd1_data_pins[] = {
1837         /* TX, RX */
1838         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1839 };
1840 static const unsigned int canfd1_data_mux[] = {
1841         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1842 };
1843
1844 #if defined(CONFIG_PINCTRL_PFC_R8A7796)
1845 /* - DRIF0 --------------------------------------------------------------- */
1846 static const unsigned int drif0_ctrl_a_pins[] = {
1847         /* CLK, SYNC */
1848         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1849 };
1850 static const unsigned int drif0_ctrl_a_mux[] = {
1851         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1852 };
1853 static const unsigned int drif0_data0_a_pins[] = {
1854         /* D0 */
1855         RCAR_GP_PIN(6, 10),
1856 };
1857 static const unsigned int drif0_data0_a_mux[] = {
1858         RIF0_D0_A_MARK,
1859 };
1860 static const unsigned int drif0_data1_a_pins[] = {
1861         /* D1 */
1862         RCAR_GP_PIN(6, 7),
1863 };
1864 static const unsigned int drif0_data1_a_mux[] = {
1865         RIF0_D1_A_MARK,
1866 };
1867 static const unsigned int drif0_ctrl_b_pins[] = {
1868         /* CLK, SYNC */
1869         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1870 };
1871 static const unsigned int drif0_ctrl_b_mux[] = {
1872         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1873 };
1874 static const unsigned int drif0_data0_b_pins[] = {
1875         /* D0 */
1876         RCAR_GP_PIN(5, 1),
1877 };
1878 static const unsigned int drif0_data0_b_mux[] = {
1879         RIF0_D0_B_MARK,
1880 };
1881 static const unsigned int drif0_data1_b_pins[] = {
1882         /* D1 */
1883         RCAR_GP_PIN(5, 2),
1884 };
1885 static const unsigned int drif0_data1_b_mux[] = {
1886         RIF0_D1_B_MARK,
1887 };
1888 static const unsigned int drif0_ctrl_c_pins[] = {
1889         /* CLK, SYNC */
1890         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1891 };
1892 static const unsigned int drif0_ctrl_c_mux[] = {
1893         RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1894 };
1895 static const unsigned int drif0_data0_c_pins[] = {
1896         /* D0 */
1897         RCAR_GP_PIN(5, 13),
1898 };
1899 static const unsigned int drif0_data0_c_mux[] = {
1900         RIF0_D0_C_MARK,
1901 };
1902 static const unsigned int drif0_data1_c_pins[] = {
1903         /* D1 */
1904         RCAR_GP_PIN(5, 14),
1905 };
1906 static const unsigned int drif0_data1_c_mux[] = {
1907         RIF0_D1_C_MARK,
1908 };
1909 /* - DRIF1 --------------------------------------------------------------- */
1910 static const unsigned int drif1_ctrl_a_pins[] = {
1911         /* CLK, SYNC */
1912         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1913 };
1914 static const unsigned int drif1_ctrl_a_mux[] = {
1915         RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1916 };
1917 static const unsigned int drif1_data0_a_pins[] = {
1918         /* D0 */
1919         RCAR_GP_PIN(6, 19),
1920 };
1921 static const unsigned int drif1_data0_a_mux[] = {
1922         RIF1_D0_A_MARK,
1923 };
1924 static const unsigned int drif1_data1_a_pins[] = {
1925         /* D1 */
1926         RCAR_GP_PIN(6, 20),
1927 };
1928 static const unsigned int drif1_data1_a_mux[] = {
1929         RIF1_D1_A_MARK,
1930 };
1931 static const unsigned int drif1_ctrl_b_pins[] = {
1932         /* CLK, SYNC */
1933         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1934 };
1935 static const unsigned int drif1_ctrl_b_mux[] = {
1936         RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1937 };
1938 static const unsigned int drif1_data0_b_pins[] = {
1939         /* D0 */
1940         RCAR_GP_PIN(5, 7),
1941 };
1942 static const unsigned int drif1_data0_b_mux[] = {
1943         RIF1_D0_B_MARK,
1944 };
1945 static const unsigned int drif1_data1_b_pins[] = {
1946         /* D1 */
1947         RCAR_GP_PIN(5, 8),
1948 };
1949 static const unsigned int drif1_data1_b_mux[] = {
1950         RIF1_D1_B_MARK,
1951 };
1952 static const unsigned int drif1_ctrl_c_pins[] = {
1953         /* CLK, SYNC */
1954         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1955 };
1956 static const unsigned int drif1_ctrl_c_mux[] = {
1957         RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1958 };
1959 static const unsigned int drif1_data0_c_pins[] = {
1960         /* D0 */
1961         RCAR_GP_PIN(5, 6),
1962 };
1963 static const unsigned int drif1_data0_c_mux[] = {
1964         RIF1_D0_C_MARK,
1965 };
1966 static const unsigned int drif1_data1_c_pins[] = {
1967         /* D1 */
1968         RCAR_GP_PIN(5, 10),
1969 };
1970 static const unsigned int drif1_data1_c_mux[] = {
1971         RIF1_D1_C_MARK,
1972 };
1973 /* - DRIF2 --------------------------------------------------------------- */
1974 static const unsigned int drif2_ctrl_a_pins[] = {
1975         /* CLK, SYNC */
1976         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1977 };
1978 static const unsigned int drif2_ctrl_a_mux[] = {
1979         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1980 };
1981 static const unsigned int drif2_data0_a_pins[] = {
1982         /* D0 */
1983         RCAR_GP_PIN(6, 7),
1984 };
1985 static const unsigned int drif2_data0_a_mux[] = {
1986         RIF2_D0_A_MARK,
1987 };
1988 static const unsigned int drif2_data1_a_pins[] = {
1989         /* D1 */
1990         RCAR_GP_PIN(6, 10),
1991 };
1992 static const unsigned int drif2_data1_a_mux[] = {
1993         RIF2_D1_A_MARK,
1994 };
1995 static const unsigned int drif2_ctrl_b_pins[] = {
1996         /* CLK, SYNC */
1997         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1998 };
1999 static const unsigned int drif2_ctrl_b_mux[] = {
2000         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
2001 };
2002 static const unsigned int drif2_data0_b_pins[] = {
2003         /* D0 */
2004         RCAR_GP_PIN(6, 30),
2005 };
2006 static const unsigned int drif2_data0_b_mux[] = {
2007         RIF2_D0_B_MARK,
2008 };
2009 static const unsigned int drif2_data1_b_pins[] = {
2010         /* D1 */
2011         RCAR_GP_PIN(6, 31),
2012 };
2013 static const unsigned int drif2_data1_b_mux[] = {
2014         RIF2_D1_B_MARK,
2015 };
2016 /* - DRIF3 --------------------------------------------------------------- */
2017 static const unsigned int drif3_ctrl_a_pins[] = {
2018         /* CLK, SYNC */
2019         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2020 };
2021 static const unsigned int drif3_ctrl_a_mux[] = {
2022         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2023 };
2024 static const unsigned int drif3_data0_a_pins[] = {
2025         /* D0 */
2026         RCAR_GP_PIN(6, 19),
2027 };
2028 static const unsigned int drif3_data0_a_mux[] = {
2029         RIF3_D0_A_MARK,
2030 };
2031 static const unsigned int drif3_data1_a_pins[] = {
2032         /* D1 */
2033         RCAR_GP_PIN(6, 20),
2034 };
2035 static const unsigned int drif3_data1_a_mux[] = {
2036         RIF3_D1_A_MARK,
2037 };
2038 static const unsigned int drif3_ctrl_b_pins[] = {
2039         /* CLK, SYNC */
2040         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2041 };
2042 static const unsigned int drif3_ctrl_b_mux[] = {
2043         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2044 };
2045 static const unsigned int drif3_data0_b_pins[] = {
2046         /* D0 */
2047         RCAR_GP_PIN(6, 28),
2048 };
2049 static const unsigned int drif3_data0_b_mux[] = {
2050         RIF3_D0_B_MARK,
2051 };
2052 static const unsigned int drif3_data1_b_pins[] = {
2053         /* D1 */
2054         RCAR_GP_PIN(6, 29),
2055 };
2056 static const unsigned int drif3_data1_b_mux[] = {
2057         RIF3_D1_B_MARK,
2058 };
2059 #endif /* CONFIG_PINCTRL_PFC_R8A7796 */
2060
2061 /* - DU --------------------------------------------------------------------- */
2062 static const unsigned int du_rgb666_pins[] = {
2063         /* R[7:2], G[7:2], B[7:2] */
2064         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2065         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2066         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2067         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2068         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2069         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2070 };
2071 static const unsigned int du_rgb666_mux[] = {
2072         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2073         DU_DR3_MARK, DU_DR2_MARK,
2074         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2075         DU_DG3_MARK, DU_DG2_MARK,
2076         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2077         DU_DB3_MARK, DU_DB2_MARK,
2078 };
2079 static const unsigned int du_rgb888_pins[] = {
2080         /* R[7:0], G[7:0], B[7:0] */
2081         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2082         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2083         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2084         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2085         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2086         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2087         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2088         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2089         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2090 };
2091 static const unsigned int du_rgb888_mux[] = {
2092         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2093         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2094         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2095         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2096         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2097         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2098 };
2099 static const unsigned int du_clk_out_0_pins[] = {
2100         /* CLKOUT */
2101         RCAR_GP_PIN(1, 27),
2102 };
2103 static const unsigned int du_clk_out_0_mux[] = {
2104         DU_DOTCLKOUT0_MARK
2105 };
2106 static const unsigned int du_clk_out_1_pins[] = {
2107         /* CLKOUT */
2108         RCAR_GP_PIN(2, 3),
2109 };
2110 static const unsigned int du_clk_out_1_mux[] = {
2111         DU_DOTCLKOUT1_MARK
2112 };
2113 static const unsigned int du_sync_pins[] = {
2114         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2115         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2116 };
2117 static const unsigned int du_sync_mux[] = {
2118         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2119 };
2120 static const unsigned int du_oddf_pins[] = {
2121         /* EXDISP/EXODDF/EXCDE */
2122         RCAR_GP_PIN(2, 2),
2123 };
2124 static const unsigned int du_oddf_mux[] = {
2125         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2126 };
2127 static const unsigned int du_cde_pins[] = {
2128         /* CDE */
2129         RCAR_GP_PIN(2, 0),
2130 };
2131 static const unsigned int du_cde_mux[] = {
2132         DU_CDE_MARK,
2133 };
2134 static const unsigned int du_disp_pins[] = {
2135         /* DISP */
2136         RCAR_GP_PIN(2, 1),
2137 };
2138 static const unsigned int du_disp_mux[] = {
2139         DU_DISP_MARK,
2140 };
2141
2142 /* - HSCIF0 ----------------------------------------------------------------- */
2143 static const unsigned int hscif0_data_pins[] = {
2144         /* RX, TX */
2145         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2146 };
2147 static const unsigned int hscif0_data_mux[] = {
2148         HRX0_MARK, HTX0_MARK,
2149 };
2150 static const unsigned int hscif0_clk_pins[] = {
2151         /* SCK */
2152         RCAR_GP_PIN(5, 12),
2153 };
2154 static const unsigned int hscif0_clk_mux[] = {
2155         HSCK0_MARK,
2156 };
2157 static const unsigned int hscif0_ctrl_pins[] = {
2158         /* RTS, CTS */
2159         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2160 };
2161 static const unsigned int hscif0_ctrl_mux[] = {
2162         HRTS0_N_MARK, HCTS0_N_MARK,
2163 };
2164 /* - HSCIF1 ----------------------------------------------------------------- */
2165 static const unsigned int hscif1_data_a_pins[] = {
2166         /* RX, TX */
2167         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2168 };
2169 static const unsigned int hscif1_data_a_mux[] = {
2170         HRX1_A_MARK, HTX1_A_MARK,
2171 };
2172 static const unsigned int hscif1_clk_a_pins[] = {
2173         /* SCK */
2174         RCAR_GP_PIN(6, 21),
2175 };
2176 static const unsigned int hscif1_clk_a_mux[] = {
2177         HSCK1_A_MARK,
2178 };
2179 static const unsigned int hscif1_ctrl_a_pins[] = {
2180         /* RTS, CTS */
2181         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2182 };
2183 static const unsigned int hscif1_ctrl_a_mux[] = {
2184         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2185 };
2186
2187 static const unsigned int hscif1_data_b_pins[] = {
2188         /* RX, TX */
2189         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2190 };
2191 static const unsigned int hscif1_data_b_mux[] = {
2192         HRX1_B_MARK, HTX1_B_MARK,
2193 };
2194 static const unsigned int hscif1_clk_b_pins[] = {
2195         /* SCK */
2196         RCAR_GP_PIN(5, 0),
2197 };
2198 static const unsigned int hscif1_clk_b_mux[] = {
2199         HSCK1_B_MARK,
2200 };
2201 static const unsigned int hscif1_ctrl_b_pins[] = {
2202         /* RTS, CTS */
2203         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2204 };
2205 static const unsigned int hscif1_ctrl_b_mux[] = {
2206         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2207 };
2208 /* - HSCIF2 ----------------------------------------------------------------- */
2209 static const unsigned int hscif2_data_a_pins[] = {
2210         /* RX, TX */
2211         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2212 };
2213 static const unsigned int hscif2_data_a_mux[] = {
2214         HRX2_A_MARK, HTX2_A_MARK,
2215 };
2216 static const unsigned int hscif2_clk_a_pins[] = {
2217         /* SCK */
2218         RCAR_GP_PIN(6, 10),
2219 };
2220 static const unsigned int hscif2_clk_a_mux[] = {
2221         HSCK2_A_MARK,
2222 };
2223 static const unsigned int hscif2_ctrl_a_pins[] = {
2224         /* RTS, CTS */
2225         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2226 };
2227 static const unsigned int hscif2_ctrl_a_mux[] = {
2228         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2229 };
2230
2231 static const unsigned int hscif2_data_b_pins[] = {
2232         /* RX, TX */
2233         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2234 };
2235 static const unsigned int hscif2_data_b_mux[] = {
2236         HRX2_B_MARK, HTX2_B_MARK,
2237 };
2238 static const unsigned int hscif2_clk_b_pins[] = {
2239         /* SCK */
2240         RCAR_GP_PIN(6, 21),
2241 };
2242 static const unsigned int hscif2_clk_b_mux[] = {
2243         HSCK2_B_MARK,
2244 };
2245 static const unsigned int hscif2_ctrl_b_pins[] = {
2246         /* RTS, CTS */
2247         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2248 };
2249 static const unsigned int hscif2_ctrl_b_mux[] = {
2250         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2251 };
2252
2253 static const unsigned int hscif2_data_c_pins[] = {
2254         /* RX, TX */
2255         RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2256 };
2257 static const unsigned int hscif2_data_c_mux[] = {
2258         HRX2_C_MARK, HTX2_C_MARK,
2259 };
2260 static const unsigned int hscif2_clk_c_pins[] = {
2261         /* SCK */
2262         RCAR_GP_PIN(6, 24),
2263 };
2264 static const unsigned int hscif2_clk_c_mux[] = {
2265         HSCK2_C_MARK,
2266 };
2267 static const unsigned int hscif2_ctrl_c_pins[] = {
2268         /* RTS, CTS */
2269         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2270 };
2271 static const unsigned int hscif2_ctrl_c_mux[] = {
2272         HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2273 };
2274 /* - HSCIF3 ----------------------------------------------------------------- */
2275 static const unsigned int hscif3_data_a_pins[] = {
2276         /* RX, TX */
2277         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2278 };
2279 static const unsigned int hscif3_data_a_mux[] = {
2280         HRX3_A_MARK, HTX3_A_MARK,
2281 };
2282 static const unsigned int hscif3_clk_pins[] = {
2283         /* SCK */
2284         RCAR_GP_PIN(1, 22),
2285 };
2286 static const unsigned int hscif3_clk_mux[] = {
2287         HSCK3_MARK,
2288 };
2289 static const unsigned int hscif3_ctrl_pins[] = {
2290         /* RTS, CTS */
2291         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2292 };
2293 static const unsigned int hscif3_ctrl_mux[] = {
2294         HRTS3_N_MARK, HCTS3_N_MARK,
2295 };
2296
2297 static const unsigned int hscif3_data_b_pins[] = {
2298         /* RX, TX */
2299         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2300 };
2301 static const unsigned int hscif3_data_b_mux[] = {
2302         HRX3_B_MARK, HTX3_B_MARK,
2303 };
2304 static const unsigned int hscif3_data_c_pins[] = {
2305         /* RX, TX */
2306         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2307 };
2308 static const unsigned int hscif3_data_c_mux[] = {
2309         HRX3_C_MARK, HTX3_C_MARK,
2310 };
2311 static const unsigned int hscif3_data_d_pins[] = {
2312         /* RX, TX */
2313         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2314 };
2315 static const unsigned int hscif3_data_d_mux[] = {
2316         HRX3_D_MARK, HTX3_D_MARK,
2317 };
2318 /* - HSCIF4 ----------------------------------------------------------------- */
2319 static const unsigned int hscif4_data_a_pins[] = {
2320         /* RX, TX */
2321         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2322 };
2323 static const unsigned int hscif4_data_a_mux[] = {
2324         HRX4_A_MARK, HTX4_A_MARK,
2325 };
2326 static const unsigned int hscif4_clk_pins[] = {
2327         /* SCK */
2328         RCAR_GP_PIN(1, 11),
2329 };
2330 static const unsigned int hscif4_clk_mux[] = {
2331         HSCK4_MARK,
2332 };
2333 static const unsigned int hscif4_ctrl_pins[] = {
2334         /* RTS, CTS */
2335         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2336 };
2337 static const unsigned int hscif4_ctrl_mux[] = {
2338         HRTS4_N_MARK, HCTS4_N_MARK,
2339 };
2340
2341 static const unsigned int hscif4_data_b_pins[] = {
2342         /* RX, TX */
2343         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2344 };
2345 static const unsigned int hscif4_data_b_mux[] = {
2346         HRX4_B_MARK, HTX4_B_MARK,
2347 };
2348
2349 /* - I2C -------------------------------------------------------------------- */
2350 static const unsigned int i2c0_pins[] = {
2351         /* SCL, SDA */
2352         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2353 };
2354
2355 static const unsigned int i2c0_mux[] = {
2356         SCL0_MARK, SDA0_MARK,
2357 };
2358
2359 static const unsigned int i2c1_a_pins[] = {
2360         /* SDA, SCL */
2361         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2362 };
2363 static const unsigned int i2c1_a_mux[] = {
2364         SDA1_A_MARK, SCL1_A_MARK,
2365 };
2366 static const unsigned int i2c1_b_pins[] = {
2367         /* SDA, SCL */
2368         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2369 };
2370 static const unsigned int i2c1_b_mux[] = {
2371         SDA1_B_MARK, SCL1_B_MARK,
2372 };
2373 static const unsigned int i2c2_a_pins[] = {
2374         /* SDA, SCL */
2375         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2376 };
2377 static const unsigned int i2c2_a_mux[] = {
2378         SDA2_A_MARK, SCL2_A_MARK,
2379 };
2380 static const unsigned int i2c2_b_pins[] = {
2381         /* SDA, SCL */
2382         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2383 };
2384 static const unsigned int i2c2_b_mux[] = {
2385         SDA2_B_MARK, SCL2_B_MARK,
2386 };
2387
2388 static const unsigned int i2c3_pins[] = {
2389         /* SCL, SDA */
2390         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2391 };
2392
2393 static const unsigned int i2c3_mux[] = {
2394         SCL3_MARK, SDA3_MARK,
2395 };
2396
2397 static const unsigned int i2c5_pins[] = {
2398         /* SCL, SDA */
2399         RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2400 };
2401
2402 static const unsigned int i2c5_mux[] = {
2403         SCL5_MARK, SDA5_MARK,
2404 };
2405
2406 static const unsigned int i2c6_a_pins[] = {
2407         /* SDA, SCL */
2408         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2409 };
2410 static const unsigned int i2c6_a_mux[] = {
2411         SDA6_A_MARK, SCL6_A_MARK,
2412 };
2413 static const unsigned int i2c6_b_pins[] = {
2414         /* SDA, SCL */
2415         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2416 };
2417 static const unsigned int i2c6_b_mux[] = {
2418         SDA6_B_MARK, SCL6_B_MARK,
2419 };
2420 static const unsigned int i2c6_c_pins[] = {
2421         /* SDA, SCL */
2422         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2423 };
2424 static const unsigned int i2c6_c_mux[] = {
2425         SDA6_C_MARK, SCL6_C_MARK,
2426 };
2427
2428 /* - INTC-EX ---------------------------------------------------------------- */
2429 static const unsigned int intc_ex_irq0_pins[] = {
2430         /* IRQ0 */
2431         RCAR_GP_PIN(2, 0),
2432 };
2433 static const unsigned int intc_ex_irq0_mux[] = {
2434         IRQ0_MARK,
2435 };
2436 static const unsigned int intc_ex_irq1_pins[] = {
2437         /* IRQ1 */
2438         RCAR_GP_PIN(2, 1),
2439 };
2440 static const unsigned int intc_ex_irq1_mux[] = {
2441         IRQ1_MARK,
2442 };
2443 static const unsigned int intc_ex_irq2_pins[] = {
2444         /* IRQ2 */
2445         RCAR_GP_PIN(2, 2),
2446 };
2447 static const unsigned int intc_ex_irq2_mux[] = {
2448         IRQ2_MARK,
2449 };
2450 static const unsigned int intc_ex_irq3_pins[] = {
2451         /* IRQ3 */
2452         RCAR_GP_PIN(2, 3),
2453 };
2454 static const unsigned int intc_ex_irq3_mux[] = {
2455         IRQ3_MARK,
2456 };
2457 static const unsigned int intc_ex_irq4_pins[] = {
2458         /* IRQ4 */
2459         RCAR_GP_PIN(2, 4),
2460 };
2461 static const unsigned int intc_ex_irq4_mux[] = {
2462         IRQ4_MARK,
2463 };
2464 static const unsigned int intc_ex_irq5_pins[] = {
2465         /* IRQ5 */
2466         RCAR_GP_PIN(2, 5),
2467 };
2468 static const unsigned int intc_ex_irq5_mux[] = {
2469         IRQ5_MARK,
2470 };
2471
2472 /* - MSIOF0 ----------------------------------------------------------------- */
2473 static const unsigned int msiof0_clk_pins[] = {
2474         /* SCK */
2475         RCAR_GP_PIN(5, 17),
2476 };
2477 static const unsigned int msiof0_clk_mux[] = {
2478         MSIOF0_SCK_MARK,
2479 };
2480 static const unsigned int msiof0_sync_pins[] = {
2481         /* SYNC */
2482         RCAR_GP_PIN(5, 18),
2483 };
2484 static const unsigned int msiof0_sync_mux[] = {
2485         MSIOF0_SYNC_MARK,
2486 };
2487 static const unsigned int msiof0_ss1_pins[] = {
2488         /* SS1 */
2489         RCAR_GP_PIN(5, 19),
2490 };
2491 static const unsigned int msiof0_ss1_mux[] = {
2492         MSIOF0_SS1_MARK,
2493 };
2494 static const unsigned int msiof0_ss2_pins[] = {
2495         /* SS2 */
2496         RCAR_GP_PIN(5, 21),
2497 };
2498 static const unsigned int msiof0_ss2_mux[] = {
2499         MSIOF0_SS2_MARK,
2500 };
2501 static const unsigned int msiof0_txd_pins[] = {
2502         /* TXD */
2503         RCAR_GP_PIN(5, 20),
2504 };
2505 static const unsigned int msiof0_txd_mux[] = {
2506         MSIOF0_TXD_MARK,
2507 };
2508 static const unsigned int msiof0_rxd_pins[] = {
2509         /* RXD */
2510         RCAR_GP_PIN(5, 22),
2511 };
2512 static const unsigned int msiof0_rxd_mux[] = {
2513         MSIOF0_RXD_MARK,
2514 };
2515 /* - MSIOF1 ----------------------------------------------------------------- */
2516 static const unsigned int msiof1_clk_a_pins[] = {
2517         /* SCK */
2518         RCAR_GP_PIN(6, 8),
2519 };
2520 static const unsigned int msiof1_clk_a_mux[] = {
2521         MSIOF1_SCK_A_MARK,
2522 };
2523 static const unsigned int msiof1_sync_a_pins[] = {
2524         /* SYNC */
2525         RCAR_GP_PIN(6, 9),
2526 };
2527 static const unsigned int msiof1_sync_a_mux[] = {
2528         MSIOF1_SYNC_A_MARK,
2529 };
2530 static const unsigned int msiof1_ss1_a_pins[] = {
2531         /* SS1 */
2532         RCAR_GP_PIN(6, 5),
2533 };
2534 static const unsigned int msiof1_ss1_a_mux[] = {
2535         MSIOF1_SS1_A_MARK,
2536 };
2537 static const unsigned int msiof1_ss2_a_pins[] = {
2538         /* SS2 */
2539         RCAR_GP_PIN(6, 6),
2540 };
2541 static const unsigned int msiof1_ss2_a_mux[] = {
2542         MSIOF1_SS2_A_MARK,
2543 };
2544 static const unsigned int msiof1_txd_a_pins[] = {
2545         /* TXD */
2546         RCAR_GP_PIN(6, 7),
2547 };
2548 static const unsigned int msiof1_txd_a_mux[] = {
2549         MSIOF1_TXD_A_MARK,
2550 };
2551 static const unsigned int msiof1_rxd_a_pins[] = {
2552         /* RXD */
2553         RCAR_GP_PIN(6, 10),
2554 };
2555 static const unsigned int msiof1_rxd_a_mux[] = {
2556         MSIOF1_RXD_A_MARK,
2557 };
2558 static const unsigned int msiof1_clk_b_pins[] = {
2559         /* SCK */
2560         RCAR_GP_PIN(5, 9),
2561 };
2562 static const unsigned int msiof1_clk_b_mux[] = {
2563         MSIOF1_SCK_B_MARK,
2564 };
2565 static const unsigned int msiof1_sync_b_pins[] = {
2566         /* SYNC */
2567         RCAR_GP_PIN(5, 3),
2568 };
2569 static const unsigned int msiof1_sync_b_mux[] = {
2570         MSIOF1_SYNC_B_MARK,
2571 };
2572 static const unsigned int msiof1_ss1_b_pins[] = {
2573         /* SS1 */
2574         RCAR_GP_PIN(5, 4),
2575 };
2576 static const unsigned int msiof1_ss1_b_mux[] = {
2577         MSIOF1_SS1_B_MARK,
2578 };
2579 static const unsigned int msiof1_ss2_b_pins[] = {
2580         /* SS2 */
2581         RCAR_GP_PIN(5, 0),
2582 };
2583 static const unsigned int msiof1_ss2_b_mux[] = {
2584         MSIOF1_SS2_B_MARK,
2585 };
2586 static const unsigned int msiof1_txd_b_pins[] = {
2587         /* TXD */
2588         RCAR_GP_PIN(5, 8),
2589 };
2590 static const unsigned int msiof1_txd_b_mux[] = {
2591         MSIOF1_TXD_B_MARK,
2592 };
2593 static const unsigned int msiof1_rxd_b_pins[] = {
2594         /* RXD */
2595         RCAR_GP_PIN(5, 7),
2596 };
2597 static const unsigned int msiof1_rxd_b_mux[] = {
2598         MSIOF1_RXD_B_MARK,
2599 };
2600 static const unsigned int msiof1_clk_c_pins[] = {
2601         /* SCK */
2602         RCAR_GP_PIN(6, 17),
2603 };
2604 static const unsigned int msiof1_clk_c_mux[] = {
2605         MSIOF1_SCK_C_MARK,
2606 };
2607 static const unsigned int msiof1_sync_c_pins[] = {
2608         /* SYNC */
2609         RCAR_GP_PIN(6, 18),
2610 };
2611 static const unsigned int msiof1_sync_c_mux[] = {
2612         MSIOF1_SYNC_C_MARK,
2613 };
2614 static const unsigned int msiof1_ss1_c_pins[] = {
2615         /* SS1 */
2616         RCAR_GP_PIN(6, 21),
2617 };
2618 static const unsigned int msiof1_ss1_c_mux[] = {
2619         MSIOF1_SS1_C_MARK,
2620 };
2621 static const unsigned int msiof1_ss2_c_pins[] = {
2622         /* SS2 */
2623         RCAR_GP_PIN(6, 27),
2624 };
2625 static const unsigned int msiof1_ss2_c_mux[] = {
2626         MSIOF1_SS2_C_MARK,
2627 };
2628 static const unsigned int msiof1_txd_c_pins[] = {
2629         /* TXD */
2630         RCAR_GP_PIN(6, 20),
2631 };
2632 static const unsigned int msiof1_txd_c_mux[] = {
2633         MSIOF1_TXD_C_MARK,
2634 };
2635 static const unsigned int msiof1_rxd_c_pins[] = {
2636         /* RXD */
2637         RCAR_GP_PIN(6, 19),
2638 };
2639 static const unsigned int msiof1_rxd_c_mux[] = {
2640         MSIOF1_RXD_C_MARK,
2641 };
2642 static const unsigned int msiof1_clk_d_pins[] = {
2643         /* SCK */
2644         RCAR_GP_PIN(5, 12),
2645 };
2646 static const unsigned int msiof1_clk_d_mux[] = {
2647         MSIOF1_SCK_D_MARK,
2648 };
2649 static const unsigned int msiof1_sync_d_pins[] = {
2650         /* SYNC */
2651         RCAR_GP_PIN(5, 15),
2652 };
2653 static const unsigned int msiof1_sync_d_mux[] = {
2654         MSIOF1_SYNC_D_MARK,
2655 };
2656 static const unsigned int msiof1_ss1_d_pins[] = {
2657         /* SS1 */
2658         RCAR_GP_PIN(5, 16),
2659 };
2660 static const unsigned int msiof1_ss1_d_mux[] = {
2661         MSIOF1_SS1_D_MARK,
2662 };
2663 static const unsigned int msiof1_ss2_d_pins[] = {
2664         /* SS2 */
2665         RCAR_GP_PIN(5, 21),
2666 };
2667 static const unsigned int msiof1_ss2_d_mux[] = {
2668         MSIOF1_SS2_D_MARK,
2669 };
2670 static const unsigned int msiof1_txd_d_pins[] = {
2671         /* TXD */
2672         RCAR_GP_PIN(5, 14),
2673 };
2674 static const unsigned int msiof1_txd_d_mux[] = {
2675         MSIOF1_TXD_D_MARK,
2676 };
2677 static const unsigned int msiof1_rxd_d_pins[] = {
2678         /* RXD */
2679         RCAR_GP_PIN(5, 13),
2680 };
2681 static const unsigned int msiof1_rxd_d_mux[] = {
2682         MSIOF1_RXD_D_MARK,
2683 };
2684 static const unsigned int msiof1_clk_e_pins[] = {
2685         /* SCK */
2686         RCAR_GP_PIN(3, 0),
2687 };
2688 static const unsigned int msiof1_clk_e_mux[] = {
2689         MSIOF1_SCK_E_MARK,
2690 };
2691 static const unsigned int msiof1_sync_e_pins[] = {
2692         /* SYNC */
2693         RCAR_GP_PIN(3, 1),
2694 };
2695 static const unsigned int msiof1_sync_e_mux[] = {
2696         MSIOF1_SYNC_E_MARK,
2697 };
2698 static const unsigned int msiof1_ss1_e_pins[] = {
2699         /* SS1 */
2700         RCAR_GP_PIN(3, 4),
2701 };
2702 static const unsigned int msiof1_ss1_e_mux[] = {
2703         MSIOF1_SS1_E_MARK,
2704 };
2705 static const unsigned int msiof1_ss2_e_pins[] = {
2706         /* SS2 */
2707         RCAR_GP_PIN(3, 5),
2708 };
2709 static const unsigned int msiof1_ss2_e_mux[] = {
2710         MSIOF1_SS2_E_MARK,
2711 };
2712 static const unsigned int msiof1_txd_e_pins[] = {
2713         /* TXD */
2714         RCAR_GP_PIN(3, 3),
2715 };
2716 static const unsigned int msiof1_txd_e_mux[] = {
2717         MSIOF1_TXD_E_MARK,
2718 };
2719 static const unsigned int msiof1_rxd_e_pins[] = {
2720         /* RXD */
2721         RCAR_GP_PIN(3, 2),
2722 };
2723 static const unsigned int msiof1_rxd_e_mux[] = {
2724         MSIOF1_RXD_E_MARK,
2725 };
2726 static const unsigned int msiof1_clk_f_pins[] = {
2727         /* SCK */
2728         RCAR_GP_PIN(5, 23),
2729 };
2730 static const unsigned int msiof1_clk_f_mux[] = {
2731         MSIOF1_SCK_F_MARK,
2732 };
2733 static const unsigned int msiof1_sync_f_pins[] = {
2734         /* SYNC */
2735         RCAR_GP_PIN(5, 24),
2736 };
2737 static const unsigned int msiof1_sync_f_mux[] = {
2738         MSIOF1_SYNC_F_MARK,
2739 };
2740 static const unsigned int msiof1_ss1_f_pins[] = {
2741         /* SS1 */
2742         RCAR_GP_PIN(6, 1),
2743 };
2744 static const unsigned int msiof1_ss1_f_mux[] = {
2745         MSIOF1_SS1_F_MARK,
2746 };
2747 static const unsigned int msiof1_ss2_f_pins[] = {
2748         /* SS2 */
2749         RCAR_GP_PIN(6, 2),
2750 };
2751 static const unsigned int msiof1_ss2_f_mux[] = {
2752         MSIOF1_SS2_F_MARK,
2753 };
2754 static const unsigned int msiof1_txd_f_pins[] = {
2755         /* TXD */
2756         RCAR_GP_PIN(6, 0),
2757 };
2758 static const unsigned int msiof1_txd_f_mux[] = {
2759         MSIOF1_TXD_F_MARK,
2760 };
2761 static const unsigned int msiof1_rxd_f_pins[] = {
2762         /* RXD */
2763         RCAR_GP_PIN(5, 25),
2764 };
2765 static const unsigned int msiof1_rxd_f_mux[] = {
2766         MSIOF1_RXD_F_MARK,
2767 };
2768 static const unsigned int msiof1_clk_g_pins[] = {
2769         /* SCK */
2770         RCAR_GP_PIN(3, 6),
2771 };
2772 static const unsigned int msiof1_clk_g_mux[] = {
2773         MSIOF1_SCK_G_MARK,
2774 };
2775 static const unsigned int msiof1_sync_g_pins[] = {
2776         /* SYNC */
2777         RCAR_GP_PIN(3, 7),
2778 };
2779 static const unsigned int msiof1_sync_g_mux[] = {
2780         MSIOF1_SYNC_G_MARK,
2781 };
2782 static const unsigned int msiof1_ss1_g_pins[] = {
2783         /* SS1 */
2784         RCAR_GP_PIN(3, 10),
2785 };
2786 static const unsigned int msiof1_ss1_g_mux[] = {
2787         MSIOF1_SS1_G_MARK,
2788 };
2789 static const unsigned int msiof1_ss2_g_pins[] = {
2790         /* SS2 */
2791         RCAR_GP_PIN(3, 11),
2792 };
2793 static const unsigned int msiof1_ss2_g_mux[] = {
2794         MSIOF1_SS2_G_MARK,
2795 };
2796 static const unsigned int msiof1_txd_g_pins[] = {
2797         /* TXD */
2798         RCAR_GP_PIN(3, 9),
2799 };
2800 static const unsigned int msiof1_txd_g_mux[] = {
2801         MSIOF1_TXD_G_MARK,
2802 };
2803 static const unsigned int msiof1_rxd_g_pins[] = {
2804         /* RXD */
2805         RCAR_GP_PIN(3, 8),
2806 };
2807 static const unsigned int msiof1_rxd_g_mux[] = {
2808         MSIOF1_RXD_G_MARK,
2809 };
2810 /* - MSIOF2 ----------------------------------------------------------------- */
2811 static const unsigned int msiof2_clk_a_pins[] = {
2812         /* SCK */
2813         RCAR_GP_PIN(1, 9),
2814 };
2815 static const unsigned int msiof2_clk_a_mux[] = {
2816         MSIOF2_SCK_A_MARK,
2817 };
2818 static const unsigned int msiof2_sync_a_pins[] = {
2819         /* SYNC */
2820         RCAR_GP_PIN(1, 8),
2821 };
2822 static const unsigned int msiof2_sync_a_mux[] = {
2823         MSIOF2_SYNC_A_MARK,
2824 };
2825 static const unsigned int msiof2_ss1_a_pins[] = {
2826         /* SS1 */
2827         RCAR_GP_PIN(1, 6),
2828 };
2829 static const unsigned int msiof2_ss1_a_mux[] = {
2830         MSIOF2_SS1_A_MARK,
2831 };
2832 static const unsigned int msiof2_ss2_a_pins[] = {
2833         /* SS2 */
2834         RCAR_GP_PIN(1, 7),
2835 };
2836 static const unsigned int msiof2_ss2_a_mux[] = {
2837         MSIOF2_SS2_A_MARK,
2838 };
2839 static const unsigned int msiof2_txd_a_pins[] = {
2840         /* TXD */
2841         RCAR_GP_PIN(1, 11),
2842 };
2843 static const unsigned int msiof2_txd_a_mux[] = {
2844         MSIOF2_TXD_A_MARK,
2845 };
2846 static const unsigned int msiof2_rxd_a_pins[] = {
2847         /* RXD */
2848         RCAR_GP_PIN(1, 10),
2849 };
2850 static const unsigned int msiof2_rxd_a_mux[] = {
2851         MSIOF2_RXD_A_MARK,
2852 };
2853 static const unsigned int msiof2_clk_b_pins[] = {
2854         /* SCK */
2855         RCAR_GP_PIN(0, 4),
2856 };
2857 static const unsigned int msiof2_clk_b_mux[] = {
2858         MSIOF2_SCK_B_MARK,
2859 };
2860 static const unsigned int msiof2_sync_b_pins[] = {
2861         /* SYNC */
2862         RCAR_GP_PIN(0, 5),
2863 };
2864 static const unsigned int msiof2_sync_b_mux[] = {
2865         MSIOF2_SYNC_B_MARK,
2866 };
2867 static const unsigned int msiof2_ss1_b_pins[] = {
2868         /* SS1 */
2869         RCAR_GP_PIN(0, 0),
2870 };
2871 static const unsigned int msiof2_ss1_b_mux[] = {
2872         MSIOF2_SS1_B_MARK,
2873 };
2874 static const unsigned int msiof2_ss2_b_pins[] = {
2875         /* SS2 */
2876         RCAR_GP_PIN(0, 1),
2877 };
2878 static const unsigned int msiof2_ss2_b_mux[] = {
2879         MSIOF2_SS2_B_MARK,
2880 };
2881 static const unsigned int msiof2_txd_b_pins[] = {
2882         /* TXD */
2883         RCAR_GP_PIN(0, 7),
2884 };
2885 static const unsigned int msiof2_txd_b_mux[] = {
2886         MSIOF2_TXD_B_MARK,
2887 };
2888 static const unsigned int msiof2_rxd_b_pins[] = {
2889         /* RXD */
2890         RCAR_GP_PIN(0, 6),
2891 };
2892 static const unsigned int msiof2_rxd_b_mux[] = {
2893         MSIOF2_RXD_B_MARK,
2894 };
2895 static const unsigned int msiof2_clk_c_pins[] = {
2896         /* SCK */
2897         RCAR_GP_PIN(2, 12),
2898 };
2899 static const unsigned int msiof2_clk_c_mux[] = {
2900         MSIOF2_SCK_C_MARK,
2901 };
2902 static const unsigned int msiof2_sync_c_pins[] = {
2903         /* SYNC */
2904         RCAR_GP_PIN(2, 11),
2905 };
2906 static const unsigned int msiof2_sync_c_mux[] = {
2907         MSIOF2_SYNC_C_MARK,
2908 };
2909 static const unsigned int msiof2_ss1_c_pins[] = {
2910         /* SS1 */
2911         RCAR_GP_PIN(2, 10),
2912 };
2913 static const unsigned int msiof2_ss1_c_mux[] = {
2914         MSIOF2_SS1_C_MARK,
2915 };
2916 static const unsigned int msiof2_ss2_c_pins[] = {
2917         /* SS2 */
2918         RCAR_GP_PIN(2, 9),
2919 };
2920 static const unsigned int msiof2_ss2_c_mux[] = {
2921         MSIOF2_SS2_C_MARK,
2922 };
2923 static const unsigned int msiof2_txd_c_pins[] = {
2924         /* TXD */
2925         RCAR_GP_PIN(2, 14),
2926 };
2927 static const unsigned int msiof2_txd_c_mux[] = {
2928         MSIOF2_TXD_C_MARK,
2929 };
2930 static const unsigned int msiof2_rxd_c_pins[] = {
2931         /* RXD */
2932         RCAR_GP_PIN(2, 13),
2933 };
2934 static const unsigned int msiof2_rxd_c_mux[] = {
2935         MSIOF2_RXD_C_MARK,
2936 };
2937 static const unsigned int msiof2_clk_d_pins[] = {
2938         /* SCK */
2939         RCAR_GP_PIN(0, 8),
2940 };
2941 static const unsigned int msiof2_clk_d_mux[] = {
2942         MSIOF2_SCK_D_MARK,
2943 };
2944 static const unsigned int msiof2_sync_d_pins[] = {
2945         /* SYNC */
2946         RCAR_GP_PIN(0, 9),
2947 };
2948 static const unsigned int msiof2_sync_d_mux[] = {
2949         MSIOF2_SYNC_D_MARK,
2950 };
2951 static const unsigned int msiof2_ss1_d_pins[] = {
2952         /* SS1 */
2953         RCAR_GP_PIN(0, 12),
2954 };
2955 static const unsigned int msiof2_ss1_d_mux[] = {
2956         MSIOF2_SS1_D_MARK,
2957 };
2958 static const unsigned int msiof2_ss2_d_pins[] = {
2959         /* SS2 */
2960         RCAR_GP_PIN(0, 13),
2961 };
2962 static const unsigned int msiof2_ss2_d_mux[] = {
2963         MSIOF2_SS2_D_MARK,
2964 };
2965 static const unsigned int msiof2_txd_d_pins[] = {
2966         /* TXD */
2967         RCAR_GP_PIN(0, 11),
2968 };
2969 static const unsigned int msiof2_txd_d_mux[] = {
2970         MSIOF2_TXD_D_MARK,
2971 };
2972 static const unsigned int msiof2_rxd_d_pins[] = {
2973         /* RXD */
2974         RCAR_GP_PIN(0, 10),
2975 };
2976 static const unsigned int msiof2_rxd_d_mux[] = {
2977         MSIOF2_RXD_D_MARK,
2978 };
2979 /* - MSIOF3 ----------------------------------------------------------------- */
2980 static const unsigned int msiof3_clk_a_pins[] = {
2981         /* SCK */
2982         RCAR_GP_PIN(0, 0),
2983 };
2984 static const unsigned int msiof3_clk_a_mux[] = {
2985         MSIOF3_SCK_A_MARK,
2986 };
2987 static const unsigned int msiof3_sync_a_pins[] = {
2988         /* SYNC */
2989         RCAR_GP_PIN(0, 1),
2990 };
2991 static const unsigned int msiof3_sync_a_mux[] = {
2992         MSIOF3_SYNC_A_MARK,
2993 };
2994 static const unsigned int msiof3_ss1_a_pins[] = {
2995         /* SS1 */
2996         RCAR_GP_PIN(0, 14),
2997 };
2998 static const unsigned int msiof3_ss1_a_mux[] = {
2999         MSIOF3_SS1_A_MARK,
3000 };
3001 static const unsigned int msiof3_ss2_a_pins[] = {
3002         /* SS2 */
3003         RCAR_GP_PIN(0, 15),
3004 };
3005 static const unsigned int msiof3_ss2_a_mux[] = {
3006         MSIOF3_SS2_A_MARK,
3007 };
3008 static const unsigned int msiof3_txd_a_pins[] = {
3009         /* TXD */
3010         RCAR_GP_PIN(0, 3),
3011 };
3012 static const unsigned int msiof3_txd_a_mux[] = {
3013         MSIOF3_TXD_A_MARK,
3014 };
3015 static const unsigned int msiof3_rxd_a_pins[] = {
3016         /* RXD */
3017         RCAR_GP_PIN(0, 2),
3018 };
3019 static const unsigned int msiof3_rxd_a_mux[] = {
3020         MSIOF3_RXD_A_MARK,
3021 };
3022 static const unsigned int msiof3_clk_b_pins[] = {
3023         /* SCK */
3024         RCAR_GP_PIN(1, 2),
3025 };
3026 static const unsigned int msiof3_clk_b_mux[] = {
3027         MSIOF3_SCK_B_MARK,
3028 };
3029 static const unsigned int msiof3_sync_b_pins[] = {
3030         /* SYNC */
3031         RCAR_GP_PIN(1, 0),
3032 };
3033 static const unsigned int msiof3_sync_b_mux[] = {
3034         MSIOF3_SYNC_B_MARK,
3035 };
3036 static const unsigned int msiof3_ss1_b_pins[] = {
3037         /* SS1 */
3038         RCAR_GP_PIN(1, 4),
3039 };
3040 static const unsigned int msiof3_ss1_b_mux[] = {
3041         MSIOF3_SS1_B_MARK,
3042 };
3043 static const unsigned int msiof3_ss2_b_pins[] = {
3044         /* SS2 */
3045         RCAR_GP_PIN(1, 5),
3046 };
3047 static const unsigned int msiof3_ss2_b_mux[] = {
3048         MSIOF3_SS2_B_MARK,
3049 };
3050 static const unsigned int msiof3_txd_b_pins[] = {
3051         /* TXD */
3052         RCAR_GP_PIN(1, 1),
3053 };
3054 static const unsigned int msiof3_txd_b_mux[] = {
3055         MSIOF3_TXD_B_MARK,
3056 };
3057 static const unsigned int msiof3_rxd_b_pins[] = {
3058         /* RXD */
3059         RCAR_GP_PIN(1, 3),
3060 };
3061 static const unsigned int msiof3_rxd_b_mux[] = {
3062         MSIOF3_RXD_B_MARK,
3063 };
3064 static const unsigned int msiof3_clk_c_pins[] = {
3065         /* SCK */
3066         RCAR_GP_PIN(1, 12),
3067 };
3068 static const unsigned int msiof3_clk_c_mux[] = {
3069         MSIOF3_SCK_C_MARK,
3070 };
3071 static const unsigned int msiof3_sync_c_pins[] = {
3072         /* SYNC */
3073         RCAR_GP_PIN(1, 13),
3074 };
3075 static const unsigned int msiof3_sync_c_mux[] = {
3076         MSIOF3_SYNC_C_MARK,
3077 };
3078 static const unsigned int msiof3_txd_c_pins[] = {
3079         /* TXD */
3080         RCAR_GP_PIN(1, 15),
3081 };
3082 static const unsigned int msiof3_txd_c_mux[] = {
3083         MSIOF3_TXD_C_MARK,
3084 };
3085 static const unsigned int msiof3_rxd_c_pins[] = {
3086         /* RXD */
3087         RCAR_GP_PIN(1, 14),
3088 };
3089 static const unsigned int msiof3_rxd_c_mux[] = {
3090         MSIOF3_RXD_C_MARK,
3091 };
3092 static const unsigned int msiof3_clk_d_pins[] = {
3093         /* SCK */
3094         RCAR_GP_PIN(1, 22),
3095 };
3096 static const unsigned int msiof3_clk_d_mux[] = {
3097         MSIOF3_SCK_D_MARK,
3098 };
3099 static const unsigned int msiof3_sync_d_pins[] = {
3100         /* SYNC */
3101         RCAR_GP_PIN(1, 23),
3102 };
3103 static const unsigned int msiof3_sync_d_mux[] = {
3104         MSIOF3_SYNC_D_MARK,
3105 };
3106 static const unsigned int msiof3_ss1_d_pins[] = {
3107         /* SS1 */
3108         RCAR_GP_PIN(1, 26),
3109 };
3110 static const unsigned int msiof3_ss1_d_mux[] = {
3111         MSIOF3_SS1_D_MARK,
3112 };
3113 static const unsigned int msiof3_txd_d_pins[] = {
3114         /* TXD */
3115         RCAR_GP_PIN(1, 25),
3116 };
3117 static const unsigned int msiof3_txd_d_mux[] = {
3118         MSIOF3_TXD_D_MARK,
3119 };
3120 static const unsigned int msiof3_rxd_d_pins[] = {
3121         /* RXD */
3122         RCAR_GP_PIN(1, 24),
3123 };
3124 static const unsigned int msiof3_rxd_d_mux[] = {
3125         MSIOF3_RXD_D_MARK,
3126 };
3127
3128 static const unsigned int msiof3_clk_e_pins[] = {
3129         /* SCK */
3130         RCAR_GP_PIN(2, 3),
3131 };
3132 static const unsigned int msiof3_clk_e_mux[] = {
3133         MSIOF3_SCK_E_MARK,
3134 };
3135 static const unsigned int msiof3_sync_e_pins[] = {
3136         /* SYNC */
3137         RCAR_GP_PIN(2, 2),
3138 };
3139 static const unsigned int msiof3_sync_e_mux[] = {
3140         MSIOF3_SYNC_E_MARK,
3141 };
3142 static const unsigned int msiof3_ss1_e_pins[] = {
3143         /* SS1 */
3144         RCAR_GP_PIN(2, 1),
3145 };
3146 static const unsigned int msiof3_ss1_e_mux[] = {
3147         MSIOF3_SS1_E_MARK,
3148 };
3149 static const unsigned int msiof3_ss2_e_pins[] = {
3150         /* SS2 */
3151         RCAR_GP_PIN(2, 0),
3152 };
3153 static const unsigned int msiof3_ss2_e_mux[] = {
3154         MSIOF3_SS2_E_MARK,
3155 };
3156 static const unsigned int msiof3_txd_e_pins[] = {
3157         /* TXD */
3158         RCAR_GP_PIN(2, 5),
3159 };
3160 static const unsigned int msiof3_txd_e_mux[] = {
3161         MSIOF3_TXD_E_MARK,
3162 };
3163 static const unsigned int msiof3_rxd_e_pins[] = {
3164         /* RXD */
3165         RCAR_GP_PIN(2, 4),
3166 };
3167 static const unsigned int msiof3_rxd_e_mux[] = {
3168         MSIOF3_RXD_E_MARK,
3169 };
3170
3171 /* - PWM0 --------------------------------------------------------------------*/
3172 static const unsigned int pwm0_pins[] = {
3173         /* PWM */
3174         RCAR_GP_PIN(2, 6),
3175 };
3176 static const unsigned int pwm0_mux[] = {
3177         PWM0_MARK,
3178 };
3179 /* - PWM1 --------------------------------------------------------------------*/
3180 static const unsigned int pwm1_a_pins[] = {
3181         /* PWM */
3182         RCAR_GP_PIN(2, 7),
3183 };
3184 static const unsigned int pwm1_a_mux[] = {
3185         PWM1_A_MARK,
3186 };
3187 static const unsigned int pwm1_b_pins[] = {
3188         /* PWM */
3189         RCAR_GP_PIN(1, 8),
3190 };
3191 static const unsigned int pwm1_b_mux[] = {
3192         PWM1_B_MARK,
3193 };
3194 /* - PWM2 --------------------------------------------------------------------*/
3195 static const unsigned int pwm2_a_pins[] = {
3196         /* PWM */
3197         RCAR_GP_PIN(2, 8),
3198 };
3199 static const unsigned int pwm2_a_mux[] = {
3200         PWM2_A_MARK,
3201 };
3202 static const unsigned int pwm2_b_pins[] = {
3203         /* PWM */
3204         RCAR_GP_PIN(1, 11),
3205 };
3206 static const unsigned int pwm2_b_mux[] = {
3207         PWM2_B_MARK,
3208 };
3209 /* - PWM3 --------------------------------------------------------------------*/
3210 static const unsigned int pwm3_a_pins[] = {
3211         /* PWM */
3212         RCAR_GP_PIN(1, 0),
3213 };
3214 static const unsigned int pwm3_a_mux[] = {
3215         PWM3_A_MARK,
3216 };
3217 static const unsigned int pwm3_b_pins[] = {
3218         /* PWM */
3219         RCAR_GP_PIN(2, 2),
3220 };
3221 static const unsigned int pwm3_b_mux[] = {
3222         PWM3_B_MARK,
3223 };
3224 /* - PWM4 --------------------------------------------------------------------*/
3225 static const unsigned int pwm4_a_pins[] = {
3226         /* PWM */
3227         RCAR_GP_PIN(1, 1),
3228 };
3229 static const unsigned int pwm4_a_mux[] = {
3230         PWM4_A_MARK,
3231 };
3232 static const unsigned int pwm4_b_pins[] = {
3233         /* PWM */
3234         RCAR_GP_PIN(2, 3),
3235 };
3236 static const unsigned int pwm4_b_mux[] = {
3237         PWM4_B_MARK,
3238 };
3239 /* - PWM5 --------------------------------------------------------------------*/
3240 static const unsigned int pwm5_a_pins[] = {
3241         /* PWM */
3242         RCAR_GP_PIN(1, 2),
3243 };
3244 static const unsigned int pwm5_a_mux[] = {
3245         PWM5_A_MARK,
3246 };
3247 static const unsigned int pwm5_b_pins[] = {
3248         /* PWM */
3249         RCAR_GP_PIN(2, 4),
3250 };
3251 static const unsigned int pwm5_b_mux[] = {
3252         PWM5_B_MARK,
3253 };
3254 /* - PWM6 --------------------------------------------------------------------*/
3255 static const unsigned int pwm6_a_pins[] = {
3256         /* PWM */
3257         RCAR_GP_PIN(1, 3),
3258 };
3259 static const unsigned int pwm6_a_mux[] = {
3260         PWM6_A_MARK,
3261 };
3262 static const unsigned int pwm6_b_pins[] = {
3263         /* PWM */
3264         RCAR_GP_PIN(2, 5),
3265 };
3266 static const unsigned int pwm6_b_mux[] = {
3267         PWM6_B_MARK,
3268 };
3269
3270 /* - SCIF0 ------------------------------------------------------------------ */
3271 static const unsigned int scif0_data_pins[] = {
3272         /* RX, TX */
3273         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3274 };
3275 static const unsigned int scif0_data_mux[] = {
3276         RX0_MARK, TX0_MARK,
3277 };
3278 static const unsigned int scif0_clk_pins[] = {
3279         /* SCK */
3280         RCAR_GP_PIN(5, 0),
3281 };
3282 static const unsigned int scif0_clk_mux[] = {
3283         SCK0_MARK,
3284 };
3285 static const unsigned int scif0_ctrl_pins[] = {
3286         /* RTS, CTS */
3287         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3288 };
3289 static const unsigned int scif0_ctrl_mux[] = {
3290         RTS0_N_MARK, CTS0_N_MARK,
3291 };
3292 /* - SCIF1 ------------------------------------------------------------------ */
3293 static const unsigned int scif1_data_a_pins[] = {
3294         /* RX, TX */
3295         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3296 };
3297 static const unsigned int scif1_data_a_mux[] = {
3298         RX1_A_MARK, TX1_A_MARK,
3299 };
3300 static const unsigned int scif1_clk_pins[] = {
3301         /* SCK */
3302         RCAR_GP_PIN(6, 21),
3303 };
3304 static const unsigned int scif1_clk_mux[] = {
3305         SCK1_MARK,
3306 };
3307 static const unsigned int scif1_ctrl_pins[] = {
3308         /* RTS, CTS */
3309         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3310 };
3311 static const unsigned int scif1_ctrl_mux[] = {
3312         RTS1_N_MARK, CTS1_N_MARK,
3313 };
3314
3315 static const unsigned int scif1_data_b_pins[] = {
3316         /* RX, TX */
3317         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3318 };
3319 static const unsigned int scif1_data_b_mux[] = {
3320         RX1_B_MARK, TX1_B_MARK,
3321 };
3322 /* - SCIF2 ------------------------------------------------------------------ */
3323 static const unsigned int scif2_data_a_pins[] = {
3324         /* RX, TX */
3325         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3326 };
3327 static const unsigned int scif2_data_a_mux[] = {
3328         RX2_A_MARK, TX2_A_MARK,
3329 };
3330 static const unsigned int scif2_clk_pins[] = {
3331         /* SCK */
3332         RCAR_GP_PIN(5, 9),
3333 };
3334 static const unsigned int scif2_clk_mux[] = {
3335         SCK2_MARK,
3336 };
3337 static const unsigned int scif2_data_b_pins[] = {
3338         /* RX, TX */
3339         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3340 };
3341 static const unsigned int scif2_data_b_mux[] = {
3342         RX2_B_MARK, TX2_B_MARK,
3343 };
3344 /* - SCIF3 ------------------------------------------------------------------ */
3345 static const unsigned int scif3_data_a_pins[] = {
3346         /* RX, TX */
3347         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3348 };
3349 static const unsigned int scif3_data_a_mux[] = {
3350         RX3_A_MARK, TX3_A_MARK,
3351 };
3352 static const unsigned int scif3_clk_pins[] = {
3353         /* SCK */
3354         RCAR_GP_PIN(1, 22),
3355 };
3356 static const unsigned int scif3_clk_mux[] = {
3357         SCK3_MARK,
3358 };
3359 static const unsigned int scif3_ctrl_pins[] = {
3360         /* RTS, CTS */
3361         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3362 };
3363 static const unsigned int scif3_ctrl_mux[] = {
3364         RTS3_N_MARK, CTS3_N_MARK,
3365 };
3366 static const unsigned int scif3_data_b_pins[] = {
3367         /* RX, TX */
3368         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3369 };
3370 static const unsigned int scif3_data_b_mux[] = {
3371         RX3_B_MARK, TX3_B_MARK,
3372 };
3373 /* - SCIF4 ------------------------------------------------------------------ */
3374 static const unsigned int scif4_data_a_pins[] = {
3375         /* RX, TX */
3376         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3377 };
3378 static const unsigned int scif4_data_a_mux[] = {
3379         RX4_A_MARK, TX4_A_MARK,
3380 };
3381 static const unsigned int scif4_clk_a_pins[] = {
3382         /* SCK */
3383         RCAR_GP_PIN(2, 10),
3384 };
3385 static const unsigned int scif4_clk_a_mux[] = {
3386         SCK4_A_MARK,
3387 };
3388 static const unsigned int scif4_ctrl_a_pins[] = {
3389         /* RTS, CTS */
3390         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3391 };
3392 static const unsigned int scif4_ctrl_a_mux[] = {
3393         RTS4_N_A_MARK, CTS4_N_A_MARK,
3394 };
3395 static const unsigned int scif4_data_b_pins[] = {
3396         /* RX, TX */
3397         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3398 };
3399 static const unsigned int scif4_data_b_mux[] = {
3400         RX4_B_MARK, TX4_B_MARK,
3401 };
3402 static const unsigned int scif4_clk_b_pins[] = {
3403         /* SCK */
3404         RCAR_GP_PIN(1, 5),
3405 };
3406 static const unsigned int scif4_clk_b_mux[] = {
3407         SCK4_B_MARK,
3408 };
3409 static const unsigned int scif4_ctrl_b_pins[] = {
3410         /* RTS, CTS */
3411         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3412 };
3413 static const unsigned int scif4_ctrl_b_mux[] = {
3414         RTS4_N_B_MARK, CTS4_N_B_MARK,
3415 };
3416 static const unsigned int scif4_data_c_pins[] = {
3417         /* RX, TX */
3418         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3419 };
3420 static const unsigned int scif4_data_c_mux[] = {
3421         RX4_C_MARK, TX4_C_MARK,
3422 };
3423 static const unsigned int scif4_clk_c_pins[] = {
3424         /* SCK */
3425         RCAR_GP_PIN(0, 8),
3426 };
3427 static const unsigned int scif4_clk_c_mux[] = {
3428         SCK4_C_MARK,
3429 };
3430 static const unsigned int scif4_ctrl_c_pins[] = {
3431         /* RTS, CTS */
3432         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3433 };
3434 static const unsigned int scif4_ctrl_c_mux[] = {
3435         RTS4_N_C_MARK, CTS4_N_C_MARK,
3436 };
3437 /* - SCIF5 ------------------------------------------------------------------ */
3438 static const unsigned int scif5_data_a_pins[] = {
3439         /* RX, TX */
3440         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3441 };
3442 static const unsigned int scif5_data_a_mux[] = {
3443         RX5_A_MARK, TX5_A_MARK,
3444 };
3445 static const unsigned int scif5_clk_a_pins[] = {
3446         /* SCK */
3447         RCAR_GP_PIN(6, 21),
3448 };
3449 static const unsigned int scif5_clk_a_mux[] = {
3450         SCK5_A_MARK,
3451 };
3452
3453 static const unsigned int scif5_data_b_pins[] = {
3454         /* RX, TX */
3455         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3456 };
3457 static const unsigned int scif5_data_b_mux[] = {
3458         RX5_B_MARK, TX5_B_MARK,
3459 };
3460 static const unsigned int scif5_clk_b_pins[] = {
3461         /* SCK */
3462         RCAR_GP_PIN(5, 0),
3463 };
3464 static const unsigned int scif5_clk_b_mux[] = {
3465         SCK5_B_MARK,
3466 };
3467
3468 /* - SCIF Clock ------------------------------------------------------------- */
3469 static const unsigned int scif_clk_a_pins[] = {
3470         /* SCIF_CLK */
3471         RCAR_GP_PIN(6, 23),
3472 };
3473 static const unsigned int scif_clk_a_mux[] = {
3474         SCIF_CLK_A_MARK,
3475 };
3476 static const unsigned int scif_clk_b_pins[] = {
3477         /* SCIF_CLK */
3478         RCAR_GP_PIN(5, 9),
3479 };
3480 static const unsigned int scif_clk_b_mux[] = {
3481         SCIF_CLK_B_MARK,
3482 };
3483
3484 /* - SDHI0 ------------------------------------------------------------------ */
3485 static const unsigned int sdhi0_data1_pins[] = {
3486         /* D0 */
3487         RCAR_GP_PIN(3, 2),
3488 };
3489 static const unsigned int sdhi0_data1_mux[] = {
3490         SD0_DAT0_MARK,
3491 };
3492 static const unsigned int sdhi0_data4_pins[] = {
3493         /* D[0:3] */
3494         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3495         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3496 };
3497 static const unsigned int sdhi0_data4_mux[] = {
3498         SD0_DAT0_MARK, SD0_DAT1_MARK,
3499         SD0_DAT2_MARK, SD0_DAT3_MARK,
3500 };
3501 static const unsigned int sdhi0_ctrl_pins[] = {
3502         /* CLK, CMD */
3503         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3504 };
3505 static const unsigned int sdhi0_ctrl_mux[] = {
3506         SD0_CLK_MARK, SD0_CMD_MARK,
3507 };
3508 static const unsigned int sdhi0_cd_pins[] = {
3509         /* CD */
3510         RCAR_GP_PIN(3, 12),
3511 };
3512 static const unsigned int sdhi0_cd_mux[] = {
3513         SD0_CD_MARK,
3514 };
3515 static const unsigned int sdhi0_wp_pins[] = {
3516         /* WP */
3517         RCAR_GP_PIN(3, 13),
3518 };
3519 static const unsigned int sdhi0_wp_mux[] = {
3520         SD0_WP_MARK,
3521 };
3522 /* - SDHI1 ------------------------------------------------------------------ */
3523 static const unsigned int sdhi1_data1_pins[] = {
3524         /* D0 */
3525         RCAR_GP_PIN(3, 8),
3526 };
3527 static const unsigned int sdhi1_data1_mux[] = {
3528         SD1_DAT0_MARK,
3529 };
3530 static const unsigned int sdhi1_data4_pins[] = {
3531         /* D[0:3] */
3532         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3533         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3534 };
3535 static const unsigned int sdhi1_data4_mux[] = {
3536         SD1_DAT0_MARK, SD1_DAT1_MARK,
3537         SD1_DAT2_MARK, SD1_DAT3_MARK,
3538 };
3539 static const unsigned int sdhi1_ctrl_pins[] = {
3540         /* CLK, CMD */
3541         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3542 };
3543 static const unsigned int sdhi1_ctrl_mux[] = {
3544         SD1_CLK_MARK, SD1_CMD_MARK,
3545 };
3546 static const unsigned int sdhi1_cd_pins[] = {
3547         /* CD */
3548         RCAR_GP_PIN(3, 14),
3549 };
3550 static const unsigned int sdhi1_cd_mux[] = {
3551         SD1_CD_MARK,
3552 };
3553 static const unsigned int sdhi1_wp_pins[] = {
3554         /* WP */
3555         RCAR_GP_PIN(3, 15),
3556 };
3557 static const unsigned int sdhi1_wp_mux[] = {
3558         SD1_WP_MARK,
3559 };
3560 /* - SDHI2 ------------------------------------------------------------------ */
3561 static const unsigned int sdhi2_data1_pins[] = {
3562         /* D0 */
3563         RCAR_GP_PIN(4, 2),
3564 };
3565 static const unsigned int sdhi2_data1_mux[] = {
3566         SD2_DAT0_MARK,
3567 };
3568 static const unsigned int sdhi2_data4_pins[] = {
3569         /* D[0:3] */
3570         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3571         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3572 };
3573 static const unsigned int sdhi2_data4_mux[] = {
3574         SD2_DAT0_MARK, SD2_DAT1_MARK,
3575         SD2_DAT2_MARK, SD2_DAT3_MARK,
3576 };
3577 static const unsigned int sdhi2_data8_pins[] = {
3578         /* D[0:7] */
3579         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3580         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3581         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3582         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3583 };
3584 static const unsigned int sdhi2_data8_mux[] = {
3585         SD2_DAT0_MARK, SD2_DAT1_MARK,
3586         SD2_DAT2_MARK, SD2_DAT3_MARK,
3587         SD2_DAT4_MARK, SD2_DAT5_MARK,
3588         SD2_DAT6_MARK, SD2_DAT7_MARK,
3589 };
3590 static const unsigned int sdhi2_ctrl_pins[] = {
3591         /* CLK, CMD */
3592         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3593 };
3594 static const unsigned int sdhi2_ctrl_mux[] = {
3595         SD2_CLK_MARK, SD2_CMD_MARK,
3596 };
3597 static const unsigned int sdhi2_cd_a_pins[] = {
3598         /* CD */
3599         RCAR_GP_PIN(4, 13),
3600 };
3601 static const unsigned int sdhi2_cd_a_mux[] = {
3602         SD2_CD_A_MARK,
3603 };
3604 static const unsigned int sdhi2_cd_b_pins[] = {
3605         /* CD */
3606         RCAR_GP_PIN(5, 10),
3607 };
3608 static const unsigned int sdhi2_cd_b_mux[] = {
3609         SD2_CD_B_MARK,
3610 };
3611 static const unsigned int sdhi2_wp_a_pins[] = {
3612         /* WP */
3613         RCAR_GP_PIN(4, 14),
3614 };
3615 static const unsigned int sdhi2_wp_a_mux[] = {
3616         SD2_WP_A_MARK,
3617 };
3618 static const unsigned int sdhi2_wp_b_pins[] = {
3619         /* WP */
3620         RCAR_GP_PIN(5, 11),
3621 };
3622 static const unsigned int sdhi2_wp_b_mux[] = {
3623         SD2_WP_B_MARK,
3624 };
3625 static const unsigned int sdhi2_ds_pins[] = {
3626         /* DS */
3627         RCAR_GP_PIN(4, 6),
3628 };
3629 static const unsigned int sdhi2_ds_mux[] = {
3630         SD2_DS_MARK,
3631 };
3632 /* - SDHI3 ------------------------------------------------------------------ */
3633 static const unsigned int sdhi3_data1_pins[] = {
3634         /* D0 */
3635         RCAR_GP_PIN(4, 9),
3636 };
3637 static const unsigned int sdhi3_data1_mux[] = {
3638         SD3_DAT0_MARK,
3639 };
3640 static const unsigned int sdhi3_data4_pins[] = {
3641         /* D[0:3] */
3642         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3643         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3644 };
3645 static const unsigned int sdhi3_data4_mux[] = {
3646         SD3_DAT0_MARK, SD3_DAT1_MARK,
3647         SD3_DAT2_MARK, SD3_DAT3_MARK,
3648 };
3649 static const unsigned int sdhi3_data8_pins[] = {
3650         /* D[0:7] */
3651         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3652         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3653         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3654         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3655 };
3656 static const unsigned int sdhi3_data8_mux[] = {
3657         SD3_DAT0_MARK, SD3_DAT1_MARK,
3658         SD3_DAT2_MARK, SD3_DAT3_MARK,
3659         SD3_DAT4_MARK, SD3_DAT5_MARK,
3660         SD3_DAT6_MARK, SD3_DAT7_MARK,
3661 };
3662 static const unsigned int sdhi3_ctrl_pins[] = {
3663         /* CLK, CMD */
3664         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3665 };
3666 static const unsigned int sdhi3_ctrl_mux[] = {
3667         SD3_CLK_MARK, SD3_CMD_MARK,
3668 };
3669 static const unsigned int sdhi3_cd_pins[] = {
3670         /* CD */
3671         RCAR_GP_PIN(4, 15),
3672 };
3673 static const unsigned int sdhi3_cd_mux[] = {
3674         SD3_CD_MARK,
3675 };
3676 static const unsigned int sdhi3_wp_pins[] = {
3677         /* WP */
3678         RCAR_GP_PIN(4, 16),
3679 };
3680 static const unsigned int sdhi3_wp_mux[] = {
3681         SD3_WP_MARK,
3682 };
3683 static const unsigned int sdhi3_ds_pins[] = {
3684         /* DS */
3685         RCAR_GP_PIN(4, 17),
3686 };
3687 static const unsigned int sdhi3_ds_mux[] = {
3688         SD3_DS_MARK,
3689 };
3690
3691 /* - SSI -------------------------------------------------------------------- */
3692 static const unsigned int ssi0_data_pins[] = {
3693         /* SDATA */
3694         RCAR_GP_PIN(6, 2),
3695 };
3696 static const unsigned int ssi0_data_mux[] = {
3697         SSI_SDATA0_MARK,
3698 };
3699 static const unsigned int ssi01239_ctrl_pins[] = {
3700         /* SCK, WS */
3701         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3702 };
3703 static const unsigned int ssi01239_ctrl_mux[] = {
3704         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3705 };
3706 static const unsigned int ssi1_data_a_pins[] = {
3707         /* SDATA */
3708         RCAR_GP_PIN(6, 3),
3709 };
3710 static const unsigned int ssi1_data_a_mux[] = {
3711         SSI_SDATA1_A_MARK,
3712 };
3713 static const unsigned int ssi1_data_b_pins[] = {
3714         /* SDATA */
3715         RCAR_GP_PIN(5, 12),
3716 };
3717 static const unsigned int ssi1_data_b_mux[] = {
3718         SSI_SDATA1_B_MARK,
3719 };
3720 static const unsigned int ssi1_ctrl_a_pins[] = {
3721         /* SCK, WS */
3722         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3723 };
3724 static const unsigned int ssi1_ctrl_a_mux[] = {
3725         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3726 };
3727 static const unsigned int ssi1_ctrl_b_pins[] = {
3728         /* SCK, WS */
3729         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3730 };
3731 static const unsigned int ssi1_ctrl_b_mux[] = {
3732         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3733 };
3734 static const unsigned int ssi2_data_a_pins[] = {
3735         /* SDATA */
3736         RCAR_GP_PIN(6, 4),
3737 };
3738 static const unsigned int ssi2_data_a_mux[] = {
3739         SSI_SDATA2_A_MARK,
3740 };
3741 static const unsigned int ssi2_data_b_pins[] = {
3742         /* SDATA */
3743         RCAR_GP_PIN(5, 13),
3744 };
3745 static const unsigned int ssi2_data_b_mux[] = {
3746         SSI_SDATA2_B_MARK,
3747 };
3748 static const unsigned int ssi2_ctrl_a_pins[] = {
3749         /* SCK, WS */
3750         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3751 };
3752 static const unsigned int ssi2_ctrl_a_mux[] = {
3753         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3754 };
3755 static const unsigned int ssi2_ctrl_b_pins[] = {
3756         /* SCK, WS */
3757         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3758 };
3759 static const unsigned int ssi2_ctrl_b_mux[] = {
3760         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3761 };
3762 static const unsigned int ssi3_data_pins[] = {
3763         /* SDATA */
3764         RCAR_GP_PIN(6, 7),
3765 };
3766 static const unsigned int ssi3_data_mux[] = {
3767         SSI_SDATA3_MARK,
3768 };
3769 static const unsigned int ssi349_ctrl_pins[] = {
3770         /* SCK, WS */
3771         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3772 };
3773 static const unsigned int ssi349_ctrl_mux[] = {
3774         SSI_SCK349_MARK, SSI_WS349_MARK,
3775 };
3776 static const unsigned int ssi4_data_pins[] = {
3777         /* SDATA */
3778         RCAR_GP_PIN(6, 10),
3779 };
3780 static const unsigned int ssi4_data_mux[] = {
3781         SSI_SDATA4_MARK,
3782 };
3783 static const unsigned int ssi4_ctrl_pins[] = {
3784         /* SCK, WS */
3785         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3786 };
3787 static const unsigned int ssi4_ctrl_mux[] = {
3788         SSI_SCK4_MARK, SSI_WS4_MARK,
3789 };
3790 static const unsigned int ssi5_data_pins[] = {
3791         /* SDATA */
3792         RCAR_GP_PIN(6, 13),
3793 };
3794 static const unsigned int ssi5_data_mux[] = {
3795         SSI_SDATA5_MARK,
3796 };
3797 static const unsigned int ssi5_ctrl_pins[] = {
3798         /* SCK, WS */
3799         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3800 };
3801 static const unsigned int ssi5_ctrl_mux[] = {
3802         SSI_SCK5_MARK, SSI_WS5_MARK,
3803 };
3804 static const unsigned int ssi6_data_pins[] = {
3805         /* SDATA */
3806         RCAR_GP_PIN(6, 16),
3807 };
3808 static const unsigned int ssi6_data_mux[] = {
3809         SSI_SDATA6_MARK,
3810 };
3811 static const unsigned int ssi6_ctrl_pins[] = {
3812         /* SCK, WS */
3813         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3814 };
3815 static const unsigned int ssi6_ctrl_mux[] = {
3816         SSI_SCK6_MARK, SSI_WS6_MARK,
3817 };
3818 static const unsigned int ssi7_data_pins[] = {
3819         /* SDATA */
3820         RCAR_GP_PIN(6, 19),
3821 };
3822 static const unsigned int ssi7_data_mux[] = {
3823         SSI_SDATA7_MARK,
3824 };
3825 static const unsigned int ssi78_ctrl_pins[] = {
3826         /* SCK, WS */
3827         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3828 };
3829 static const unsigned int ssi78_ctrl_mux[] = {
3830         SSI_SCK78_MARK, SSI_WS78_MARK,
3831 };
3832 static const unsigned int ssi8_data_pins[] = {
3833         /* SDATA */
3834         RCAR_GP_PIN(6, 20),
3835 };
3836 static const unsigned int ssi8_data_mux[] = {
3837         SSI_SDATA8_MARK,
3838 };
3839 static const unsigned int ssi9_data_a_pins[] = {
3840         /* SDATA */
3841         RCAR_GP_PIN(6, 21),
3842 };
3843 static const unsigned int ssi9_data_a_mux[] = {
3844         SSI_SDATA9_A_MARK,
3845 };
3846 static const unsigned int ssi9_data_b_pins[] = {
3847         /* SDATA */
3848         RCAR_GP_PIN(5, 14),
3849 };
3850 static const unsigned int ssi9_data_b_mux[] = {
3851         SSI_SDATA9_B_MARK,
3852 };
3853 static const unsigned int ssi9_ctrl_a_pins[] = {
3854         /* SCK, WS */
3855         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3856 };
3857 static const unsigned int ssi9_ctrl_a_mux[] = {
3858         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3859 };
3860 static const unsigned int ssi9_ctrl_b_pins[] = {
3861         /* SCK, WS */
3862         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3863 };
3864 static const unsigned int ssi9_ctrl_b_mux[] = {
3865         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3866 };
3867
3868 /* - TMU -------------------------------------------------------------------- */
3869 static const unsigned int tmu_tclk1_a_pins[] = {
3870         /* TCLK */
3871         RCAR_GP_PIN(6, 23),
3872 };
3873 static const unsigned int tmu_tclk1_a_mux[] = {
3874         TCLK1_A_MARK,
3875 };
3876 static const unsigned int tmu_tclk1_b_pins[] = {
3877         /* TCLK */
3878         RCAR_GP_PIN(5, 19),
3879 };
3880 static const unsigned int tmu_tclk1_b_mux[] = {
3881         TCLK1_B_MARK,
3882 };
3883 static const unsigned int tmu_tclk2_a_pins[] = {
3884         /* TCLK */
3885         RCAR_GP_PIN(6, 19),
3886 };
3887 static const unsigned int tmu_tclk2_a_mux[] = {
3888         TCLK2_A_MARK,
3889 };
3890 static const unsigned int tmu_tclk2_b_pins[] = {
3891         /* TCLK */
3892         RCAR_GP_PIN(6, 28),
3893 };
3894 static const unsigned int tmu_tclk2_b_mux[] = {
3895         TCLK2_B_MARK,
3896 };
3897
3898 /* - USB0 ------------------------------------------------------------------- */
3899 static const unsigned int usb0_pins[] = {
3900         /* PWEN, OVC */
3901         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3902 };
3903 static const unsigned int usb0_mux[] = {
3904         USB0_PWEN_MARK, USB0_OVC_MARK,
3905 };
3906 /* - USB1 ------------------------------------------------------------------- */
3907 static const unsigned int usb1_pins[] = {
3908         /* PWEN, OVC */
3909         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3910 };
3911 static const unsigned int usb1_mux[] = {
3912         USB1_PWEN_MARK, USB1_OVC_MARK,
3913 };
3914
3915 /* - USB30 ------------------------------------------------------------------ */
3916 static const unsigned int usb30_pins[] = {
3917         /* PWEN, OVC */
3918         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3919 };
3920 static const unsigned int usb30_mux[] = {
3921         USB30_PWEN_MARK, USB30_OVC_MARK,
3922 };
3923
3924 /* - VIN4 ------------------------------------------------------------------- */
3925 static const unsigned int vin4_data18_a_pins[] = {
3926         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3927         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3928         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3929         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3930         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3931         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3932         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3933         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3934         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3935 };
3936 static const unsigned int vin4_data18_a_mux[] = {
3937         VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3938         VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3939         VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3940         VI4_DATA10_MARK, VI4_DATA11_MARK,
3941         VI4_DATA12_MARK, VI4_DATA13_MARK,
3942         VI4_DATA14_MARK, VI4_DATA15_MARK,
3943         VI4_DATA18_MARK, VI4_DATA19_MARK,
3944         VI4_DATA20_MARK, VI4_DATA21_MARK,
3945         VI4_DATA22_MARK, VI4_DATA23_MARK,
3946 };
3947 static const unsigned int vin4_data18_b_pins[] = {
3948         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3949         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3950         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3951         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3952         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3953         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3954         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3955         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3956         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3957 };
3958 static const unsigned int vin4_data18_b_mux[] = {
3959         VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3960         VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3961         VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3962         VI4_DATA10_MARK, VI4_DATA11_MARK,
3963         VI4_DATA12_MARK, VI4_DATA13_MARK,
3964         VI4_DATA14_MARK, VI4_DATA15_MARK,
3965         VI4_DATA18_MARK, VI4_DATA19_MARK,
3966         VI4_DATA20_MARK, VI4_DATA21_MARK,
3967         VI4_DATA22_MARK, VI4_DATA23_MARK,
3968 };
3969 static const union vin_data vin4_data_a_pins = {
3970         .data24 = {
3971                 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3972                 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3973                 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3974                 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3975                 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3976                 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3977                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3978                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3979                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3980                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3981                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3982                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3983         },
3984 };
3985 static const union vin_data vin4_data_a_mux = {
3986         .data24 = {
3987                 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3988                 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3989                 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3990                 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3991                 VI4_DATA8_MARK,  VI4_DATA9_MARK,
3992                 VI4_DATA10_MARK, VI4_DATA11_MARK,
3993                 VI4_DATA12_MARK, VI4_DATA13_MARK,
3994                 VI4_DATA14_MARK, VI4_DATA15_MARK,
3995                 VI4_DATA16_MARK, VI4_DATA17_MARK,
3996                 VI4_DATA18_MARK, VI4_DATA19_MARK,
3997                 VI4_DATA20_MARK, VI4_DATA21_MARK,
3998                 VI4_DATA22_MARK, VI4_DATA23_MARK,
3999         },
4000 };
4001 static const union vin_data vin4_data_b_pins = {
4002         .data24 = {
4003                 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4004                 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4005                 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4006                 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4007                 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4008                 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4009                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4010                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4011                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4012                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4013                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4014                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4015         },
4016 };
4017 static const union vin_data vin4_data_b_mux = {
4018         .data24 = {
4019                 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4020                 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4021                 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4022                 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4023                 VI4_DATA8_MARK,  VI4_DATA9_MARK,
4024                 VI4_DATA10_MARK, VI4_DATA11_MARK,
4025                 VI4_DATA12_MARK, VI4_DATA13_MARK,
4026                 VI4_DATA14_MARK, VI4_DATA15_MARK,
4027                 VI4_DATA16_MARK, VI4_DATA17_MARK,
4028                 VI4_DATA18_MARK, VI4_DATA19_MARK,
4029                 VI4_DATA20_MARK, VI4_DATA21_MARK,
4030                 VI4_DATA22_MARK, VI4_DATA23_MARK,
4031         },
4032 };
4033 static const unsigned int vin4_sync_pins[] = {
4034         /* HSYNC#, VSYNC# */
4035         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4036 };
4037 static const unsigned int vin4_sync_mux[] = {
4038         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4039 };
4040 static const unsigned int vin4_field_pins[] = {
4041         /* FIELD */
4042         RCAR_GP_PIN(1, 16),
4043 };
4044 static const unsigned int vin4_field_mux[] = {
4045         VI4_FIELD_MARK,
4046 };
4047 static const unsigned int vin4_clkenb_pins[] = {
4048         /* CLKENB */
4049         RCAR_GP_PIN(1, 19),
4050 };
4051 static const unsigned int vin4_clkenb_mux[] = {
4052         VI4_CLKENB_MARK,
4053 };
4054 static const unsigned int vin4_clk_pins[] = {
4055         /* CLK */
4056         RCAR_GP_PIN(1, 27),
4057 };
4058 static const unsigned int vin4_clk_mux[] = {
4059         VI4_CLK_MARK,
4060 };
4061
4062 /* - VIN5 ------------------------------------------------------------------- */
4063 static const union vin_data16 vin5_data_pins = {
4064         .data16 = {
4065                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4066                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4067                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4068                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4069                 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4070                 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4071                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4072                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4073         },
4074 };
4075 static const union vin_data16 vin5_data_mux = {
4076         .data16 = {
4077                 VI5_DATA0_MARK, VI5_DATA1_MARK,
4078                 VI5_DATA2_MARK, VI5_DATA3_MARK,
4079                 VI5_DATA4_MARK, VI5_DATA5_MARK,
4080                 VI5_DATA6_MARK, VI5_DATA7_MARK,
4081                 VI5_DATA8_MARK,  VI5_DATA9_MARK,
4082                 VI5_DATA10_MARK, VI5_DATA11_MARK,
4083                 VI5_DATA12_MARK, VI5_DATA13_MARK,
4084                 VI5_DATA14_MARK, VI5_DATA15_MARK,
4085         },
4086 };
4087 static const unsigned int vin5_sync_pins[] = {
4088         /* HSYNC#, VSYNC# */
4089         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4090 };
4091 static const unsigned int vin5_sync_mux[] = {
4092         VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4093 };
4094 static const unsigned int vin5_field_pins[] = {
4095         RCAR_GP_PIN(1, 11),
4096 };
4097 static const unsigned int vin5_field_mux[] = {
4098         /* FIELD */
4099         VI5_FIELD_MARK,
4100 };
4101 static const unsigned int vin5_clkenb_pins[] = {
4102         RCAR_GP_PIN(1, 20),
4103 };
4104 static const unsigned int vin5_clkenb_mux[] = {
4105         /* CLKENB */
4106         VI5_CLKENB_MARK,
4107 };
4108 static const unsigned int vin5_clk_pins[] = {
4109         RCAR_GP_PIN(1, 21),
4110 };
4111 static const unsigned int vin5_clk_mux[] = {
4112         /* CLK */
4113         VI5_CLK_MARK,
4114 };
4115
4116 static const struct {
4117         struct sh_pfc_pin_group common[312];
4118 #if defined(CONFIG_PINCTRL_PFC_R8A7796)
4119         struct sh_pfc_pin_group automotive[30];
4120 #endif
4121 } pinmux_groups = {
4122         .common = {
4123                 SH_PFC_PIN_GROUP(audio_clk_a_a),
4124                 SH_PFC_PIN_GROUP(audio_clk_a_b),
4125                 SH_PFC_PIN_GROUP(audio_clk_a_c),
4126                 SH_PFC_PIN_GROUP(audio_clk_b_a),
4127                 SH_PFC_PIN_GROUP(audio_clk_b_b),
4128                 SH_PFC_PIN_GROUP(audio_clk_c_a),
4129                 SH_PFC_PIN_GROUP(audio_clk_c_b),
4130                 SH_PFC_PIN_GROUP(audio_clkout_a),
4131                 SH_PFC_PIN_GROUP(audio_clkout_b),
4132                 SH_PFC_PIN_GROUP(audio_clkout_c),
4133                 SH_PFC_PIN_GROUP(audio_clkout_d),
4134                 SH_PFC_PIN_GROUP(audio_clkout1_a),
4135                 SH_PFC_PIN_GROUP(audio_clkout1_b),
4136                 SH_PFC_PIN_GROUP(audio_clkout2_a),
4137                 SH_PFC_PIN_GROUP(audio_clkout2_b),
4138                 SH_PFC_PIN_GROUP(audio_clkout3_a),
4139                 SH_PFC_PIN_GROUP(audio_clkout3_b),
4140                 SH_PFC_PIN_GROUP(avb_link),
4141                 SH_PFC_PIN_GROUP(avb_magic),
4142                 SH_PFC_PIN_GROUP(avb_phy_int),
4143                 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4144                 SH_PFC_PIN_GROUP(avb_mdio),
4145                 SH_PFC_PIN_GROUP(avb_mii),
4146                 SH_PFC_PIN_GROUP(avb_avtp_pps),
4147                 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4148                 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4149                 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4150                 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4151                 SH_PFC_PIN_GROUP(can0_data_a),
4152                 SH_PFC_PIN_GROUP(can0_data_b),
4153                 SH_PFC_PIN_GROUP(can1_data),
4154                 SH_PFC_PIN_GROUP(can_clk),
4155                 SH_PFC_PIN_GROUP(canfd0_data_a),
4156                 SH_PFC_PIN_GROUP(canfd0_data_b),
4157                 SH_PFC_PIN_GROUP(canfd1_data),
4158                 SH_PFC_PIN_GROUP(du_rgb666),
4159                 SH_PFC_PIN_GROUP(du_rgb888),
4160                 SH_PFC_PIN_GROUP(du_clk_out_0),
4161                 SH_PFC_PIN_GROUP(du_clk_out_1),
4162                 SH_PFC_PIN_GROUP(du_sync),
4163                 SH_PFC_PIN_GROUP(du_oddf),
4164                 SH_PFC_PIN_GROUP(du_cde),
4165                 SH_PFC_PIN_GROUP(du_disp),
4166                 SH_PFC_PIN_GROUP(hscif0_data),
4167                 SH_PFC_PIN_GROUP(hscif0_clk),
4168                 SH_PFC_PIN_GROUP(hscif0_ctrl),
4169                 SH_PFC_PIN_GROUP(hscif1_data_a),
4170                 SH_PFC_PIN_GROUP(hscif1_clk_a),
4171                 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4172                 SH_PFC_PIN_GROUP(hscif1_data_b),
4173                 SH_PFC_PIN_GROUP(hscif1_clk_b),
4174                 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4175                 SH_PFC_PIN_GROUP(hscif2_data_a),
4176                 SH_PFC_PIN_GROUP(hscif2_clk_a),
4177                 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4178                 SH_PFC_PIN_GROUP(hscif2_data_b),
4179                 SH_PFC_PIN_GROUP(hscif2_clk_b),
4180                 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4181                 SH_PFC_PIN_GROUP(hscif2_data_c),
4182                 SH_PFC_PIN_GROUP(hscif2_clk_c),
4183                 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4184                 SH_PFC_PIN_GROUP(hscif3_data_a),
4185                 SH_PFC_PIN_GROUP(hscif3_clk),
4186                 SH_PFC_PIN_GROUP(hscif3_ctrl),
4187                 SH_PFC_PIN_GROUP(hscif3_data_b),
4188                 SH_PFC_PIN_GROUP(hscif3_data_c),
4189                 SH_PFC_PIN_GROUP(hscif3_data_d),
4190                 SH_PFC_PIN_GROUP(hscif4_data_a),
4191                 SH_PFC_PIN_GROUP(hscif4_clk),
4192                 SH_PFC_PIN_GROUP(hscif4_ctrl),
4193                 SH_PFC_PIN_GROUP(hscif4_data_b),
4194                 SH_PFC_PIN_GROUP(i2c0),
4195                 SH_PFC_PIN_GROUP(i2c1_a),
4196                 SH_PFC_PIN_GROUP(i2c1_b),
4197                 SH_PFC_PIN_GROUP(i2c2_a),
4198                 SH_PFC_PIN_GROUP(i2c2_b),
4199                 SH_PFC_PIN_GROUP(i2c3),
4200                 SH_PFC_PIN_GROUP(i2c5),
4201                 SH_PFC_PIN_GROUP(i2c6_a),
4202                 SH_PFC_PIN_GROUP(i2c6_b),
4203                 SH_PFC_PIN_GROUP(i2c6_c),
4204                 SH_PFC_PIN_GROUP(intc_ex_irq0),
4205                 SH_PFC_PIN_GROUP(intc_ex_irq1),
4206                 SH_PFC_PIN_GROUP(intc_ex_irq2),
4207                 SH_PFC_PIN_GROUP(intc_ex_irq3),
4208                 SH_PFC_PIN_GROUP(intc_ex_irq4),
4209                 SH_PFC_PIN_GROUP(intc_ex_irq5),
4210                 SH_PFC_PIN_GROUP(msiof0_clk),
4211                 SH_PFC_PIN_GROUP(msiof0_sync),
4212                 SH_PFC_PIN_GROUP(msiof0_ss1),
4213                 SH_PFC_PIN_GROUP(msiof0_ss2),
4214                 SH_PFC_PIN_GROUP(msiof0_txd),
4215                 SH_PFC_PIN_GROUP(msiof0_rxd),
4216                 SH_PFC_PIN_GROUP(msiof1_clk_a),
4217                 SH_PFC_PIN_GROUP(msiof1_sync_a),
4218                 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4219                 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4220                 SH_PFC_PIN_GROUP(msiof1_txd_a),
4221                 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4222                 SH_PFC_PIN_GROUP(msiof1_clk_b),
4223                 SH_PFC_PIN_GROUP(msiof1_sync_b),
4224                 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4225                 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4226                 SH_PFC_PIN_GROUP(msiof1_txd_b),
4227                 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4228                 SH_PFC_PIN_GROUP(msiof1_clk_c),
4229                 SH_PFC_PIN_GROUP(msiof1_sync_c),
4230                 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4231                 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4232                 SH_PFC_PIN_GROUP(msiof1_txd_c),
4233                 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4234                 SH_PFC_PIN_GROUP(msiof1_clk_d),
4235                 SH_PFC_PIN_GROUP(msiof1_sync_d),
4236                 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4237                 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4238                 SH_PFC_PIN_GROUP(msiof1_txd_d),
4239                 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4240                 SH_PFC_PIN_GROUP(msiof1_clk_e),
4241                 SH_PFC_PIN_GROUP(msiof1_sync_e),
4242                 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4243                 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4244                 SH_PFC_PIN_GROUP(msiof1_txd_e),
4245                 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4246                 SH_PFC_PIN_GROUP(msiof1_clk_f),
4247                 SH_PFC_PIN_GROUP(msiof1_sync_f),
4248                 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4249                 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4250                 SH_PFC_PIN_GROUP(msiof1_txd_f),
4251                 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4252                 SH_PFC_PIN_GROUP(msiof1_clk_g),
4253                 SH_PFC_PIN_GROUP(msiof1_sync_g),
4254                 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4255                 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4256                 SH_PFC_PIN_GROUP(msiof1_txd_g),
4257                 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4258                 SH_PFC_PIN_GROUP(msiof2_clk_a),
4259                 SH_PFC_PIN_GROUP(msiof2_sync_a),
4260                 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4261                 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4262                 SH_PFC_PIN_GROUP(msiof2_txd_a),
4263                 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4264                 SH_PFC_PIN_GROUP(msiof2_clk_b),
4265                 SH_PFC_PIN_GROUP(msiof2_sync_b),
4266                 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4267                 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4268                 SH_PFC_PIN_GROUP(msiof2_txd_b),
4269                 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4270                 SH_PFC_PIN_GROUP(msiof2_clk_c),
4271                 SH_PFC_PIN_GROUP(msiof2_sync_c),
4272                 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4273                 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4274                 SH_PFC_PIN_GROUP(msiof2_txd_c),
4275                 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4276                 SH_PFC_PIN_GROUP(msiof2_clk_d),
4277                 SH_PFC_PIN_GROUP(msiof2_sync_d),
4278                 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4279                 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4280                 SH_PFC_PIN_GROUP(msiof2_txd_d),
4281                 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4282                 SH_PFC_PIN_GROUP(msiof3_clk_a),
4283                 SH_PFC_PIN_GROUP(msiof3_sync_a),
4284                 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4285                 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4286                 SH_PFC_PIN_GROUP(msiof3_txd_a),
4287                 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4288                 SH_PFC_PIN_GROUP(msiof3_clk_b),
4289                 SH_PFC_PIN_GROUP(msiof3_sync_b),
4290                 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4291                 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4292                 SH_PFC_PIN_GROUP(msiof3_txd_b),
4293                 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4294                 SH_PFC_PIN_GROUP(msiof3_clk_c),
4295                 SH_PFC_PIN_GROUP(msiof3_sync_c),
4296                 SH_PFC_PIN_GROUP(msiof3_txd_c),
4297                 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4298                 SH_PFC_PIN_GROUP(msiof3_clk_d),
4299                 SH_PFC_PIN_GROUP(msiof3_sync_d),
4300                 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4301                 SH_PFC_PIN_GROUP(msiof3_txd_d),
4302                 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4303                 SH_PFC_PIN_GROUP(msiof3_clk_e),
4304                 SH_PFC_PIN_GROUP(msiof3_sync_e),
4305                 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4306                 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4307                 SH_PFC_PIN_GROUP(msiof3_txd_e),
4308                 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4309                 SH_PFC_PIN_GROUP(pwm0),
4310                 SH_PFC_PIN_GROUP(pwm1_a),
4311                 SH_PFC_PIN_GROUP(pwm1_b),
4312                 SH_PFC_PIN_GROUP(pwm2_a),
4313                 SH_PFC_PIN_GROUP(pwm2_b),
4314                 SH_PFC_PIN_GROUP(pwm3_a),
4315                 SH_PFC_PIN_GROUP(pwm3_b),
4316                 SH_PFC_PIN_GROUP(pwm4_a),
4317                 SH_PFC_PIN_GROUP(pwm4_b),
4318                 SH_PFC_PIN_GROUP(pwm5_a),
4319                 SH_PFC_PIN_GROUP(pwm5_b),
4320                 SH_PFC_PIN_GROUP(pwm6_a),
4321                 SH_PFC_PIN_GROUP(pwm6_b),
4322                 SH_PFC_PIN_GROUP(scif0_data),
4323                 SH_PFC_PIN_GROUP(scif0_clk),
4324                 SH_PFC_PIN_GROUP(scif0_ctrl),
4325                 SH_PFC_PIN_GROUP(scif1_data_a),
4326                 SH_PFC_PIN_GROUP(scif1_clk),
4327                 SH_PFC_PIN_GROUP(scif1_ctrl),
4328                 SH_PFC_PIN_GROUP(scif1_data_b),
4329                 SH_PFC_PIN_GROUP(scif2_data_a),
4330                 SH_PFC_PIN_GROUP(scif2_clk),
4331                 SH_PFC_PIN_GROUP(scif2_data_b),
4332                 SH_PFC_PIN_GROUP(scif3_data_a),
4333                 SH_PFC_PIN_GROUP(scif3_clk),
4334                 SH_PFC_PIN_GROUP(scif3_ctrl),
4335                 SH_PFC_PIN_GROUP(scif3_data_b),
4336                 SH_PFC_PIN_GROUP(scif4_data_a),
4337                 SH_PFC_PIN_GROUP(scif4_clk_a),
4338                 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4339                 SH_PFC_PIN_GROUP(scif4_data_b),
4340                 SH_PFC_PIN_GROUP(scif4_clk_b),
4341                 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4342                 SH_PFC_PIN_GROUP(scif4_data_c),
4343                 SH_PFC_PIN_GROUP(scif4_clk_c),
4344                 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4345                 SH_PFC_PIN_GROUP(scif5_data_a),
4346                 SH_PFC_PIN_GROUP(scif5_clk_a),
4347                 SH_PFC_PIN_GROUP(scif5_data_b),
4348                 SH_PFC_PIN_GROUP(scif5_clk_b),
4349                 SH_PFC_PIN_GROUP(scif_clk_a),
4350                 SH_PFC_PIN_GROUP(scif_clk_b),
4351                 SH_PFC_PIN_GROUP(sdhi0_data1),
4352                 SH_PFC_PIN_GROUP(sdhi0_data4),
4353                 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4354                 SH_PFC_PIN_GROUP(sdhi0_cd),
4355                 SH_PFC_PIN_GROUP(sdhi0_wp),
4356                 SH_PFC_PIN_GROUP(sdhi1_data1),
4357                 SH_PFC_PIN_GROUP(sdhi1_data4),
4358                 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4359                 SH_PFC_PIN_GROUP(sdhi1_cd),
4360                 SH_PFC_PIN_GROUP(sdhi1_wp),
4361                 SH_PFC_PIN_GROUP(sdhi2_data1),
4362                 SH_PFC_PIN_GROUP(sdhi2_data4),
4363                 SH_PFC_PIN_GROUP(sdhi2_data8),
4364                 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4365                 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4366                 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4367                 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4368                 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4369                 SH_PFC_PIN_GROUP(sdhi2_ds),
4370                 SH_PFC_PIN_GROUP(sdhi3_data1),
4371                 SH_PFC_PIN_GROUP(sdhi3_data4),
4372                 SH_PFC_PIN_GROUP(sdhi3_data8),
4373                 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4374                 SH_PFC_PIN_GROUP(sdhi3_cd),
4375                 SH_PFC_PIN_GROUP(sdhi3_wp),
4376                 SH_PFC_PIN_GROUP(sdhi3_ds),
4377                 SH_PFC_PIN_GROUP(ssi0_data),
4378                 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4379                 SH_PFC_PIN_GROUP(ssi1_data_a),
4380                 SH_PFC_PIN_GROUP(ssi1_data_b),
4381                 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4382                 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4383                 SH_PFC_PIN_GROUP(ssi2_data_a),
4384                 SH_PFC_PIN_GROUP(ssi2_data_b),
4385                 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4386                 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4387                 SH_PFC_PIN_GROUP(ssi3_data),
4388                 SH_PFC_PIN_GROUP(ssi349_ctrl),
4389                 SH_PFC_PIN_GROUP(ssi4_data),
4390                 SH_PFC_PIN_GROUP(ssi4_ctrl),
4391                 SH_PFC_PIN_GROUP(ssi5_data),
4392                 SH_PFC_PIN_GROUP(ssi5_ctrl),
4393                 SH_PFC_PIN_GROUP(ssi6_data),
4394                 SH_PFC_PIN_GROUP(ssi6_ctrl),
4395                 SH_PFC_PIN_GROUP(ssi7_data),
4396                 SH_PFC_PIN_GROUP(ssi78_ctrl),
4397                 SH_PFC_PIN_GROUP(ssi8_data),
4398                 SH_PFC_PIN_GROUP(ssi9_data_a),
4399                 SH_PFC_PIN_GROUP(ssi9_data_b),
4400                 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4401                 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4402                 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4403                 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4404                 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4405                 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4406                 SH_PFC_PIN_GROUP(usb0),
4407                 SH_PFC_PIN_GROUP(usb1),
4408                 SH_PFC_PIN_GROUP(usb30),
4409                 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4410                 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4411                 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4412                 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4413                 SH_PFC_PIN_GROUP(vin4_data18_a),
4414                 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4415                 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4416                 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4417                 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4418                 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4419                 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4420                 SH_PFC_PIN_GROUP(vin4_data18_b),
4421                 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4422                 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4423                 SH_PFC_PIN_GROUP(vin4_sync),
4424                 SH_PFC_PIN_GROUP(vin4_field),
4425                 SH_PFC_PIN_GROUP(vin4_clkenb),
4426                 SH_PFC_PIN_GROUP(vin4_clk),
4427                 VIN_DATA_PIN_GROUP(vin5_data, 8),
4428                 VIN_DATA_PIN_GROUP(vin5_data, 10),
4429                 VIN_DATA_PIN_GROUP(vin5_data, 12),
4430                 VIN_DATA_PIN_GROUP(vin5_data, 16),
4431                 SH_PFC_PIN_GROUP(vin5_sync),
4432                 SH_PFC_PIN_GROUP(vin5_field),
4433                 SH_PFC_PIN_GROUP(vin5_clkenb),
4434                 SH_PFC_PIN_GROUP(vin5_clk),
4435         },
4436 #if defined(CONFIG_PINCTRL_PFC_R8A7796)
4437         .automotive = {
4438                 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4439                 SH_PFC_PIN_GROUP(drif0_data0_a),
4440                 SH_PFC_PIN_GROUP(drif0_data1_a),
4441                 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4442                 SH_PFC_PIN_GROUP(drif0_data0_b),
4443                 SH_PFC_PIN_GROUP(drif0_data1_b),
4444                 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4445                 SH_PFC_PIN_GROUP(drif0_data0_c),
4446                 SH_PFC_PIN_GROUP(drif0_data1_c),
4447                 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4448                 SH_PFC_PIN_GROUP(drif1_data0_a),
4449                 SH_PFC_PIN_GROUP(drif1_data1_a),
4450                 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4451                 SH_PFC_PIN_GROUP(drif1_data0_b),
4452                 SH_PFC_PIN_GROUP(drif1_data1_b),
4453                 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4454                 SH_PFC_PIN_GROUP(drif1_data0_c),
4455                 SH_PFC_PIN_GROUP(drif1_data1_c),
4456                 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4457                 SH_PFC_PIN_GROUP(drif2_data0_a),
4458                 SH_PFC_PIN_GROUP(drif2_data1_a),
4459                 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4460                 SH_PFC_PIN_GROUP(drif2_data0_b),
4461                 SH_PFC_PIN_GROUP(drif2_data1_b),
4462                 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4463                 SH_PFC_PIN_GROUP(drif3_data0_a),
4464                 SH_PFC_PIN_GROUP(drif3_data1_a),
4465                 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4466                 SH_PFC_PIN_GROUP(drif3_data0_b),
4467                 SH_PFC_PIN_GROUP(drif3_data1_b),
4468         }
4469 #endif /* CONFIG_PINCTRL_PFC_R8A7796 */
4470 };
4471
4472 static const char * const audio_clk_groups[] = {
4473         "audio_clk_a_a",
4474         "audio_clk_a_b",
4475         "audio_clk_a_c",
4476         "audio_clk_b_a",
4477         "audio_clk_b_b",
4478         "audio_clk_c_a",
4479         "audio_clk_c_b",
4480         "audio_clkout_a",
4481         "audio_clkout_b",
4482         "audio_clkout_c",
4483         "audio_clkout_d",
4484         "audio_clkout1_a",
4485         "audio_clkout1_b",
4486         "audio_clkout2_a",
4487         "audio_clkout2_b",
4488         "audio_clkout3_a",
4489         "audio_clkout3_b",
4490 };
4491
4492 static const char * const avb_groups[] = {
4493         "avb_link",
4494         "avb_magic",
4495         "avb_phy_int",
4496         "avb_mdc",      /* Deprecated, please use "avb_mdio" instead */
4497         "avb_mdio",
4498         "avb_mii",
4499         "avb_avtp_pps",
4500         "avb_avtp_match_a",
4501         "avb_avtp_capture_a",
4502         "avb_avtp_match_b",
4503         "avb_avtp_capture_b",
4504 };
4505
4506 static const char * const can0_groups[] = {
4507         "can0_data_a",
4508         "can0_data_b",
4509 };
4510
4511 static const char * const can1_groups[] = {
4512         "can1_data",
4513 };
4514
4515 static const char * const can_clk_groups[] = {
4516         "can_clk",
4517 };
4518
4519 static const char * const canfd0_groups[] = {
4520         "canfd0_data_a",
4521         "canfd0_data_b",
4522 };
4523
4524 static const char * const canfd1_groups[] = {
4525         "canfd1_data",
4526 };
4527
4528 #if defined(CONFIG_PINCTRL_PFC_R8A7796)
4529 static const char * const drif0_groups[] = {
4530         "drif0_ctrl_a",
4531         "drif0_data0_a",
4532         "drif0_data1_a",
4533         "drif0_ctrl_b",
4534         "drif0_data0_b",
4535         "drif0_data1_b",
4536         "drif0_ctrl_c",
4537         "drif0_data0_c",
4538         "drif0_data1_c",
4539 };
4540
4541 static const char * const drif1_groups[] = {
4542         "drif1_ctrl_a",
4543         "drif1_data0_a",
4544         "drif1_data1_a",
4545         "drif1_ctrl_b",
4546         "drif1_data0_b",
4547         "drif1_data1_b",
4548         "drif1_ctrl_c",
4549         "drif1_data0_c",
4550         "drif1_data1_c",
4551 };
4552
4553 static const char * const drif2_groups[] = {
4554         "drif2_ctrl_a",
4555         "drif2_data0_a",
4556         "drif2_data1_a",
4557         "drif2_ctrl_b",
4558         "drif2_data0_b",
4559         "drif2_data1_b",
4560 };
4561
4562 static const char * const drif3_groups[] = {
4563         "drif3_ctrl_a",
4564         "drif3_data0_a",
4565         "drif3_data1_a",
4566         "drif3_ctrl_b",
4567         "drif3_data0_b",
4568         "drif3_data1_b",
4569 };
4570 #endif /* CONFIG_PINCTRL_PFC_R8A7796 */
4571
4572 static const char * const du_groups[] = {
4573         "du_rgb666",
4574         "du_rgb888",
4575         "du_clk_out_0",
4576         "du_clk_out_1",
4577         "du_sync",
4578         "du_oddf",
4579         "du_cde",
4580         "du_disp",
4581 };
4582
4583 static const char * const hscif0_groups[] = {
4584         "hscif0_data",
4585         "hscif0_clk",
4586         "hscif0_ctrl",
4587 };
4588
4589 static const char * const hscif1_groups[] = {
4590         "hscif1_data_a",
4591         "hscif1_clk_a",
4592         "hscif1_ctrl_a",
4593         "hscif1_data_b",
4594         "hscif1_clk_b",
4595         "hscif1_ctrl_b",
4596 };
4597
4598 static const char * const hscif2_groups[] = {
4599         "hscif2_data_a",
4600         "hscif2_clk_a",
4601         "hscif2_ctrl_a",
4602         "hscif2_data_b",
4603         "hscif2_clk_b",
4604         "hscif2_ctrl_b",
4605         "hscif2_data_c",
4606         "hscif2_clk_c",
4607         "hscif2_ctrl_c",
4608 };
4609
4610 static const char * const hscif3_groups[] = {
4611         "hscif3_data_a",
4612         "hscif3_clk",
4613         "hscif3_ctrl",
4614         "hscif3_data_b",
4615         "hscif3_data_c",
4616         "hscif3_data_d",
4617 };
4618
4619 static const char * const hscif4_groups[] = {
4620         "hscif4_data_a",
4621         "hscif4_clk",
4622         "hscif4_ctrl",
4623         "hscif4_data_b",
4624 };
4625
4626 static const char * const i2c0_groups[] = {
4627         "i2c0",
4628 };
4629
4630 static const char * const i2c1_groups[] = {
4631         "i2c1_a",
4632         "i2c1_b",
4633 };
4634
4635 static const char * const i2c2_groups[] = {
4636         "i2c2_a",
4637         "i2c2_b",
4638 };
4639
4640 static const char * const i2c3_groups[] = {
4641         "i2c3",
4642 };
4643
4644 static const char * const i2c5_groups[] = {
4645         "i2c5",
4646 };
4647
4648 static const char * const i2c6_groups[] = {
4649         "i2c6_a",
4650         "i2c6_b",
4651         "i2c6_c",
4652 };
4653
4654 static const char * const intc_ex_groups[] = {
4655         "intc_ex_irq0",
4656         "intc_ex_irq1",
4657         "intc_ex_irq2",
4658         "intc_ex_irq3",
4659         "intc_ex_irq4",
4660         "intc_ex_irq5",
4661 };
4662
4663 static const char * const msiof0_groups[] = {
4664         "msiof0_clk",
4665         "msiof0_sync",
4666         "msiof0_ss1",
4667         "msiof0_ss2",
4668         "msiof0_txd",
4669         "msiof0_rxd",
4670 };
4671
4672 static const char * const msiof1_groups[] = {
4673         "msiof1_clk_a",
4674         "msiof1_sync_a",
4675         "msiof1_ss1_a",
4676         "msiof1_ss2_a",
4677         "msiof1_txd_a",
4678         "msiof1_rxd_a",
4679         "msiof1_clk_b",
4680         "msiof1_sync_b",
4681         "msiof1_ss1_b",
4682         "msiof1_ss2_b",
4683         "msiof1_txd_b",
4684         "msiof1_rxd_b",
4685         "msiof1_clk_c",
4686         "msiof1_sync_c",
4687         "msiof1_ss1_c",
4688         "msiof1_ss2_c",
4689         "msiof1_txd_c",
4690         "msiof1_rxd_c",
4691         "msiof1_clk_d",
4692         "msiof1_sync_d",
4693         "msiof1_ss1_d",
4694         "msiof1_ss2_d",
4695         "msiof1_txd_d",
4696         "msiof1_rxd_d",
4697         "msiof1_clk_e",
4698         "msiof1_sync_e",
4699         "msiof1_ss1_e",
4700         "msiof1_ss2_e",
4701         "msiof1_txd_e",
4702         "msiof1_rxd_e",
4703         "msiof1_clk_f",
4704         "msiof1_sync_f",
4705         "msiof1_ss1_f",
4706         "msiof1_ss2_f",
4707         "msiof1_txd_f",
4708         "msiof1_rxd_f",
4709         "msiof1_clk_g",
4710         "msiof1_sync_g",
4711         "msiof1_ss1_g",
4712         "msiof1_ss2_g",
4713         "msiof1_txd_g",
4714         "msiof1_rxd_g",
4715 };
4716
4717 static const char * const msiof2_groups[] = {
4718         "msiof2_clk_a",
4719         "msiof2_sync_a",
4720         "msiof2_ss1_a",
4721         "msiof2_ss2_a",
4722         "msiof2_txd_a",
4723         "msiof2_rxd_a",
4724         "msiof2_clk_b",
4725         "msiof2_sync_b",
4726         "msiof2_ss1_b",
4727         "msiof2_ss2_b",
4728         "msiof2_txd_b",
4729         "msiof2_rxd_b",
4730         "msiof2_clk_c",
4731         "msiof2_sync_c",
4732         "msiof2_ss1_c",
4733         "msiof2_ss2_c",
4734         "msiof2_txd_c",
4735         "msiof2_rxd_c",
4736         "msiof2_clk_d",
4737         "msiof2_sync_d",
4738         "msiof2_ss1_d",
4739         "msiof2_ss2_d",
4740         "msiof2_txd_d",
4741         "msiof2_rxd_d",
4742 };
4743
4744 static const char * const msiof3_groups[] = {
4745         "msiof3_clk_a",
4746         "msiof3_sync_a",
4747         "msiof3_ss1_a",
4748         "msiof3_ss2_a",
4749         "msiof3_txd_a",
4750         "msiof3_rxd_a",
4751         "msiof3_clk_b",
4752         "msiof3_sync_b",
4753         "msiof3_ss1_b",
4754         "msiof3_ss2_b",
4755         "msiof3_txd_b",
4756         "msiof3_rxd_b",
4757         "msiof3_clk_c",
4758         "msiof3_sync_c",
4759         "msiof3_txd_c",
4760         "msiof3_rxd_c",
4761         "msiof3_clk_d",
4762         "msiof3_sync_d",
4763         "msiof3_ss1_d",
4764         "msiof3_txd_d",
4765         "msiof3_rxd_d",
4766         "msiof3_clk_e",
4767         "msiof3_sync_e",
4768         "msiof3_ss1_e",
4769         "msiof3_ss2_e",
4770         "msiof3_txd_e",
4771         "msiof3_rxd_e",
4772 };
4773
4774 static const char * const pwm0_groups[] = {
4775         "pwm0",
4776 };
4777
4778 static const char * const pwm1_groups[] = {
4779         "pwm1_a",
4780         "pwm1_b",
4781 };
4782
4783 static const char * const pwm2_groups[] = {
4784         "pwm2_a",
4785         "pwm2_b",
4786 };
4787
4788 static const char * const pwm3_groups[] = {
4789         "pwm3_a",
4790         "pwm3_b",
4791 };
4792
4793 static const char * const pwm4_groups[] = {
4794         "pwm4_a",
4795         "pwm4_b",
4796 };
4797
4798 static const char * const pwm5_groups[] = {
4799         "pwm5_a",
4800         "pwm5_b",
4801 };
4802
4803 static const char * const pwm6_groups[] = {
4804         "pwm6_a",
4805         "pwm6_b",
4806 };
4807
4808 static const char * const scif0_groups[] = {
4809         "scif0_data",
4810         "scif0_clk",
4811         "scif0_ctrl",
4812 };
4813
4814 static const char * const scif1_groups[] = {
4815         "scif1_data_a",
4816         "scif1_clk",
4817         "scif1_ctrl",
4818         "scif1_data_b",
4819 };
4820
4821 static const char * const scif2_groups[] = {
4822         "scif2_data_a",
4823         "scif2_clk",
4824         "scif2_data_b",
4825 };
4826
4827 static const char * const scif3_groups[] = {
4828         "scif3_data_a",
4829         "scif3_clk",
4830         "scif3_ctrl",
4831         "scif3_data_b",
4832 };
4833
4834 static const char * const scif4_groups[] = {
4835         "scif4_data_a",
4836         "scif4_clk_a",
4837         "scif4_ctrl_a",
4838         "scif4_data_b",
4839         "scif4_clk_b",
4840         "scif4_ctrl_b",
4841         "scif4_data_c",
4842         "scif4_clk_c",
4843         "scif4_ctrl_c",
4844 };
4845
4846 static const char * const scif5_groups[] = {
4847         "scif5_data_a",
4848         "scif5_clk_a",
4849         "scif5_data_b",
4850         "scif5_clk_b",
4851 };
4852
4853 static const char * const scif_clk_groups[] = {
4854         "scif_clk_a",
4855         "scif_clk_b",
4856 };
4857
4858 static const char * const sdhi0_groups[] = {
4859         "sdhi0_data1",
4860         "sdhi0_data4",
4861         "sdhi0_ctrl",
4862         "sdhi0_cd",
4863         "sdhi0_wp",
4864 };
4865
4866 static const char * const sdhi1_groups[] = {
4867         "sdhi1_data1",
4868         "sdhi1_data4",
4869         "sdhi1_ctrl",
4870         "sdhi1_cd",
4871         "sdhi1_wp",
4872 };
4873
4874 static const char * const sdhi2_groups[] = {
4875         "sdhi2_data1",
4876         "sdhi2_data4",
4877         "sdhi2_data8",
4878         "sdhi2_ctrl",
4879         "sdhi2_cd_a",
4880         "sdhi2_wp_a",
4881         "sdhi2_cd_b",
4882         "sdhi2_wp_b",
4883         "sdhi2_ds",
4884 };
4885
4886 static const char * const sdhi3_groups[] = {
4887         "sdhi3_data1",
4888         "sdhi3_data4",
4889         "sdhi3_data8",
4890         "sdhi3_ctrl",
4891         "sdhi3_cd",
4892         "sdhi3_wp",
4893         "sdhi3_ds",
4894 };
4895
4896 static const char * const ssi_groups[] = {
4897         "ssi0_data",
4898         "ssi01239_ctrl",
4899         "ssi1_data_a",
4900         "ssi1_data_b",
4901         "ssi1_ctrl_a",
4902         "ssi1_ctrl_b",
4903         "ssi2_data_a",
4904         "ssi2_data_b",
4905         "ssi2_ctrl_a",
4906         "ssi2_ctrl_b",
4907         "ssi3_data",
4908         "ssi349_ctrl",
4909         "ssi4_data",
4910         "ssi4_ctrl",
4911         "ssi5_data",
4912         "ssi5_ctrl",
4913         "ssi6_data",
4914         "ssi6_ctrl",
4915         "ssi7_data",
4916         "ssi78_ctrl",
4917         "ssi8_data",
4918         "ssi9_data_a",
4919         "ssi9_data_b",
4920         "ssi9_ctrl_a",
4921         "ssi9_ctrl_b",
4922 };
4923
4924 static const char * const tmu_groups[] = {
4925         "tmu_tclk1_a",
4926         "tmu_tclk1_b",
4927         "tmu_tclk2_a",
4928         "tmu_tclk2_b",
4929 };
4930
4931 static const char * const usb0_groups[] = {
4932         "usb0",
4933 };
4934
4935 static const char * const usb1_groups[] = {
4936         "usb1",
4937 };
4938
4939 static const char * const usb30_groups[] = {
4940         "usb30",
4941 };
4942
4943 static const char * const vin4_groups[] = {
4944         "vin4_data8_a",
4945         "vin4_data10_a",
4946         "vin4_data12_a",
4947         "vin4_data16_a",
4948         "vin4_data18_a",
4949         "vin4_data20_a",
4950         "vin4_data24_a",
4951         "vin4_data8_b",
4952         "vin4_data10_b",
4953         "vin4_data12_b",
4954         "vin4_data16_b",
4955         "vin4_data18_b",
4956         "vin4_data20_b",
4957         "vin4_data24_b",
4958         "vin4_sync",
4959         "vin4_field",
4960         "vin4_clkenb",
4961         "vin4_clk",
4962 };
4963
4964 static const char * const vin5_groups[] = {
4965         "vin5_data8",
4966         "vin5_data10",
4967         "vin5_data12",
4968         "vin5_data16",
4969         "vin5_sync",
4970         "vin5_field",
4971         "vin5_clkenb",
4972         "vin5_clk",
4973 };
4974
4975 static const struct {
4976         struct sh_pfc_function common[49];
4977 #if defined(CONFIG_PINCTRL_PFC_R8A7796)
4978         struct sh_pfc_function automotive[4];
4979 #endif
4980 } pinmux_functions = {
4981         .common = {
4982                 SH_PFC_FUNCTION(audio_clk),
4983                 SH_PFC_FUNCTION(avb),
4984                 SH_PFC_FUNCTION(can0),
4985                 SH_PFC_FUNCTION(can1),
4986                 SH_PFC_FUNCTION(can_clk),
4987                 SH_PFC_FUNCTION(canfd0),
4988                 SH_PFC_FUNCTION(canfd1),
4989                 SH_PFC_FUNCTION(du),
4990                 SH_PFC_FUNCTION(hscif0),
4991                 SH_PFC_FUNCTION(hscif1),
4992                 SH_PFC_FUNCTION(hscif2),
4993                 SH_PFC_FUNCTION(hscif3),
4994                 SH_PFC_FUNCTION(hscif4),
4995                 SH_PFC_FUNCTION(i2c0),
4996                 SH_PFC_FUNCTION(i2c1),
4997                 SH_PFC_FUNCTION(i2c2),
4998                 SH_PFC_FUNCTION(i2c3),
4999                 SH_PFC_FUNCTION(i2c5),
5000                 SH_PFC_FUNCTION(i2c6),
5001                 SH_PFC_FUNCTION(intc_ex),
5002                 SH_PFC_FUNCTION(msiof0),
5003                 SH_PFC_FUNCTION(msiof1),
5004                 SH_PFC_FUNCTION(msiof2),
5005                 SH_PFC_FUNCTION(msiof3),
5006                 SH_PFC_FUNCTION(pwm0),
5007                 SH_PFC_FUNCTION(pwm1),
5008                 SH_PFC_FUNCTION(pwm2),
5009                 SH_PFC_FUNCTION(pwm3),
5010                 SH_PFC_FUNCTION(pwm4),
5011                 SH_PFC_FUNCTION(pwm5),
5012                 SH_PFC_FUNCTION(pwm6),
5013                 SH_PFC_FUNCTION(scif0),
5014                 SH_PFC_FUNCTION(scif1),
5015                 SH_PFC_FUNCTION(scif2),
5016                 SH_PFC_FUNCTION(scif3),
5017                 SH_PFC_FUNCTION(scif4),
5018                 SH_PFC_FUNCTION(scif5),
5019                 SH_PFC_FUNCTION(scif_clk),
5020                 SH_PFC_FUNCTION(sdhi0),
5021                 SH_PFC_FUNCTION(sdhi1),
5022                 SH_PFC_FUNCTION(sdhi2),
5023                 SH_PFC_FUNCTION(sdhi3),
5024                 SH_PFC_FUNCTION(ssi),
5025                 SH_PFC_FUNCTION(tmu),
5026                 SH_PFC_FUNCTION(usb0),
5027                 SH_PFC_FUNCTION(usb1),
5028                 SH_PFC_FUNCTION(usb30),
5029                 SH_PFC_FUNCTION(vin4),
5030                 SH_PFC_FUNCTION(vin5),
5031         },
5032 #if defined(CONFIG_PINCTRL_PFC_R8A7796)
5033         .automotive = {
5034                 SH_PFC_FUNCTION(drif0),
5035                 SH_PFC_FUNCTION(drif1),
5036                 SH_PFC_FUNCTION(drif2),
5037                 SH_PFC_FUNCTION(drif3),
5038         }
5039 #endif /* CONFIG_PINCTRL_PFC_R8A7796 */
5040 };
5041
5042 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5043 #define F_(x, y)        FN_##y
5044 #define FM(x)           FN_##x
5045         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5046                 0, 0,
5047                 0, 0,
5048                 0, 0,
5049                 0, 0,
5050                 0, 0,
5051                 0, 0,
5052                 0, 0,
5053                 0, 0,
5054                 0, 0,
5055                 0, 0,
5056                 0, 0,
5057                 0, 0,
5058                 0, 0,
5059                 0, 0,
5060                 0, 0,
5061                 0, 0,
5062                 GP_0_15_FN,     GPSR0_15,
5063                 GP_0_14_FN,     GPSR0_14,
5064                 GP_0_13_FN,     GPSR0_13,
5065                 GP_0_12_FN,     GPSR0_12,
5066                 GP_0_11_FN,     GPSR0_11,
5067                 GP_0_10_FN,     GPSR0_10,
5068                 GP_0_9_FN,      GPSR0_9,
5069                 GP_0_8_FN,      GPSR0_8,
5070                 GP_0_7_FN,      GPSR0_7,
5071                 GP_0_6_FN,      GPSR0_6,
5072                 GP_0_5_FN,      GPSR0_5,
5073                 GP_0_4_FN,      GPSR0_4,
5074                 GP_0_3_FN,      GPSR0_3,
5075                 GP_0_2_FN,      GPSR0_2,
5076                 GP_0_1_FN,      GPSR0_1,
5077                 GP_0_0_FN,      GPSR0_0, ))
5078         },
5079         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5080                 0, 0,
5081                 0, 0,
5082                 0, 0,
5083                 GP_1_28_FN,     GPSR1_28,
5084                 GP_1_27_FN,     GPSR1_27,
5085                 GP_1_26_FN,     GPSR1_26,
5086                 GP_1_25_FN,     GPSR1_25,
5087                 GP_1_24_FN,     GPSR1_24,
5088                 GP_1_23_FN,     GPSR1_23,
5089                 GP_1_22_FN,     GPSR1_22,
5090                 GP_1_21_FN,     GPSR1_21,
5091                 GP_1_20_FN,     GPSR1_20,
5092                 GP_1_19_FN,     GPSR1_19,
5093                 GP_1_18_FN,     GPSR1_18,
5094                 GP_1_17_FN,     GPSR1_17,
5095                 GP_1_16_FN,     GPSR1_16,
5096                 GP_1_15_FN,     GPSR1_15,
5097                 GP_1_14_FN,     GPSR1_14,
5098                 GP_1_13_FN,     GPSR1_13,
5099                 GP_1_12_FN,     GPSR1_12,
5100                 GP_1_11_FN,     GPSR1_11,
5101                 GP_1_10_FN,     GPSR1_10,
5102                 GP_1_9_FN,      GPSR1_9,
5103                 GP_1_8_FN,      GPSR1_8,
5104                 GP_1_7_FN,      GPSR1_7,
5105                 GP_1_6_FN,      GPSR1_6,
5106                 GP_1_5_FN,      GPSR1_5,
5107                 GP_1_4_FN,      GPSR1_4,
5108                 GP_1_3_FN,      GPSR1_3,
5109                 GP_1_2_FN,      GPSR1_2,
5110                 GP_1_1_FN,      GPSR1_1,
5111                 GP_1_0_FN,      GPSR1_0, ))
5112         },
5113         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5114                 0, 0,
5115                 0, 0,
5116                 0, 0,
5117                 0, 0,
5118                 0, 0,
5119                 0, 0,
5120                 0, 0,
5121                 0, 0,
5122                 0, 0,
5123                 0, 0,
5124                 0, 0,
5125                 0, 0,
5126                 0, 0,
5127                 0, 0,
5128                 0, 0,
5129                 0, 0,
5130                 0, 0,
5131                 GP_2_14_FN,     GPSR2_14,
5132                 GP_2_13_FN,     GPSR2_13,
5133                 GP_2_12_FN,     GPSR2_12,
5134                 GP_2_11_FN,     GPSR2_11,
5135                 GP_2_10_FN,     GPSR2_10,
5136                 GP_2_9_FN,      GPSR2_9,
5137                 GP_2_8_FN,      GPSR2_8,
5138                 GP_2_7_FN,      GPSR2_7,
5139                 GP_2_6_FN,      GPSR2_6,
5140                 GP_2_5_FN,      GPSR2_5,
5141                 GP_2_4_FN,      GPSR2_4,
5142                 GP_2_3_FN,      GPSR2_3,
5143                 GP_2_2_FN,      GPSR2_2,
5144                 GP_2_1_FN,      GPSR2_1,
5145                 GP_2_0_FN,      GPSR2_0, ))
5146         },
5147         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5148                 0, 0,
5149                 0, 0,
5150                 0, 0,
5151                 0, 0,
5152                 0, 0,
5153                 0, 0,
5154                 0, 0,
5155                 0, 0,
5156                 0, 0,
5157                 0, 0,
5158                 0, 0,
5159                 0, 0,
5160                 0, 0,
5161                 0, 0,
5162                 0, 0,
5163                 0, 0,
5164                 GP_3_15_FN,     GPSR3_15,
5165                 GP_3_14_FN,     GPSR3_14,
5166                 GP_3_13_FN,     GPSR3_13,
5167                 GP_3_12_FN,     GPSR3_12,
5168                 GP_3_11_FN,     GPSR3_11,
5169                 GP_3_10_FN,     GPSR3_10,
5170                 GP_3_9_FN,      GPSR3_9,
5171                 GP_3_8_FN,      GPSR3_8,
5172                 GP_3_7_FN,      GPSR3_7,
5173                 GP_3_6_FN,      GPSR3_6,
5174                 GP_3_5_FN,      GPSR3_5,
5175                 GP_3_4_FN,      GPSR3_4,
5176                 GP_3_3_FN,      GPSR3_3,
5177                 GP_3_2_FN,      GPSR3_2,
5178                 GP_3_1_FN,      GPSR3_1,
5179                 GP_3_0_FN,      GPSR3_0, ))
5180         },
5181         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5182                 0, 0,
5183                 0, 0,
5184                 0, 0,
5185                 0, 0,
5186                 0, 0,
5187                 0, 0,
5188                 0, 0,
5189                 0, 0,
5190                 0, 0,
5191                 0, 0,
5192                 0, 0,
5193                 0, 0,
5194                 0, 0,
5195                 0, 0,
5196                 GP_4_17_FN,     GPSR4_17,
5197                 GP_4_16_FN,     GPSR4_16,
5198                 GP_4_15_FN,     GPSR4_15,
5199                 GP_4_14_FN,     GPSR4_14,
5200                 GP_4_13_FN,     GPSR4_13,
5201                 GP_4_12_FN,     GPSR4_12,
5202                 GP_4_11_FN,     GPSR4_11,
5203                 GP_4_10_FN,     GPSR4_10,
5204                 GP_4_9_FN,      GPSR4_9,
5205                 GP_4_8_FN,      GPSR4_8,
5206                 GP_4_7_FN,      GPSR4_7,
5207                 GP_4_6_FN,      GPSR4_6,
5208                 GP_4_5_FN,      GPSR4_5,
5209                 GP_4_4_FN,      GPSR4_4,
5210                 GP_4_3_FN,      GPSR4_3,
5211                 GP_4_2_FN,      GPSR4_2,
5212                 GP_4_1_FN,      GPSR4_1,
5213                 GP_4_0_FN,      GPSR4_0, ))
5214         },
5215         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5216                 0, 0,
5217                 0, 0,
5218                 0, 0,
5219                 0, 0,
5220                 0, 0,
5221                 0, 0,
5222                 GP_5_25_FN,     GPSR5_25,
5223                 GP_5_24_FN,     GPSR5_24,
5224                 GP_5_23_FN,     GPSR5_23,
5225                 GP_5_22_FN,     GPSR5_22,
5226                 GP_5_21_FN,     GPSR5_21,
5227                 GP_5_20_FN,     GPSR5_20,
5228                 GP_5_19_FN,     GPSR5_19,
5229                 GP_5_18_FN,     GPSR5_18,
5230                 GP_5_17_FN,     GPSR5_17,
5231                 GP_5_16_FN,     GPSR5_16,
5232                 GP_5_15_FN,     GPSR5_15,
5233                 GP_5_14_FN,     GPSR5_14,
5234                 GP_5_13_FN,     GPSR5_13,
5235                 GP_5_12_FN,     GPSR5_12,
5236                 GP_5_11_FN,     GPSR5_11,
5237                 GP_5_10_FN,     GPSR5_10,
5238                 GP_5_9_FN,      GPSR5_9,
5239                 GP_5_8_FN,      GPSR5_8,
5240                 GP_5_7_FN,      GPSR5_7,
5241                 GP_5_6_FN,      GPSR5_6,
5242                 GP_5_5_FN,      GPSR5_5,
5243                 GP_5_4_FN,      GPSR5_4,
5244                 GP_5_3_FN,      GPSR5_3,
5245                 GP_5_2_FN,      GPSR5_2,
5246                 GP_5_1_FN,      GPSR5_1,
5247                 GP_5_0_FN,      GPSR5_0, ))
5248         },
5249         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5250                 GP_6_31_FN,     GPSR6_31,
5251                 GP_6_30_FN,     GPSR6_30,
5252                 GP_6_29_FN,     GPSR6_29,
5253                 GP_6_28_FN,     GPSR6_28,
5254                 GP_6_27_FN,     GPSR6_27,
5255                 GP_6_26_FN,     GPSR6_26,
5256                 GP_6_25_FN,     GPSR6_25,
5257                 GP_6_24_FN,     GPSR6_24,
5258                 GP_6_23_FN,     GPSR6_23,
5259                 GP_6_22_FN,     GPSR6_22,
5260                 GP_6_21_FN,     GPSR6_21,
5261                 GP_6_20_FN,     GPSR6_20,
5262                 GP_6_19_FN,     GPSR6_19,
5263                 GP_6_18_FN,     GPSR6_18,
5264                 GP_6_17_FN,     GPSR6_17,
5265                 GP_6_16_FN,     GPSR6_16,
5266                 GP_6_15_FN,     GPSR6_15,
5267                 GP_6_14_FN,     GPSR6_14,
5268                 GP_6_13_FN,     GPSR6_13,
5269                 GP_6_12_FN,     GPSR6_12,
5270                 GP_6_11_FN,     GPSR6_11,
5271                 GP_6_10_FN,     GPSR6_10,
5272                 GP_6_9_FN,      GPSR6_9,
5273                 GP_6_8_FN,      GPSR6_8,
5274                 GP_6_7_FN,      GPSR6_7,
5275                 GP_6_6_FN,      GPSR6_6,
5276                 GP_6_5_FN,      GPSR6_5,
5277                 GP_6_4_FN,      GPSR6_4,
5278                 GP_6_3_FN,      GPSR6_3,
5279                 GP_6_2_FN,      GPSR6_2,
5280                 GP_6_1_FN,      GPSR6_1,
5281                 GP_6_0_FN,      GPSR6_0, ))
5282         },
5283         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5284                 0, 0,
5285                 0, 0,
5286                 0, 0,
5287                 0, 0,
5288                 0, 0,
5289                 0, 0,
5290                 0, 0,
5291                 0, 0,
5292                 0, 0,
5293                 0, 0,
5294                 0, 0,
5295                 0, 0,
5296                 0, 0,
5297                 0, 0,
5298                 0, 0,
5299                 0, 0,
5300                 0, 0,
5301                 0, 0,
5302                 0, 0,
5303                 0, 0,
5304                 0, 0,
5305                 0, 0,
5306                 0, 0,
5307                 0, 0,
5308                 0, 0,
5309                 0, 0,
5310                 0, 0,
5311                 0, 0,
5312                 GP_7_3_FN, GPSR7_3,
5313                 GP_7_2_FN, GPSR7_2,
5314                 GP_7_1_FN, GPSR7_1,
5315                 GP_7_0_FN, GPSR7_0, ))
5316         },
5317 #undef F_
5318 #undef FM
5319
5320 #define F_(x, y)        x,
5321 #define FM(x)           FN_##x,
5322         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5323                 IP0_31_28
5324                 IP0_27_24
5325                 IP0_23_20
5326                 IP0_19_16
5327                 IP0_15_12
5328                 IP0_11_8
5329                 IP0_7_4
5330                 IP0_3_0 ))
5331         },
5332         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5333                 IP1_31_28
5334                 IP1_27_24
5335                 IP1_23_20
5336                 IP1_19_16
5337                 IP1_15_12
5338                 IP1_11_8
5339                 IP1_7_4
5340                 IP1_3_0 ))
5341         },
5342         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5343                 IP2_31_28
5344                 IP2_27_24
5345                 IP2_23_20
5346                 IP2_19_16
5347                 IP2_15_12
5348                 IP2_11_8
5349                 IP2_7_4
5350                 IP2_3_0 ))
5351         },
5352         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5353                 IP3_31_28
5354                 IP3_27_24
5355                 IP3_23_20
5356                 IP3_19_16
5357                 IP3_15_12
5358                 IP3_11_8
5359                 IP3_7_4
5360                 IP3_3_0 ))
5361         },
5362         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5363                 IP4_31_28
5364                 IP4_27_24
5365                 IP4_23_20
5366                 IP4_19_16
5367                 IP4_15_12
5368                 IP4_11_8
5369                 IP4_7_4
5370                 IP4_3_0 ))
5371         },
5372         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5373                 IP5_31_28
5374                 IP5_27_24
5375                 IP5_23_20
5376                 IP5_19_16
5377                 IP5_15_12
5378                 IP5_11_8
5379                 IP5_7_4
5380                 IP5_3_0 ))
5381         },
5382         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5383                 IP6_31_28
5384                 IP6_27_24
5385                 IP6_23_20
5386                 IP6_19_16
5387                 IP6_15_12
5388                 IP6_11_8
5389                 IP6_7_4
5390                 IP6_3_0 ))
5391         },
5392         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5393                 IP7_31_28
5394                 IP7_27_24
5395                 IP7_23_20
5396                 IP7_19_16
5397                 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5398                 IP7_11_8
5399                 IP7_7_4
5400                 IP7_3_0 ))
5401         },
5402         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5403                 IP8_31_28
5404                 IP8_27_24
5405                 IP8_23_20
5406                 IP8_19_16
5407                 IP8_15_12
5408                 IP8_11_8
5409                 IP8_7_4
5410                 IP8_3_0 ))
5411         },
5412         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5413                 IP9_31_28
5414                 IP9_27_24
5415                 IP9_23_20
5416                 IP9_19_16
5417                 IP9_15_12
5418                 IP9_11_8
5419                 IP9_7_4
5420                 IP9_3_0 ))
5421         },
5422         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5423                 IP10_31_28
5424                 IP10_27_24
5425                 IP10_23_20
5426                 IP10_19_16
5427                 IP10_15_12
5428                 IP10_11_8
5429                 IP10_7_4
5430                 IP10_3_0 ))
5431         },
5432         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5433                 IP11_31_28
5434                 IP11_27_24
5435                 IP11_23_20
5436                 IP11_19_16
5437                 IP11_15_12
5438                 IP11_11_8
5439                 IP11_7_4
5440                 IP11_3_0 ))
5441         },
5442         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5443                 IP12_31_28
5444                 IP12_27_24
5445                 IP12_23_20
5446                 IP12_19_16
5447                 IP12_15_12
5448                 IP12_11_8
5449                 IP12_7_4
5450                 IP12_3_0 ))
5451         },
5452         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5453                 IP13_31_28
5454                 IP13_27_24
5455                 IP13_23_20
5456                 IP13_19_16
5457                 IP13_15_12
5458                 IP13_11_8
5459                 IP13_7_4
5460                 IP13_3_0 ))
5461         },
5462         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5463                 IP14_31_28
5464                 IP14_27_24
5465                 IP14_23_20
5466                 IP14_19_16
5467                 IP14_15_12
5468                 IP14_11_8
5469                 IP14_7_4
5470                 IP14_3_0 ))
5471         },
5472         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5473                 IP15_31_28
5474                 IP15_27_24
5475                 IP15_23_20
5476                 IP15_19_16
5477                 IP15_15_12
5478                 IP15_11_8
5479                 IP15_7_4
5480                 IP15_3_0 ))
5481         },
5482         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5483                 IP16_31_28
5484                 IP16_27_24
5485                 IP16_23_20
5486                 IP16_19_16
5487                 IP16_15_12
5488                 IP16_11_8
5489                 IP16_7_4
5490                 IP16_3_0 ))
5491         },
5492         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5493                 IP17_31_28
5494                 IP17_27_24
5495                 IP17_23_20
5496                 IP17_19_16
5497                 IP17_15_12
5498                 IP17_11_8
5499                 IP17_7_4
5500                 IP17_3_0 ))
5501         },
5502         { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
5503                 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5504                 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5505                 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5506                 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5507                 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5508                 /* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5509                 IP18_7_4
5510                 IP18_3_0 ))
5511         },
5512 #undef F_
5513 #undef FM
5514
5515 #define F_(x, y)        x,
5516 #define FM(x)           FN_##x,
5517         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5518                              GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5519                                    1, 1, 1, 2, 2, 1, 2, 3),
5520                              GROUP(
5521                 MOD_SEL0_31_30_29
5522                 MOD_SEL0_28_27
5523                 MOD_SEL0_26_25_24
5524                 MOD_SEL0_23
5525                 MOD_SEL0_22
5526                 MOD_SEL0_21
5527                 MOD_SEL0_20
5528                 MOD_SEL0_19
5529                 MOD_SEL0_18_17
5530                 MOD_SEL0_16
5531                 0, 0, /* RESERVED 15 */
5532                 MOD_SEL0_14_13
5533                 MOD_SEL0_12
5534                 MOD_SEL0_11
5535                 MOD_SEL0_10
5536                 MOD_SEL0_9_8
5537                 MOD_SEL0_7_6
5538                 MOD_SEL0_5
5539                 MOD_SEL0_4_3
5540                 /* RESERVED 2, 1, 0 */
5541                 0, 0, 0, 0, 0, 0, 0, 0 ))
5542         },
5543         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5544                              GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5545                                    1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5546                              GROUP(
5547                 MOD_SEL1_31_30
5548                 MOD_SEL1_29_28_27
5549                 MOD_SEL1_26
5550                 MOD_SEL1_25_24
5551                 MOD_SEL1_23_22_21
5552                 MOD_SEL1_20
5553                 MOD_SEL1_19
5554                 MOD_SEL1_18_17
5555                 MOD_SEL1_16
5556                 MOD_SEL1_15_14
5557                 MOD_SEL1_13
5558                 MOD_SEL1_12
5559                 MOD_SEL1_11
5560                 MOD_SEL1_10
5561                 MOD_SEL1_9
5562                 0, 0, 0, 0, /* RESERVED 8, 7 */
5563                 MOD_SEL1_6
5564                 MOD_SEL1_5
5565                 MOD_SEL1_4
5566                 MOD_SEL1_3
5567                 MOD_SEL1_2
5568                 MOD_SEL1_1
5569                 MOD_SEL1_0 ))
5570         },
5571         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5572                              GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5573                                    1, 4, 4, 4, 3, 1),
5574                              GROUP(
5575                 MOD_SEL2_31
5576                 MOD_SEL2_30
5577                 MOD_SEL2_29
5578                 MOD_SEL2_28_27
5579                 MOD_SEL2_26
5580                 MOD_SEL2_25_24_23
5581                 MOD_SEL2_22
5582                 MOD_SEL2_21
5583                 MOD_SEL2_20
5584                 MOD_SEL2_19
5585                 MOD_SEL2_18
5586                 MOD_SEL2_17
5587                 /* RESERVED 16 */
5588                 0, 0,
5589                 /* RESERVED 15, 14, 13, 12 */
5590                 0, 0, 0, 0, 0, 0, 0, 0,
5591                 0, 0, 0, 0, 0, 0, 0, 0,
5592                 /* RESERVED 11, 10, 9, 8 */
5593                 0, 0, 0, 0, 0, 0, 0, 0,
5594                 0, 0, 0, 0, 0, 0, 0, 0,
5595                 /* RESERVED 7, 6, 5, 4 */
5596                 0, 0, 0, 0, 0, 0, 0, 0,
5597                 0, 0, 0, 0, 0, 0, 0, 0,
5598                 /* RESERVED 3, 2, 1 */
5599                 0, 0, 0, 0, 0, 0, 0, 0,
5600                 MOD_SEL2_0 ))
5601         },
5602         { },
5603 };
5604
5605 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5606         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5607                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5608                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5609                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5610                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5611                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5612                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5613                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5614                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5615         } },
5616         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5617                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5618                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5619                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5620                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5621                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5622                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5623                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5624                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5625         } },
5626         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5627                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5628                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5629                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5630                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5631                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5632                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5633                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5634                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5635         } },
5636         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5637                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5638                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5639                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5640                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5641                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5642                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5643                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5644                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5645         } },
5646         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5647                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5648                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5649                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5650                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5651                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5652                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5653                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5654                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5655         } },
5656         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5657                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5658                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5659                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5660                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5661                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5662                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5663                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5664                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5665         } },
5666         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5667                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5668                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5669                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5670                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5671                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5672                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5673                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5674                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5675         } },
5676         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5677                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5678                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5679                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5680                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5681                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5682                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5683                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5684                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5685         } },
5686         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5687                 { RCAR_GP_PIN(1, 28), 28, 3 },  /* CLKOUT */
5688                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5689                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5690                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5691                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5692                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5693                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5694                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5695         } },
5696         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5697                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5698                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5699                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5700                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5701                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5702                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5703                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5704                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5705         } },
5706         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5707                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5708                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5709                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5710                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5711                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5712                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5713                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5714                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5715         } },
5716         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5717                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5718                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5719                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5720                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5721                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* GP7_02 */
5722                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* GP7_03 */
5723                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5724                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5725         } },
5726         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5727                 { PIN_A_NUMBER('R', 8),  28, 2 },       /* DU_DOTCLKIN2 */
5728                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST */
5729                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5730         } },
5731         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5732                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5733                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5734                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5735                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5736                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5737                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5738                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5739                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5740         } },
5741         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5742                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5743                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5744                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5745                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5746                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5747                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5748                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5749                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5750         } },
5751         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5752                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5753                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5754                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5755                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5756                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5757                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5758                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5759                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5760         } },
5761         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5762                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5763                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5764                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5765                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5766                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5767                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5768                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5769                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5770         } },
5771         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5772                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5773                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5774                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5775                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5776                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5777                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5778                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5779                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5780         } },
5781         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5782                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0 */
5783                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5784                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5785                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5786                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1 */
5787                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5788                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5789                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5790         } },
5791         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5792                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5793                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5794                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5795                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5796                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5797                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5798                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5799                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5800         } },
5801         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5802                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5803                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5804                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5805                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5806                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5807                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5808                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5809                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5810         } },
5811         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5812                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5813                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5814                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5815                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5816                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5817                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5818                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5819                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5820         } },
5821         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5822                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5823                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5824                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5825                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5826                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5827                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5828                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5829                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5830         } },
5831         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5832                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5833                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5834                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5835                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5836                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5837                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5838                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5839                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5840         } },
5841         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5842                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5843                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5844                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5845                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5846                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5847                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* GP6_30 */
5848                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* GP6_31 */
5849         } },
5850         { },
5851 };
5852
5853 enum ioctrl_regs {
5854         POCCTRL,
5855         TDSELCTRL,
5856 };
5857
5858 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5859         [POCCTRL] = { 0xe6060380, },
5860         [TDSELCTRL] = { 0xe60603c0, },
5861         { /* sentinel */ },
5862 };
5863
5864 static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5865 {
5866         int bit = -EINVAL;
5867
5868         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5869
5870         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5871                 bit = pin & 0x1f;
5872
5873         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5874                 bit = (pin & 0x1f) + 12;
5875
5876         return bit;
5877 }
5878
5879 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5880         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5881                 [ 0] = PIN_NUMBER('W', 3),      /* QSPI0_SPCLK */
5882                 [ 1] = PIN_A_NUMBER('C', 5),    /* QSPI0_MOSI_IO0 */
5883                 [ 2] = PIN_A_NUMBER('B', 4),    /* QSPI0_MISO_IO1 */
5884                 [ 3] = PIN_NUMBER('Y', 6),      /* QSPI0_IO2 */
5885                 [ 4] = PIN_A_NUMBER('B', 6),    /* QSPI0_IO3 */
5886                 [ 5] = PIN_NUMBER('Y', 3),      /* QSPI0_SSL */
5887                 [ 6] = PIN_NUMBER('V', 3),      /* QSPI1_SPCLK */
5888                 [ 7] = PIN_A_NUMBER('C', 7),    /* QSPI1_MOSI_IO0 */
5889                 [ 8] = PIN_A_NUMBER('E', 5),    /* QSPI1_MISO_IO1 */
5890                 [ 9] = PIN_A_NUMBER('E', 4),    /* QSPI1_IO2 */
5891                 [10] = PIN_A_NUMBER('C', 3),    /* QSPI1_IO3 */
5892                 [11] = PIN_NUMBER('V', 5),      /* QSPI1_SSL */
5893                 [12] = PIN_NUMBER('Y', 7),      /* RPC_INT# */
5894                 [13] = PIN_NUMBER('V', 6),      /* RPC_WP# */
5895                 [14] = PIN_NUMBER('V', 7),      /* RPC_RESET# */
5896                 [15] = PIN_NUMBER('A', 16),     /* AVB_RX_CTL */
5897                 [16] = PIN_NUMBER('B', 19),     /* AVB_RXC */
5898                 [17] = PIN_NUMBER('A', 13),     /* AVB_RD0 */
5899                 [18] = PIN_NUMBER('B', 13),     /* AVB_RD1 */
5900                 [19] = PIN_NUMBER('A', 14),     /* AVB_RD2 */
5901                 [20] = PIN_NUMBER('B', 14),     /* AVB_RD3 */
5902                 [21] = PIN_NUMBER('A', 8),      /* AVB_TX_CTL */
5903                 [22] = PIN_NUMBER('A', 19),     /* AVB_TXC */
5904                 [23] = PIN_NUMBER('A', 18),     /* AVB_TD0 */
5905                 [24] = PIN_NUMBER('B', 18),     /* AVB_TD1 */
5906                 [25] = PIN_NUMBER('A', 17),     /* AVB_TD2 */
5907                 [26] = PIN_NUMBER('B', 17),     /* AVB_TD3 */
5908                 [27] = PIN_NUMBER('A', 12),     /* AVB_TXCREFCLK */
5909                 [28] = PIN_NUMBER('A', 9),      /* AVB_MDIO */
5910                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
5911                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
5912                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
5913         } },
5914         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5915                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
5916                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
5917                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
5918                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
5919                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
5920                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
5921                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
5922                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
5923                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
5924                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
5925                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
5926                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
5927                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
5928                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
5929                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
5930                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
5931                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
5932                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
5933                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
5934                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
5935                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
5936                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
5937                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
5938                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
5939                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
5940                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
5941                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
5942                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
5943                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
5944                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
5945                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
5946                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
5947         } },
5948         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5949                 [ 0] = RCAR_GP_PIN(1, 28),      /* CLKOUT */
5950                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
5951                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N */
5952                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
5953                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
5954                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
5955                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
5956                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
5957                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
5958                 [ 9] = PIN_NUMBER('C', 1),      /* PRESETOUT# */
5959                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
5960                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
5961                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
5962                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
5963                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
5964                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
5965                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
5966                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
5967                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
5968                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
5969                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
5970                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
5971                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
5972                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
5973                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
5974                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
5975                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
5976                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
5977                 [28] = RCAR_GP_PIN(7,  2),      /* GP7_02 */
5978                 [29] = RCAR_GP_PIN(7,  3),      /* GP7_03 */
5979                 [30] = PIN_A_NUMBER('P', 7),    /* DU_DOTCLKIN0 */
5980                 [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
5981         } },
5982         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5983                 [ 0] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN2 */
5984                 [ 1] = PIN_NONE,
5985                 [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST */
5986                 [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
5987                 [ 4] = PIN_A_NUMBER('R', 26),   /* TRST# */
5988                 [ 5] = PIN_A_NUMBER('T', 27),   /* TCK */
5989                 [ 6] = PIN_A_NUMBER('R', 30),   /* TMS */
5990                 [ 7] = PIN_A_NUMBER('R', 29),   /* TDI */
5991                 [ 8] = PIN_NONE,
5992                 [ 9] = PIN_A_NUMBER('T', 30),   /* ASEBRK */
5993                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
5994                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
5995                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
5996                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
5997                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
5998                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
5999                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
6000                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
6001                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
6002                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
6003                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
6004                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
6005                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
6006                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
6007                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
6008                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
6009                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
6010                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
6011                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
6012                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
6013                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
6014                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
6015         } },
6016         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6017                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
6018                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
6019                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
6020                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
6021                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
6022                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
6023                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
6024                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
6025                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
6026                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
6027                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
6028                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
6029                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
6030                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
6031                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
6032                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
6033                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N */
6034                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
6035                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
6036                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
6037                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N */
6038                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
6039                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
6040                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
6041                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
6042                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
6043                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
6044                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
6045                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
6046                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
6047                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
6048                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
6049         } },
6050         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6051                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
6052                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
6053                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
6054                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
6055                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
6056                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
6057                 [ 6] = PIN_NUMBER('H', 37),     /* MLB_REF */
6058                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
6059                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
6060                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
6061                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
6062                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
6063                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
6064                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
6065                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
6066                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
6067                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
6068                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
6069                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
6070                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
6071                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
6072                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
6073                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
6074                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
6075                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
6076                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
6077                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
6078                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
6079                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
6080                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
6081                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
6082                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
6083         } },
6084         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6085                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
6086                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
6087                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
6088                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
6089                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
6090                 [ 5] = RCAR_GP_PIN(6, 30),      /* GP6_30 */
6091                 [ 6] = RCAR_GP_PIN(6, 31),      /* GP6_31 */
6092                 [ 7] = PIN_NONE,
6093                 [ 8] = PIN_NONE,
6094                 [ 9] = PIN_NONE,
6095                 [10] = PIN_NONE,
6096                 [11] = PIN_NONE,
6097                 [12] = PIN_NONE,
6098                 [13] = PIN_NONE,
6099                 [14] = PIN_NONE,
6100                 [15] = PIN_NONE,
6101                 [16] = PIN_NONE,
6102                 [17] = PIN_NONE,
6103                 [18] = PIN_NONE,
6104                 [19] = PIN_NONE,
6105                 [20] = PIN_NONE,
6106                 [21] = PIN_NONE,
6107                 [22] = PIN_NONE,
6108                 [23] = PIN_NONE,
6109                 [24] = PIN_NONE,
6110                 [25] = PIN_NONE,
6111                 [26] = PIN_NONE,
6112                 [27] = PIN_NONE,
6113                 [28] = PIN_NONE,
6114                 [29] = PIN_NONE,
6115                 [30] = PIN_NONE,
6116                 [31] = PIN_NONE,
6117         } },
6118         { /* sentinel */ },
6119 };
6120
6121 static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
6122                                             unsigned int pin)
6123 {
6124         const struct pinmux_bias_reg *reg;
6125         unsigned int bit;
6126
6127         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6128         if (!reg)
6129                 return PIN_CONFIG_BIAS_DISABLE;
6130
6131         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6132                 return PIN_CONFIG_BIAS_DISABLE;
6133         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6134                 return PIN_CONFIG_BIAS_PULL_UP;
6135         else
6136                 return PIN_CONFIG_BIAS_PULL_DOWN;
6137 }
6138
6139 static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6140                                    unsigned int bias)
6141 {
6142         const struct pinmux_bias_reg *reg;
6143         u32 enable, updown;
6144         unsigned int bit;
6145
6146         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6147         if (!reg)
6148                 return;
6149
6150         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6151         if (bias != PIN_CONFIG_BIAS_DISABLE)
6152                 enable |= BIT(bit);
6153
6154         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6155         if (bias == PIN_CONFIG_BIAS_PULL_UP)
6156                 updown |= BIT(bit);
6157
6158         sh_pfc_write(pfc, reg->pud, updown);
6159         sh_pfc_write(pfc, reg->puen, enable);
6160 }
6161
6162 static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
6163         .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
6164         .get_bias = r8a7796_pinmux_get_bias,
6165         .set_bias = r8a7796_pinmux_set_bias,
6166 };
6167
6168 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
6169 const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
6170         .name = "r8a774a1_pfc",
6171         .ops = &r8a7796_pinmux_ops,
6172         .unlock_reg = 0xe6060000, /* PMMR */
6173
6174         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6175
6176         .pins = pinmux_pins,
6177         .nr_pins = ARRAY_SIZE(pinmux_pins),
6178         .groups = pinmux_groups.common,
6179         .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6180         .functions = pinmux_functions.common,
6181         .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6182
6183         .cfg_regs = pinmux_config_regs,
6184         .drive_regs = pinmux_drive_regs,
6185         .bias_regs = pinmux_bias_regs,
6186         .ioctrl_regs = pinmux_ioctrl_regs,
6187
6188         .pinmux_data = pinmux_data,
6189         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6190 };
6191 #endif
6192
6193 #ifdef CONFIG_PINCTRL_PFC_R8A7796
6194 const struct sh_pfc_soc_info r8a7796_pinmux_info = {
6195         .name = "r8a77960_pfc",
6196         .ops = &r8a7796_pinmux_ops,
6197         .unlock_reg = 0xe6060000, /* PMMR */
6198
6199         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6200
6201         .pins = pinmux_pins,
6202         .nr_pins = ARRAY_SIZE(pinmux_pins),
6203         .groups = pinmux_groups.common,
6204         .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6205                 ARRAY_SIZE(pinmux_groups.automotive),
6206         .functions = pinmux_functions.common,
6207         .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6208                 ARRAY_SIZE(pinmux_functions.automotive),
6209
6210         .cfg_regs = pinmux_config_regs,
6211         .drive_regs = pinmux_drive_regs,
6212         .bias_regs = pinmux_bias_regs,
6213         .ioctrl_regs = pinmux_ioctrl_regs,
6214
6215         .pinmux_data = pinmux_data,
6216         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6217 };
6218 #endif