drivers/pinctrl/renesas/pfc-r8a7796.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A7796 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2016-2019 Renesas Electronics Corp.
   6  *
   7  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
   8  *
   9  * R-Car Gen3 processor support - PFC hardware block.
  10  *
  11  * Copyright (C) 2015  Renesas Electronics Corporation
  12  */
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <dm/pinctrl.h>
  18 #include <linux/kernel.h>
  19
  20 #include "sh_pfc.h"
  21
  22 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  23                    SH_PFC_PIN_CFG_PULL_UP | \
  24                    SH_PFC_PIN_CFG_PULL_DOWN)
  25
  26 #define CPU_ALL_PORT(fn, sfx)                                           \
  27         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  28         PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
  29         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  30         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  31         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  32         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  33         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  34         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  35         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  36         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  37         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  38         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  39 /*
  40  * F_() : just information
  41  * FM() : macro for FN_xxx / xxx_MARK
  42  */
  43
  44 /* GPSR0 */
  45 #define GPSR0_15        F_(D15,                 IP7_11_8)
  46 #define GPSR0_14        F_(D14,                 IP7_7_4)
  47 #define GPSR0_13        F_(D13,                 IP7_3_0)
  48 #define GPSR0_12        F_(D12,                 IP6_31_28)
  49 #define GPSR0_11        F_(D11,                 IP6_27_24)
  50 #define GPSR0_10        F_(D10,                 IP6_23_20)
  51 #define GPSR0_9         F_(D9,                  IP6_19_16)
  52 #define GPSR0_8         F_(D8,                  IP6_15_12)
  53 #define GPSR0_7         F_(D7,                  IP6_11_8)
  54 #define GPSR0_6         F_(D6,                  IP6_7_4)
  55 #define GPSR0_5         F_(D5,                  IP6_3_0)
  56 #define GPSR0_4         F_(D4,                  IP5_31_28)
  57 #define GPSR0_3         F_(D3,                  IP5_27_24)
  58 #define GPSR0_2         F_(D2,                  IP5_23_20)
  59 #define GPSR0_1         F_(D1,                  IP5_19_16)
  60 #define GPSR0_0         F_(D0,                  IP5_15_12)
  61
  62 /* GPSR1 */
  63 #define GPSR1_28        FM(CLKOUT)
  64 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  65 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  66 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  67 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  68 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  69 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  70 #define GPSR1_21        F_(CS1_N,               IP4_19_16)
  71 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  72 #define GPSR1_19        F_(A19,                 IP4_11_8)
  73 #define GPSR1_18        F_(A18,                 IP4_7_4)
  74 #define GPSR1_17        F_(A17,                 IP4_3_0)
  75 #define GPSR1_16        F_(A16,                 IP3_31_28)
  76 #define GPSR1_15        F_(A15,                 IP3_27_24)
  77 #define GPSR1_14        F_(A14,                 IP3_23_20)
  78 #define GPSR1_13        F_(A13,                 IP3_19_16)
  79 #define GPSR1_12        F_(A12,                 IP3_15_12)
  80 #define GPSR1_11        F_(A11,                 IP3_11_8)
  81 #define GPSR1_10        F_(A10,                 IP3_7_4)
  82 #define GPSR1_9         F_(A9,                  IP3_3_0)
  83 #define GPSR1_8         F_(A8,                  IP2_31_28)
  84 #define GPSR1_7         F_(A7,                  IP2_27_24)
  85 #define GPSR1_6         F_(A6,                  IP2_23_20)
  86 #define GPSR1_5         F_(A5,                  IP2_19_16)
  87 #define GPSR1_4         F_(A4,                  IP2_15_12)
  88 #define GPSR1_3         F_(A3,                  IP2_11_8)
  89 #define GPSR1_2         F_(A2,                  IP2_7_4)
  90 #define GPSR1_1         F_(A1,                  IP2_3_0)
  91 #define GPSR1_0         F_(A0,                  IP1_31_28)
  92
  93 /* GPSR2 */
  94 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  95 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  96 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  97 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  98 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
  99 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
 100 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
 101 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
 102 #define GPSR2_6         F_(PWM0,                IP1_19_16)
 103 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
 104 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
 105 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
 106 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
 107 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
 108 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
 109
 110 /* GPSR3 */
 111 #define GPSR3_15        F_(SD1_WP,              IP11_23_20)
 112 #define GPSR3_14        F_(SD1_CD,              IP11_19_16)
 113 #define GPSR3_13        F_(SD0_WP,              IP11_15_12)
 114 #define GPSR3_12        F_(SD0_CD,              IP11_11_8)
 115 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 116 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 117 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 118 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 119 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 120 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 121 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 122 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 123 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 124 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 125 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 126 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 127
 128 /* GPSR4 */
 129 #define GPSR4_17        F_(SD3_DS,              IP11_7_4)
 130 #define GPSR4_16        F_(SD3_DAT7,            IP11_3_0)
 131 #define GPSR4_15        F_(SD3_DAT6,            IP10_31_28)
 132 #define GPSR4_14        F_(SD3_DAT5,            IP10_27_24)
 133 #define GPSR4_13        F_(SD3_DAT4,            IP10_23_20)
 134 #define GPSR4_12        F_(SD3_DAT3,            IP10_19_16)
 135 #define GPSR4_11        F_(SD3_DAT2,            IP10_15_12)
 136 #define GPSR4_10        F_(SD3_DAT1,            IP10_11_8)
 137 #define GPSR4_9         F_(SD3_DAT0,            IP10_7_4)
 138 #define GPSR4_8         F_(SD3_CMD,             IP10_3_0)
 139 #define GPSR4_7         F_(SD3_CLK,             IP9_31_28)
 140 #define GPSR4_6         F_(SD2_DS,              IP9_27_24)
 141 #define GPSR4_5         F_(SD2_DAT3,            IP9_23_20)
 142 #define GPSR4_4         F_(SD2_DAT2,            IP9_19_16)
 143 #define GPSR4_3         F_(SD2_DAT1,            IP9_15_12)
 144 #define GPSR4_2         F_(SD2_DAT0,            IP9_11_8)
 145 #define GPSR4_1         F_(SD2_CMD,             IP9_7_4)
 146 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 147
 148 /* GPSR5 */
 149 #define GPSR5_25        F_(MLB_DAT,             IP14_19_16)
 150 #define GPSR5_24        F_(MLB_SIG,             IP14_15_12)
 151 #define GPSR5_23        F_(MLB_CLK,             IP14_11_8)
 152 #define GPSR5_22        FM(MSIOF0_RXD)
 153 #define GPSR5_21        F_(MSIOF0_SS2,          IP14_7_4)
 154 #define GPSR5_20        FM(MSIOF0_TXD)
 155 #define GPSR5_19        F_(MSIOF0_SS1,          IP14_3_0)
 156 #define GPSR5_18        F_(MSIOF0_SYNC,         IP13_31_28)
 157 #define GPSR5_17        FM(MSIOF0_SCK)
 158 #define GPSR5_16        F_(HRTS0_N,             IP13_27_24)
 159 #define GPSR5_15        F_(HCTS0_N,             IP13_23_20)
 160 #define GPSR5_14        F_(HTX0,                IP13_19_16)
 161 #define GPSR5_13        F_(HRX0,                IP13_15_12)
 162 #define GPSR5_12        F_(HSCK0,               IP13_11_8)
 163 #define GPSR5_11        F_(RX2_A,               IP13_7_4)
 164 #define GPSR5_10        F_(TX2_A,               IP13_3_0)
 165 #define GPSR5_9         F_(SCK2,                IP12_31_28)
 166 #define GPSR5_8         F_(RTS1_N,              IP12_27_24)
 167 #define GPSR5_7         F_(CTS1_N,              IP12_23_20)
 168 #define GPSR5_6         F_(TX1_A,               IP12_19_16)
 169 #define GPSR5_5         F_(RX1_A,               IP12_15_12)
 170 #define GPSR5_4         F_(RTS0_N,              IP12_11_8)
 171 #define GPSR5_3         F_(CTS0_N,              IP12_7_4)
 172 #define GPSR5_2         F_(TX0,                 IP12_3_0)
 173 #define GPSR5_1         F_(RX0,                 IP11_31_28)
 174 #define GPSR5_0         F_(SCK0,                IP11_27_24)
 175
 176 /* GPSR6 */
 177 #define GPSR6_31        F_(GP6_31,              IP18_7_4)
 178 #define GPSR6_30        F_(GP6_30,              IP18_3_0)
 179 #define GPSR6_29        F_(USB30_OVC,           IP17_31_28)
 180 #define GPSR6_28        F_(USB30_PWEN,          IP17_27_24)
 181 #define GPSR6_27        F_(USB1_OVC,            IP17_23_20)
 182 #define GPSR6_26        F_(USB1_PWEN,           IP17_19_16)
 183 #define GPSR6_25        F_(USB0_OVC,            IP17_15_12)
 184 #define GPSR6_24        F_(USB0_PWEN,           IP17_11_8)
 185 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP17_7_4)
 186 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP17_3_0)
 187 #define GPSR6_21        F_(SSI_SDATA9_A,        IP16_31_28)
 188 #define GPSR6_20        F_(SSI_SDATA8,          IP16_27_24)
 189 #define GPSR6_19        F_(SSI_SDATA7,          IP16_23_20)
 190 #define GPSR6_18        F_(SSI_WS78,            IP16_19_16)
 191 #define GPSR6_17        F_(SSI_SCK78,           IP16_15_12)
 192 #define GPSR6_16        F_(SSI_SDATA6,          IP16_11_8)
 193 #define GPSR6_15        F_(SSI_WS6,             IP16_7_4)
 194 #define GPSR6_14        F_(SSI_SCK6,            IP16_3_0)
 195 #define GPSR6_13        FM(SSI_SDATA5)
 196 #define GPSR6_12        FM(SSI_WS5)
 197 #define GPSR6_11        FM(SSI_SCK5)
 198 #define GPSR6_10        F_(SSI_SDATA4,          IP15_31_28)
 199 #define GPSR6_9         F_(SSI_WS4,             IP15_27_24)
 200 #define GPSR6_8         F_(SSI_SCK4,            IP15_23_20)
 201 #define GPSR6_7         F_(SSI_SDATA3,          IP15_19_16)
 202 #define GPSR6_6         F_(SSI_WS349,           IP15_15_12)
 203 #define GPSR6_5         F_(SSI_SCK349,          IP15_11_8)
 204 #define GPSR6_4         F_(SSI_SDATA2_A,        IP15_7_4)
 205 #define GPSR6_3         F_(SSI_SDATA1_A,        IP15_3_0)
 206 #define GPSR6_2         F_(SSI_SDATA0,          IP14_31_28)
 207 #define GPSR6_1         F_(SSI_WS01239,         IP14_27_24)
 208 #define GPSR6_0         F_(SSI_SCK01239,        IP14_23_20)
 209
 210 /* GPSR7 */
 211 #define GPSR7_3         FM(GP7_03)
 212 #define GPSR7_2         FM(GP7_02)
 213 #define GPSR7_1         FM(AVS2)
 214 #define GPSR7_0         FM(AVS1)
 215
 216
 217 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 218 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         FM(MSIOF3_SS2_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         FM(MSIOF3_SS1_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SYNC_E) F_(0, 0)              FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   F_(0, 0)                FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SCK_E) F_(0, 0)               FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    F_(0, 0)                FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_RXD_E) F_(0, 0)               FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 229 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    F_(0, 0)                FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_TXD_E) F_(0, 0)               FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 231 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        F_(0, 0)                FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 232 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        F_(0, 0)                FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_B)                    F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 244 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 245
 246 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 247 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP4_19_16       FM(CS1_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N)                      FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_C)    FM(DU_DR3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 275 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 276
 277 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 278 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       FM(NFCE_N_B)                    F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        FM(NFWP_N_B)                    F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        FM(NFDATA14_B)                  F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        FM(NFDATA15_B)                  F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        FM(NFRB_N_B)                    F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        FM(NFDATA8)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP9_7_4         FM(SD2_CMD)             F_(0, 0)        FM(NFDATA9)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP9_11_8        FM(SD2_DAT0)            F_(0, 0)        FM(NFDATA10)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP9_15_12       FM(SD2_DAT1)            F_(0, 0)        FM(NFDATA11)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP9_19_16       FM(SD2_DAT2)            F_(0, 0)        FM(NFDATA12)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP9_23_20       FM(SD2_DAT3)            F_(0, 0)        FM(NFDATA13)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP9_27_24       FM(SD2_DS)              F_(0, 0)        FM(NFALE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP9_31_28       FM(SD3_CLK)             F_(0, 0)        FM(NFWE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP10_3_0        FM(SD3_CMD)             F_(0, 0)        FM(NFRE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP10_7_4        FM(SD3_DAT0)            F_(0, 0)        FM(NFDATA0)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP10_11_8       FM(SD3_DAT1)            F_(0, 0)        FM(NFDATA1)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP10_15_12      FM(SD3_DAT2)            F_(0, 0)        FM(NFDATA2)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP10_19_16      FM(SD3_DAT3)            F_(0, 0)        FM(NFDATA3)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306 #define IP10_23_20      FM(SD3_DAT4)            FM(SD2_CD_A)    FM(NFDATA4)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP10_27_24      FM(SD3_DAT5)            FM(SD2_WP_A)    FM(NFDATA5)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP10_31_28      FM(SD3_DAT6)            FM(SD3_CD)      FM(NFDATA6)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP11_3_0        FM(SD3_DAT7)            FM(SD3_WP)      FM(NFDATA7)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310 #define IP11_7_4        FM(SD3_DS)              F_(0, 0)        FM(NFCLE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311 #define IP11_11_8       FM(SD0_CD)              F_(0, 0)        FM(NFDATA14_A)          F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312
 313 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 314 #define IP11_15_12      FM(SD0_WP)              F_(0, 0)        FM(NFDATA15_A)          F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315 #define IP11_19_16      FM(SD1_CD)              F_(0, 0)        FM(NFRB_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316 #define IP11_23_20      FM(SD1_WP)              F_(0, 0)        FM(NFCE_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317 #define IP11_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     FM(SCK5_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318 #define IP11_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319 #define IP12_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320 #define IP12_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP12_11_8       FM(RTS0_N)              FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP12_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP12_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP12_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP12_27_24      FM(RTS1_N)              FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP12_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP13_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP13_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP13_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        FM(RX5_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP13_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP13_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP13_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333 #define IP13_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334 #define IP13_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        FM(TX5_B)       F_(0, 0)        F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
 335 #define IP14_3_0        FM(MSIOF0_SS1)          FM(RX5_A)       FM(NFWP_N_A)            FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336 #define IP14_7_4        FM(MSIOF0_SS2)          FM(TX5_A)       FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP14_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP14_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP14_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340 #define IP14_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341 #define IP14_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342
 343 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 344 #define IP14_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP15_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP15_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP15_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP15_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP15_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP15_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP15_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352 #define IP15_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353 #define IP16_3_0        FM(SSI_SCK6)            F_(0, 0)        F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354 #define IP16_7_4        FM(SSI_WS6)             F_(0, 0)        F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355 #define IP16_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 356 #define IP16_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 357 #define IP16_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 358 #define IP16_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 359 #define IP16_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 360 #define IP16_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5_A)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 361 #define IP17_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 362 #define IP17_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 363 #define IP17_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
 364 #define IP17_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
 365 #define IP17_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
 366 #define IP17_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
 367 #define IP17_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 368 #define IP17_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_N)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 369 #define IP18_3_0        FM(GP6_30)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
 370 #define IP18_7_4        FM(GP6_31)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
 371
 372 #define PINMUX_GPSR     \
 373 \
 374                                                                                                 GPSR6_31 \
 375                                                                                                 GPSR6_30 \
 376                                                                                                 GPSR6_29 \
 377                 GPSR1_28                                                                        GPSR6_28 \
 378                 GPSR1_27                                                                        GPSR6_27 \
 379                 GPSR1_26                                                                        GPSR6_26 \
 380                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 381                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 382                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 383                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 384                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 385                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 386                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 387                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 388                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 389                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 390 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 391 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 392 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 393 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 394 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 395 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 396 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 397 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 398 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 399 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 400 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 401 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 402 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 403 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 404 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 405 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 406
 407 #define PINMUX_IPSR                             \
 408 \
 409 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 410 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 411 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 412 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 413 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 414 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 415 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 416 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 417 \
 418 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 419 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 420 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 421 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12 \
 422 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 423 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 424 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 425 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 426 \
 427 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 428 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 429 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 430 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 431 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 432 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 433 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 434 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 435 \
 436 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 437 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 438 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 439 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 440 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 441 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 442 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 443 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 444 \
 445 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0        FM(IP18_3_0)    IP18_3_0 \
 446 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4        FM(IP18_7_4)    IP18_7_4 \
 447 FM(IP16_11_8)   IP16_11_8       FM(IP17_11_8)   IP17_11_8 \
 448 FM(IP16_15_12)  IP16_15_12      FM(IP17_15_12)  IP17_15_12 \
 449 FM(IP16_19_16)  IP16_19_16      FM(IP17_19_16)  IP17_19_16 \
 450 FM(IP16_23_20)  IP16_23_20      FM(IP17_23_20)  IP17_23_20 \
 451 FM(IP16_27_24)  IP16_27_24      FM(IP17_27_24)  IP17_27_24 \
 452 FM(IP16_31_28)  IP16_31_28      FM(IP17_31_28)  IP17_31_28
 453
 454 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 455 #define MOD_SEL0_31_30_29       FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)        FM(SEL_MSIOF3_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 456 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 457 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 458 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 459 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 460 #define MOD_SEL0_21             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 461 #define MOD_SEL0_20             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 462 #define MOD_SEL0_19             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 463 #define MOD_SEL0_18_17          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 464 #define MOD_SEL0_16             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 465 #define MOD_SEL0_14_13          FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)        FM(SEL_HSCIF2_2)        F_(0, 0)
 466 #define MOD_SEL0_12             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 467 #define MOD_SEL0_11             FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 468 #define MOD_SEL0_10             FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 469 #define MOD_SEL0_9_8            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 470 #define MOD_SEL0_7_6            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 471 #define MOD_SEL0_5              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 472 #define MOD_SEL0_4_3            FM(SEL_ADGA_0)          FM(SEL_ADGA_1)          FM(SEL_ADGA_2)          FM(SEL_ADGA_3)
 473
 474 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 475 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 476 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 477 #define MOD_SEL1_26             FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
 478 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 479 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 480 #define MOD_SEL1_20             FM(SEL_SSI1_0)          FM(SEL_SSI1_1)
 481 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 482 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 483 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 484 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 485 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 486 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 487 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 488 #define MOD_SEL1_10             FM(SEL_SCIF_0)          FM(SEL_SCIF_1)
 489 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 490 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 491 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 492 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 493 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 494 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 495 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 496 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 497
 498 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 499 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 500 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 501 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 502 #define MOD_SEL2_28_27          FM(SEL_FM_0)            FM(SEL_FM_1)            FM(SEL_FM_2)            FM(SEL_FM_3)
 503 #define MOD_SEL2_26             FM(SEL_SCIF5_0)         FM(SEL_SCIF5_1)
 504 #define MOD_SEL2_25_24_23       FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)
 505 #define MOD_SEL2_22             FM(SEL_NDF_0)           FM(SEL_NDF_1)
 506 #define MOD_SEL2_21             FM(SEL_SSI2_0)          FM(SEL_SSI2_1)
 507 #define MOD_SEL2_20             FM(SEL_SSI9_0)          FM(SEL_SSI9_1)
 508 #define MOD_SEL2_19             FM(SEL_TIMER_TMU2_0)    FM(SEL_TIMER_TMU2_1)
 509 #define MOD_SEL2_18             FM(SEL_ADGB_0)          FM(SEL_ADGB_1)
 510 #define MOD_SEL2_17             FM(SEL_ADGC_0)          FM(SEL_ADGC_1)
 511 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 512
 513 #define PINMUX_MOD_SELS \
 514 \
 515 MOD_SEL0_31_30_29       MOD_SEL1_31_30          MOD_SEL2_31 \
 516                                                 MOD_SEL2_30 \
 517                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 518 MOD_SEL0_28_27                                  MOD_SEL2_28_27 \
 519 MOD_SEL0_26_25_24       MOD_SEL1_26             MOD_SEL2_26 \
 520                         MOD_SEL1_25_24          MOD_SEL2_25_24_23 \
 521 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 522 MOD_SEL0_22                                     MOD_SEL2_22 \
 523 MOD_SEL0_21                                     MOD_SEL2_21 \
 524 MOD_SEL0_20             MOD_SEL1_20             MOD_SEL2_20 \
 525 MOD_SEL0_19             MOD_SEL1_19             MOD_SEL2_19 \
 526 MOD_SEL0_18_17          MOD_SEL1_18_17          MOD_SEL2_18 \
 527                                                 MOD_SEL2_17 \
 528 MOD_SEL0_16             MOD_SEL1_16 \
 529                         MOD_SEL1_15_14 \
 530 MOD_SEL0_14_13 \
 531                         MOD_SEL1_13 \
 532 MOD_SEL0_12             MOD_SEL1_12 \
 533 MOD_SEL0_11             MOD_SEL1_11 \
 534 MOD_SEL0_10             MOD_SEL1_10 \
 535 MOD_SEL0_9_8            MOD_SEL1_9 \
 536 MOD_SEL0_7_6 \
 537                         MOD_SEL1_6 \
 538 MOD_SEL0_5              MOD_SEL1_5 \
 539 MOD_SEL0_4_3            MOD_SEL1_4 \
 540                         MOD_SEL1_3 \
 541                         MOD_SEL1_2 \
 542                         MOD_SEL1_1 \
 543                         MOD_SEL1_0              MOD_SEL2_0
 544
 545 /*
 546  * These pins are not able to be muxed but have other properties
 547  * that can be set, such as drive-strength or pull-up/pull-down enable.
 548  */
 549 #define PINMUX_STATIC \
 550         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 551         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 552         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 553         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 554         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 555         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 556         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 557         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 558         FM(PRESETOUT) \
 559         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
 560         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 561
 562 #define PINMUX_PHYS \
 563         FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
 564
 565 enum {
 566         PINMUX_RESERVED = 0,
 567
 568         PINMUX_DATA_BEGIN,
 569         GP_ALL(DATA),
 570         PINMUX_DATA_END,
 571
 572 #define F_(x, y)
 573 #define FM(x)   FN_##x,
 574         PINMUX_FUNCTION_BEGIN,
 575         GP_ALL(FN),
 576         PINMUX_GPSR
 577         PINMUX_IPSR
 578         PINMUX_MOD_SELS
 579         PINMUX_FUNCTION_END,
 580 #undef F_
 581 #undef FM
 582
 583 #define F_(x, y)
 584 #define FM(x)   x##_MARK,
 585         PINMUX_MARK_BEGIN,
 586         PINMUX_GPSR
 587         PINMUX_IPSR
 588         PINMUX_MOD_SELS
 589         PINMUX_STATIC
 590         PINMUX_PHYS
 591         PINMUX_MARK_END,
 592 #undef F_
 593 #undef FM
 594 };
 595
 596 static const u16 pinmux_data[] = {
 597         PINMUX_DATA_GP_ALL(),
 598
 599         PINMUX_SINGLE(AVS1),
 600         PINMUX_SINGLE(AVS2),
 601         PINMUX_SINGLE(CLKOUT),
 602         PINMUX_SINGLE(GP7_03),
 603         PINMUX_SINGLE(GP7_02),
 604         PINMUX_SINGLE(MSIOF0_RXD),
 605         PINMUX_SINGLE(MSIOF0_SCK),
 606         PINMUX_SINGLE(MSIOF0_TXD),
 607         PINMUX_SINGLE(SSI_SCK5),
 608         PINMUX_SINGLE(SSI_SDATA5),
 609         PINMUX_SINGLE(SSI_WS5),
 610
 611         /* IPSR0 */
 612         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 613         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 614
 615         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 616         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 617         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 618
 619         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 620         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 621         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 622
 623         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 624         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 625         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 626
 627         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,      I2C_SEL_5_0,    SEL_ETHERAVB_0),
 628         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,          I2C_SEL_5_0,    SEL_MSIOF2_2),
 629         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,              I2C_SEL_5_0,    SEL_SCIF4_0),
 630         PINMUX_IPSR_PHYS(IP0_19_16,     SCL5,                   I2C_SEL_5_1),
 631
 632         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,    I2C_SEL_5_0,    SEL_ETHERAVB_0),
 633         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,          I2C_SEL_5_0,    SEL_MSIOF2_2),
 634         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A,              I2C_SEL_5_0,    SEL_SCIF4_0),
 635         PINMUX_IPSR_PHYS(IP0_23_20,     SDA5,                   I2C_SEL_5_1),
 636
 637         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 638         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 639         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 640         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 641         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 642         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 643         PINMUX_IPSR_MSEL(IP0_27_24,     MSIOF3_SS2_E,           SEL_MSIOF3_4),
 644
 645         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 646         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 647         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 648         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 649         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 650         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 651         PINMUX_IPSR_MSEL(IP0_31_28,     MSIOF3_SS1_E,           SEL_MSIOF3_4),
 652
 653         /* IPSR1 */
 654         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 655         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 656         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 657         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 658         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 659         PINMUX_IPSR_MSEL(IP1_3_0,       MSIOF3_SYNC_E,          SEL_MSIOF3_4),
 660
 661         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 662         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 663         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 664         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 665         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 666         PINMUX_IPSR_MSEL(IP1_7_4,       MSIOF3_SCK_E,           SEL_MSIOF3_4),
 667
 668         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 669         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 670         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 671         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 672         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 673         PINMUX_IPSR_MSEL(IP1_11_8,      MSIOF3_RXD_E,           SEL_MSIOF3_4),
 674
 675         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 676         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 677         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 678         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 679         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 680         PINMUX_IPSR_MSEL(IP1_15_12,     MSIOF3_TXD_E,           SEL_MSIOF3_4),
 681
 682         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 683         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 684         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 685         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 686
 687         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,                I2C_SEL_3_0,    SEL_PWM1_0),
 688         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,                I2C_SEL_3_0,    SEL_HSCIF3_3),
 689         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,           I2C_SEL_3_0,    SEL_VIN4_1),
 690         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,                I2C_SEL_3_0,    SEL_IEBUS_1),
 691         PINMUX_IPSR_PHYS(IP0_23_20,     SCL3,                   I2C_SEL_3_1),
 692
 693         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,                I2C_SEL_3_0,    SEL_PWM2_0),
 694         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,                I2C_SEL_3_0,    SEL_HSCIF3_3),
 695         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,                I2C_SEL_3_0,    SEL_IEBUS_1),
 696         PINMUX_IPSR_PHYS(IP1_27_24,     SDA3,                   I2C_SEL_3_1),
 697
 698         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 699         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 700         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 701         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 702         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 703         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 704
 705         /* IPSR2 */
 706         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 707         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 708         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 709         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 710         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 711         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 712
 713         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 714         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 715         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 716         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 717         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 718         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 719
 720         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 721         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 722         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 723         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 724         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 725         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 726
 727         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 728         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 729         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 730         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 731         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 732         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 733
 734         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 735         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 736         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 737         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 738         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 739         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 740         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 741
 742         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 743         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 744         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 745         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 746         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 747         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 748         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 749
 750         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 751         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 752         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 753         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 754         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 755         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 756         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 757
 758         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 759         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 760         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 761         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 762         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 763         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 764         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 765
 766         /* IPSR3 */
 767         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 768         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 769         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 770         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 771
 772         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 773         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 774         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_B,               SEL_SCIF4_1),
 775         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 776
 777         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 778         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 779         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 780         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 781         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 782         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 783         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 784         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 785         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 786
 787         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 788         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 789         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 790         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 791         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 792         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 793
 794         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 795         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 796         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 797         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 798         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 799         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 800
 801         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 802         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 803         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 804         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 805         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 806         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 807
 808         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 809         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 810         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 811         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 812         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 813         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 814
 815         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 816         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 817         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 818         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 819
 820         /* IPSR4 */
 821         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 822         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 823         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 824         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 825
 826         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 827         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 828         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 829         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 830
 831         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 832         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 833         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 834         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 835
 836         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 837         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 838
 839         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N),
 840         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 841         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 842
 843         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 844         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 845         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 846         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 847         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 848         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 849         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 850         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 851
 852         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 853         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 854         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 855         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 856         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 857         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 858
 859         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 860         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 861         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 862         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 863         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 864         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 865
 866         /* IPSR5 */
 867         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 868         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 869         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 870         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 871         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 872         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 873         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 874
 875         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 876         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 877         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N),
 878         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 879         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 880         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 881         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 882         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 883
 884         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 885         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 886         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 887         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 888
 889         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 890         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 891         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 892         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 893         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 894
 895         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 896         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 897         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 898         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 899         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 900
 901         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 902         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 903         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 904         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 905
 906         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 907         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 908         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 909         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 910
 911         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 912         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 913         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 914         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 915
 916         /* IPSR6 */
 917         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 918         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 919         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 920         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 921
 922         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 923         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 924         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 925         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 926
 927         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 928         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 929         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 930         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 931
 932         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 933         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 934         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 935         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 936         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 937         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 938
 939         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 940         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 941         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 942         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 943         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 944
 945         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 946         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 947         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 948         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 949         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 950         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 951         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 952
 953         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 954         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 955         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 956         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 957         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 958         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_C,               SEL_SCIF4_2),
 959         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 960
 961         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 962         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 963         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 964         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 965         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 966         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 967
 968         /* IPSR7 */
 969         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 970         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 971         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 972         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 973         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 974         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 975
 976         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 977         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 978         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 979         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 980         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 981         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 982         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 983
 984         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 985         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 986         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 987         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 988         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 989         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 990         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 991
 992         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 993         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 994         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 995
 996         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 997         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 998         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 999
1000         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
1001         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
1002         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
1003         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
1004
1005         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
1006         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
1007         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
1008         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
1009
1010         /* IPSR8 */
1011         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
1012         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
1013         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
1014         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1015
1016         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1017         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1018         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1019         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1020
1021         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1022         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1023         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1024
1025         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1026         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1027         PINMUX_IPSR_MSEL(IP8_15_12,     NFCE_N_B,               SEL_NDF_1),
1028         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1029         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1030
1031         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1032         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1033         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1034         PINMUX_IPSR_MSEL(IP8_19_16,     NFWP_N_B,               SEL_NDF_1),
1035         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1036         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1037
1038         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1039         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1040         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1041         PINMUX_IPSR_MSEL(IP8_23_20,     NFDATA14_B,             SEL_NDF_1),
1042         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1043         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1044
1045         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1046         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1047         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1048         PINMUX_IPSR_MSEL(IP8_27_24,     NFDATA15_B,             SEL_NDF_1),
1049         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1050         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1051
1052         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1053         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1054         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1055         PINMUX_IPSR_MSEL(IP8_31_28,     NFRB_N_B,               SEL_NDF_1),
1056         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1057         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1058
1059         /* IPSR9 */
1060         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1061         PINMUX_IPSR_GPSR(IP9_3_0,       NFDATA8),
1062
1063         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_CMD),
1064         PINMUX_IPSR_GPSR(IP9_7_4,       NFDATA9),
1065
1066         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT0),
1067         PINMUX_IPSR_GPSR(IP9_11_8,      NFDATA10),
1068
1069         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT1),
1070         PINMUX_IPSR_GPSR(IP9_15_12,     NFDATA11),
1071
1072         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT2),
1073         PINMUX_IPSR_GPSR(IP9_19_16,     NFDATA12),
1074
1075         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DAT3),
1076         PINMUX_IPSR_GPSR(IP9_23_20,     NFDATA13),
1077
1078         PINMUX_IPSR_GPSR(IP9_27_24,     SD2_DS),
1079         PINMUX_IPSR_GPSR(IP9_27_24,     NFALE),
1080
1081         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_CLK),
1082         PINMUX_IPSR_GPSR(IP9_31_28,     NFWE_N),
1083
1084         /* IPSR10 */
1085         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CMD),
1086         PINMUX_IPSR_GPSR(IP10_3_0,      NFRE_N),
1087
1088         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT0),
1089         PINMUX_IPSR_GPSR(IP10_7_4,      NFDATA0),
1090
1091         PINMUX_IPSR_GPSR(IP10_11_8,     SD3_DAT1),
1092         PINMUX_IPSR_GPSR(IP10_11_8,     NFDATA1),
1093
1094         PINMUX_IPSR_GPSR(IP10_15_12,    SD3_DAT2),
1095         PINMUX_IPSR_GPSR(IP10_15_12,    NFDATA2),
1096
1097         PINMUX_IPSR_GPSR(IP10_19_16,    SD3_DAT3),
1098         PINMUX_IPSR_GPSR(IP10_19_16,    NFDATA3),
1099
1100         PINMUX_IPSR_GPSR(IP10_23_20,    SD3_DAT4),
1101         PINMUX_IPSR_MSEL(IP10_23_20,    SD2_CD_A,               SEL_SDHI2_0),
1102         PINMUX_IPSR_GPSR(IP10_23_20,    NFDATA4),
1103
1104         PINMUX_IPSR_GPSR(IP10_27_24,    SD3_DAT5),
1105         PINMUX_IPSR_MSEL(IP10_27_24,    SD2_WP_A,               SEL_SDHI2_0),
1106         PINMUX_IPSR_GPSR(IP10_27_24,    NFDATA5),
1107
1108         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_DAT6),
1109         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_CD),
1110         PINMUX_IPSR_GPSR(IP10_31_28,    NFDATA6),
1111
1112         /* IPSR11 */
1113         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_DAT7),
1114         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_WP),
1115         PINMUX_IPSR_GPSR(IP11_3_0,      NFDATA7),
1116
1117         PINMUX_IPSR_GPSR(IP11_7_4,      SD3_DS),
1118         PINMUX_IPSR_GPSR(IP11_7_4,      NFCLE),
1119
1120         PINMUX_IPSR_GPSR(IP11_11_8,     SD0_CD),
1121         PINMUX_IPSR_MSEL(IP11_11_8,     NFDATA14_A,             SEL_NDF_0),
1122         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_B,                 SEL_I2C2_1),
1123         PINMUX_IPSR_MSEL(IP11_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1124
1125         PINMUX_IPSR_GPSR(IP11_15_12,    SD0_WP),
1126         PINMUX_IPSR_MSEL(IP11_15_12,    NFDATA15_A,             SEL_NDF_0),
1127         PINMUX_IPSR_MSEL(IP11_15_12,    SDA2_B,                 SEL_I2C2_1),
1128
1129         PINMUX_IPSR_MSEL(IP11_19_16,    SD1_CD,                 I2C_SEL_0_0),
1130         PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A,             I2C_SEL_0_0,    SEL_NDF_0),
1131         PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B,           I2C_SEL_0_0,    SEL_SIMCARD_1),
1132         PINMUX_IPSR_PHYS(IP11_19_16,    SCL0,                   I2C_SEL_0_1),
1133
1134         PINMUX_IPSR_MSEL(IP11_23_20,    SD1_WP,                 I2C_SEL_0_0),
1135         PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A,             I2C_SEL_0_0,    SEL_NDF_0),
1136         PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B,             I2C_SEL_0_0,    SEL_SIMCARD_1),
1137         PINMUX_IPSR_PHYS(IP11_23_20,    SDA0,                   I2C_SEL_0_1),
1138
1139         PINMUX_IPSR_GPSR(IP11_27_24,    SCK0),
1140         PINMUX_IPSR_MSEL(IP11_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1141         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1142         PINMUX_IPSR_MSEL(IP11_27_24,    AUDIO_CLKC_B,           SEL_ADGC_1),
1143         PINMUX_IPSR_MSEL(IP11_27_24,    SDA2_A,                 SEL_I2C2_0),
1144         PINMUX_IPSR_MSEL(IP11_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1145         PINMUX_IPSR_MSEL(IP11_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1146         PINMUX_IPSR_MSEL(IP11_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1147         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS2),
1148         PINMUX_IPSR_MSEL(IP11_27_24,    SCK5_B,                 SEL_SCIF5_1),
1149
1150         PINMUX_IPSR_GPSR(IP11_31_28,    RX0),
1151         PINMUX_IPSR_MSEL(IP11_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1152         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1153         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1154         PINMUX_IPSR_MSEL(IP11_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1155
1156         /* IPSR12 */
1157         PINMUX_IPSR_GPSR(IP12_3_0,      TX0),
1158         PINMUX_IPSR_MSEL(IP12_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1159         PINMUX_IPSR_MSEL(IP12_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1160         PINMUX_IPSR_MSEL(IP12_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1161         PINMUX_IPSR_MSEL(IP12_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1162
1163         PINMUX_IPSR_GPSR(IP12_7_4,      CTS0_N),
1164         PINMUX_IPSR_MSEL(IP12_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1165         PINMUX_IPSR_MSEL(IP12_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1166         PINMUX_IPSR_MSEL(IP12_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1167         PINMUX_IPSR_MSEL(IP12_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1168         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1169         PINMUX_IPSR_GPSR(IP12_7_4,      AUDIO_CLKOUT_C),
1170         PINMUX_IPSR_GPSR(IP12_7_4,      ADICS_SAMP),
1171
1172         PINMUX_IPSR_GPSR(IP12_11_8,     RTS0_N),
1173         PINMUX_IPSR_MSEL(IP12_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1174         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1175         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKA_B,           SEL_ADGA_1),
1176         PINMUX_IPSR_MSEL(IP12_11_8,     SCL2_A,                 SEL_I2C2_0),
1177         PINMUX_IPSR_MSEL(IP12_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1178         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1179         PINMUX_IPSR_GPSR(IP12_11_8,     ADICHS1),
1180
1181         PINMUX_IPSR_MSEL(IP12_15_12,    RX1_A,                  SEL_SCIF1_0),
1182         PINMUX_IPSR_MSEL(IP12_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1183         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1184         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1185         PINMUX_IPSR_MSEL(IP12_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1186
1187         PINMUX_IPSR_MSEL(IP12_19_16,    TX1_A,                  SEL_SCIF1_0),
1188         PINMUX_IPSR_MSEL(IP12_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1189         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1190         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1191         PINMUX_IPSR_MSEL(IP12_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1192
1193         PINMUX_IPSR_GPSR(IP12_23_20,    CTS1_N),
1194         PINMUX_IPSR_MSEL(IP12_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1195         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1196         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1197         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1198         PINMUX_IPSR_MSEL(IP12_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1199         PINMUX_IPSR_GPSR(IP12_23_20,    ADIDATA),
1200
1201         PINMUX_IPSR_GPSR(IP12_27_24,    RTS1_N),
1202         PINMUX_IPSR_MSEL(IP12_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1203         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1204         PINMUX_IPSR_MSEL(IP12_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1205         PINMUX_IPSR_MSEL(IP12_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1206         PINMUX_IPSR_MSEL(IP12_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1207         PINMUX_IPSR_GPSR(IP12_27_24,    ADICHS0),
1208
1209         PINMUX_IPSR_GPSR(IP12_31_28,    SCK2),
1210         PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,             SEL_SCIF_1),
1211         PINMUX_IPSR_MSEL(IP12_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1212         PINMUX_IPSR_MSEL(IP12_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1213         PINMUX_IPSR_MSEL(IP12_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1214         PINMUX_IPSR_MSEL(IP12_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1215         PINMUX_IPSR_GPSR(IP12_31_28,    ADICLK),
1216
1217         /* IPSR13 */
1218         PINMUX_IPSR_MSEL(IP13_3_0,      TX2_A,                  SEL_SCIF2_0),
1219         PINMUX_IPSR_MSEL(IP13_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1220         PINMUX_IPSR_MSEL(IP13_3_0,      SCL1_A,                 SEL_I2C1_0),
1221         PINMUX_IPSR_MSEL(IP13_3_0,      FMCLK_A,                SEL_FM_0),
1222         PINMUX_IPSR_MSEL(IP13_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1223         PINMUX_IPSR_GPSR(IP13_3_0,      FSO_CFE_0_N),
1224
1225         PINMUX_IPSR_MSEL(IP13_7_4,      RX2_A,                  SEL_SCIF2_0),
1226         PINMUX_IPSR_MSEL(IP13_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1227         PINMUX_IPSR_MSEL(IP13_7_4,      SDA1_A,                 SEL_I2C1_0),
1228         PINMUX_IPSR_MSEL(IP13_7_4,      FMIN_A,                 SEL_FM_0),
1229         PINMUX_IPSR_MSEL(IP13_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1230         PINMUX_IPSR_GPSR(IP13_7_4,      FSO_CFE_1_N),
1231
1232         PINMUX_IPSR_GPSR(IP13_11_8,     HSCK0),
1233         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1234         PINMUX_IPSR_MSEL(IP13_11_8,     AUDIO_CLKB_A,           SEL_ADGB_0),
1235         PINMUX_IPSR_MSEL(IP13_11_8,     SSI_SDATA1_B,           SEL_SSI1_1),
1236         PINMUX_IPSR_MSEL(IP13_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1237         PINMUX_IPSR_MSEL(IP13_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1238         PINMUX_IPSR_MSEL(IP13_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1239         PINMUX_IPSR_MSEL(IP13_11_8,     RX5_B,                  SEL_SCIF5_1),
1240
1241         PINMUX_IPSR_GPSR(IP13_15_12,    HRX0),
1242         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1243         PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,           SEL_SSI2_1),
1244         PINMUX_IPSR_MSEL(IP13_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1245         PINMUX_IPSR_MSEL(IP13_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1246         PINMUX_IPSR_MSEL(IP13_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1247
1248         PINMUX_IPSR_GPSR(IP13_19_16,    HTX0),
1249         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1250         PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,           SEL_SSI9_1),
1251         PINMUX_IPSR_MSEL(IP13_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1252         PINMUX_IPSR_MSEL(IP13_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1253         PINMUX_IPSR_MSEL(IP13_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1254
1255         PINMUX_IPSR_GPSR(IP13_23_20,    HCTS0_N),
1256         PINMUX_IPSR_MSEL(IP13_23_20,    RX2_B,                  SEL_SCIF2_1),
1257         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1258         PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,             SEL_SSI9_0),
1259         PINMUX_IPSR_MSEL(IP13_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1260         PINMUX_IPSR_MSEL(IP13_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1261         PINMUX_IPSR_MSEL(IP13_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1262         PINMUX_IPSR_GPSR(IP13_23_20,    AUDIO_CLKOUT1_A),
1263
1264         PINMUX_IPSR_GPSR(IP13_27_24,    HRTS0_N),
1265         PINMUX_IPSR_MSEL(IP13_27_24,    TX2_B,                  SEL_SCIF2_1),
1266         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1267         PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,              SEL_SSI9_0),
1268         PINMUX_IPSR_MSEL(IP13_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1269         PINMUX_IPSR_MSEL(IP13_27_24,    BPFCLK_A,               SEL_FM_0),
1270         PINMUX_IPSR_GPSR(IP13_27_24,    AUDIO_CLKOUT2_A),
1271
1272         PINMUX_IPSR_GPSR(IP13_31_28,    MSIOF0_SYNC),
1273         PINMUX_IPSR_GPSR(IP13_31_28,    AUDIO_CLKOUT_A),
1274         PINMUX_IPSR_MSEL(IP13_31_28,    TX5_B,                  SEL_SCIF5_1),
1275         PINMUX_IPSR_MSEL(IP13_31_28,    BPFCLK_D,               SEL_FM_3),
1276
1277         /* IPSR14 */
1278         PINMUX_IPSR_GPSR(IP14_3_0,      MSIOF0_SS1),
1279         PINMUX_IPSR_MSEL(IP14_3_0,      RX5_A,                  SEL_SCIF5_0),
1280         PINMUX_IPSR_MSEL(IP14_3_0,      NFWP_N_A,               SEL_NDF_0),
1281         PINMUX_IPSR_MSEL(IP14_3_0,      AUDIO_CLKA_C,           SEL_ADGA_2),
1282         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SCK2_A,             SEL_SSI2_0),
1283         PINMUX_IPSR_MSEL(IP14_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1284         PINMUX_IPSR_GPSR(IP14_3_0,      AUDIO_CLKOUT3_A),
1285         PINMUX_IPSR_MSEL(IP14_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
1286
1287         PINMUX_IPSR_GPSR(IP14_7_4,      MSIOF0_SS2),
1288         PINMUX_IPSR_MSEL(IP14_7_4,      TX5_A,                  SEL_SCIF5_0),
1289         PINMUX_IPSR_MSEL(IP14_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1290         PINMUX_IPSR_MSEL(IP14_7_4,      AUDIO_CLKC_A,           SEL_ADGC_0),
1291         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_WS2_A,              SEL_SSI2_0),
1292         PINMUX_IPSR_MSEL(IP14_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1293         PINMUX_IPSR_GPSR(IP14_7_4,      AUDIO_CLKOUT_D),
1294         PINMUX_IPSR_MSEL(IP14_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1295
1296         PINMUX_IPSR_GPSR(IP14_11_8,     MLB_CLK),
1297         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1298         PINMUX_IPSR_MSEL(IP14_11_8,     SCL1_B,                 SEL_I2C1_1),
1299
1300         PINMUX_IPSR_GPSR(IP14_15_12,    MLB_SIG),
1301         PINMUX_IPSR_MSEL(IP14_15_12,    RX1_B,                  SEL_SCIF1_1),
1302         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1303         PINMUX_IPSR_MSEL(IP14_15_12,    SDA1_B,                 SEL_I2C1_1),
1304
1305         PINMUX_IPSR_GPSR(IP14_19_16,    MLB_DAT),
1306         PINMUX_IPSR_MSEL(IP14_19_16,    TX1_B,                  SEL_SCIF1_1),
1307         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1308
1309         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK01239),
1310         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1311
1312         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS01239),
1313         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1314
1315         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA0),
1316         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1317
1318         /* IPSR15 */
1319         PINMUX_IPSR_MSEL(IP15_3_0,      SSI_SDATA1_A,           SEL_SSI1_0),
1320
1321         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SDATA2_A,           SEL_SSI2_0),
1322         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SCK1_B,             SEL_SSI1_1),
1323
1324         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SCK349),
1325         PINMUX_IPSR_MSEL(IP15_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1326         PINMUX_IPSR_MSEL(IP15_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1327
1328         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_WS349),
1329         PINMUX_IPSR_MSEL(IP15_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1330         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1331         PINMUX_IPSR_MSEL(IP15_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1332
1333         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_SDATA3),
1334         PINMUX_IPSR_MSEL(IP15_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1335         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1336         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1337         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1338         PINMUX_IPSR_MSEL(IP15_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1339         PINMUX_IPSR_MSEL(IP15_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1340
1341         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SCK4),
1342         PINMUX_IPSR_MSEL(IP15_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1343         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1344         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1345         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1346         PINMUX_IPSR_MSEL(IP15_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1347         PINMUX_IPSR_MSEL(IP15_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1348
1349         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_WS4),
1350         PINMUX_IPSR_MSEL(IP15_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1351         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1352         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1353         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1354         PINMUX_IPSR_MSEL(IP15_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1355         PINMUX_IPSR_MSEL(IP15_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1356
1357         PINMUX_IPSR_GPSR(IP15_31_28,    SSI_SDATA4),
1358         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1359         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1360         PINMUX_IPSR_MSEL(IP15_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1361         PINMUX_IPSR_MSEL(IP15_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1362         PINMUX_IPSR_MSEL(IP15_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1363         PINMUX_IPSR_MSEL(IP15_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1364
1365         /* IPSR16 */
1366         PINMUX_IPSR_GPSR(IP16_3_0,      SSI_SCK6),
1367         PINMUX_IPSR_MSEL(IP16_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1368
1369         PINMUX_IPSR_GPSR(IP16_7_4,      SSI_WS6),
1370         PINMUX_IPSR_MSEL(IP16_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1371
1372         PINMUX_IPSR_GPSR(IP16_11_8,     SSI_SDATA6),
1373         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1374
1375         PINMUX_IPSR_GPSR(IP16_15_12,    SSI_SCK78),
1376         PINMUX_IPSR_MSEL(IP16_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1377         PINMUX_IPSR_MSEL(IP16_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1378         PINMUX_IPSR_MSEL(IP16_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1379         PINMUX_IPSR_MSEL(IP16_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1380         PINMUX_IPSR_MSEL(IP16_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1381         PINMUX_IPSR_MSEL(IP16_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1382
1383         PINMUX_IPSR_GPSR(IP16_19_16,    SSI_WS78),
1384         PINMUX_IPSR_MSEL(IP16_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1385         PINMUX_IPSR_MSEL(IP16_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1386         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1387         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1388         PINMUX_IPSR_MSEL(IP16_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1389         PINMUX_IPSR_MSEL(IP16_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1390
1391         PINMUX_IPSR_GPSR(IP16_23_20,    SSI_SDATA7),
1392         PINMUX_IPSR_MSEL(IP16_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1393         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1394         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1395         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1396         PINMUX_IPSR_MSEL(IP16_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1397         PINMUX_IPSR_MSEL(IP16_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1398         PINMUX_IPSR_MSEL(IP16_23_20,    TCLK2_A,                SEL_TIMER_TMU2_0),
1399
1400         PINMUX_IPSR_GPSR(IP16_27_24,    SSI_SDATA8),
1401         PINMUX_IPSR_MSEL(IP16_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1402         PINMUX_IPSR_MSEL(IP16_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1403         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1404         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1405         PINMUX_IPSR_MSEL(IP16_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1406         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1407
1408         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,           SEL_SSI9_0),
1409         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1410         PINMUX_IPSR_MSEL(IP16_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1411         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1412         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,              SEL_SSI1_1),
1413         PINMUX_IPSR_GPSR(IP16_31_28,    SCK1),
1414         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1415         PINMUX_IPSR_MSEL(IP16_31_28,    SCK5_A,                 SEL_SCIF5_0),
1416
1417         /* IPSR17 */
1418         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKA_A,           SEL_ADGA_0),
1419
1420         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKB_B,           SEL_ADGB_1),
1421         PINMUX_IPSR_MSEL(IP17_7_4,      SCIF_CLK_A,             SEL_SCIF_0),
1422         PINMUX_IPSR_MSEL(IP17_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1423         PINMUX_IPSR_MSEL(IP17_7_4,      REMOCON_A,              SEL_REMOCON_0),
1424         PINMUX_IPSR_MSEL(IP17_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
1425
1426         PINMUX_IPSR_GPSR(IP17_11_8,     USB0_PWEN),
1427         PINMUX_IPSR_MSEL(IP17_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1428         PINMUX_IPSR_MSEL(IP17_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1429         PINMUX_IPSR_MSEL(IP17_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1430         PINMUX_IPSR_MSEL(IP17_11_8,     BPFCLK_B,               SEL_FM_1),
1431         PINMUX_IPSR_MSEL(IP17_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1432         PINMUX_IPSR_MSEL(IP17_11_8,     HSCK2_C,                SEL_HSCIF2_2),
1433
1434         PINMUX_IPSR_GPSR(IP17_15_12,    USB0_OVC),
1435         PINMUX_IPSR_MSEL(IP17_15_12,    SIM0_D_C,               SEL_SIMCARD_2),
1436         PINMUX_IPSR_MSEL(IP17_15_12,    TS_SDAT1_D,             SEL_TSIF1_3),
1437         PINMUX_IPSR_MSEL(IP17_15_12,    STP_ISD_1_D,            SEL_SSP1_1_3),
1438         PINMUX_IPSR_MSEL(IP17_15_12,    RIF3_SYNC_B,            SEL_DRIF3_1),
1439         PINMUX_IPSR_MSEL(IP17_15_12,    HRX2_C,                 SEL_HSCIF2_2),
1440
1441         PINMUX_IPSR_GPSR(IP17_19_16,    USB1_PWEN),
1442         PINMUX_IPSR_MSEL(IP17_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1443         PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,             SEL_SSI1_0),
1444         PINMUX_IPSR_MSEL(IP17_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1445         PINMUX_IPSR_MSEL(IP17_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1446         PINMUX_IPSR_MSEL(IP17_19_16,    FMCLK_B,                SEL_FM_1),
1447         PINMUX_IPSR_MSEL(IP17_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1448         PINMUX_IPSR_MSEL(IP17_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1449         PINMUX_IPSR_MSEL(IP17_19_16,    HTX2_C,                 SEL_HSCIF2_2),
1450
1451         PINMUX_IPSR_GPSR(IP17_23_20,    USB1_OVC),
1452         PINMUX_IPSR_MSEL(IP17_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1453         PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,              SEL_SSI1_0),
1454         PINMUX_IPSR_MSEL(IP17_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1455         PINMUX_IPSR_MSEL(IP17_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1456         PINMUX_IPSR_MSEL(IP17_23_20,    FMIN_B,                 SEL_FM_1),
1457         PINMUX_IPSR_MSEL(IP17_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1458         PINMUX_IPSR_MSEL(IP17_23_20,    REMOCON_B,              SEL_REMOCON_1),
1459         PINMUX_IPSR_MSEL(IP17_23_20,    HCTS2_N_C,              SEL_HSCIF2_2),
1460
1461         PINMUX_IPSR_GPSR(IP17_27_24,    USB30_PWEN),
1462         PINMUX_IPSR_GPSR(IP17_27_24,    AUDIO_CLKOUT_B),
1463         PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,             SEL_SSI2_1),
1464         PINMUX_IPSR_MSEL(IP17_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1465         PINMUX_IPSR_MSEL(IP17_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1466         PINMUX_IPSR_MSEL(IP17_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1467         PINMUX_IPSR_MSEL(IP17_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1468         PINMUX_IPSR_MSEL(IP17_27_24,    TCLK2_B,                SEL_TIMER_TMU2_1),
1469         PINMUX_IPSR_GPSR(IP17_27_24,    TPU0TO0),
1470         PINMUX_IPSR_MSEL(IP17_27_24,    BPFCLK_C,               SEL_FM_2),
1471         PINMUX_IPSR_MSEL(IP17_27_24,    HRTS2_N_C,              SEL_HSCIF2_2),
1472
1473         PINMUX_IPSR_GPSR(IP17_31_28,    USB30_OVC),
1474         PINMUX_IPSR_GPSR(IP17_31_28,    AUDIO_CLKOUT1_B),
1475         PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,              SEL_SSI2_1),
1476         PINMUX_IPSR_MSEL(IP17_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1477         PINMUX_IPSR_MSEL(IP17_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1478         PINMUX_IPSR_MSEL(IP17_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1479         PINMUX_IPSR_MSEL(IP17_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1480         PINMUX_IPSR_GPSR(IP17_31_28,    FSO_TOE_N),
1481         PINMUX_IPSR_GPSR(IP17_31_28,    TPU0TO1),
1482
1483         /* IPSR18 */
1484         PINMUX_IPSR_GPSR(IP18_3_0,      GP6_30),
1485         PINMUX_IPSR_GPSR(IP18_3_0,      AUDIO_CLKOUT2_B),
1486         PINMUX_IPSR_MSEL(IP18_3_0,      SSI_SCK9_B,             SEL_SSI9_1),
1487         PINMUX_IPSR_MSEL(IP18_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1488         PINMUX_IPSR_MSEL(IP18_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1489         PINMUX_IPSR_MSEL(IP18_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1490         PINMUX_IPSR_GPSR(IP18_3_0,      TPU0TO2),
1491         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_C,                SEL_FM_2),
1492         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_D,                SEL_FM_3),
1493
1494         PINMUX_IPSR_GPSR(IP18_7_4,      GP6_31),
1495         PINMUX_IPSR_GPSR(IP18_7_4,      AUDIO_CLKOUT3_B),
1496         PINMUX_IPSR_MSEL(IP18_7_4,      SSI_WS9_B,              SEL_SSI9_1),
1497         PINMUX_IPSR_MSEL(IP18_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1498         PINMUX_IPSR_MSEL(IP18_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1499         PINMUX_IPSR_MSEL(IP18_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1500         PINMUX_IPSR_GPSR(IP18_7_4,      TPU0TO3),
1501         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_C,                 SEL_FM_2),
1502         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_D,                 SEL_FM_3),
1503
1504 /*
1505  * Static pins can not be muxed between different functions but
1506  * still need mark entries in the pinmux list. Add each static
1507  * pin to the list without an associated function. The sh-pfc
1508  * core will do the right thing and skip trying to mux the pin
1509  * while still applying configuration to it.
1510  */
1511 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1512         PINMUX_STATIC
1513 #undef FM
1514 };
1515
1516 /*
1517  * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1518  * Physical layout rows: A - AW, cols: 1 - 39.
1519  */
1520 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1521 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1522 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1523 #define PIN_NONE U16_MAX
1524
1525 static const struct sh_pfc_pin pinmux_pins[] = {
1526         PINMUX_GPIO_GP_ALL(),
1527
1528         /*
1529          * Pins not associated with a GPIO port.
1530          *
1531          * The pin positions are different between different r8a7796
1532          * packages, all that is needed for the pfc driver is a unique
1533          * number for each pin. To this end use the pin layout from
1534          * R-Car M3SiP to calculate a unique number for each pin.
1535          */
1536         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1537         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1538         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1539         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1540         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1541         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1542         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1543         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1544         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1545         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1546         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1547         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1548         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1549         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1550         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1551         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1552         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1553         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1554         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1555         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1556         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1557         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1558         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1559         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1560         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1561         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1562         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1563         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1564         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1565         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1566         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1567         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1568         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1569         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1570         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1571         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN2, CFG_FLAGS),
1572         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1573         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1575         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1576         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1577         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1578 };
1579
1580 /* - AUDIO CLOCK ------------------------------------------------------------ */
1581 static const unsigned int audio_clk_a_a_pins[] = {
1582         /* CLK A */
1583         RCAR_GP_PIN(6, 22),
1584 };
1585 static const unsigned int audio_clk_a_a_mux[] = {
1586         AUDIO_CLKA_A_MARK,
1587 };
1588 static const unsigned int audio_clk_a_b_pins[] = {
1589         /* CLK A */
1590         RCAR_GP_PIN(5, 4),
1591 };
1592 static const unsigned int audio_clk_a_b_mux[] = {
1593         AUDIO_CLKA_B_MARK,
1594 };
1595 static const unsigned int audio_clk_a_c_pins[] = {
1596         /* CLK A */
1597         RCAR_GP_PIN(5, 19),
1598 };
1599 static const unsigned int audio_clk_a_c_mux[] = {
1600         AUDIO_CLKA_C_MARK,
1601 };
1602 static const unsigned int audio_clk_b_a_pins[] = {
1603         /* CLK B */
1604         RCAR_GP_PIN(5, 12),
1605 };
1606 static const unsigned int audio_clk_b_a_mux[] = {
1607         AUDIO_CLKB_A_MARK,
1608 };
1609 static const unsigned int audio_clk_b_b_pins[] = {
1610         /* CLK B */
1611         RCAR_GP_PIN(6, 23),
1612 };
1613 static const unsigned int audio_clk_b_b_mux[] = {
1614         AUDIO_CLKB_B_MARK,
1615 };
1616 static const unsigned int audio_clk_c_a_pins[] = {
1617         /* CLK C */
1618         RCAR_GP_PIN(5, 21),
1619 };
1620 static const unsigned int audio_clk_c_a_mux[] = {
1621         AUDIO_CLKC_A_MARK,
1622 };
1623 static const unsigned int audio_clk_c_b_pins[] = {
1624         /* CLK C */
1625         RCAR_GP_PIN(5, 0),
1626 };
1627 static const unsigned int audio_clk_c_b_mux[] = {
1628         AUDIO_CLKC_B_MARK,
1629 };
1630 static const unsigned int audio_clkout_a_pins[] = {
1631         /* CLKOUT */
1632         RCAR_GP_PIN(5, 18),
1633 };
1634 static const unsigned int audio_clkout_a_mux[] = {
1635         AUDIO_CLKOUT_A_MARK,
1636 };
1637 static const unsigned int audio_clkout_b_pins[] = {
1638         /* CLKOUT */
1639         RCAR_GP_PIN(6, 28),
1640 };
1641 static const unsigned int audio_clkout_b_mux[] = {
1642         AUDIO_CLKOUT_B_MARK,
1643 };
1644 static const unsigned int audio_clkout_c_pins[] = {
1645         /* CLKOUT */
1646         RCAR_GP_PIN(5, 3),
1647 };
1648 static const unsigned int audio_clkout_c_mux[] = {
1649         AUDIO_CLKOUT_C_MARK,
1650 };
1651 static const unsigned int audio_clkout_d_pins[] = {
1652         /* CLKOUT */
1653         RCAR_GP_PIN(5, 21),
1654 };
1655 static const unsigned int audio_clkout_d_mux[] = {
1656         AUDIO_CLKOUT_D_MARK,
1657 };
1658 static const unsigned int audio_clkout1_a_pins[] = {
1659         /* CLKOUT1 */
1660         RCAR_GP_PIN(5, 15),
1661 };
1662 static const unsigned int audio_clkout1_a_mux[] = {
1663         AUDIO_CLKOUT1_A_MARK,
1664 };
1665 static const unsigned int audio_clkout1_b_pins[] = {
1666         /* CLKOUT1 */
1667         RCAR_GP_PIN(6, 29),
1668 };
1669 static const unsigned int audio_clkout1_b_mux[] = {
1670         AUDIO_CLKOUT1_B_MARK,
1671 };
1672 static const unsigned int audio_clkout2_a_pins[] = {
1673         /* CLKOUT2 */
1674         RCAR_GP_PIN(5, 16),
1675 };
1676 static const unsigned int audio_clkout2_a_mux[] = {
1677         AUDIO_CLKOUT2_A_MARK,
1678 };
1679 static const unsigned int audio_clkout2_b_pins[] = {
1680         /* CLKOUT2 */
1681         RCAR_GP_PIN(6, 30),
1682 };
1683 static const unsigned int audio_clkout2_b_mux[] = {
1684         AUDIO_CLKOUT2_B_MARK,
1685 };
1686
1687 static const unsigned int audio_clkout3_a_pins[] = {
1688         /* CLKOUT3 */
1689         RCAR_GP_PIN(5, 19),
1690 };
1691 static const unsigned int audio_clkout3_a_mux[] = {
1692         AUDIO_CLKOUT3_A_MARK,
1693 };
1694 static const unsigned int audio_clkout3_b_pins[] = {
1695         /* CLKOUT3 */
1696         RCAR_GP_PIN(6, 31),
1697 };
1698 static const unsigned int audio_clkout3_b_mux[] = {
1699         AUDIO_CLKOUT3_B_MARK,
1700 };
1701
1702 /* - EtherAVB --------------------------------------------------------------- */
1703 static const unsigned int avb_link_pins[] = {
1704         /* AVB_LINK */
1705         RCAR_GP_PIN(2, 12),
1706 };
1707 static const unsigned int avb_link_mux[] = {
1708         AVB_LINK_MARK,
1709 };
1710 static const unsigned int avb_magic_pins[] = {
1711         /* AVB_MAGIC_ */
1712         RCAR_GP_PIN(2, 10),
1713 };
1714 static const unsigned int avb_magic_mux[] = {
1715         AVB_MAGIC_MARK,
1716 };
1717 static const unsigned int avb_phy_int_pins[] = {
1718         /* AVB_PHY_INT */
1719         RCAR_GP_PIN(2, 11),
1720 };
1721 static const unsigned int avb_phy_int_mux[] = {
1722         AVB_PHY_INT_MARK,
1723 };
1724 static const unsigned int avb_mdio_pins[] = {
1725         /* AVB_MDC, AVB_MDIO */
1726         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1727 };
1728 static const unsigned int avb_mdio_mux[] = {
1729         AVB_MDC_MARK, AVB_MDIO_MARK,
1730 };
1731 static const unsigned int avb_mii_pins[] = {
1732         /*
1733          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1734          * AVB_TD1, AVB_TD2, AVB_TD3,
1735          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1736          * AVB_RD1, AVB_RD2, AVB_RD3,
1737          * AVB_TXCREFCLK
1738          */
1739         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1740         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1741         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1742         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1743         PIN_NUMBER('A', 12),
1744
1745 };
1746 static const unsigned int avb_mii_mux[] = {
1747         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1748         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1749         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1750         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1751         AVB_TXCREFCLK_MARK,
1752 };
1753 static const unsigned int avb_avtp_pps_pins[] = {
1754         /* AVB_AVTP_PPS */
1755         RCAR_GP_PIN(2, 6),
1756 };
1757 static const unsigned int avb_avtp_pps_mux[] = {
1758         AVB_AVTP_PPS_MARK,
1759 };
1760 static const unsigned int avb_avtp_match_a_pins[] = {
1761         /* AVB_AVTP_MATCH_A */
1762         RCAR_GP_PIN(2, 13),
1763 };
1764 static const unsigned int avb_avtp_match_a_mux[] = {
1765         AVB_AVTP_MATCH_A_MARK,
1766 };
1767 static const unsigned int avb_avtp_capture_a_pins[] = {
1768         /* AVB_AVTP_CAPTURE_A */
1769         RCAR_GP_PIN(2, 14),
1770 };
1771 static const unsigned int avb_avtp_capture_a_mux[] = {
1772         AVB_AVTP_CAPTURE_A_MARK,
1773 };
1774 static const unsigned int avb_avtp_match_b_pins[] = {
1775         /*  AVB_AVTP_MATCH_B */
1776         RCAR_GP_PIN(1, 8),
1777 };
1778 static const unsigned int avb_avtp_match_b_mux[] = {
1779         AVB_AVTP_MATCH_B_MARK,
1780 };
1781 static const unsigned int avb_avtp_capture_b_pins[] = {
1782         /* AVB_AVTP_CAPTURE_B */
1783         RCAR_GP_PIN(1, 11),
1784 };
1785 static const unsigned int avb_avtp_capture_b_mux[] = {
1786         AVB_AVTP_CAPTURE_B_MARK,
1787 };
1788
1789 /* - CAN ------------------------------------------------------------------ */
1790 static const unsigned int can0_data_a_pins[] = {
1791         /* TX, RX */
1792         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1793 };
1794 static const unsigned int can0_data_a_mux[] = {
1795         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1796 };
1797 static const unsigned int can0_data_b_pins[] = {
1798         /* TX, RX */
1799         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1800 };
1801 static const unsigned int can0_data_b_mux[] = {
1802         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1803 };
1804 static const unsigned int can1_data_pins[] = {
1805         /* TX, RX */
1806         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1807 };
1808 static const unsigned int can1_data_mux[] = {
1809         CAN1_TX_MARK,           CAN1_RX_MARK,
1810 };
1811
1812 /* - CAN Clock -------------------------------------------------------------- */
1813 static const unsigned int can_clk_pins[] = {
1814         /* CLK */
1815         RCAR_GP_PIN(1, 25),
1816 };
1817 static const unsigned int can_clk_mux[] = {
1818         CAN_CLK_MARK,
1819 };
1820
1821 /* - CAN FD --------------------------------------------------------------- */
1822 static const unsigned int canfd0_data_a_pins[] = {
1823         /* TX, RX */
1824         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1825 };
1826 static const unsigned int canfd0_data_a_mux[] = {
1827         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1828 };
1829 static const unsigned int canfd0_data_b_pins[] = {
1830         /* TX, RX */
1831         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1832 };
1833 static const unsigned int canfd0_data_b_mux[] = {
1834         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1835 };
1836 static const unsigned int canfd1_data_pins[] = {
1837         /* TX, RX */
1838         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1839 };
1840 static const unsigned int canfd1_data_mux[] = {
1841         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1842 };
1843
1844 /* - DRIF0 --------------------------------------------------------------- */
1845 static const unsigned int drif0_ctrl_a_pins[] = {
1846         /* CLK, SYNC */
1847         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1848 };
1849 static const unsigned int drif0_ctrl_a_mux[] = {
1850         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1851 };
1852 static const unsigned int drif0_data0_a_pins[] = {
1853         /* D0 */
1854         RCAR_GP_PIN(6, 10),
1855 };
1856 static const unsigned int drif0_data0_a_mux[] = {
1857         RIF0_D0_A_MARK,
1858 };
1859 static const unsigned int drif0_data1_a_pins[] = {
1860         /* D1 */
1861         RCAR_GP_PIN(6, 7),
1862 };
1863 static const unsigned int drif0_data1_a_mux[] = {
1864         RIF0_D1_A_MARK,
1865 };
1866 static const unsigned int drif0_ctrl_b_pins[] = {
1867         /* CLK, SYNC */
1868         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1869 };
1870 static const unsigned int drif0_ctrl_b_mux[] = {
1871         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1872 };
1873 static const unsigned int drif0_data0_b_pins[] = {
1874         /* D0 */
1875         RCAR_GP_PIN(5, 1),
1876 };
1877 static const unsigned int drif0_data0_b_mux[] = {
1878         RIF0_D0_B_MARK,
1879 };
1880 static const unsigned int drif0_data1_b_pins[] = {
1881         /* D1 */
1882         RCAR_GP_PIN(5, 2),
1883 };
1884 static const unsigned int drif0_data1_b_mux[] = {
1885         RIF0_D1_B_MARK,
1886 };
1887 static const unsigned int drif0_ctrl_c_pins[] = {
1888         /* CLK, SYNC */
1889         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1890 };
1891 static const unsigned int drif0_ctrl_c_mux[] = {
1892         RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1893 };
1894 static const unsigned int drif0_data0_c_pins[] = {
1895         /* D0 */
1896         RCAR_GP_PIN(5, 13),
1897 };
1898 static const unsigned int drif0_data0_c_mux[] = {
1899         RIF0_D0_C_MARK,
1900 };
1901 static const unsigned int drif0_data1_c_pins[] = {
1902         /* D1 */
1903         RCAR_GP_PIN(5, 14),
1904 };
1905 static const unsigned int drif0_data1_c_mux[] = {
1906         RIF0_D1_C_MARK,
1907 };
1908 /* - DRIF1 --------------------------------------------------------------- */
1909 static const unsigned int drif1_ctrl_a_pins[] = {
1910         /* CLK, SYNC */
1911         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1912 };
1913 static const unsigned int drif1_ctrl_a_mux[] = {
1914         RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1915 };
1916 static const unsigned int drif1_data0_a_pins[] = {
1917         /* D0 */
1918         RCAR_GP_PIN(6, 19),
1919 };
1920 static const unsigned int drif1_data0_a_mux[] = {
1921         RIF1_D0_A_MARK,
1922 };
1923 static const unsigned int drif1_data1_a_pins[] = {
1924         /* D1 */
1925         RCAR_GP_PIN(6, 20),
1926 };
1927 static const unsigned int drif1_data1_a_mux[] = {
1928         RIF1_D1_A_MARK,
1929 };
1930 static const unsigned int drif1_ctrl_b_pins[] = {
1931         /* CLK, SYNC */
1932         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1933 };
1934 static const unsigned int drif1_ctrl_b_mux[] = {
1935         RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1936 };
1937 static const unsigned int drif1_data0_b_pins[] = {
1938         /* D0 */
1939         RCAR_GP_PIN(5, 7),
1940 };
1941 static const unsigned int drif1_data0_b_mux[] = {
1942         RIF1_D0_B_MARK,
1943 };
1944 static const unsigned int drif1_data1_b_pins[] = {
1945         /* D1 */
1946         RCAR_GP_PIN(5, 8),
1947 };
1948 static const unsigned int drif1_data1_b_mux[] = {
1949         RIF1_D1_B_MARK,
1950 };
1951 static const unsigned int drif1_ctrl_c_pins[] = {
1952         /* CLK, SYNC */
1953         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1954 };
1955 static const unsigned int drif1_ctrl_c_mux[] = {
1956         RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1957 };
1958 static const unsigned int drif1_data0_c_pins[] = {
1959         /* D0 */
1960         RCAR_GP_PIN(5, 6),
1961 };
1962 static const unsigned int drif1_data0_c_mux[] = {
1963         RIF1_D0_C_MARK,
1964 };
1965 static const unsigned int drif1_data1_c_pins[] = {
1966         /* D1 */
1967         RCAR_GP_PIN(5, 10),
1968 };
1969 static const unsigned int drif1_data1_c_mux[] = {
1970         RIF1_D1_C_MARK,
1971 };
1972 /* - DRIF2 --------------------------------------------------------------- */
1973 static const unsigned int drif2_ctrl_a_pins[] = {
1974         /* CLK, SYNC */
1975         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1976 };
1977 static const unsigned int drif2_ctrl_a_mux[] = {
1978         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1979 };
1980 static const unsigned int drif2_data0_a_pins[] = {
1981         /* D0 */
1982         RCAR_GP_PIN(6, 7),
1983 };
1984 static const unsigned int drif2_data0_a_mux[] = {
1985         RIF2_D0_A_MARK,
1986 };
1987 static const unsigned int drif2_data1_a_pins[] = {
1988         /* D1 */
1989         RCAR_GP_PIN(6, 10),
1990 };
1991 static const unsigned int drif2_data1_a_mux[] = {
1992         RIF2_D1_A_MARK,
1993 };
1994 static const unsigned int drif2_ctrl_b_pins[] = {
1995         /* CLK, SYNC */
1996         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1997 };
1998 static const unsigned int drif2_ctrl_b_mux[] = {
1999         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
2000 };
2001 static const unsigned int drif2_data0_b_pins[] = {
2002         /* D0 */
2003         RCAR_GP_PIN(6, 30),
2004 };
2005 static const unsigned int drif2_data0_b_mux[] = {
2006         RIF2_D0_B_MARK,
2007 };
2008 static const unsigned int drif2_data1_b_pins[] = {
2009         /* D1 */
2010         RCAR_GP_PIN(6, 31),
2011 };
2012 static const unsigned int drif2_data1_b_mux[] = {
2013         RIF2_D1_B_MARK,
2014 };
2015 /* - DRIF3 --------------------------------------------------------------- */
2016 static const unsigned int drif3_ctrl_a_pins[] = {
2017         /* CLK, SYNC */
2018         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2019 };
2020 static const unsigned int drif3_ctrl_a_mux[] = {
2021         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2022 };
2023 static const unsigned int drif3_data0_a_pins[] = {
2024         /* D0 */
2025         RCAR_GP_PIN(6, 19),
2026 };
2027 static const unsigned int drif3_data0_a_mux[] = {
2028         RIF3_D0_A_MARK,
2029 };
2030 static const unsigned int drif3_data1_a_pins[] = {
2031         /* D1 */
2032         RCAR_GP_PIN(6, 20),
2033 };
2034 static const unsigned int drif3_data1_a_mux[] = {
2035         RIF3_D1_A_MARK,
2036 };
2037 static const unsigned int drif3_ctrl_b_pins[] = {
2038         /* CLK, SYNC */
2039         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2040 };
2041 static const unsigned int drif3_ctrl_b_mux[] = {
2042         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2043 };
2044 static const unsigned int drif3_data0_b_pins[] = {
2045         /* D0 */
2046         RCAR_GP_PIN(6, 28),
2047 };
2048 static const unsigned int drif3_data0_b_mux[] = {
2049         RIF3_D0_B_MARK,
2050 };
2051 static const unsigned int drif3_data1_b_pins[] = {
2052         /* D1 */
2053         RCAR_GP_PIN(6, 29),
2054 };
2055 static const unsigned int drif3_data1_b_mux[] = {
2056         RIF3_D1_B_MARK,
2057 };
2058
2059 /* - DU --------------------------------------------------------------------- */
2060 static const unsigned int du_rgb666_pins[] = {
2061         /* R[7:2], G[7:2], B[7:2] */
2062         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2063         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2064         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2065         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2066         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2067         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2068 };
2069 static const unsigned int du_rgb666_mux[] = {
2070         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2071         DU_DR3_MARK, DU_DR2_MARK,
2072         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2073         DU_DG3_MARK, DU_DG2_MARK,
2074         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2075         DU_DB3_MARK, DU_DB2_MARK,
2076 };
2077 static const unsigned int du_rgb888_pins[] = {
2078         /* R[7:0], G[7:0], B[7:0] */
2079         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2080         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2081         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2082         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2083         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2084         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2085         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2086         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2087         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2088 };
2089 static const unsigned int du_rgb888_mux[] = {
2090         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2091         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2092         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2093         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2094         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2095         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2096 };
2097 static const unsigned int du_clk_out_0_pins[] = {
2098         /* CLKOUT */
2099         RCAR_GP_PIN(1, 27),
2100 };
2101 static const unsigned int du_clk_out_0_mux[] = {
2102         DU_DOTCLKOUT0_MARK
2103 };
2104 static const unsigned int du_clk_out_1_pins[] = {
2105         /* CLKOUT */
2106         RCAR_GP_PIN(2, 3),
2107 };
2108 static const unsigned int du_clk_out_1_mux[] = {
2109         DU_DOTCLKOUT1_MARK
2110 };
2111 static const unsigned int du_sync_pins[] = {
2112         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2113         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2114 };
2115 static const unsigned int du_sync_mux[] = {
2116         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2117 };
2118 static const unsigned int du_oddf_pins[] = {
2119         /* EXDISP/EXODDF/EXCDE */
2120         RCAR_GP_PIN(2, 2),
2121 };
2122 static const unsigned int du_oddf_mux[] = {
2123         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2124 };
2125 static const unsigned int du_cde_pins[] = {
2126         /* CDE */
2127         RCAR_GP_PIN(2, 0),
2128 };
2129 static const unsigned int du_cde_mux[] = {
2130         DU_CDE_MARK,
2131 };
2132 static const unsigned int du_disp_pins[] = {
2133         /* DISP */
2134         RCAR_GP_PIN(2, 1),
2135 };
2136 static const unsigned int du_disp_mux[] = {
2137         DU_DISP_MARK,
2138 };
2139
2140 /* - HSCIF0 ----------------------------------------------------------------- */
2141 static const unsigned int hscif0_data_pins[] = {
2142         /* RX, TX */
2143         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2144 };
2145 static const unsigned int hscif0_data_mux[] = {
2146         HRX0_MARK, HTX0_MARK,
2147 };
2148 static const unsigned int hscif0_clk_pins[] = {
2149         /* SCK */
2150         RCAR_GP_PIN(5, 12),
2151 };
2152 static const unsigned int hscif0_clk_mux[] = {
2153         HSCK0_MARK,
2154 };
2155 static const unsigned int hscif0_ctrl_pins[] = {
2156         /* RTS, CTS */
2157         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2158 };
2159 static const unsigned int hscif0_ctrl_mux[] = {
2160         HRTS0_N_MARK, HCTS0_N_MARK,
2161 };
2162 /* - HSCIF1 ----------------------------------------------------------------- */
2163 static const unsigned int hscif1_data_a_pins[] = {
2164         /* RX, TX */
2165         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2166 };
2167 static const unsigned int hscif1_data_a_mux[] = {
2168         HRX1_A_MARK, HTX1_A_MARK,
2169 };
2170 static const unsigned int hscif1_clk_a_pins[] = {
2171         /* SCK */
2172         RCAR_GP_PIN(6, 21),
2173 };
2174 static const unsigned int hscif1_clk_a_mux[] = {
2175         HSCK1_A_MARK,
2176 };
2177 static const unsigned int hscif1_ctrl_a_pins[] = {
2178         /* RTS, CTS */
2179         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2180 };
2181 static const unsigned int hscif1_ctrl_a_mux[] = {
2182         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2183 };
2184
2185 static const unsigned int hscif1_data_b_pins[] = {
2186         /* RX, TX */
2187         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2188 };
2189 static const unsigned int hscif1_data_b_mux[] = {
2190         HRX1_B_MARK, HTX1_B_MARK,
2191 };
2192 static const unsigned int hscif1_clk_b_pins[] = {
2193         /* SCK */
2194         RCAR_GP_PIN(5, 0),
2195 };
2196 static const unsigned int hscif1_clk_b_mux[] = {
2197         HSCK1_B_MARK,
2198 };
2199 static const unsigned int hscif1_ctrl_b_pins[] = {
2200         /* RTS, CTS */
2201         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2202 };
2203 static const unsigned int hscif1_ctrl_b_mux[] = {
2204         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2205 };
2206 /* - HSCIF2 ----------------------------------------------------------------- */
2207 static const unsigned int hscif2_data_a_pins[] = {
2208         /* RX, TX */
2209         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2210 };
2211 static const unsigned int hscif2_data_a_mux[] = {
2212         HRX2_A_MARK, HTX2_A_MARK,
2213 };
2214 static const unsigned int hscif2_clk_a_pins[] = {
2215         /* SCK */
2216         RCAR_GP_PIN(6, 10),
2217 };
2218 static const unsigned int hscif2_clk_a_mux[] = {
2219         HSCK2_A_MARK,
2220 };
2221 static const unsigned int hscif2_ctrl_a_pins[] = {
2222         /* RTS, CTS */
2223         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2224 };
2225 static const unsigned int hscif2_ctrl_a_mux[] = {
2226         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2227 };
2228
2229 static const unsigned int hscif2_data_b_pins[] = {
2230         /* RX, TX */
2231         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2232 };
2233 static const unsigned int hscif2_data_b_mux[] = {
2234         HRX2_B_MARK, HTX2_B_MARK,
2235 };
2236 static const unsigned int hscif2_clk_b_pins[] = {
2237         /* SCK */
2238         RCAR_GP_PIN(6, 21),
2239 };
2240 static const unsigned int hscif2_clk_b_mux[] = {
2241         HSCK2_B_MARK,
2242 };
2243 static const unsigned int hscif2_ctrl_b_pins[] = {
2244         /* RTS, CTS */
2245         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2246 };
2247 static const unsigned int hscif2_ctrl_b_mux[] = {
2248         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2249 };
2250
2251 static const unsigned int hscif2_data_c_pins[] = {
2252         /* RX, TX */
2253         RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2254 };
2255 static const unsigned int hscif2_data_c_mux[] = {
2256         HRX2_C_MARK, HTX2_C_MARK,
2257 };
2258 static const unsigned int hscif2_clk_c_pins[] = {
2259         /* SCK */
2260         RCAR_GP_PIN(6, 24),
2261 };
2262 static const unsigned int hscif2_clk_c_mux[] = {
2263         HSCK2_C_MARK,
2264 };
2265 static const unsigned int hscif2_ctrl_c_pins[] = {
2266         /* RTS, CTS */
2267         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2268 };
2269 static const unsigned int hscif2_ctrl_c_mux[] = {
2270         HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2271 };
2272 /* - HSCIF3 ----------------------------------------------------------------- */
2273 static const unsigned int hscif3_data_a_pins[] = {
2274         /* RX, TX */
2275         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2276 };
2277 static const unsigned int hscif3_data_a_mux[] = {
2278         HRX3_A_MARK, HTX3_A_MARK,
2279 };
2280 static const unsigned int hscif3_clk_pins[] = {
2281         /* SCK */
2282         RCAR_GP_PIN(1, 22),
2283 };
2284 static const unsigned int hscif3_clk_mux[] = {
2285         HSCK3_MARK,
2286 };
2287 static const unsigned int hscif3_ctrl_pins[] = {
2288         /* RTS, CTS */
2289         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2290 };
2291 static const unsigned int hscif3_ctrl_mux[] = {
2292         HRTS3_N_MARK, HCTS3_N_MARK,
2293 };
2294
2295 static const unsigned int hscif3_data_b_pins[] = {
2296         /* RX, TX */
2297         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2298 };
2299 static const unsigned int hscif3_data_b_mux[] = {
2300         HRX3_B_MARK, HTX3_B_MARK,
2301 };
2302 static const unsigned int hscif3_data_c_pins[] = {
2303         /* RX, TX */
2304         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2305 };
2306 static const unsigned int hscif3_data_c_mux[] = {
2307         HRX3_C_MARK, HTX3_C_MARK,
2308 };
2309 static const unsigned int hscif3_data_d_pins[] = {
2310         /* RX, TX */
2311         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2312 };
2313 static const unsigned int hscif3_data_d_mux[] = {
2314         HRX3_D_MARK, HTX3_D_MARK,
2315 };
2316 /* - HSCIF4 ----------------------------------------------------------------- */
2317 static const unsigned int hscif4_data_a_pins[] = {
2318         /* RX, TX */
2319         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2320 };
2321 static const unsigned int hscif4_data_a_mux[] = {
2322         HRX4_A_MARK, HTX4_A_MARK,
2323 };
2324 static const unsigned int hscif4_clk_pins[] = {
2325         /* SCK */
2326         RCAR_GP_PIN(1, 11),
2327 };
2328 static const unsigned int hscif4_clk_mux[] = {
2329         HSCK4_MARK,
2330 };
2331 static const unsigned int hscif4_ctrl_pins[] = {
2332         /* RTS, CTS */
2333         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2334 };
2335 static const unsigned int hscif4_ctrl_mux[] = {
2336         HRTS4_N_MARK, HCTS4_N_MARK,
2337 };
2338
2339 static const unsigned int hscif4_data_b_pins[] = {
2340         /* RX, TX */
2341         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2342 };
2343 static const unsigned int hscif4_data_b_mux[] = {
2344         HRX4_B_MARK, HTX4_B_MARK,
2345 };
2346
2347 /* - I2C -------------------------------------------------------------------- */
2348 static const unsigned int i2c0_pins[] = {
2349         /* SCL, SDA */
2350         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2351 };
2352
2353 static const unsigned int i2c0_mux[] = {
2354         SCL0_MARK, SDA0_MARK,
2355 };
2356
2357 static const unsigned int i2c1_a_pins[] = {
2358         /* SDA, SCL */
2359         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2360 };
2361 static const unsigned int i2c1_a_mux[] = {
2362         SDA1_A_MARK, SCL1_A_MARK,
2363 };
2364 static const unsigned int i2c1_b_pins[] = {
2365         /* SDA, SCL */
2366         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2367 };
2368 static const unsigned int i2c1_b_mux[] = {
2369         SDA1_B_MARK, SCL1_B_MARK,
2370 };
2371 static const unsigned int i2c2_a_pins[] = {
2372         /* SDA, SCL */
2373         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2374 };
2375 static const unsigned int i2c2_a_mux[] = {
2376         SDA2_A_MARK, SCL2_A_MARK,
2377 };
2378 static const unsigned int i2c2_b_pins[] = {
2379         /* SDA, SCL */
2380         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2381 };
2382 static const unsigned int i2c2_b_mux[] = {
2383         SDA2_B_MARK, SCL2_B_MARK,
2384 };
2385
2386 static const unsigned int i2c3_pins[] = {
2387         /* SCL, SDA */
2388         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2389 };
2390
2391 static const unsigned int i2c3_mux[] = {
2392         SCL3_MARK, SDA3_MARK,
2393 };
2394
2395 static const unsigned int i2c5_pins[] = {
2396         /* SCL, SDA */
2397         RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2398 };
2399
2400 static const unsigned int i2c5_mux[] = {
2401         SCL5_MARK, SDA5_MARK,
2402 };
2403
2404 static const unsigned int i2c6_a_pins[] = {
2405         /* SDA, SCL */
2406         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2407 };
2408 static const unsigned int i2c6_a_mux[] = {
2409         SDA6_A_MARK, SCL6_A_MARK,
2410 };
2411 static const unsigned int i2c6_b_pins[] = {
2412         /* SDA, SCL */
2413         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2414 };
2415 static const unsigned int i2c6_b_mux[] = {
2416         SDA6_B_MARK, SCL6_B_MARK,
2417 };
2418 static const unsigned int i2c6_c_pins[] = {
2419         /* SDA, SCL */
2420         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2421 };
2422 static const unsigned int i2c6_c_mux[] = {
2423         SDA6_C_MARK, SCL6_C_MARK,
2424 };
2425
2426 /* - INTC-EX ---------------------------------------------------------------- */
2427 static const unsigned int intc_ex_irq0_pins[] = {
2428         /* IRQ0 */
2429         RCAR_GP_PIN(2, 0),
2430 };
2431 static const unsigned int intc_ex_irq0_mux[] = {
2432         IRQ0_MARK,
2433 };
2434 static const unsigned int intc_ex_irq1_pins[] = {
2435         /* IRQ1 */
2436         RCAR_GP_PIN(2, 1),
2437 };
2438 static const unsigned int intc_ex_irq1_mux[] = {
2439         IRQ1_MARK,
2440 };
2441 static const unsigned int intc_ex_irq2_pins[] = {
2442         /* IRQ2 */
2443         RCAR_GP_PIN(2, 2),
2444 };
2445 static const unsigned int intc_ex_irq2_mux[] = {
2446         IRQ2_MARK,
2447 };
2448 static const unsigned int intc_ex_irq3_pins[] = {
2449         /* IRQ3 */
2450         RCAR_GP_PIN(2, 3),
2451 };
2452 static const unsigned int intc_ex_irq3_mux[] = {
2453         IRQ3_MARK,
2454 };
2455 static const unsigned int intc_ex_irq4_pins[] = {
2456         /* IRQ4 */
2457         RCAR_GP_PIN(2, 4),
2458 };
2459 static const unsigned int intc_ex_irq4_mux[] = {
2460         IRQ4_MARK,
2461 };
2462 static const unsigned int intc_ex_irq5_pins[] = {
2463         /* IRQ5 */
2464         RCAR_GP_PIN(2, 5),
2465 };
2466 static const unsigned int intc_ex_irq5_mux[] = {
2467         IRQ5_MARK,
2468 };
2469
2470 /* - MSIOF0 ----------------------------------------------------------------- */
2471 static const unsigned int msiof0_clk_pins[] = {
2472         /* SCK */
2473         RCAR_GP_PIN(5, 17),
2474 };
2475 static const unsigned int msiof0_clk_mux[] = {
2476         MSIOF0_SCK_MARK,
2477 };
2478 static const unsigned int msiof0_sync_pins[] = {
2479         /* SYNC */
2480         RCAR_GP_PIN(5, 18),
2481 };
2482 static const unsigned int msiof0_sync_mux[] = {
2483         MSIOF0_SYNC_MARK,
2484 };
2485 static const unsigned int msiof0_ss1_pins[] = {
2486         /* SS1 */
2487         RCAR_GP_PIN(5, 19),
2488 };
2489 static const unsigned int msiof0_ss1_mux[] = {
2490         MSIOF0_SS1_MARK,
2491 };
2492 static const unsigned int msiof0_ss2_pins[] = {
2493         /* SS2 */
2494         RCAR_GP_PIN(5, 21),
2495 };
2496 static const unsigned int msiof0_ss2_mux[] = {
2497         MSIOF0_SS2_MARK,
2498 };
2499 static const unsigned int msiof0_txd_pins[] = {
2500         /* TXD */
2501         RCAR_GP_PIN(5, 20),
2502 };
2503 static const unsigned int msiof0_txd_mux[] = {
2504         MSIOF0_TXD_MARK,
2505 };
2506 static const unsigned int msiof0_rxd_pins[] = {
2507         /* RXD */
2508         RCAR_GP_PIN(5, 22),
2509 };
2510 static const unsigned int msiof0_rxd_mux[] = {
2511         MSIOF0_RXD_MARK,
2512 };
2513 /* - MSIOF1 ----------------------------------------------------------------- */
2514 static const unsigned int msiof1_clk_a_pins[] = {
2515         /* SCK */
2516         RCAR_GP_PIN(6, 8),
2517 };
2518 static const unsigned int msiof1_clk_a_mux[] = {
2519         MSIOF1_SCK_A_MARK,
2520 };
2521 static const unsigned int msiof1_sync_a_pins[] = {
2522         /* SYNC */
2523         RCAR_GP_PIN(6, 9),
2524 };
2525 static const unsigned int msiof1_sync_a_mux[] = {
2526         MSIOF1_SYNC_A_MARK,
2527 };
2528 static const unsigned int msiof1_ss1_a_pins[] = {
2529         /* SS1 */
2530         RCAR_GP_PIN(6, 5),
2531 };
2532 static const unsigned int msiof1_ss1_a_mux[] = {
2533         MSIOF1_SS1_A_MARK,
2534 };
2535 static const unsigned int msiof1_ss2_a_pins[] = {
2536         /* SS2 */
2537         RCAR_GP_PIN(6, 6),
2538 };
2539 static const unsigned int msiof1_ss2_a_mux[] = {
2540         MSIOF1_SS2_A_MARK,
2541 };
2542 static const unsigned int msiof1_txd_a_pins[] = {
2543         /* TXD */
2544         RCAR_GP_PIN(6, 7),
2545 };
2546 static const unsigned int msiof1_txd_a_mux[] = {
2547         MSIOF1_TXD_A_MARK,
2548 };
2549 static const unsigned int msiof1_rxd_a_pins[] = {
2550         /* RXD */
2551         RCAR_GP_PIN(6, 10),
2552 };
2553 static const unsigned int msiof1_rxd_a_mux[] = {
2554         MSIOF1_RXD_A_MARK,
2555 };
2556 static const unsigned int msiof1_clk_b_pins[] = {
2557         /* SCK */
2558         RCAR_GP_PIN(5, 9),
2559 };
2560 static const unsigned int msiof1_clk_b_mux[] = {
2561         MSIOF1_SCK_B_MARK,
2562 };
2563 static const unsigned int msiof1_sync_b_pins[] = {
2564         /* SYNC */
2565         RCAR_GP_PIN(5, 3),
2566 };
2567 static const unsigned int msiof1_sync_b_mux[] = {
2568         MSIOF1_SYNC_B_MARK,
2569 };
2570 static const unsigned int msiof1_ss1_b_pins[] = {
2571         /* SS1 */
2572         RCAR_GP_PIN(5, 4),
2573 };
2574 static const unsigned int msiof1_ss1_b_mux[] = {
2575         MSIOF1_SS1_B_MARK,
2576 };
2577 static const unsigned int msiof1_ss2_b_pins[] = {
2578         /* SS2 */
2579         RCAR_GP_PIN(5, 0),
2580 };
2581 static const unsigned int msiof1_ss2_b_mux[] = {
2582         MSIOF1_SS2_B_MARK,
2583 };
2584 static const unsigned int msiof1_txd_b_pins[] = {
2585         /* TXD */
2586         RCAR_GP_PIN(5, 8),
2587 };
2588 static const unsigned int msiof1_txd_b_mux[] = {
2589         MSIOF1_TXD_B_MARK,
2590 };
2591 static const unsigned int msiof1_rxd_b_pins[] = {
2592         /* RXD */
2593         RCAR_GP_PIN(5, 7),
2594 };
2595 static const unsigned int msiof1_rxd_b_mux[] = {
2596         MSIOF1_RXD_B_MARK,
2597 };
2598 static const unsigned int msiof1_clk_c_pins[] = {
2599         /* SCK */
2600         RCAR_GP_PIN(6, 17),
2601 };
2602 static const unsigned int msiof1_clk_c_mux[] = {
2603         MSIOF1_SCK_C_MARK,
2604 };
2605 static const unsigned int msiof1_sync_c_pins[] = {
2606         /* SYNC */
2607         RCAR_GP_PIN(6, 18),
2608 };
2609 static const unsigned int msiof1_sync_c_mux[] = {
2610         MSIOF1_SYNC_C_MARK,
2611 };
2612 static const unsigned int msiof1_ss1_c_pins[] = {
2613         /* SS1 */
2614         RCAR_GP_PIN(6, 21),
2615 };
2616 static const unsigned int msiof1_ss1_c_mux[] = {
2617         MSIOF1_SS1_C_MARK,
2618 };
2619 static const unsigned int msiof1_ss2_c_pins[] = {
2620         /* SS2 */
2621         RCAR_GP_PIN(6, 27),
2622 };
2623 static const unsigned int msiof1_ss2_c_mux[] = {
2624         MSIOF1_SS2_C_MARK,
2625 };
2626 static const unsigned int msiof1_txd_c_pins[] = {
2627         /* TXD */
2628         RCAR_GP_PIN(6, 20),
2629 };
2630 static const unsigned int msiof1_txd_c_mux[] = {
2631         MSIOF1_TXD_C_MARK,
2632 };
2633 static const unsigned int msiof1_rxd_c_pins[] = {
2634         /* RXD */
2635         RCAR_GP_PIN(6, 19),
2636 };
2637 static const unsigned int msiof1_rxd_c_mux[] = {
2638         MSIOF1_RXD_C_MARK,
2639 };
2640 static const unsigned int msiof1_clk_d_pins[] = {
2641         /* SCK */
2642         RCAR_GP_PIN(5, 12),
2643 };
2644 static const unsigned int msiof1_clk_d_mux[] = {
2645         MSIOF1_SCK_D_MARK,
2646 };
2647 static const unsigned int msiof1_sync_d_pins[] = {
2648         /* SYNC */
2649         RCAR_GP_PIN(5, 15),
2650 };
2651 static const unsigned int msiof1_sync_d_mux[] = {
2652         MSIOF1_SYNC_D_MARK,
2653 };
2654 static const unsigned int msiof1_ss1_d_pins[] = {
2655         /* SS1 */
2656         RCAR_GP_PIN(5, 16),
2657 };
2658 static const unsigned int msiof1_ss1_d_mux[] = {
2659         MSIOF1_SS1_D_MARK,
2660 };
2661 static const unsigned int msiof1_ss2_d_pins[] = {
2662         /* SS2 */
2663         RCAR_GP_PIN(5, 21),
2664 };
2665 static const unsigned int msiof1_ss2_d_mux[] = {
2666         MSIOF1_SS2_D_MARK,
2667 };
2668 static const unsigned int msiof1_txd_d_pins[] = {
2669         /* TXD */
2670         RCAR_GP_PIN(5, 14),
2671 };
2672 static const unsigned int msiof1_txd_d_mux[] = {
2673         MSIOF1_TXD_D_MARK,
2674 };
2675 static const unsigned int msiof1_rxd_d_pins[] = {
2676         /* RXD */
2677         RCAR_GP_PIN(5, 13),
2678 };
2679 static const unsigned int msiof1_rxd_d_mux[] = {
2680         MSIOF1_RXD_D_MARK,
2681 };
2682 static const unsigned int msiof1_clk_e_pins[] = {
2683         /* SCK */
2684         RCAR_GP_PIN(3, 0),
2685 };
2686 static const unsigned int msiof1_clk_e_mux[] = {
2687         MSIOF1_SCK_E_MARK,
2688 };
2689 static const unsigned int msiof1_sync_e_pins[] = {
2690         /* SYNC */
2691         RCAR_GP_PIN(3, 1),
2692 };
2693 static const unsigned int msiof1_sync_e_mux[] = {
2694         MSIOF1_SYNC_E_MARK,
2695 };
2696 static const unsigned int msiof1_ss1_e_pins[] = {
2697         /* SS1 */
2698         RCAR_GP_PIN(3, 4),
2699 };
2700 static const unsigned int msiof1_ss1_e_mux[] = {
2701         MSIOF1_SS1_E_MARK,
2702 };
2703 static const unsigned int msiof1_ss2_e_pins[] = {
2704         /* SS2 */
2705         RCAR_GP_PIN(3, 5),
2706 };
2707 static const unsigned int msiof1_ss2_e_mux[] = {
2708         MSIOF1_SS2_E_MARK,
2709 };
2710 static const unsigned int msiof1_txd_e_pins[] = {
2711         /* TXD */
2712         RCAR_GP_PIN(3, 3),
2713 };
2714 static const unsigned int msiof1_txd_e_mux[] = {
2715         MSIOF1_TXD_E_MARK,
2716 };
2717 static const unsigned int msiof1_rxd_e_pins[] = {
2718         /* RXD */
2719         RCAR_GP_PIN(3, 2),
2720 };
2721 static const unsigned int msiof1_rxd_e_mux[] = {
2722         MSIOF1_RXD_E_MARK,
2723 };
2724 static const unsigned int msiof1_clk_f_pins[] = {
2725         /* SCK */
2726         RCAR_GP_PIN(5, 23),
2727 };
2728 static const unsigned int msiof1_clk_f_mux[] = {
2729         MSIOF1_SCK_F_MARK,
2730 };
2731 static const unsigned int msiof1_sync_f_pins[] = {
2732         /* SYNC */
2733         RCAR_GP_PIN(5, 24),
2734 };
2735 static const unsigned int msiof1_sync_f_mux[] = {
2736         MSIOF1_SYNC_F_MARK,
2737 };
2738 static const unsigned int msiof1_ss1_f_pins[] = {
2739         /* SS1 */
2740         RCAR_GP_PIN(6, 1),
2741 };
2742 static const unsigned int msiof1_ss1_f_mux[] = {
2743         MSIOF1_SS1_F_MARK,
2744 };
2745 static const unsigned int msiof1_ss2_f_pins[] = {
2746         /* SS2 */
2747         RCAR_GP_PIN(6, 2),
2748 };
2749 static const unsigned int msiof1_ss2_f_mux[] = {
2750         MSIOF1_SS2_F_MARK,
2751 };
2752 static const unsigned int msiof1_txd_f_pins[] = {
2753         /* TXD */
2754         RCAR_GP_PIN(6, 0),
2755 };
2756 static const unsigned int msiof1_txd_f_mux[] = {
2757         MSIOF1_TXD_F_MARK,
2758 };
2759 static const unsigned int msiof1_rxd_f_pins[] = {
2760         /* RXD */
2761         RCAR_GP_PIN(5, 25),
2762 };
2763 static const unsigned int msiof1_rxd_f_mux[] = {
2764         MSIOF1_RXD_F_MARK,
2765 };
2766 static const unsigned int msiof1_clk_g_pins[] = {
2767         /* SCK */
2768         RCAR_GP_PIN(3, 6),
2769 };
2770 static const unsigned int msiof1_clk_g_mux[] = {
2771         MSIOF1_SCK_G_MARK,
2772 };
2773 static const unsigned int msiof1_sync_g_pins[] = {
2774         /* SYNC */
2775         RCAR_GP_PIN(3, 7),
2776 };
2777 static const unsigned int msiof1_sync_g_mux[] = {
2778         MSIOF1_SYNC_G_MARK,
2779 };
2780 static const unsigned int msiof1_ss1_g_pins[] = {
2781         /* SS1 */
2782         RCAR_GP_PIN(3, 10),
2783 };
2784 static const unsigned int msiof1_ss1_g_mux[] = {
2785         MSIOF1_SS1_G_MARK,
2786 };
2787 static const unsigned int msiof1_ss2_g_pins[] = {
2788         /* SS2 */
2789         RCAR_GP_PIN(3, 11),
2790 };
2791 static const unsigned int msiof1_ss2_g_mux[] = {
2792         MSIOF1_SS2_G_MARK,
2793 };
2794 static const unsigned int msiof1_txd_g_pins[] = {
2795         /* TXD */
2796         RCAR_GP_PIN(3, 9),
2797 };
2798 static const unsigned int msiof1_txd_g_mux[] = {
2799         MSIOF1_TXD_G_MARK,
2800 };
2801 static const unsigned int msiof1_rxd_g_pins[] = {
2802         /* RXD */
2803         RCAR_GP_PIN(3, 8),
2804 };
2805 static const unsigned int msiof1_rxd_g_mux[] = {
2806         MSIOF1_RXD_G_MARK,
2807 };
2808 /* - MSIOF2 ----------------------------------------------------------------- */
2809 static const unsigned int msiof2_clk_a_pins[] = {
2810         /* SCK */
2811         RCAR_GP_PIN(1, 9),
2812 };
2813 static const unsigned int msiof2_clk_a_mux[] = {
2814         MSIOF2_SCK_A_MARK,
2815 };
2816 static const unsigned int msiof2_sync_a_pins[] = {
2817         /* SYNC */
2818         RCAR_GP_PIN(1, 8),
2819 };
2820 static const unsigned int msiof2_sync_a_mux[] = {
2821         MSIOF2_SYNC_A_MARK,
2822 };
2823 static const unsigned int msiof2_ss1_a_pins[] = {
2824         /* SS1 */
2825         RCAR_GP_PIN(1, 6),
2826 };
2827 static const unsigned int msiof2_ss1_a_mux[] = {
2828         MSIOF2_SS1_A_MARK,
2829 };
2830 static const unsigned int msiof2_ss2_a_pins[] = {
2831         /* SS2 */
2832         RCAR_GP_PIN(1, 7),
2833 };
2834 static const unsigned int msiof2_ss2_a_mux[] = {
2835         MSIOF2_SS2_A_MARK,
2836 };
2837 static const unsigned int msiof2_txd_a_pins[] = {
2838         /* TXD */
2839         RCAR_GP_PIN(1, 11),
2840 };
2841 static const unsigned int msiof2_txd_a_mux[] = {
2842         MSIOF2_TXD_A_MARK,
2843 };
2844 static const unsigned int msiof2_rxd_a_pins[] = {
2845         /* RXD */
2846         RCAR_GP_PIN(1, 10),
2847 };
2848 static const unsigned int msiof2_rxd_a_mux[] = {
2849         MSIOF2_RXD_A_MARK,
2850 };
2851 static const unsigned int msiof2_clk_b_pins[] = {
2852         /* SCK */
2853         RCAR_GP_PIN(0, 4),
2854 };
2855 static const unsigned int msiof2_clk_b_mux[] = {
2856         MSIOF2_SCK_B_MARK,
2857 };
2858 static const unsigned int msiof2_sync_b_pins[] = {
2859         /* SYNC */
2860         RCAR_GP_PIN(0, 5),
2861 };
2862 static const unsigned int msiof2_sync_b_mux[] = {
2863         MSIOF2_SYNC_B_MARK,
2864 };
2865 static const unsigned int msiof2_ss1_b_pins[] = {
2866         /* SS1 */
2867         RCAR_GP_PIN(0, 0),
2868 };
2869 static const unsigned int msiof2_ss1_b_mux[] = {
2870         MSIOF2_SS1_B_MARK,
2871 };
2872 static const unsigned int msiof2_ss2_b_pins[] = {
2873         /* SS2 */
2874         RCAR_GP_PIN(0, 1),
2875 };
2876 static const unsigned int msiof2_ss2_b_mux[] = {
2877         MSIOF2_SS2_B_MARK,
2878 };
2879 static const unsigned int msiof2_txd_b_pins[] = {
2880         /* TXD */
2881         RCAR_GP_PIN(0, 7),
2882 };
2883 static const unsigned int msiof2_txd_b_mux[] = {
2884         MSIOF2_TXD_B_MARK,
2885 };
2886 static const unsigned int msiof2_rxd_b_pins[] = {
2887         /* RXD */
2888         RCAR_GP_PIN(0, 6),
2889 };
2890 static const unsigned int msiof2_rxd_b_mux[] = {
2891         MSIOF2_RXD_B_MARK,
2892 };
2893 static const unsigned int msiof2_clk_c_pins[] = {
2894         /* SCK */
2895         RCAR_GP_PIN(2, 12),
2896 };
2897 static const unsigned int msiof2_clk_c_mux[] = {
2898         MSIOF2_SCK_C_MARK,
2899 };
2900 static const unsigned int msiof2_sync_c_pins[] = {
2901         /* SYNC */
2902         RCAR_GP_PIN(2, 11),
2903 };
2904 static const unsigned int msiof2_sync_c_mux[] = {
2905         MSIOF2_SYNC_C_MARK,
2906 };
2907 static const unsigned int msiof2_ss1_c_pins[] = {
2908         /* SS1 */
2909         RCAR_GP_PIN(2, 10),
2910 };
2911 static const unsigned int msiof2_ss1_c_mux[] = {
2912         MSIOF2_SS1_C_MARK,
2913 };
2914 static const unsigned int msiof2_ss2_c_pins[] = {
2915         /* SS2 */
2916         RCAR_GP_PIN(2, 9),
2917 };
2918 static const unsigned int msiof2_ss2_c_mux[] = {
2919         MSIOF2_SS2_C_MARK,
2920 };
2921 static const unsigned int msiof2_txd_c_pins[] = {
2922         /* TXD */
2923         RCAR_GP_PIN(2, 14),
2924 };
2925 static const unsigned int msiof2_txd_c_mux[] = {
2926         MSIOF2_TXD_C_MARK,
2927 };
2928 static const unsigned int msiof2_rxd_c_pins[] = {
2929         /* RXD */
2930         RCAR_GP_PIN(2, 13),
2931 };
2932 static const unsigned int msiof2_rxd_c_mux[] = {
2933         MSIOF2_RXD_C_MARK,
2934 };
2935 static const unsigned int msiof2_clk_d_pins[] = {
2936         /* SCK */
2937         RCAR_GP_PIN(0, 8),
2938 };
2939 static const unsigned int msiof2_clk_d_mux[] = {
2940         MSIOF2_SCK_D_MARK,
2941 };
2942 static const unsigned int msiof2_sync_d_pins[] = {
2943         /* SYNC */
2944         RCAR_GP_PIN(0, 9),
2945 };
2946 static const unsigned int msiof2_sync_d_mux[] = {
2947         MSIOF2_SYNC_D_MARK,
2948 };
2949 static const unsigned int msiof2_ss1_d_pins[] = {
2950         /* SS1 */
2951         RCAR_GP_PIN(0, 12),
2952 };
2953 static const unsigned int msiof2_ss1_d_mux[] = {
2954         MSIOF2_SS1_D_MARK,
2955 };
2956 static const unsigned int msiof2_ss2_d_pins[] = {
2957         /* SS2 */
2958         RCAR_GP_PIN(0, 13),
2959 };
2960 static const unsigned int msiof2_ss2_d_mux[] = {
2961         MSIOF2_SS2_D_MARK,
2962 };
2963 static const unsigned int msiof2_txd_d_pins[] = {
2964         /* TXD */
2965         RCAR_GP_PIN(0, 11),
2966 };
2967 static const unsigned int msiof2_txd_d_mux[] = {
2968         MSIOF2_TXD_D_MARK,
2969 };
2970 static const unsigned int msiof2_rxd_d_pins[] = {
2971         /* RXD */
2972         RCAR_GP_PIN(0, 10),
2973 };
2974 static const unsigned int msiof2_rxd_d_mux[] = {
2975         MSIOF2_RXD_D_MARK,
2976 };
2977 /* - MSIOF3 ----------------------------------------------------------------- */
2978 static const unsigned int msiof3_clk_a_pins[] = {
2979         /* SCK */
2980         RCAR_GP_PIN(0, 0),
2981 };
2982 static const unsigned int msiof3_clk_a_mux[] = {
2983         MSIOF3_SCK_A_MARK,
2984 };
2985 static const unsigned int msiof3_sync_a_pins[] = {
2986         /* SYNC */
2987         RCAR_GP_PIN(0, 1),
2988 };
2989 static const unsigned int msiof3_sync_a_mux[] = {
2990         MSIOF3_SYNC_A_MARK,
2991 };
2992 static const unsigned int msiof3_ss1_a_pins[] = {
2993         /* SS1 */
2994         RCAR_GP_PIN(0, 14),
2995 };
2996 static const unsigned int msiof3_ss1_a_mux[] = {
2997         MSIOF3_SS1_A_MARK,
2998 };
2999 static const unsigned int msiof3_ss2_a_pins[] = {
3000         /* SS2 */
3001         RCAR_GP_PIN(0, 15),
3002 };
3003 static const unsigned int msiof3_ss2_a_mux[] = {
3004         MSIOF3_SS2_A_MARK,
3005 };
3006 static const unsigned int msiof3_txd_a_pins[] = {
3007         /* TXD */
3008         RCAR_GP_PIN(0, 3),
3009 };
3010 static const unsigned int msiof3_txd_a_mux[] = {
3011         MSIOF3_TXD_A_MARK,
3012 };
3013 static const unsigned int msiof3_rxd_a_pins[] = {
3014         /* RXD */
3015         RCAR_GP_PIN(0, 2),
3016 };
3017 static const unsigned int msiof3_rxd_a_mux[] = {
3018         MSIOF3_RXD_A_MARK,
3019 };
3020 static const unsigned int msiof3_clk_b_pins[] = {
3021         /* SCK */
3022         RCAR_GP_PIN(1, 2),
3023 };
3024 static const unsigned int msiof3_clk_b_mux[] = {
3025         MSIOF3_SCK_B_MARK,
3026 };
3027 static const unsigned int msiof3_sync_b_pins[] = {
3028         /* SYNC */
3029         RCAR_GP_PIN(1, 0),
3030 };
3031 static const unsigned int msiof3_sync_b_mux[] = {
3032         MSIOF3_SYNC_B_MARK,
3033 };
3034 static const unsigned int msiof3_ss1_b_pins[] = {
3035         /* SS1 */
3036         RCAR_GP_PIN(1, 4),
3037 };
3038 static const unsigned int msiof3_ss1_b_mux[] = {
3039         MSIOF3_SS1_B_MARK,
3040 };
3041 static const unsigned int msiof3_ss2_b_pins[] = {
3042         /* SS2 */
3043         RCAR_GP_PIN(1, 5),
3044 };
3045 static const unsigned int msiof3_ss2_b_mux[] = {
3046         MSIOF3_SS2_B_MARK,
3047 };
3048 static const unsigned int msiof3_txd_b_pins[] = {
3049         /* TXD */
3050         RCAR_GP_PIN(1, 1),
3051 };
3052 static const unsigned int msiof3_txd_b_mux[] = {
3053         MSIOF3_TXD_B_MARK,
3054 };
3055 static const unsigned int msiof3_rxd_b_pins[] = {
3056         /* RXD */
3057         RCAR_GP_PIN(1, 3),
3058 };
3059 static const unsigned int msiof3_rxd_b_mux[] = {
3060         MSIOF3_RXD_B_MARK,
3061 };
3062 static const unsigned int msiof3_clk_c_pins[] = {
3063         /* SCK */
3064         RCAR_GP_PIN(1, 12),
3065 };
3066 static const unsigned int msiof3_clk_c_mux[] = {
3067         MSIOF3_SCK_C_MARK,
3068 };
3069 static const unsigned int msiof3_sync_c_pins[] = {
3070         /* SYNC */
3071         RCAR_GP_PIN(1, 13),
3072 };
3073 static const unsigned int msiof3_sync_c_mux[] = {
3074         MSIOF3_SYNC_C_MARK,
3075 };
3076 static const unsigned int msiof3_txd_c_pins[] = {
3077         /* TXD */
3078         RCAR_GP_PIN(1, 15),
3079 };
3080 static const unsigned int msiof3_txd_c_mux[] = {
3081         MSIOF3_TXD_C_MARK,
3082 };
3083 static const unsigned int msiof3_rxd_c_pins[] = {
3084         /* RXD */
3085         RCAR_GP_PIN(1, 14),
3086 };
3087 static const unsigned int msiof3_rxd_c_mux[] = {
3088         MSIOF3_RXD_C_MARK,
3089 };
3090 static const unsigned int msiof3_clk_d_pins[] = {
3091         /* SCK */
3092         RCAR_GP_PIN(1, 22),
3093 };
3094 static const unsigned int msiof3_clk_d_mux[] = {
3095         MSIOF3_SCK_D_MARK,
3096 };
3097 static const unsigned int msiof3_sync_d_pins[] = {
3098         /* SYNC */
3099         RCAR_GP_PIN(1, 23),
3100 };
3101 static const unsigned int msiof3_sync_d_mux[] = {
3102         MSIOF3_SYNC_D_MARK,
3103 };
3104 static const unsigned int msiof3_ss1_d_pins[] = {
3105         /* SS1 */
3106         RCAR_GP_PIN(1, 26),
3107 };
3108 static const unsigned int msiof3_ss1_d_mux[] = {
3109         MSIOF3_SS1_D_MARK,
3110 };
3111 static const unsigned int msiof3_txd_d_pins[] = {
3112         /* TXD */
3113         RCAR_GP_PIN(1, 25),
3114 };
3115 static const unsigned int msiof3_txd_d_mux[] = {
3116         MSIOF3_TXD_D_MARK,
3117 };
3118 static const unsigned int msiof3_rxd_d_pins[] = {
3119         /* RXD */
3120         RCAR_GP_PIN(1, 24),
3121 };
3122 static const unsigned int msiof3_rxd_d_mux[] = {
3123         MSIOF3_RXD_D_MARK,
3124 };
3125
3126 static const unsigned int msiof3_clk_e_pins[] = {
3127         /* SCK */
3128         RCAR_GP_PIN(2, 3),
3129 };
3130 static const unsigned int msiof3_clk_e_mux[] = {
3131         MSIOF3_SCK_E_MARK,
3132 };
3133 static const unsigned int msiof3_sync_e_pins[] = {
3134         /* SYNC */
3135         RCAR_GP_PIN(2, 2),
3136 };
3137 static const unsigned int msiof3_sync_e_mux[] = {
3138         MSIOF3_SYNC_E_MARK,
3139 };
3140 static const unsigned int msiof3_ss1_e_pins[] = {
3141         /* SS1 */
3142         RCAR_GP_PIN(2, 1),
3143 };
3144 static const unsigned int msiof3_ss1_e_mux[] = {
3145         MSIOF3_SS1_E_MARK,
3146 };
3147 static const unsigned int msiof3_ss2_e_pins[] = {
3148         /* SS2 */
3149         RCAR_GP_PIN(2, 0),
3150 };
3151 static const unsigned int msiof3_ss2_e_mux[] = {
3152         MSIOF3_SS2_E_MARK,
3153 };
3154 static const unsigned int msiof3_txd_e_pins[] = {
3155         /* TXD */
3156         RCAR_GP_PIN(2, 5),
3157 };
3158 static const unsigned int msiof3_txd_e_mux[] = {
3159         MSIOF3_TXD_E_MARK,
3160 };
3161 static const unsigned int msiof3_rxd_e_pins[] = {
3162         /* RXD */
3163         RCAR_GP_PIN(2, 4),
3164 };
3165 static const unsigned int msiof3_rxd_e_mux[] = {
3166         MSIOF3_RXD_E_MARK,
3167 };
3168
3169 /* - PWM0 --------------------------------------------------------------------*/
3170 static const unsigned int pwm0_pins[] = {
3171         /* PWM */
3172         RCAR_GP_PIN(2, 6),
3173 };
3174 static const unsigned int pwm0_mux[] = {
3175         PWM0_MARK,
3176 };
3177 /* - PWM1 --------------------------------------------------------------------*/
3178 static const unsigned int pwm1_a_pins[] = {
3179         /* PWM */
3180         RCAR_GP_PIN(2, 7),
3181 };
3182 static const unsigned int pwm1_a_mux[] = {
3183         PWM1_A_MARK,
3184 };
3185 static const unsigned int pwm1_b_pins[] = {
3186         /* PWM */
3187         RCAR_GP_PIN(1, 8),
3188 };
3189 static const unsigned int pwm1_b_mux[] = {
3190         PWM1_B_MARK,
3191 };
3192 /* - PWM2 --------------------------------------------------------------------*/
3193 static const unsigned int pwm2_a_pins[] = {
3194         /* PWM */
3195         RCAR_GP_PIN(2, 8),
3196 };
3197 static const unsigned int pwm2_a_mux[] = {
3198         PWM2_A_MARK,
3199 };
3200 static const unsigned int pwm2_b_pins[] = {
3201         /* PWM */
3202         RCAR_GP_PIN(1, 11),
3203 };
3204 static const unsigned int pwm2_b_mux[] = {
3205         PWM2_B_MARK,
3206 };
3207 /* - PWM3 --------------------------------------------------------------------*/
3208 static const unsigned int pwm3_a_pins[] = {
3209         /* PWM */
3210         RCAR_GP_PIN(1, 0),
3211 };
3212 static const unsigned int pwm3_a_mux[] = {
3213         PWM3_A_MARK,
3214 };
3215 static const unsigned int pwm3_b_pins[] = {
3216         /* PWM */
3217         RCAR_GP_PIN(2, 2),
3218 };
3219 static const unsigned int pwm3_b_mux[] = {
3220         PWM3_B_MARK,
3221 };
3222 /* - PWM4 --------------------------------------------------------------------*/
3223 static const unsigned int pwm4_a_pins[] = {
3224         /* PWM */
3225         RCAR_GP_PIN(1, 1),
3226 };
3227 static const unsigned int pwm4_a_mux[] = {
3228         PWM4_A_MARK,
3229 };
3230 static const unsigned int pwm4_b_pins[] = {
3231         /* PWM */
3232         RCAR_GP_PIN(2, 3),
3233 };
3234 static const unsigned int pwm4_b_mux[] = {
3235         PWM4_B_MARK,
3236 };
3237 /* - PWM5 --------------------------------------------------------------------*/
3238 static const unsigned int pwm5_a_pins[] = {
3239         /* PWM */
3240         RCAR_GP_PIN(1, 2),
3241 };
3242 static const unsigned int pwm5_a_mux[] = {
3243         PWM5_A_MARK,
3244 };
3245 static const unsigned int pwm5_b_pins[] = {
3246         /* PWM */
3247         RCAR_GP_PIN(2, 4),
3248 };
3249 static const unsigned int pwm5_b_mux[] = {
3250         PWM5_B_MARK,
3251 };
3252 /* - PWM6 --------------------------------------------------------------------*/
3253 static const unsigned int pwm6_a_pins[] = {
3254         /* PWM */
3255         RCAR_GP_PIN(1, 3),
3256 };
3257 static const unsigned int pwm6_a_mux[] = {
3258         PWM6_A_MARK,
3259 };
3260 static const unsigned int pwm6_b_pins[] = {
3261         /* PWM */
3262         RCAR_GP_PIN(2, 5),
3263 };
3264 static const unsigned int pwm6_b_mux[] = {
3265         PWM6_B_MARK,
3266 };
3267
3268 /* - SCIF0 ------------------------------------------------------------------ */
3269 static const unsigned int scif0_data_pins[] = {
3270         /* RX, TX */
3271         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3272 };
3273 static const unsigned int scif0_data_mux[] = {
3274         RX0_MARK, TX0_MARK,
3275 };
3276 static const unsigned int scif0_clk_pins[] = {
3277         /* SCK */
3278         RCAR_GP_PIN(5, 0),
3279 };
3280 static const unsigned int scif0_clk_mux[] = {
3281         SCK0_MARK,
3282 };
3283 static const unsigned int scif0_ctrl_pins[] = {
3284         /* RTS, CTS */
3285         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3286 };
3287 static const unsigned int scif0_ctrl_mux[] = {
3288         RTS0_N_MARK, CTS0_N_MARK,
3289 };
3290 /* - SCIF1 ------------------------------------------------------------------ */
3291 static const unsigned int scif1_data_a_pins[] = {
3292         /* RX, TX */
3293         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3294 };
3295 static const unsigned int scif1_data_a_mux[] = {
3296         RX1_A_MARK, TX1_A_MARK,
3297 };
3298 static const unsigned int scif1_clk_pins[] = {
3299         /* SCK */
3300         RCAR_GP_PIN(6, 21),
3301 };
3302 static const unsigned int scif1_clk_mux[] = {
3303         SCK1_MARK,
3304 };
3305 static const unsigned int scif1_ctrl_pins[] = {
3306         /* RTS, CTS */
3307         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3308 };
3309 static const unsigned int scif1_ctrl_mux[] = {
3310         RTS1_N_MARK, CTS1_N_MARK,
3311 };
3312
3313 static const unsigned int scif1_data_b_pins[] = {
3314         /* RX, TX */
3315         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3316 };
3317 static const unsigned int scif1_data_b_mux[] = {
3318         RX1_B_MARK, TX1_B_MARK,
3319 };
3320 /* - SCIF2 ------------------------------------------------------------------ */
3321 static const unsigned int scif2_data_a_pins[] = {
3322         /* RX, TX */
3323         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3324 };
3325 static const unsigned int scif2_data_a_mux[] = {
3326         RX2_A_MARK, TX2_A_MARK,
3327 };
3328 static const unsigned int scif2_clk_pins[] = {
3329         /* SCK */
3330         RCAR_GP_PIN(5, 9),
3331 };
3332 static const unsigned int scif2_clk_mux[] = {
3333         SCK2_MARK,
3334 };
3335 static const unsigned int scif2_data_b_pins[] = {
3336         /* RX, TX */
3337         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3338 };
3339 static const unsigned int scif2_data_b_mux[] = {
3340         RX2_B_MARK, TX2_B_MARK,
3341 };
3342 /* - SCIF3 ------------------------------------------------------------------ */
3343 static const unsigned int scif3_data_a_pins[] = {
3344         /* RX, TX */
3345         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3346 };
3347 static const unsigned int scif3_data_a_mux[] = {
3348         RX3_A_MARK, TX3_A_MARK,
3349 };
3350 static const unsigned int scif3_clk_pins[] = {
3351         /* SCK */
3352         RCAR_GP_PIN(1, 22),
3353 };
3354 static const unsigned int scif3_clk_mux[] = {
3355         SCK3_MARK,
3356 };
3357 static const unsigned int scif3_ctrl_pins[] = {
3358         /* RTS, CTS */
3359         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3360 };
3361 static const unsigned int scif3_ctrl_mux[] = {
3362         RTS3_N_MARK, CTS3_N_MARK,
3363 };
3364 static const unsigned int scif3_data_b_pins[] = {
3365         /* RX, TX */
3366         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3367 };
3368 static const unsigned int scif3_data_b_mux[] = {
3369         RX3_B_MARK, TX3_B_MARK,
3370 };
3371 /* - SCIF4 ------------------------------------------------------------------ */
3372 static const unsigned int scif4_data_a_pins[] = {
3373         /* RX, TX */
3374         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3375 };
3376 static const unsigned int scif4_data_a_mux[] = {
3377         RX4_A_MARK, TX4_A_MARK,
3378 };
3379 static const unsigned int scif4_clk_a_pins[] = {
3380         /* SCK */
3381         RCAR_GP_PIN(2, 10),
3382 };
3383 static const unsigned int scif4_clk_a_mux[] = {
3384         SCK4_A_MARK,
3385 };
3386 static const unsigned int scif4_ctrl_a_pins[] = {
3387         /* RTS, CTS */
3388         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3389 };
3390 static const unsigned int scif4_ctrl_a_mux[] = {
3391         RTS4_N_A_MARK, CTS4_N_A_MARK,
3392 };
3393 static const unsigned int scif4_data_b_pins[] = {
3394         /* RX, TX */
3395         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3396 };
3397 static const unsigned int scif4_data_b_mux[] = {
3398         RX4_B_MARK, TX4_B_MARK,
3399 };
3400 static const unsigned int scif4_clk_b_pins[] = {
3401         /* SCK */
3402         RCAR_GP_PIN(1, 5),
3403 };
3404 static const unsigned int scif4_clk_b_mux[] = {
3405         SCK4_B_MARK,
3406 };
3407 static const unsigned int scif4_ctrl_b_pins[] = {
3408         /* RTS, CTS */
3409         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3410 };
3411 static const unsigned int scif4_ctrl_b_mux[] = {
3412         RTS4_N_B_MARK, CTS4_N_B_MARK,
3413 };
3414 static const unsigned int scif4_data_c_pins[] = {
3415         /* RX, TX */
3416         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3417 };
3418 static const unsigned int scif4_data_c_mux[] = {
3419         RX4_C_MARK, TX4_C_MARK,
3420 };
3421 static const unsigned int scif4_clk_c_pins[] = {
3422         /* SCK */
3423         RCAR_GP_PIN(0, 8),
3424 };
3425 static const unsigned int scif4_clk_c_mux[] = {
3426         SCK4_C_MARK,
3427 };
3428 static const unsigned int scif4_ctrl_c_pins[] = {
3429         /* RTS, CTS */
3430         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3431 };
3432 static const unsigned int scif4_ctrl_c_mux[] = {
3433         RTS4_N_C_MARK, CTS4_N_C_MARK,
3434 };
3435 /* - SCIF5 ------------------------------------------------------------------ */
3436 static const unsigned int scif5_data_a_pins[] = {
3437         /* RX, TX */
3438         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3439 };
3440 static const unsigned int scif5_data_a_mux[] = {
3441         RX5_A_MARK, TX5_A_MARK,
3442 };
3443 static const unsigned int scif5_clk_a_pins[] = {
3444         /* SCK */
3445         RCAR_GP_PIN(6, 21),
3446 };
3447 static const unsigned int scif5_clk_a_mux[] = {
3448         SCK5_A_MARK,
3449 };
3450
3451 static const unsigned int scif5_data_b_pins[] = {
3452         /* RX, TX */
3453         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3454 };
3455 static const unsigned int scif5_data_b_mux[] = {
3456         RX5_B_MARK, TX5_B_MARK,
3457 };
3458 static const unsigned int scif5_clk_b_pins[] = {
3459         /* SCK */
3460         RCAR_GP_PIN(5, 0),
3461 };
3462 static const unsigned int scif5_clk_b_mux[] = {
3463         SCK5_B_MARK,
3464 };
3465
3466 /* - SCIF Clock ------------------------------------------------------------- */
3467 static const unsigned int scif_clk_a_pins[] = {
3468         /* SCIF_CLK */
3469         RCAR_GP_PIN(6, 23),
3470 };
3471 static const unsigned int scif_clk_a_mux[] = {
3472         SCIF_CLK_A_MARK,
3473 };
3474 static const unsigned int scif_clk_b_pins[] = {
3475         /* SCIF_CLK */
3476         RCAR_GP_PIN(5, 9),
3477 };
3478 static const unsigned int scif_clk_b_mux[] = {
3479         SCIF_CLK_B_MARK,
3480 };
3481
3482 /* - SDHI0 ------------------------------------------------------------------ */
3483 static const unsigned int sdhi0_data1_pins[] = {
3484         /* D0 */
3485         RCAR_GP_PIN(3, 2),
3486 };
3487 static const unsigned int sdhi0_data1_mux[] = {
3488         SD0_DAT0_MARK,
3489 };
3490 static const unsigned int sdhi0_data4_pins[] = {
3491         /* D[0:3] */
3492         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3493         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3494 };
3495 static const unsigned int sdhi0_data4_mux[] = {
3496         SD0_DAT0_MARK, SD0_DAT1_MARK,
3497         SD0_DAT2_MARK, SD0_DAT3_MARK,
3498 };
3499 static const unsigned int sdhi0_ctrl_pins[] = {
3500         /* CLK, CMD */
3501         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3502 };
3503 static const unsigned int sdhi0_ctrl_mux[] = {
3504         SD0_CLK_MARK, SD0_CMD_MARK,
3505 };
3506 static const unsigned int sdhi0_cd_pins[] = {
3507         /* CD */
3508         RCAR_GP_PIN(3, 12),
3509 };
3510 static const unsigned int sdhi0_cd_mux[] = {
3511         SD0_CD_MARK,
3512 };
3513 static const unsigned int sdhi0_wp_pins[] = {
3514         /* WP */
3515         RCAR_GP_PIN(3, 13),
3516 };
3517 static const unsigned int sdhi0_wp_mux[] = {
3518         SD0_WP_MARK,
3519 };
3520 /* - SDHI1 ------------------------------------------------------------------ */
3521 static const unsigned int sdhi1_data1_pins[] = {
3522         /* D0 */
3523         RCAR_GP_PIN(3, 8),
3524 };
3525 static const unsigned int sdhi1_data1_mux[] = {
3526         SD1_DAT0_MARK,
3527 };
3528 static const unsigned int sdhi1_data4_pins[] = {
3529         /* D[0:3] */
3530         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3531         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3532 };
3533 static const unsigned int sdhi1_data4_mux[] = {
3534         SD1_DAT0_MARK, SD1_DAT1_MARK,
3535         SD1_DAT2_MARK, SD1_DAT3_MARK,
3536 };
3537 static const unsigned int sdhi1_ctrl_pins[] = {
3538         /* CLK, CMD */
3539         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3540 };
3541 static const unsigned int sdhi1_ctrl_mux[] = {
3542         SD1_CLK_MARK, SD1_CMD_MARK,
3543 };
3544 static const unsigned int sdhi1_cd_pins[] = {
3545         /* CD */
3546         RCAR_GP_PIN(3, 14),
3547 };
3548 static const unsigned int sdhi1_cd_mux[] = {
3549         SD1_CD_MARK,
3550 };
3551 static const unsigned int sdhi1_wp_pins[] = {
3552         /* WP */
3553         RCAR_GP_PIN(3, 15),
3554 };
3555 static const unsigned int sdhi1_wp_mux[] = {
3556         SD1_WP_MARK,
3557 };
3558 /* - SDHI2 ------------------------------------------------------------------ */
3559 static const unsigned int sdhi2_data1_pins[] = {
3560         /* D0 */
3561         RCAR_GP_PIN(4, 2),
3562 };
3563 static const unsigned int sdhi2_data1_mux[] = {
3564         SD2_DAT0_MARK,
3565 };
3566 static const unsigned int sdhi2_data4_pins[] = {
3567         /* D[0:3] */
3568         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3569         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3570 };
3571 static const unsigned int sdhi2_data4_mux[] = {
3572         SD2_DAT0_MARK, SD2_DAT1_MARK,
3573         SD2_DAT2_MARK, SD2_DAT3_MARK,
3574 };
3575 static const unsigned int sdhi2_data8_pins[] = {
3576         /* D[0:7] */
3577         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3578         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3579         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3580         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3581 };
3582 static const unsigned int sdhi2_data8_mux[] = {
3583         SD2_DAT0_MARK, SD2_DAT1_MARK,
3584         SD2_DAT2_MARK, SD2_DAT3_MARK,
3585         SD2_DAT4_MARK, SD2_DAT5_MARK,
3586         SD2_DAT6_MARK, SD2_DAT7_MARK,
3587 };
3588 static const unsigned int sdhi2_ctrl_pins[] = {
3589         /* CLK, CMD */
3590         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3591 };
3592 static const unsigned int sdhi2_ctrl_mux[] = {
3593         SD2_CLK_MARK, SD2_CMD_MARK,
3594 };
3595 static const unsigned int sdhi2_cd_a_pins[] = {
3596         /* CD */
3597         RCAR_GP_PIN(4, 13),
3598 };
3599 static const unsigned int sdhi2_cd_a_mux[] = {
3600         SD2_CD_A_MARK,
3601 };
3602 static const unsigned int sdhi2_cd_b_pins[] = {
3603         /* CD */
3604         RCAR_GP_PIN(5, 10),
3605 };
3606 static const unsigned int sdhi2_cd_b_mux[] = {
3607         SD2_CD_B_MARK,
3608 };
3609 static const unsigned int sdhi2_wp_a_pins[] = {
3610         /* WP */
3611         RCAR_GP_PIN(4, 14),
3612 };
3613 static const unsigned int sdhi2_wp_a_mux[] = {
3614         SD2_WP_A_MARK,
3615 };
3616 static const unsigned int sdhi2_wp_b_pins[] = {
3617         /* WP */
3618         RCAR_GP_PIN(5, 11),
3619 };
3620 static const unsigned int sdhi2_wp_b_mux[] = {
3621         SD2_WP_B_MARK,
3622 };
3623 static const unsigned int sdhi2_ds_pins[] = {
3624         /* DS */
3625         RCAR_GP_PIN(4, 6),
3626 };
3627 static const unsigned int sdhi2_ds_mux[] = {
3628         SD2_DS_MARK,
3629 };
3630 /* - SDHI3 ------------------------------------------------------------------ */
3631 static const unsigned int sdhi3_data1_pins[] = {
3632         /* D0 */
3633         RCAR_GP_PIN(4, 9),
3634 };
3635 static const unsigned int sdhi3_data1_mux[] = {
3636         SD3_DAT0_MARK,
3637 };
3638 static const unsigned int sdhi3_data4_pins[] = {
3639         /* D[0:3] */
3640         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3641         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3642 };
3643 static const unsigned int sdhi3_data4_mux[] = {
3644         SD3_DAT0_MARK, SD3_DAT1_MARK,
3645         SD3_DAT2_MARK, SD3_DAT3_MARK,
3646 };
3647 static const unsigned int sdhi3_data8_pins[] = {
3648         /* D[0:7] */
3649         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3650         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3651         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3652         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3653 };
3654 static const unsigned int sdhi3_data8_mux[] = {
3655         SD3_DAT0_MARK, SD3_DAT1_MARK,
3656         SD3_DAT2_MARK, SD3_DAT3_MARK,
3657         SD3_DAT4_MARK, SD3_DAT5_MARK,
3658         SD3_DAT6_MARK, SD3_DAT7_MARK,
3659 };
3660 static const unsigned int sdhi3_ctrl_pins[] = {
3661         /* CLK, CMD */
3662         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3663 };
3664 static const unsigned int sdhi3_ctrl_mux[] = {
3665         SD3_CLK_MARK, SD3_CMD_MARK,
3666 };
3667 static const unsigned int sdhi3_cd_pins[] = {
3668         /* CD */
3669         RCAR_GP_PIN(4, 15),
3670 };
3671 static const unsigned int sdhi3_cd_mux[] = {
3672         SD3_CD_MARK,
3673 };
3674 static const unsigned int sdhi3_wp_pins[] = {
3675         /* WP */
3676         RCAR_GP_PIN(4, 16),
3677 };
3678 static const unsigned int sdhi3_wp_mux[] = {
3679         SD3_WP_MARK,
3680 };
3681 static const unsigned int sdhi3_ds_pins[] = {
3682         /* DS */
3683         RCAR_GP_PIN(4, 17),
3684 };
3685 static const unsigned int sdhi3_ds_mux[] = {
3686         SD3_DS_MARK,
3687 };
3688
3689 /* - SSI -------------------------------------------------------------------- */
3690 static const unsigned int ssi0_data_pins[] = {
3691         /* SDATA */
3692         RCAR_GP_PIN(6, 2),
3693 };
3694 static const unsigned int ssi0_data_mux[] = {
3695         SSI_SDATA0_MARK,
3696 };
3697 static const unsigned int ssi01239_ctrl_pins[] = {
3698         /* SCK, WS */
3699         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3700 };
3701 static const unsigned int ssi01239_ctrl_mux[] = {
3702         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3703 };
3704 static const unsigned int ssi1_data_a_pins[] = {
3705         /* SDATA */
3706         RCAR_GP_PIN(6, 3),
3707 };
3708 static const unsigned int ssi1_data_a_mux[] = {
3709         SSI_SDATA1_A_MARK,
3710 };
3711 static const unsigned int ssi1_data_b_pins[] = {
3712         /* SDATA */
3713         RCAR_GP_PIN(5, 12),
3714 };
3715 static const unsigned int ssi1_data_b_mux[] = {
3716         SSI_SDATA1_B_MARK,
3717 };
3718 static const unsigned int ssi1_ctrl_a_pins[] = {
3719         /* SCK, WS */
3720         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3721 };
3722 static const unsigned int ssi1_ctrl_a_mux[] = {
3723         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3724 };
3725 static const unsigned int ssi1_ctrl_b_pins[] = {
3726         /* SCK, WS */
3727         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3728 };
3729 static const unsigned int ssi1_ctrl_b_mux[] = {
3730         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3731 };
3732 static const unsigned int ssi2_data_a_pins[] = {
3733         /* SDATA */
3734         RCAR_GP_PIN(6, 4),
3735 };
3736 static const unsigned int ssi2_data_a_mux[] = {
3737         SSI_SDATA2_A_MARK,
3738 };
3739 static const unsigned int ssi2_data_b_pins[] = {
3740         /* SDATA */
3741         RCAR_GP_PIN(5, 13),
3742 };
3743 static const unsigned int ssi2_data_b_mux[] = {
3744         SSI_SDATA2_B_MARK,
3745 };
3746 static const unsigned int ssi2_ctrl_a_pins[] = {
3747         /* SCK, WS */
3748         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3749 };
3750 static const unsigned int ssi2_ctrl_a_mux[] = {
3751         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3752 };
3753 static const unsigned int ssi2_ctrl_b_pins[] = {
3754         /* SCK, WS */
3755         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3756 };
3757 static const unsigned int ssi2_ctrl_b_mux[] = {
3758         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3759 };
3760 static const unsigned int ssi3_data_pins[] = {
3761         /* SDATA */
3762         RCAR_GP_PIN(6, 7),
3763 };
3764 static const unsigned int ssi3_data_mux[] = {
3765         SSI_SDATA3_MARK,
3766 };
3767 static const unsigned int ssi349_ctrl_pins[] = {
3768         /* SCK, WS */
3769         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3770 };
3771 static const unsigned int ssi349_ctrl_mux[] = {
3772         SSI_SCK349_MARK, SSI_WS349_MARK,
3773 };
3774 static const unsigned int ssi4_data_pins[] = {
3775         /* SDATA */
3776         RCAR_GP_PIN(6, 10),
3777 };
3778 static const unsigned int ssi4_data_mux[] = {
3779         SSI_SDATA4_MARK,
3780 };
3781 static const unsigned int ssi4_ctrl_pins[] = {
3782         /* SCK, WS */
3783         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3784 };
3785 static const unsigned int ssi4_ctrl_mux[] = {
3786         SSI_SCK4_MARK, SSI_WS4_MARK,
3787 };
3788 static const unsigned int ssi5_data_pins[] = {
3789         /* SDATA */
3790         RCAR_GP_PIN(6, 13),
3791 };
3792 static const unsigned int ssi5_data_mux[] = {
3793         SSI_SDATA5_MARK,
3794 };
3795 static const unsigned int ssi5_ctrl_pins[] = {
3796         /* SCK, WS */
3797         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3798 };
3799 static const unsigned int ssi5_ctrl_mux[] = {
3800         SSI_SCK5_MARK, SSI_WS5_MARK,
3801 };
3802 static const unsigned int ssi6_data_pins[] = {
3803         /* SDATA */
3804         RCAR_GP_PIN(6, 16),
3805 };
3806 static const unsigned int ssi6_data_mux[] = {
3807         SSI_SDATA6_MARK,
3808 };
3809 static const unsigned int ssi6_ctrl_pins[] = {
3810         /* SCK, WS */
3811         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3812 };
3813 static const unsigned int ssi6_ctrl_mux[] = {
3814         SSI_SCK6_MARK, SSI_WS6_MARK,
3815 };
3816 static const unsigned int ssi7_data_pins[] = {
3817         /* SDATA */
3818         RCAR_GP_PIN(6, 19),
3819 };
3820 static const unsigned int ssi7_data_mux[] = {
3821         SSI_SDATA7_MARK,
3822 };
3823 static const unsigned int ssi78_ctrl_pins[] = {
3824         /* SCK, WS */
3825         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3826 };
3827 static const unsigned int ssi78_ctrl_mux[] = {
3828         SSI_SCK78_MARK, SSI_WS78_MARK,
3829 };
3830 static const unsigned int ssi8_data_pins[] = {
3831         /* SDATA */
3832         RCAR_GP_PIN(6, 20),
3833 };
3834 static const unsigned int ssi8_data_mux[] = {
3835         SSI_SDATA8_MARK,
3836 };
3837 static const unsigned int ssi9_data_a_pins[] = {
3838         /* SDATA */
3839         RCAR_GP_PIN(6, 21),
3840 };
3841 static const unsigned int ssi9_data_a_mux[] = {
3842         SSI_SDATA9_A_MARK,
3843 };
3844 static const unsigned int ssi9_data_b_pins[] = {
3845         /* SDATA */
3846         RCAR_GP_PIN(5, 14),
3847 };
3848 static const unsigned int ssi9_data_b_mux[] = {
3849         SSI_SDATA9_B_MARK,
3850 };
3851 static const unsigned int ssi9_ctrl_a_pins[] = {
3852         /* SCK, WS */
3853         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3854 };
3855 static const unsigned int ssi9_ctrl_a_mux[] = {
3856         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3857 };
3858 static const unsigned int ssi9_ctrl_b_pins[] = {
3859         /* SCK, WS */
3860         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3861 };
3862 static const unsigned int ssi9_ctrl_b_mux[] = {
3863         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3864 };
3865
3866 /* - TMU -------------------------------------------------------------------- */
3867 static const unsigned int tmu_tclk1_a_pins[] = {
3868         /* TCLK */
3869         RCAR_GP_PIN(6, 23),
3870 };
3871 static const unsigned int tmu_tclk1_a_mux[] = {
3872         TCLK1_A_MARK,
3873 };
3874 static const unsigned int tmu_tclk1_b_pins[] = {
3875         /* TCLK */
3876         RCAR_GP_PIN(5, 19),
3877 };
3878 static const unsigned int tmu_tclk1_b_mux[] = {
3879         TCLK1_B_MARK,
3880 };
3881 static const unsigned int tmu_tclk2_a_pins[] = {
3882         /* TCLK */
3883         RCAR_GP_PIN(6, 19),
3884 };
3885 static const unsigned int tmu_tclk2_a_mux[] = {
3886         TCLK2_A_MARK,
3887 };
3888 static const unsigned int tmu_tclk2_b_pins[] = {
3889         /* TCLK */
3890         RCAR_GP_PIN(6, 28),
3891 };
3892 static const unsigned int tmu_tclk2_b_mux[] = {
3893         TCLK2_B_MARK,
3894 };
3895
3896 /* - USB0 ------------------------------------------------------------------- */
3897 static const unsigned int usb0_pins[] = {
3898         /* PWEN, OVC */
3899         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3900 };
3901 static const unsigned int usb0_mux[] = {
3902         USB0_PWEN_MARK, USB0_OVC_MARK,
3903 };
3904 /* - USB1 ------------------------------------------------------------------- */
3905 static const unsigned int usb1_pins[] = {
3906         /* PWEN, OVC */
3907         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3908 };
3909 static const unsigned int usb1_mux[] = {
3910         USB1_PWEN_MARK, USB1_OVC_MARK,
3911 };
3912
3913 /* - USB30 ------------------------------------------------------------------ */
3914 static const unsigned int usb30_pins[] = {
3915         /* PWEN, OVC */
3916         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3917 };
3918 static const unsigned int usb30_mux[] = {
3919         USB30_PWEN_MARK, USB30_OVC_MARK,
3920 };
3921
3922 /* - VIN4 ------------------------------------------------------------------- */
3923 static const unsigned int vin4_data18_a_pins[] = {
3924         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3925         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3926         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3927         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3928         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3929         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3930         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3931         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3932         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3933 };
3934 static const unsigned int vin4_data18_a_mux[] = {
3935         VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3936         VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3937         VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3938         VI4_DATA10_MARK, VI4_DATA11_MARK,
3939         VI4_DATA12_MARK, VI4_DATA13_MARK,
3940         VI4_DATA14_MARK, VI4_DATA15_MARK,
3941         VI4_DATA18_MARK, VI4_DATA19_MARK,
3942         VI4_DATA20_MARK, VI4_DATA21_MARK,
3943         VI4_DATA22_MARK, VI4_DATA23_MARK,
3944 };
3945 static const unsigned int vin4_data18_b_pins[] = {
3946         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3947         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3948         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3949         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3950         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3951         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3952         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3953         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3954         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3955 };
3956 static const unsigned int vin4_data18_b_mux[] = {
3957         VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3958         VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3959         VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3960         VI4_DATA10_MARK, VI4_DATA11_MARK,
3961         VI4_DATA12_MARK, VI4_DATA13_MARK,
3962         VI4_DATA14_MARK, VI4_DATA15_MARK,
3963         VI4_DATA18_MARK, VI4_DATA19_MARK,
3964         VI4_DATA20_MARK, VI4_DATA21_MARK,
3965         VI4_DATA22_MARK, VI4_DATA23_MARK,
3966 };
3967 static const union vin_data vin4_data_a_pins = {
3968         .data24 = {
3969                 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3970                 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3971                 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3972                 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3973                 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3974                 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3975                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3976                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3977                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3978                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3979                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3980                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3981         },
3982 };
3983 static const union vin_data vin4_data_a_mux = {
3984         .data24 = {
3985                 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3986                 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3987                 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3988                 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3989                 VI4_DATA8_MARK,  VI4_DATA9_MARK,
3990                 VI4_DATA10_MARK, VI4_DATA11_MARK,
3991                 VI4_DATA12_MARK, VI4_DATA13_MARK,
3992                 VI4_DATA14_MARK, VI4_DATA15_MARK,
3993                 VI4_DATA16_MARK, VI4_DATA17_MARK,
3994                 VI4_DATA18_MARK, VI4_DATA19_MARK,
3995                 VI4_DATA20_MARK, VI4_DATA21_MARK,
3996                 VI4_DATA22_MARK, VI4_DATA23_MARK,
3997         },
3998 };
3999 static const union vin_data vin4_data_b_pins = {
4000         .data24 = {
4001                 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4002                 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4003                 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4004                 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4005                 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4006                 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4007                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4008                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4009                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4010                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4011                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4012                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4013         },
4014 };
4015 static const union vin_data vin4_data_b_mux = {
4016         .data24 = {
4017                 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4018                 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4019                 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4020                 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4021                 VI4_DATA8_MARK,  VI4_DATA9_MARK,
4022                 VI4_DATA10_MARK, VI4_DATA11_MARK,
4023                 VI4_DATA12_MARK, VI4_DATA13_MARK,
4024                 VI4_DATA14_MARK, VI4_DATA15_MARK,
4025                 VI4_DATA16_MARK, VI4_DATA17_MARK,
4026                 VI4_DATA18_MARK, VI4_DATA19_MARK,
4027                 VI4_DATA20_MARK, VI4_DATA21_MARK,
4028                 VI4_DATA22_MARK, VI4_DATA23_MARK,
4029         },
4030 };
4031 static const unsigned int vin4_sync_pins[] = {
4032         /* HSYNC#, VSYNC# */
4033         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4034 };
4035 static const unsigned int vin4_sync_mux[] = {
4036         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4037 };
4038 static const unsigned int vin4_field_pins[] = {
4039         /* FIELD */
4040         RCAR_GP_PIN(1, 16),
4041 };
4042 static const unsigned int vin4_field_mux[] = {
4043         VI4_FIELD_MARK,
4044 };
4045 static const unsigned int vin4_clkenb_pins[] = {
4046         /* CLKENB */
4047         RCAR_GP_PIN(1, 19),
4048 };
4049 static const unsigned int vin4_clkenb_mux[] = {
4050         VI4_CLKENB_MARK,
4051 };
4052 static const unsigned int vin4_clk_pins[] = {
4053         /* CLK */
4054         RCAR_GP_PIN(1, 27),
4055 };
4056 static const unsigned int vin4_clk_mux[] = {
4057         VI4_CLK_MARK,
4058 };
4059
4060 /* - VIN5 ------------------------------------------------------------------- */
4061 static const union vin_data16 vin5_data_pins = {
4062         .data16 = {
4063                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4064                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4065                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4066                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4067                 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4068                 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4069                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4070                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4071         },
4072 };
4073 static const union vin_data16 vin5_data_mux = {
4074         .data16 = {
4075                 VI5_DATA0_MARK, VI5_DATA1_MARK,
4076                 VI5_DATA2_MARK, VI5_DATA3_MARK,
4077                 VI5_DATA4_MARK, VI5_DATA5_MARK,
4078                 VI5_DATA6_MARK, VI5_DATA7_MARK,
4079                 VI5_DATA8_MARK,  VI5_DATA9_MARK,
4080                 VI5_DATA10_MARK, VI5_DATA11_MARK,
4081                 VI5_DATA12_MARK, VI5_DATA13_MARK,
4082                 VI5_DATA14_MARK, VI5_DATA15_MARK,
4083         },
4084 };
4085 static const unsigned int vin5_sync_pins[] = {
4086         /* HSYNC#, VSYNC# */
4087         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4088 };
4089 static const unsigned int vin5_sync_mux[] = {
4090         VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4091 };
4092 static const unsigned int vin5_field_pins[] = {
4093         RCAR_GP_PIN(1, 11),
4094 };
4095 static const unsigned int vin5_field_mux[] = {
4096         /* FIELD */
4097         VI5_FIELD_MARK,
4098 };
4099 static const unsigned int vin5_clkenb_pins[] = {
4100         RCAR_GP_PIN(1, 20),
4101 };
4102 static const unsigned int vin5_clkenb_mux[] = {
4103         /* CLKENB */
4104         VI5_CLKENB_MARK,
4105 };
4106 static const unsigned int vin5_clk_pins[] = {
4107         RCAR_GP_PIN(1, 21),
4108 };
4109 static const unsigned int vin5_clk_mux[] = {
4110         /* CLK */
4111         VI5_CLK_MARK,
4112 };
4113
4114 static const struct {
4115         struct sh_pfc_pin_group common[312];
4116         struct sh_pfc_pin_group automotive[30];
4117 } pinmux_groups = {
4118         .common = {
4119                 SH_PFC_PIN_GROUP(audio_clk_a_a),
4120                 SH_PFC_PIN_GROUP(audio_clk_a_b),
4121                 SH_PFC_PIN_GROUP(audio_clk_a_c),
4122                 SH_PFC_PIN_GROUP(audio_clk_b_a),
4123                 SH_PFC_PIN_GROUP(audio_clk_b_b),
4124                 SH_PFC_PIN_GROUP(audio_clk_c_a),
4125                 SH_PFC_PIN_GROUP(audio_clk_c_b),
4126                 SH_PFC_PIN_GROUP(audio_clkout_a),
4127                 SH_PFC_PIN_GROUP(audio_clkout_b),
4128                 SH_PFC_PIN_GROUP(audio_clkout_c),
4129                 SH_PFC_PIN_GROUP(audio_clkout_d),
4130                 SH_PFC_PIN_GROUP(audio_clkout1_a),
4131                 SH_PFC_PIN_GROUP(audio_clkout1_b),
4132                 SH_PFC_PIN_GROUP(audio_clkout2_a),
4133                 SH_PFC_PIN_GROUP(audio_clkout2_b),
4134                 SH_PFC_PIN_GROUP(audio_clkout3_a),
4135                 SH_PFC_PIN_GROUP(audio_clkout3_b),
4136                 SH_PFC_PIN_GROUP(avb_link),
4137                 SH_PFC_PIN_GROUP(avb_magic),
4138                 SH_PFC_PIN_GROUP(avb_phy_int),
4139                 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4140                 SH_PFC_PIN_GROUP(avb_mdio),
4141                 SH_PFC_PIN_GROUP(avb_mii),
4142                 SH_PFC_PIN_GROUP(avb_avtp_pps),
4143                 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4144                 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4145                 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4146                 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4147                 SH_PFC_PIN_GROUP(can0_data_a),
4148                 SH_PFC_PIN_GROUP(can0_data_b),
4149                 SH_PFC_PIN_GROUP(can1_data),
4150                 SH_PFC_PIN_GROUP(can_clk),
4151                 SH_PFC_PIN_GROUP(canfd0_data_a),
4152                 SH_PFC_PIN_GROUP(canfd0_data_b),
4153                 SH_PFC_PIN_GROUP(canfd1_data),
4154                 SH_PFC_PIN_GROUP(du_rgb666),
4155                 SH_PFC_PIN_GROUP(du_rgb888),
4156                 SH_PFC_PIN_GROUP(du_clk_out_0),
4157                 SH_PFC_PIN_GROUP(du_clk_out_1),
4158                 SH_PFC_PIN_GROUP(du_sync),
4159                 SH_PFC_PIN_GROUP(du_oddf),
4160                 SH_PFC_PIN_GROUP(du_cde),
4161                 SH_PFC_PIN_GROUP(du_disp),
4162                 SH_PFC_PIN_GROUP(hscif0_data),
4163                 SH_PFC_PIN_GROUP(hscif0_clk),
4164                 SH_PFC_PIN_GROUP(hscif0_ctrl),
4165                 SH_PFC_PIN_GROUP(hscif1_data_a),
4166                 SH_PFC_PIN_GROUP(hscif1_clk_a),
4167                 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4168                 SH_PFC_PIN_GROUP(hscif1_data_b),
4169                 SH_PFC_PIN_GROUP(hscif1_clk_b),
4170                 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4171                 SH_PFC_PIN_GROUP(hscif2_data_a),
4172                 SH_PFC_PIN_GROUP(hscif2_clk_a),
4173                 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4174                 SH_PFC_PIN_GROUP(hscif2_data_b),
4175                 SH_PFC_PIN_GROUP(hscif2_clk_b),
4176                 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4177                 SH_PFC_PIN_GROUP(hscif2_data_c),
4178                 SH_PFC_PIN_GROUP(hscif2_clk_c),
4179                 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4180                 SH_PFC_PIN_GROUP(hscif3_data_a),
4181                 SH_PFC_PIN_GROUP(hscif3_clk),
4182                 SH_PFC_PIN_GROUP(hscif3_ctrl),
4183                 SH_PFC_PIN_GROUP(hscif3_data_b),
4184                 SH_PFC_PIN_GROUP(hscif3_data_c),
4185                 SH_PFC_PIN_GROUP(hscif3_data_d),
4186                 SH_PFC_PIN_GROUP(hscif4_data_a),
4187                 SH_PFC_PIN_GROUP(hscif4_clk),
4188                 SH_PFC_PIN_GROUP(hscif4_ctrl),
4189                 SH_PFC_PIN_GROUP(hscif4_data_b),
4190                 SH_PFC_PIN_GROUP(i2c0),
4191                 SH_PFC_PIN_GROUP(i2c1_a),
4192                 SH_PFC_PIN_GROUP(i2c1_b),
4193                 SH_PFC_PIN_GROUP(i2c2_a),
4194                 SH_PFC_PIN_GROUP(i2c2_b),
4195                 SH_PFC_PIN_GROUP(i2c3),
4196                 SH_PFC_PIN_GROUP(i2c5),
4197                 SH_PFC_PIN_GROUP(i2c6_a),
4198                 SH_PFC_PIN_GROUP(i2c6_b),
4199                 SH_PFC_PIN_GROUP(i2c6_c),
4200                 SH_PFC_PIN_GROUP(intc_ex_irq0),
4201                 SH_PFC_PIN_GROUP(intc_ex_irq1),
4202                 SH_PFC_PIN_GROUP(intc_ex_irq2),
4203                 SH_PFC_PIN_GROUP(intc_ex_irq3),
4204                 SH_PFC_PIN_GROUP(intc_ex_irq4),
4205                 SH_PFC_PIN_GROUP(intc_ex_irq5),
4206                 SH_PFC_PIN_GROUP(msiof0_clk),
4207                 SH_PFC_PIN_GROUP(msiof0_sync),
4208                 SH_PFC_PIN_GROUP(msiof0_ss1),
4209                 SH_PFC_PIN_GROUP(msiof0_ss2),
4210                 SH_PFC_PIN_GROUP(msiof0_txd),
4211                 SH_PFC_PIN_GROUP(msiof0_rxd),
4212                 SH_PFC_PIN_GROUP(msiof1_clk_a),
4213                 SH_PFC_PIN_GROUP(msiof1_sync_a),
4214                 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4215                 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4216                 SH_PFC_PIN_GROUP(msiof1_txd_a),
4217                 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4218                 SH_PFC_PIN_GROUP(msiof1_clk_b),
4219                 SH_PFC_PIN_GROUP(msiof1_sync_b),
4220                 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4221                 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4222                 SH_PFC_PIN_GROUP(msiof1_txd_b),
4223                 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4224                 SH_PFC_PIN_GROUP(msiof1_clk_c),
4225                 SH_PFC_PIN_GROUP(msiof1_sync_c),
4226                 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4227                 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4228                 SH_PFC_PIN_GROUP(msiof1_txd_c),
4229                 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4230                 SH_PFC_PIN_GROUP(msiof1_clk_d),
4231                 SH_PFC_PIN_GROUP(msiof1_sync_d),
4232                 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4233                 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4234                 SH_PFC_PIN_GROUP(msiof1_txd_d),
4235                 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4236                 SH_PFC_PIN_GROUP(msiof1_clk_e),
4237                 SH_PFC_PIN_GROUP(msiof1_sync_e),
4238                 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4239                 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4240                 SH_PFC_PIN_GROUP(msiof1_txd_e),
4241                 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4242                 SH_PFC_PIN_GROUP(msiof1_clk_f),
4243                 SH_PFC_PIN_GROUP(msiof1_sync_f),
4244                 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4245                 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4246                 SH_PFC_PIN_GROUP(msiof1_txd_f),
4247                 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4248                 SH_PFC_PIN_GROUP(msiof1_clk_g),
4249                 SH_PFC_PIN_GROUP(msiof1_sync_g),
4250                 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4251                 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4252                 SH_PFC_PIN_GROUP(msiof1_txd_g),
4253                 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4254                 SH_PFC_PIN_GROUP(msiof2_clk_a),
4255                 SH_PFC_PIN_GROUP(msiof2_sync_a),
4256                 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4257                 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4258                 SH_PFC_PIN_GROUP(msiof2_txd_a),
4259                 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4260                 SH_PFC_PIN_GROUP(msiof2_clk_b),
4261                 SH_PFC_PIN_GROUP(msiof2_sync_b),
4262                 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4263                 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4264                 SH_PFC_PIN_GROUP(msiof2_txd_b),
4265                 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4266                 SH_PFC_PIN_GROUP(msiof2_clk_c),
4267                 SH_PFC_PIN_GROUP(msiof2_sync_c),
4268                 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4269                 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4270                 SH_PFC_PIN_GROUP(msiof2_txd_c),
4271                 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4272                 SH_PFC_PIN_GROUP(msiof2_clk_d),
4273                 SH_PFC_PIN_GROUP(msiof2_sync_d),
4274                 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4275                 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4276                 SH_PFC_PIN_GROUP(msiof2_txd_d),
4277                 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4278                 SH_PFC_PIN_GROUP(msiof3_clk_a),
4279                 SH_PFC_PIN_GROUP(msiof3_sync_a),
4280                 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4281                 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4282                 SH_PFC_PIN_GROUP(msiof3_txd_a),
4283                 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4284                 SH_PFC_PIN_GROUP(msiof3_clk_b),
4285                 SH_PFC_PIN_GROUP(msiof3_sync_b),
4286                 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4287                 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4288                 SH_PFC_PIN_GROUP(msiof3_txd_b),
4289                 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4290                 SH_PFC_PIN_GROUP(msiof3_clk_c),
4291                 SH_PFC_PIN_GROUP(msiof3_sync_c),
4292                 SH_PFC_PIN_GROUP(msiof3_txd_c),
4293                 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4294                 SH_PFC_PIN_GROUP(msiof3_clk_d),
4295                 SH_PFC_PIN_GROUP(msiof3_sync_d),
4296                 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4297                 SH_PFC_PIN_GROUP(msiof3_txd_d),
4298                 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4299                 SH_PFC_PIN_GROUP(msiof3_clk_e),
4300                 SH_PFC_PIN_GROUP(msiof3_sync_e),
4301                 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4302                 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4303                 SH_PFC_PIN_GROUP(msiof3_txd_e),
4304                 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4305                 SH_PFC_PIN_GROUP(pwm0),
4306                 SH_PFC_PIN_GROUP(pwm1_a),
4307                 SH_PFC_PIN_GROUP(pwm1_b),
4308                 SH_PFC_PIN_GROUP(pwm2_a),
4309                 SH_PFC_PIN_GROUP(pwm2_b),
4310                 SH_PFC_PIN_GROUP(pwm3_a),
4311                 SH_PFC_PIN_GROUP(pwm3_b),
4312                 SH_PFC_PIN_GROUP(pwm4_a),
4313                 SH_PFC_PIN_GROUP(pwm4_b),
4314                 SH_PFC_PIN_GROUP(pwm5_a),
4315                 SH_PFC_PIN_GROUP(pwm5_b),
4316                 SH_PFC_PIN_GROUP(pwm6_a),
4317                 SH_PFC_PIN_GROUP(pwm6_b),
4318                 SH_PFC_PIN_GROUP(scif0_data),
4319                 SH_PFC_PIN_GROUP(scif0_clk),
4320                 SH_PFC_PIN_GROUP(scif0_ctrl),
4321                 SH_PFC_PIN_GROUP(scif1_data_a),
4322                 SH_PFC_PIN_GROUP(scif1_clk),
4323                 SH_PFC_PIN_GROUP(scif1_ctrl),
4324                 SH_PFC_PIN_GROUP(scif1_data_b),
4325                 SH_PFC_PIN_GROUP(scif2_data_a),
4326                 SH_PFC_PIN_GROUP(scif2_clk),
4327                 SH_PFC_PIN_GROUP(scif2_data_b),
4328                 SH_PFC_PIN_GROUP(scif3_data_a),
4329                 SH_PFC_PIN_GROUP(scif3_clk),
4330                 SH_PFC_PIN_GROUP(scif3_ctrl),
4331                 SH_PFC_PIN_GROUP(scif3_data_b),
4332                 SH_PFC_PIN_GROUP(scif4_data_a),
4333                 SH_PFC_PIN_GROUP(scif4_clk_a),
4334                 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4335                 SH_PFC_PIN_GROUP(scif4_data_b),
4336                 SH_PFC_PIN_GROUP(scif4_clk_b),
4337                 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4338                 SH_PFC_PIN_GROUP(scif4_data_c),
4339                 SH_PFC_PIN_GROUP(scif4_clk_c),
4340                 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4341                 SH_PFC_PIN_GROUP(scif5_data_a),
4342                 SH_PFC_PIN_GROUP(scif5_clk_a),
4343                 SH_PFC_PIN_GROUP(scif5_data_b),
4344                 SH_PFC_PIN_GROUP(scif5_clk_b),
4345                 SH_PFC_PIN_GROUP(scif_clk_a),
4346                 SH_PFC_PIN_GROUP(scif_clk_b),
4347                 SH_PFC_PIN_GROUP(sdhi0_data1),
4348                 SH_PFC_PIN_GROUP(sdhi0_data4),
4349                 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4350                 SH_PFC_PIN_GROUP(sdhi0_cd),
4351                 SH_PFC_PIN_GROUP(sdhi0_wp),
4352                 SH_PFC_PIN_GROUP(sdhi1_data1),
4353                 SH_PFC_PIN_GROUP(sdhi1_data4),
4354                 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4355                 SH_PFC_PIN_GROUP(sdhi1_cd),
4356                 SH_PFC_PIN_GROUP(sdhi1_wp),
4357                 SH_PFC_PIN_GROUP(sdhi2_data1),
4358                 SH_PFC_PIN_GROUP(sdhi2_data4),
4359                 SH_PFC_PIN_GROUP(sdhi2_data8),
4360                 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4361                 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4362                 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4363                 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4364                 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4365                 SH_PFC_PIN_GROUP(sdhi2_ds),
4366                 SH_PFC_PIN_GROUP(sdhi3_data1),
4367                 SH_PFC_PIN_GROUP(sdhi3_data4),
4368                 SH_PFC_PIN_GROUP(sdhi3_data8),
4369                 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4370                 SH_PFC_PIN_GROUP(sdhi3_cd),
4371                 SH_PFC_PIN_GROUP(sdhi3_wp),
4372                 SH_PFC_PIN_GROUP(sdhi3_ds),
4373                 SH_PFC_PIN_GROUP(ssi0_data),
4374                 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4375                 SH_PFC_PIN_GROUP(ssi1_data_a),
4376                 SH_PFC_PIN_GROUP(ssi1_data_b),
4377                 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4378                 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4379                 SH_PFC_PIN_GROUP(ssi2_data_a),
4380                 SH_PFC_PIN_GROUP(ssi2_data_b),
4381                 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4382                 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4383                 SH_PFC_PIN_GROUP(ssi3_data),
4384                 SH_PFC_PIN_GROUP(ssi349_ctrl),
4385                 SH_PFC_PIN_GROUP(ssi4_data),
4386                 SH_PFC_PIN_GROUP(ssi4_ctrl),
4387                 SH_PFC_PIN_GROUP(ssi5_data),
4388                 SH_PFC_PIN_GROUP(ssi5_ctrl),
4389                 SH_PFC_PIN_GROUP(ssi6_data),
4390                 SH_PFC_PIN_GROUP(ssi6_ctrl),
4391                 SH_PFC_PIN_GROUP(ssi7_data),
4392                 SH_PFC_PIN_GROUP(ssi78_ctrl),
4393                 SH_PFC_PIN_GROUP(ssi8_data),
4394                 SH_PFC_PIN_GROUP(ssi9_data_a),
4395                 SH_PFC_PIN_GROUP(ssi9_data_b),
4396                 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4397                 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4398                 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4399                 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4400                 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4401                 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4402                 SH_PFC_PIN_GROUP(usb0),
4403                 SH_PFC_PIN_GROUP(usb1),
4404                 SH_PFC_PIN_GROUP(usb30),
4405                 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4406                 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4407                 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4408                 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4409                 SH_PFC_PIN_GROUP(vin4_data18_a),
4410                 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4411                 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4412                 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4413                 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4414                 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4415                 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4416                 SH_PFC_PIN_GROUP(vin4_data18_b),
4417                 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4418                 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4419                 SH_PFC_PIN_GROUP(vin4_sync),
4420                 SH_PFC_PIN_GROUP(vin4_field),
4421                 SH_PFC_PIN_GROUP(vin4_clkenb),
4422                 SH_PFC_PIN_GROUP(vin4_clk),
4423                 VIN_DATA_PIN_GROUP(vin5_data, 8),
4424                 VIN_DATA_PIN_GROUP(vin5_data, 10),
4425                 VIN_DATA_PIN_GROUP(vin5_data, 12),
4426                 VIN_DATA_PIN_GROUP(vin5_data, 16),
4427                 SH_PFC_PIN_GROUP(vin5_sync),
4428                 SH_PFC_PIN_GROUP(vin5_field),
4429                 SH_PFC_PIN_GROUP(vin5_clkenb),
4430                 SH_PFC_PIN_GROUP(vin5_clk),
4431         },
4432         .automotive = {
4433                 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4434                 SH_PFC_PIN_GROUP(drif0_data0_a),
4435                 SH_PFC_PIN_GROUP(drif0_data1_a),
4436                 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4437                 SH_PFC_PIN_GROUP(drif0_data0_b),
4438                 SH_PFC_PIN_GROUP(drif0_data1_b),
4439                 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4440                 SH_PFC_PIN_GROUP(drif0_data0_c),
4441                 SH_PFC_PIN_GROUP(drif0_data1_c),
4442                 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4443                 SH_PFC_PIN_GROUP(drif1_data0_a),
4444                 SH_PFC_PIN_GROUP(drif1_data1_a),
4445                 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4446                 SH_PFC_PIN_GROUP(drif1_data0_b),
4447                 SH_PFC_PIN_GROUP(drif1_data1_b),
4448                 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4449                 SH_PFC_PIN_GROUP(drif1_data0_c),
4450                 SH_PFC_PIN_GROUP(drif1_data1_c),
4451                 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4452                 SH_PFC_PIN_GROUP(drif2_data0_a),
4453                 SH_PFC_PIN_GROUP(drif2_data1_a),
4454                 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4455                 SH_PFC_PIN_GROUP(drif2_data0_b),
4456                 SH_PFC_PIN_GROUP(drif2_data1_b),
4457                 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4458                 SH_PFC_PIN_GROUP(drif3_data0_a),
4459                 SH_PFC_PIN_GROUP(drif3_data1_a),
4460                 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4461                 SH_PFC_PIN_GROUP(drif3_data0_b),
4462                 SH_PFC_PIN_GROUP(drif3_data1_b),
4463         }
4464 };
4465
4466 static const char * const audio_clk_groups[] = {
4467         "audio_clk_a_a",
4468         "audio_clk_a_b",
4469         "audio_clk_a_c",
4470         "audio_clk_b_a",
4471         "audio_clk_b_b",
4472         "audio_clk_c_a",
4473         "audio_clk_c_b",
4474         "audio_clkout_a",
4475         "audio_clkout_b",
4476         "audio_clkout_c",
4477         "audio_clkout_d",
4478         "audio_clkout1_a",
4479         "audio_clkout1_b",
4480         "audio_clkout2_a",
4481         "audio_clkout2_b",
4482         "audio_clkout3_a",
4483         "audio_clkout3_b",
4484 };
4485
4486 static const char * const avb_groups[] = {
4487         "avb_link",
4488         "avb_magic",
4489         "avb_phy_int",
4490         "avb_mdc",      /* Deprecated, please use "avb_mdio" instead */
4491         "avb_mdio",
4492         "avb_mii",
4493         "avb_avtp_pps",
4494         "avb_avtp_match_a",
4495         "avb_avtp_capture_a",
4496         "avb_avtp_match_b",
4497         "avb_avtp_capture_b",
4498 };
4499
4500 static const char * const can0_groups[] = {
4501         "can0_data_a",
4502         "can0_data_b",
4503 };
4504
4505 static const char * const can1_groups[] = {
4506         "can1_data",
4507 };
4508
4509 static const char * const can_clk_groups[] = {
4510         "can_clk",
4511 };
4512
4513 static const char * const canfd0_groups[] = {
4514         "canfd0_data_a",
4515         "canfd0_data_b",
4516 };
4517
4518 static const char * const canfd1_groups[] = {
4519         "canfd1_data",
4520 };
4521
4522 static const char * const drif0_groups[] = {
4523         "drif0_ctrl_a",
4524         "drif0_data0_a",
4525         "drif0_data1_a",
4526         "drif0_ctrl_b",
4527         "drif0_data0_b",
4528         "drif0_data1_b",
4529         "drif0_ctrl_c",
4530         "drif0_data0_c",
4531         "drif0_data1_c",
4532 };
4533
4534 static const char * const drif1_groups[] = {
4535         "drif1_ctrl_a",
4536         "drif1_data0_a",
4537         "drif1_data1_a",
4538         "drif1_ctrl_b",
4539         "drif1_data0_b",
4540         "drif1_data1_b",
4541         "drif1_ctrl_c",
4542         "drif1_data0_c",
4543         "drif1_data1_c",
4544 };
4545
4546 static const char * const drif2_groups[] = {
4547         "drif2_ctrl_a",
4548         "drif2_data0_a",
4549         "drif2_data1_a",
4550         "drif2_ctrl_b",
4551         "drif2_data0_b",
4552         "drif2_data1_b",
4553 };
4554
4555 static const char * const drif3_groups[] = {
4556         "drif3_ctrl_a",
4557         "drif3_data0_a",
4558         "drif3_data1_a",
4559         "drif3_ctrl_b",
4560         "drif3_data0_b",
4561         "drif3_data1_b",
4562 };
4563
4564 static const char * const du_groups[] = {
4565         "du_rgb666",
4566         "du_rgb888",
4567         "du_clk_out_0",
4568         "du_clk_out_1",
4569         "du_sync",
4570         "du_oddf",
4571         "du_cde",
4572         "du_disp",
4573 };
4574
4575 static const char * const hscif0_groups[] = {
4576         "hscif0_data",
4577         "hscif0_clk",
4578         "hscif0_ctrl",
4579 };
4580
4581 static const char * const hscif1_groups[] = {
4582         "hscif1_data_a",
4583         "hscif1_clk_a",
4584         "hscif1_ctrl_a",
4585         "hscif1_data_b",
4586         "hscif1_clk_b",
4587         "hscif1_ctrl_b",
4588 };
4589
4590 static const char * const hscif2_groups[] = {
4591         "hscif2_data_a",
4592         "hscif2_clk_a",
4593         "hscif2_ctrl_a",
4594         "hscif2_data_b",
4595         "hscif2_clk_b",
4596         "hscif2_ctrl_b",
4597         "hscif2_data_c",
4598         "hscif2_clk_c",
4599         "hscif2_ctrl_c",
4600 };
4601
4602 static const char * const hscif3_groups[] = {
4603         "hscif3_data_a",
4604         "hscif3_clk",
4605         "hscif3_ctrl",
4606         "hscif3_data_b",
4607         "hscif3_data_c",
4608         "hscif3_data_d",
4609 };
4610
4611 static const char * const hscif4_groups[] = {
4612         "hscif4_data_a",
4613         "hscif4_clk",
4614         "hscif4_ctrl",
4615         "hscif4_data_b",
4616 };
4617
4618 static const char * const i2c0_groups[] = {
4619         "i2c0",
4620 };
4621
4622 static const char * const i2c1_groups[] = {
4623         "i2c1_a",
4624         "i2c1_b",
4625 };
4626
4627 static const char * const i2c2_groups[] = {
4628         "i2c2_a",
4629         "i2c2_b",
4630 };
4631
4632 static const char * const i2c3_groups[] = {
4633         "i2c3",
4634 };
4635
4636 static const char * const i2c5_groups[] = {
4637         "i2c5",
4638 };
4639
4640 static const char * const i2c6_groups[] = {
4641         "i2c6_a",
4642         "i2c6_b",
4643         "i2c6_c",
4644 };
4645
4646 static const char * const intc_ex_groups[] = {
4647         "intc_ex_irq0",
4648         "intc_ex_irq1",
4649         "intc_ex_irq2",
4650         "intc_ex_irq3",
4651         "intc_ex_irq4",
4652         "intc_ex_irq5",
4653 };
4654
4655 static const char * const msiof0_groups[] = {
4656         "msiof0_clk",
4657         "msiof0_sync",
4658         "msiof0_ss1",
4659         "msiof0_ss2",
4660         "msiof0_txd",
4661         "msiof0_rxd",
4662 };
4663
4664 static const char * const msiof1_groups[] = {
4665         "msiof1_clk_a",
4666         "msiof1_sync_a",
4667         "msiof1_ss1_a",
4668         "msiof1_ss2_a",
4669         "msiof1_txd_a",
4670         "msiof1_rxd_a",
4671         "msiof1_clk_b",
4672         "msiof1_sync_b",
4673         "msiof1_ss1_b",
4674         "msiof1_ss2_b",
4675         "msiof1_txd_b",
4676         "msiof1_rxd_b",
4677         "msiof1_clk_c",
4678         "msiof1_sync_c",
4679         "msiof1_ss1_c",
4680         "msiof1_ss2_c",
4681         "msiof1_txd_c",
4682         "msiof1_rxd_c",
4683         "msiof1_clk_d",
4684         "msiof1_sync_d",
4685         "msiof1_ss1_d",
4686         "msiof1_ss2_d",
4687         "msiof1_txd_d",
4688         "msiof1_rxd_d",
4689         "msiof1_clk_e",
4690         "msiof1_sync_e",
4691         "msiof1_ss1_e",
4692         "msiof1_ss2_e",
4693         "msiof1_txd_e",
4694         "msiof1_rxd_e",
4695         "msiof1_clk_f",
4696         "msiof1_sync_f",
4697         "msiof1_ss1_f",
4698         "msiof1_ss2_f",
4699         "msiof1_txd_f",
4700         "msiof1_rxd_f",
4701         "msiof1_clk_g",
4702         "msiof1_sync_g",
4703         "msiof1_ss1_g",
4704         "msiof1_ss2_g",
4705         "msiof1_txd_g",
4706         "msiof1_rxd_g",
4707 };
4708
4709 static const char * const msiof2_groups[] = {
4710         "msiof2_clk_a",
4711         "msiof2_sync_a",
4712         "msiof2_ss1_a",
4713         "msiof2_ss2_a",
4714         "msiof2_txd_a",
4715         "msiof2_rxd_a",
4716         "msiof2_clk_b",
4717         "msiof2_sync_b",
4718         "msiof2_ss1_b",
4719         "msiof2_ss2_b",
4720         "msiof2_txd_b",
4721         "msiof2_rxd_b",
4722         "msiof2_clk_c",
4723         "msiof2_sync_c",
4724         "msiof2_ss1_c",
4725         "msiof2_ss2_c",
4726         "msiof2_txd_c",
4727         "msiof2_rxd_c",
4728         "msiof2_clk_d",
4729         "msiof2_sync_d",
4730         "msiof2_ss1_d",
4731         "msiof2_ss2_d",
4732         "msiof2_txd_d",
4733         "msiof2_rxd_d",
4734 };
4735
4736 static const char * const msiof3_groups[] = {
4737         "msiof3_clk_a",
4738         "msiof3_sync_a",
4739         "msiof3_ss1_a",
4740         "msiof3_ss2_a",
4741         "msiof3_txd_a",
4742         "msiof3_rxd_a",
4743         "msiof3_clk_b",
4744         "msiof3_sync_b",
4745         "msiof3_ss1_b",
4746         "msiof3_ss2_b",
4747         "msiof3_txd_b",
4748         "msiof3_rxd_b",
4749         "msiof3_clk_c",
4750         "msiof3_sync_c",
4751         "msiof3_txd_c",
4752         "msiof3_rxd_c",
4753         "msiof3_clk_d",
4754         "msiof3_sync_d",
4755         "msiof3_ss1_d",
4756         "msiof3_txd_d",
4757         "msiof3_rxd_d",
4758         "msiof3_clk_e",
4759         "msiof3_sync_e",
4760         "msiof3_ss1_e",
4761         "msiof3_ss2_e",
4762         "msiof3_txd_e",
4763         "msiof3_rxd_e",
4764 };
4765
4766 static const char * const pwm0_groups[] = {
4767         "pwm0",
4768 };
4769
4770 static const char * const pwm1_groups[] = {
4771         "pwm1_a",
4772         "pwm1_b",
4773 };
4774
4775 static const char * const pwm2_groups[] = {
4776         "pwm2_a",
4777         "pwm2_b",
4778 };
4779
4780 static const char * const pwm3_groups[] = {
4781         "pwm3_a",
4782         "pwm3_b",
4783 };
4784
4785 static const char * const pwm4_groups[] = {
4786         "pwm4_a",
4787         "pwm4_b",
4788 };
4789
4790 static const char * const pwm5_groups[] = {
4791         "pwm5_a",
4792         "pwm5_b",
4793 };
4794
4795 static const char * const pwm6_groups[] = {
4796         "pwm6_a",
4797         "pwm6_b",
4798 };
4799
4800 static const char * const scif0_groups[] = {
4801         "scif0_data",
4802         "scif0_clk",
4803         "scif0_ctrl",
4804 };
4805
4806 static const char * const scif1_groups[] = {
4807         "scif1_data_a",
4808         "scif1_clk",
4809         "scif1_ctrl",
4810         "scif1_data_b",
4811 };
4812
4813 static const char * const scif2_groups[] = {
4814         "scif2_data_a",
4815         "scif2_clk",
4816         "scif2_data_b",
4817 };
4818
4819 static const char * const scif3_groups[] = {
4820         "scif3_data_a",
4821         "scif3_clk",
4822         "scif3_ctrl",
4823         "scif3_data_b",
4824 };
4825
4826 static const char * const scif4_groups[] = {
4827         "scif4_data_a",
4828         "scif4_clk_a",
4829         "scif4_ctrl_a",
4830         "scif4_data_b",
4831         "scif4_clk_b",
4832         "scif4_ctrl_b",
4833         "scif4_data_c",
4834         "scif4_clk_c",
4835         "scif4_ctrl_c",
4836 };
4837
4838 static const char * const scif5_groups[] = {
4839         "scif5_data_a",
4840         "scif5_clk_a",
4841         "scif5_data_b",
4842         "scif5_clk_b",
4843 };
4844
4845 static const char * const scif_clk_groups[] = {
4846         "scif_clk_a",
4847         "scif_clk_b",
4848 };
4849
4850 static const char * const sdhi0_groups[] = {
4851         "sdhi0_data1",
4852         "sdhi0_data4",
4853         "sdhi0_ctrl",
4854         "sdhi0_cd",
4855         "sdhi0_wp",
4856 };
4857
4858 static const char * const sdhi1_groups[] = {
4859         "sdhi1_data1",
4860         "sdhi1_data4",
4861         "sdhi1_ctrl",
4862         "sdhi1_cd",
4863         "sdhi1_wp",
4864 };
4865
4866 static const char * const sdhi2_groups[] = {
4867         "sdhi2_data1",
4868         "sdhi2_data4",
4869         "sdhi2_data8",
4870         "sdhi2_ctrl",
4871         "sdhi2_cd_a",
4872         "sdhi2_wp_a",
4873         "sdhi2_cd_b",
4874         "sdhi2_wp_b",
4875         "sdhi2_ds",
4876 };
4877
4878 static const char * const sdhi3_groups[] = {
4879         "sdhi3_data1",
4880         "sdhi3_data4",
4881         "sdhi3_data8",
4882         "sdhi3_ctrl",
4883         "sdhi3_cd",
4884         "sdhi3_wp",
4885         "sdhi3_ds",
4886 };
4887
4888 static const char * const ssi_groups[] = {
4889         "ssi0_data",
4890         "ssi01239_ctrl",
4891         "ssi1_data_a",
4892         "ssi1_data_b",
4893         "ssi1_ctrl_a",
4894         "ssi1_ctrl_b",
4895         "ssi2_data_a",
4896         "ssi2_data_b",
4897         "ssi2_ctrl_a",
4898         "ssi2_ctrl_b",
4899         "ssi3_data",
4900         "ssi349_ctrl",
4901         "ssi4_data",
4902         "ssi4_ctrl",
4903         "ssi5_data",
4904         "ssi5_ctrl",
4905         "ssi6_data",
4906         "ssi6_ctrl",
4907         "ssi7_data",
4908         "ssi78_ctrl",
4909         "ssi8_data",
4910         "ssi9_data_a",
4911         "ssi9_data_b",
4912         "ssi9_ctrl_a",
4913         "ssi9_ctrl_b",
4914 };
4915
4916 static const char * const tmu_groups[] = {
4917         "tmu_tclk1_a",
4918         "tmu_tclk1_b",
4919         "tmu_tclk2_a",
4920         "tmu_tclk2_b",
4921 };
4922
4923 static const char * const usb0_groups[] = {
4924         "usb0",
4925 };
4926
4927 static const char * const usb1_groups[] = {
4928         "usb1",
4929 };
4930
4931 static const char * const usb30_groups[] = {
4932         "usb30",
4933 };
4934
4935 static const char * const vin4_groups[] = {
4936         "vin4_data8_a",
4937         "vin4_data10_a",
4938         "vin4_data12_a",
4939         "vin4_data16_a",
4940         "vin4_data18_a",
4941         "vin4_data20_a",
4942         "vin4_data24_a",
4943         "vin4_data8_b",
4944         "vin4_data10_b",
4945         "vin4_data12_b",
4946         "vin4_data16_b",
4947         "vin4_data18_b",
4948         "vin4_data20_b",
4949         "vin4_data24_b",
4950         "vin4_sync",
4951         "vin4_field",
4952         "vin4_clkenb",
4953         "vin4_clk",
4954 };
4955
4956 static const char * const vin5_groups[] = {
4957         "vin5_data8",
4958         "vin5_data10",
4959         "vin5_data12",
4960         "vin5_data16",
4961         "vin5_sync",
4962         "vin5_field",
4963         "vin5_clkenb",
4964         "vin5_clk",
4965 };
4966
4967 static const struct {
4968         struct sh_pfc_function common[49];
4969         struct sh_pfc_function automotive[4];
4970 } pinmux_functions = {
4971         .common = {
4972                 SH_PFC_FUNCTION(audio_clk),
4973                 SH_PFC_FUNCTION(avb),
4974                 SH_PFC_FUNCTION(can0),
4975                 SH_PFC_FUNCTION(can1),
4976                 SH_PFC_FUNCTION(can_clk),
4977                 SH_PFC_FUNCTION(canfd0),
4978                 SH_PFC_FUNCTION(canfd1),
4979                 SH_PFC_FUNCTION(du),
4980                 SH_PFC_FUNCTION(hscif0),
4981                 SH_PFC_FUNCTION(hscif1),
4982                 SH_PFC_FUNCTION(hscif2),
4983                 SH_PFC_FUNCTION(hscif3),
4984                 SH_PFC_FUNCTION(hscif4),
4985                 SH_PFC_FUNCTION(i2c0),
4986                 SH_PFC_FUNCTION(i2c1),
4987                 SH_PFC_FUNCTION(i2c2),
4988                 SH_PFC_FUNCTION(i2c3),
4989                 SH_PFC_FUNCTION(i2c5),
4990                 SH_PFC_FUNCTION(i2c6),
4991                 SH_PFC_FUNCTION(intc_ex),
4992                 SH_PFC_FUNCTION(msiof0),
4993                 SH_PFC_FUNCTION(msiof1),
4994                 SH_PFC_FUNCTION(msiof2),
4995                 SH_PFC_FUNCTION(msiof3),
4996                 SH_PFC_FUNCTION(pwm0),
4997                 SH_PFC_FUNCTION(pwm1),
4998                 SH_PFC_FUNCTION(pwm2),
4999                 SH_PFC_FUNCTION(pwm3),
5000                 SH_PFC_FUNCTION(pwm4),
5001                 SH_PFC_FUNCTION(pwm5),
5002                 SH_PFC_FUNCTION(pwm6),
5003                 SH_PFC_FUNCTION(scif0),
5004                 SH_PFC_FUNCTION(scif1),
5005                 SH_PFC_FUNCTION(scif2),
5006                 SH_PFC_FUNCTION(scif3),
5007                 SH_PFC_FUNCTION(scif4),
5008                 SH_PFC_FUNCTION(scif5),
5009                 SH_PFC_FUNCTION(scif_clk),
5010                 SH_PFC_FUNCTION(sdhi0),
5011                 SH_PFC_FUNCTION(sdhi1),
5012                 SH_PFC_FUNCTION(sdhi2),
5013                 SH_PFC_FUNCTION(sdhi3),
5014                 SH_PFC_FUNCTION(ssi),
5015                 SH_PFC_FUNCTION(tmu),
5016                 SH_PFC_FUNCTION(usb0),
5017                 SH_PFC_FUNCTION(usb1),
5018                 SH_PFC_FUNCTION(usb30),
5019                 SH_PFC_FUNCTION(vin4),
5020                 SH_PFC_FUNCTION(vin5),
5021         },
5022         .automotive = {
5023                 SH_PFC_FUNCTION(drif0),
5024                 SH_PFC_FUNCTION(drif1),
5025                 SH_PFC_FUNCTION(drif2),
5026                 SH_PFC_FUNCTION(drif3),
5027         }
5028 };
5029
5030 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5031 #define F_(x, y)        FN_##y
5032 #define FM(x)           FN_##x
5033         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5034                 0, 0,
5035                 0, 0,
5036                 0, 0,
5037                 0, 0,
5038                 0, 0,
5039                 0, 0,
5040                 0, 0,
5041                 0, 0,
5042                 0, 0,
5043                 0, 0,
5044                 0, 0,
5045                 0, 0,
5046                 0, 0,
5047                 0, 0,
5048                 0, 0,
5049                 0, 0,
5050                 GP_0_15_FN,     GPSR0_15,
5051                 GP_0_14_FN,     GPSR0_14,
5052                 GP_0_13_FN,     GPSR0_13,
5053                 GP_0_12_FN,     GPSR0_12,
5054                 GP_0_11_FN,     GPSR0_11,
5055                 GP_0_10_FN,     GPSR0_10,
5056                 GP_0_9_FN,      GPSR0_9,
5057                 GP_0_8_FN,      GPSR0_8,
5058                 GP_0_7_FN,      GPSR0_7,
5059                 GP_0_6_FN,      GPSR0_6,
5060                 GP_0_5_FN,      GPSR0_5,
5061                 GP_0_4_FN,      GPSR0_4,
5062                 GP_0_3_FN,      GPSR0_3,
5063                 GP_0_2_FN,      GPSR0_2,
5064                 GP_0_1_FN,      GPSR0_1,
5065                 GP_0_0_FN,      GPSR0_0, ))
5066         },
5067         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5068                 0, 0,
5069                 0, 0,
5070                 0, 0,
5071                 GP_1_28_FN,     GPSR1_28,
5072                 GP_1_27_FN,     GPSR1_27,
5073                 GP_1_26_FN,     GPSR1_26,
5074                 GP_1_25_FN,     GPSR1_25,
5075                 GP_1_24_FN,     GPSR1_24,
5076                 GP_1_23_FN,     GPSR1_23,
5077                 GP_1_22_FN,     GPSR1_22,
5078                 GP_1_21_FN,     GPSR1_21,
5079                 GP_1_20_FN,     GPSR1_20,
5080                 GP_1_19_FN,     GPSR1_19,
5081                 GP_1_18_FN,     GPSR1_18,
5082                 GP_1_17_FN,     GPSR1_17,
5083                 GP_1_16_FN,     GPSR1_16,
5084                 GP_1_15_FN,     GPSR1_15,
5085                 GP_1_14_FN,     GPSR1_14,
5086                 GP_1_13_FN,     GPSR1_13,
5087                 GP_1_12_FN,     GPSR1_12,
5088                 GP_1_11_FN,     GPSR1_11,
5089                 GP_1_10_FN,     GPSR1_10,
5090                 GP_1_9_FN,      GPSR1_9,
5091                 GP_1_8_FN,      GPSR1_8,
5092                 GP_1_7_FN,      GPSR1_7,
5093                 GP_1_6_FN,      GPSR1_6,
5094                 GP_1_5_FN,      GPSR1_5,
5095                 GP_1_4_FN,      GPSR1_4,
5096                 GP_1_3_FN,      GPSR1_3,
5097                 GP_1_2_FN,      GPSR1_2,
5098                 GP_1_1_FN,      GPSR1_1,
5099                 GP_1_0_FN,      GPSR1_0, ))
5100         },
5101         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5102                 0, 0,
5103                 0, 0,
5104                 0, 0,
5105                 0, 0,
5106                 0, 0,
5107                 0, 0,
5108                 0, 0,
5109                 0, 0,
5110                 0, 0,
5111                 0, 0,
5112                 0, 0,
5113                 0, 0,
5114                 0, 0,
5115                 0, 0,
5116                 0, 0,
5117                 0, 0,
5118                 0, 0,
5119                 GP_2_14_FN,     GPSR2_14,
5120                 GP_2_13_FN,     GPSR2_13,
5121                 GP_2_12_FN,     GPSR2_12,
5122                 GP_2_11_FN,     GPSR2_11,
5123                 GP_2_10_FN,     GPSR2_10,
5124                 GP_2_9_FN,      GPSR2_9,
5125                 GP_2_8_FN,      GPSR2_8,
5126                 GP_2_7_FN,      GPSR2_7,
5127                 GP_2_6_FN,      GPSR2_6,
5128                 GP_2_5_FN,      GPSR2_5,
5129                 GP_2_4_FN,      GPSR2_4,
5130                 GP_2_3_FN,      GPSR2_3,
5131                 GP_2_2_FN,      GPSR2_2,
5132                 GP_2_1_FN,      GPSR2_1,
5133                 GP_2_0_FN,      GPSR2_0, ))
5134         },
5135         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5136                 0, 0,
5137                 0, 0,
5138                 0, 0,
5139                 0, 0,
5140                 0, 0,
5141                 0, 0,
5142                 0, 0,
5143                 0, 0,
5144                 0, 0,
5145                 0, 0,
5146                 0, 0,
5147                 0, 0,
5148                 0, 0,
5149                 0, 0,
5150                 0, 0,
5151                 0, 0,
5152                 GP_3_15_FN,     GPSR3_15,
5153                 GP_3_14_FN,     GPSR3_14,
5154                 GP_3_13_FN,     GPSR3_13,
5155                 GP_3_12_FN,     GPSR3_12,
5156                 GP_3_11_FN,     GPSR3_11,
5157                 GP_3_10_FN,     GPSR3_10,
5158                 GP_3_9_FN,      GPSR3_9,
5159                 GP_3_8_FN,      GPSR3_8,
5160                 GP_3_7_FN,      GPSR3_7,
5161                 GP_3_6_FN,      GPSR3_6,
5162                 GP_3_5_FN,      GPSR3_5,
5163                 GP_3_4_FN,      GPSR3_4,
5164                 GP_3_3_FN,      GPSR3_3,
5165                 GP_3_2_FN,      GPSR3_2,
5166                 GP_3_1_FN,      GPSR3_1,
5167                 GP_3_0_FN,      GPSR3_0, ))
5168         },
5169         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5170                 0, 0,
5171                 0, 0,
5172                 0, 0,
5173                 0, 0,
5174                 0, 0,
5175                 0, 0,
5176                 0, 0,
5177                 0, 0,
5178                 0, 0,
5179                 0, 0,
5180                 0, 0,
5181                 0, 0,
5182                 0, 0,
5183                 0, 0,
5184                 GP_4_17_FN,     GPSR4_17,
5185                 GP_4_16_FN,     GPSR4_16,
5186                 GP_4_15_FN,     GPSR4_15,
5187                 GP_4_14_FN,     GPSR4_14,
5188                 GP_4_13_FN,     GPSR4_13,
5189                 GP_4_12_FN,     GPSR4_12,
5190                 GP_4_11_FN,     GPSR4_11,
5191                 GP_4_10_FN,     GPSR4_10,
5192                 GP_4_9_FN,      GPSR4_9,
5193                 GP_4_8_FN,      GPSR4_8,
5194                 GP_4_7_FN,      GPSR4_7,
5195                 GP_4_6_FN,      GPSR4_6,
5196                 GP_4_5_FN,      GPSR4_5,
5197                 GP_4_4_FN,      GPSR4_4,
5198                 GP_4_3_FN,      GPSR4_3,
5199                 GP_4_2_FN,      GPSR4_2,
5200                 GP_4_1_FN,      GPSR4_1,
5201                 GP_4_0_FN,      GPSR4_0, ))
5202         },
5203         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5204                 0, 0,
5205                 0, 0,
5206                 0, 0,
5207                 0, 0,
5208                 0, 0,
5209                 0, 0,
5210                 GP_5_25_FN,     GPSR5_25,
5211                 GP_5_24_FN,     GPSR5_24,
5212                 GP_5_23_FN,     GPSR5_23,
5213                 GP_5_22_FN,     GPSR5_22,
5214                 GP_5_21_FN,     GPSR5_21,
5215                 GP_5_20_FN,     GPSR5_20,
5216                 GP_5_19_FN,     GPSR5_19,
5217                 GP_5_18_FN,     GPSR5_18,
5218                 GP_5_17_FN,     GPSR5_17,
5219                 GP_5_16_FN,     GPSR5_16,
5220                 GP_5_15_FN,     GPSR5_15,
5221                 GP_5_14_FN,     GPSR5_14,
5222                 GP_5_13_FN,     GPSR5_13,
5223                 GP_5_12_FN,     GPSR5_12,
5224                 GP_5_11_FN,     GPSR5_11,
5225                 GP_5_10_FN,     GPSR5_10,
5226                 GP_5_9_FN,      GPSR5_9,
5227                 GP_5_8_FN,      GPSR5_8,
5228                 GP_5_7_FN,      GPSR5_7,
5229                 GP_5_6_FN,      GPSR5_6,
5230                 GP_5_5_FN,      GPSR5_5,
5231                 GP_5_4_FN,      GPSR5_4,
5232                 GP_5_3_FN,      GPSR5_3,
5233                 GP_5_2_FN,      GPSR5_2,
5234                 GP_5_1_FN,      GPSR5_1,
5235                 GP_5_0_FN,      GPSR5_0, ))
5236         },
5237         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5238                 GP_6_31_FN,     GPSR6_31,
5239                 GP_6_30_FN,     GPSR6_30,
5240                 GP_6_29_FN,     GPSR6_29,
5241                 GP_6_28_FN,     GPSR6_28,
5242                 GP_6_27_FN,     GPSR6_27,
5243                 GP_6_26_FN,     GPSR6_26,
5244                 GP_6_25_FN,     GPSR6_25,
5245                 GP_6_24_FN,     GPSR6_24,
5246                 GP_6_23_FN,     GPSR6_23,
5247                 GP_6_22_FN,     GPSR6_22,
5248                 GP_6_21_FN,     GPSR6_21,
5249                 GP_6_20_FN,     GPSR6_20,
5250                 GP_6_19_FN,     GPSR6_19,
5251                 GP_6_18_FN,     GPSR6_18,
5252                 GP_6_17_FN,     GPSR6_17,
5253                 GP_6_16_FN,     GPSR6_16,
5254                 GP_6_15_FN,     GPSR6_15,
5255                 GP_6_14_FN,     GPSR6_14,
5256                 GP_6_13_FN,     GPSR6_13,
5257                 GP_6_12_FN,     GPSR6_12,
5258                 GP_6_11_FN,     GPSR6_11,
5259                 GP_6_10_FN,     GPSR6_10,
5260                 GP_6_9_FN,      GPSR6_9,
5261                 GP_6_8_FN,      GPSR6_8,
5262                 GP_6_7_FN,      GPSR6_7,
5263                 GP_6_6_FN,      GPSR6_6,
5264                 GP_6_5_FN,      GPSR6_5,
5265                 GP_6_4_FN,      GPSR6_4,
5266                 GP_6_3_FN,      GPSR6_3,
5267                 GP_6_2_FN,      GPSR6_2,
5268                 GP_6_1_FN,      GPSR6_1,
5269                 GP_6_0_FN,      GPSR6_0, ))
5270         },
5271         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5272                 0, 0,
5273                 0, 0,
5274                 0, 0,
5275                 0, 0,
5276                 0, 0,
5277                 0, 0,
5278                 0, 0,
5279                 0, 0,
5280                 0, 0,
5281                 0, 0,
5282                 0, 0,
5283                 0, 0,
5284                 0, 0,
5285                 0, 0,
5286                 0, 0,
5287                 0, 0,
5288                 0, 0,
5289                 0, 0,
5290                 0, 0,
5291                 0, 0,
5292                 0, 0,
5293                 0, 0,
5294                 0, 0,
5295                 0, 0,
5296                 0, 0,
5297                 0, 0,
5298                 0, 0,
5299                 0, 0,
5300                 GP_7_3_FN, GPSR7_3,
5301                 GP_7_2_FN, GPSR7_2,
5302                 GP_7_1_FN, GPSR7_1,
5303                 GP_7_0_FN, GPSR7_0, ))
5304         },
5305 #undef F_
5306 #undef FM
5307
5308 #define F_(x, y)        x,
5309 #define FM(x)           FN_##x,
5310         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5311                 IP0_31_28
5312                 IP0_27_24
5313                 IP0_23_20
5314                 IP0_19_16
5315                 IP0_15_12
5316                 IP0_11_8
5317                 IP0_7_4
5318                 IP0_3_0 ))
5319         },
5320         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5321                 IP1_31_28
5322                 IP1_27_24
5323                 IP1_23_20
5324                 IP1_19_16
5325                 IP1_15_12
5326                 IP1_11_8
5327                 IP1_7_4
5328                 IP1_3_0 ))
5329         },
5330         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5331                 IP2_31_28
5332                 IP2_27_24
5333                 IP2_23_20
5334                 IP2_19_16
5335                 IP2_15_12
5336                 IP2_11_8
5337                 IP2_7_4
5338                 IP2_3_0 ))
5339         },
5340         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5341                 IP3_31_28
5342                 IP3_27_24
5343                 IP3_23_20
5344                 IP3_19_16
5345                 IP3_15_12
5346                 IP3_11_8
5347                 IP3_7_4
5348                 IP3_3_0 ))
5349         },
5350         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5351                 IP4_31_28
5352                 IP4_27_24
5353                 IP4_23_20
5354                 IP4_19_16
5355                 IP4_15_12
5356                 IP4_11_8
5357                 IP4_7_4
5358                 IP4_3_0 ))
5359         },
5360         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5361                 IP5_31_28
5362                 IP5_27_24
5363                 IP5_23_20
5364                 IP5_19_16
5365                 IP5_15_12
5366                 IP5_11_8
5367                 IP5_7_4
5368                 IP5_3_0 ))
5369         },
5370         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5371                 IP6_31_28
5372                 IP6_27_24
5373                 IP6_23_20
5374                 IP6_19_16
5375                 IP6_15_12
5376                 IP6_11_8
5377                 IP6_7_4
5378                 IP6_3_0 ))
5379         },
5380         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5381                 IP7_31_28
5382                 IP7_27_24
5383                 IP7_23_20
5384                 IP7_19_16
5385                 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5386                 IP7_11_8
5387                 IP7_7_4
5388                 IP7_3_0 ))
5389         },
5390         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5391                 IP8_31_28
5392                 IP8_27_24
5393                 IP8_23_20
5394                 IP8_19_16
5395                 IP8_15_12
5396                 IP8_11_8
5397                 IP8_7_4
5398                 IP8_3_0 ))
5399         },
5400         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5401                 IP9_31_28
5402                 IP9_27_24
5403                 IP9_23_20
5404                 IP9_19_16
5405                 IP9_15_12
5406                 IP9_11_8
5407                 IP9_7_4
5408                 IP9_3_0 ))
5409         },
5410         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5411                 IP10_31_28
5412                 IP10_27_24
5413                 IP10_23_20
5414                 IP10_19_16
5415                 IP10_15_12
5416                 IP10_11_8
5417                 IP10_7_4
5418                 IP10_3_0 ))
5419         },
5420         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5421                 IP11_31_28
5422                 IP11_27_24
5423                 IP11_23_20
5424                 IP11_19_16
5425                 IP11_15_12
5426                 IP11_11_8
5427                 IP11_7_4
5428                 IP11_3_0 ))
5429         },
5430         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5431                 IP12_31_28
5432                 IP12_27_24
5433                 IP12_23_20
5434                 IP12_19_16
5435                 IP12_15_12
5436                 IP12_11_8
5437                 IP12_7_4
5438                 IP12_3_0 ))
5439         },
5440         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5441                 IP13_31_28
5442                 IP13_27_24
5443                 IP13_23_20
5444                 IP13_19_16
5445                 IP13_15_12
5446                 IP13_11_8
5447                 IP13_7_4
5448                 IP13_3_0 ))
5449         },
5450         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5451                 IP14_31_28
5452                 IP14_27_24
5453                 IP14_23_20
5454                 IP14_19_16
5455                 IP14_15_12
5456                 IP14_11_8
5457                 IP14_7_4
5458                 IP14_3_0 ))
5459         },
5460         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5461                 IP15_31_28
5462                 IP15_27_24
5463                 IP15_23_20
5464                 IP15_19_16
5465                 IP15_15_12
5466                 IP15_11_8
5467                 IP15_7_4
5468                 IP15_3_0 ))
5469         },
5470         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5471                 IP16_31_28
5472                 IP16_27_24
5473                 IP16_23_20
5474                 IP16_19_16
5475                 IP16_15_12
5476                 IP16_11_8
5477                 IP16_7_4
5478                 IP16_3_0 ))
5479         },
5480         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5481                 IP17_31_28
5482                 IP17_27_24
5483                 IP17_23_20
5484                 IP17_19_16
5485                 IP17_15_12
5486                 IP17_11_8
5487                 IP17_7_4
5488                 IP17_3_0 ))
5489         },
5490         { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
5491                 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5492                 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5493                 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5494                 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5495                 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5496                 /* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5497                 IP18_7_4
5498                 IP18_3_0 ))
5499         },
5500 #undef F_
5501 #undef FM
5502
5503 #define F_(x, y)        x,
5504 #define FM(x)           FN_##x,
5505         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5506                              GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5507                                    1, 1, 1, 2, 2, 1, 2, 3),
5508                              GROUP(
5509                 MOD_SEL0_31_30_29
5510                 MOD_SEL0_28_27
5511                 MOD_SEL0_26_25_24
5512                 MOD_SEL0_23
5513                 MOD_SEL0_22
5514                 MOD_SEL0_21
5515                 MOD_SEL0_20
5516                 MOD_SEL0_19
5517                 MOD_SEL0_18_17
5518                 MOD_SEL0_16
5519                 0, 0, /* RESERVED 15 */
5520                 MOD_SEL0_14_13
5521                 MOD_SEL0_12
5522                 MOD_SEL0_11
5523                 MOD_SEL0_10
5524                 MOD_SEL0_9_8
5525                 MOD_SEL0_7_6
5526                 MOD_SEL0_5
5527                 MOD_SEL0_4_3
5528                 /* RESERVED 2, 1, 0 */
5529                 0, 0, 0, 0, 0, 0, 0, 0 ))
5530         },
5531         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5532                              GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5533                                    1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5534                              GROUP(
5535                 MOD_SEL1_31_30
5536                 MOD_SEL1_29_28_27
5537                 MOD_SEL1_26
5538                 MOD_SEL1_25_24
5539                 MOD_SEL1_23_22_21
5540                 MOD_SEL1_20
5541                 MOD_SEL1_19
5542                 MOD_SEL1_18_17
5543                 MOD_SEL1_16
5544                 MOD_SEL1_15_14
5545                 MOD_SEL1_13
5546                 MOD_SEL1_12
5547                 MOD_SEL1_11
5548                 MOD_SEL1_10
5549                 MOD_SEL1_9
5550                 0, 0, 0, 0, /* RESERVED 8, 7 */
5551                 MOD_SEL1_6
5552                 MOD_SEL1_5
5553                 MOD_SEL1_4
5554                 MOD_SEL1_3
5555                 MOD_SEL1_2
5556                 MOD_SEL1_1
5557                 MOD_SEL1_0 ))
5558         },
5559         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5560                              GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5561                                    1, 4, 4, 4, 3, 1),
5562                              GROUP(
5563                 MOD_SEL2_31
5564                 MOD_SEL2_30
5565                 MOD_SEL2_29
5566                 MOD_SEL2_28_27
5567                 MOD_SEL2_26
5568                 MOD_SEL2_25_24_23
5569                 MOD_SEL2_22
5570                 MOD_SEL2_21
5571                 MOD_SEL2_20
5572                 MOD_SEL2_19
5573                 MOD_SEL2_18
5574                 MOD_SEL2_17
5575                 /* RESERVED 16 */
5576                 0, 0,
5577                 /* RESERVED 15, 14, 13, 12 */
5578                 0, 0, 0, 0, 0, 0, 0, 0,
5579                 0, 0, 0, 0, 0, 0, 0, 0,
5580                 /* RESERVED 11, 10, 9, 8 */
5581                 0, 0, 0, 0, 0, 0, 0, 0,
5582                 0, 0, 0, 0, 0, 0, 0, 0,
5583                 /* RESERVED 7, 6, 5, 4 */
5584                 0, 0, 0, 0, 0, 0, 0, 0,
5585                 0, 0, 0, 0, 0, 0, 0, 0,
5586                 /* RESERVED 3, 2, 1 */
5587                 0, 0, 0, 0, 0, 0, 0, 0,
5588                 MOD_SEL2_0 ))
5589         },
5590         { },
5591 };
5592
5593 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5594         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5595                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5596                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5597                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5598                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5599                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5600                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5601                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5602                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5603         } },
5604         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5605                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5606                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5607                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5608                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5609                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5610                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5611                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5612                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5613         } },
5614         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5615                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5616                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5617                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5618                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5619                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5620                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5621                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5622                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5623         } },
5624         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5625                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5626                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5627                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5628                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5629                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5630                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5631                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5632                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5633         } },
5634         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5635                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5636                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5637                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5638                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5639                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5640                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5641                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5642                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5643         } },
5644         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5645                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5646                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5647                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5648                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5649                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5650                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5651                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5652                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5653         } },
5654         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5655                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5656                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5657                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5658                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5659                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5660                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5661                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5662                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5663         } },
5664         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5665                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5666                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5667                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5668                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5669                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5670                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5671                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5672                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5673         } },
5674         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5675                 { RCAR_GP_PIN(1, 28), 28, 3 },  /* CLKOUT */
5676                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5677                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5678                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5679                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5680                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5681                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5682                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5683         } },
5684         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5685                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5686                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5687                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5688                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5689                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5690                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5691                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5692                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5693         } },
5694         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5695                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5696                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5697                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5698                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5699                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5700                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5701                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5702                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5703         } },
5704         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5705                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5706                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5707                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5708                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5709                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* GP7_02 */
5710                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* GP7_03 */
5711                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5712                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5713         } },
5714         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5715                 { PIN_A_NUMBER('R', 8),  28, 2 },       /* DU_DOTCLKIN2 */
5716                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST */
5717                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5718         } },
5719         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5720                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5721                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5722                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5723                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5724                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5725                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5726                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5727                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5728         } },
5729         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5730                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5731                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5732                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5733                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5734                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5735                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5736                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5737                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5738         } },
5739         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5740                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5741                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5742                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5743                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5744                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5745                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5746                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5747                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5748         } },
5749         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5750                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5751                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5752                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5753                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5754                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5755                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5756                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5757                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5758         } },
5759         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5760                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5761                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5762                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5763                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5764                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5765                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5766                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5767                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5768         } },
5769         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5770                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0 */
5771                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5772                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5773                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5774                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1 */
5775                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5776                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5777                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5778         } },
5779         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5780                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5781                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5782                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5783                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5784                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5785                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5786                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5787                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5788         } },
5789         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5790                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5791                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5792                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5793                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5794                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5795                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5796                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5797                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5798         } },
5799         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5800                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5801                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5802                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5803                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5804                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5805                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5806                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5807                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5808         } },
5809         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5810                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5811                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5812                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5813                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5814                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5815                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5816                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5817                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5818         } },
5819         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5820                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5821                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5822                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5823                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5824                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5825                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5826                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5827                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5828         } },
5829         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5830                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5831                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5832                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5833                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5834                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5835                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* GP6_30 */
5836                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* GP6_31 */
5837         } },
5838         { },
5839 };
5840
5841 enum ioctrl_regs {
5842         POCCTRL,
5843         TDSELCTRL,
5844 };
5845
5846 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5847         [POCCTRL] = { 0xe6060380, },
5848         [TDSELCTRL] = { 0xe60603c0, },
5849         { /* sentinel */ },
5850 };
5851
5852 static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5853 {
5854         int bit = -EINVAL;
5855
5856         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5857
5858         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5859                 bit = pin & 0x1f;
5860
5861         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5862                 bit = (pin & 0x1f) + 12;
5863
5864         return bit;
5865 }
5866
5867 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5868         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5869                 [ 0] = PIN_NUMBER('W', 3),      /* QSPI0_SPCLK */
5870                 [ 1] = PIN_A_NUMBER('C', 5),    /* QSPI0_MOSI_IO0 */
5871                 [ 2] = PIN_A_NUMBER('B', 4),    /* QSPI0_MISO_IO1 */
5872                 [ 3] = PIN_NUMBER('Y', 6),      /* QSPI0_IO2 */
5873                 [ 4] = PIN_A_NUMBER('B', 6),    /* QSPI0_IO3 */
5874                 [ 5] = PIN_NUMBER('Y', 3),      /* QSPI0_SSL */
5875                 [ 6] = PIN_NUMBER('V', 3),      /* QSPI1_SPCLK */
5876                 [ 7] = PIN_A_NUMBER('C', 7),    /* QSPI1_MOSI_IO0 */
5877                 [ 8] = PIN_A_NUMBER('E', 5),    /* QSPI1_MISO_IO1 */
5878                 [ 9] = PIN_A_NUMBER('E', 4),    /* QSPI1_IO2 */
5879                 [10] = PIN_A_NUMBER('C', 3),    /* QSPI1_IO3 */
5880                 [11] = PIN_NUMBER('V', 5),      /* QSPI1_SSL */
5881                 [12] = PIN_NUMBER('Y', 7),      /* RPC_INT# */
5882                 [13] = PIN_NUMBER('V', 6),      /* RPC_WP# */
5883                 [14] = PIN_NUMBER('V', 7),      /* RPC_RESET# */
5884                 [15] = PIN_NUMBER('A', 16),     /* AVB_RX_CTL */
5885                 [16] = PIN_NUMBER('B', 19),     /* AVB_RXC */
5886                 [17] = PIN_NUMBER('A', 13),     /* AVB_RD0 */
5887                 [18] = PIN_NUMBER('B', 13),     /* AVB_RD1 */
5888                 [19] = PIN_NUMBER('A', 14),     /* AVB_RD2 */
5889                 [20] = PIN_NUMBER('B', 14),     /* AVB_RD3 */
5890                 [21] = PIN_NUMBER('A', 8),      /* AVB_TX_CTL */
5891                 [22] = PIN_NUMBER('A', 19),     /* AVB_TXC */
5892                 [23] = PIN_NUMBER('A', 18),     /* AVB_TD0 */
5893                 [24] = PIN_NUMBER('B', 18),     /* AVB_TD1 */
5894                 [25] = PIN_NUMBER('A', 17),     /* AVB_TD2 */
5895                 [26] = PIN_NUMBER('B', 17),     /* AVB_TD3 */
5896                 [27] = PIN_NUMBER('A', 12),     /* AVB_TXCREFCLK */
5897                 [28] = PIN_NUMBER('A', 9),      /* AVB_MDIO */
5898                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
5899                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
5900                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
5901         } },
5902         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5903                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
5904                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
5905                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
5906                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
5907                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
5908                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
5909                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
5910                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
5911                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
5912                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
5913                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
5914                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
5915                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
5916                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
5917                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
5918                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
5919                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
5920                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
5921                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
5922                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
5923                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
5924                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
5925                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
5926                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
5927                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
5928                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
5929                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
5930                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
5931                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
5932                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
5933                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
5934                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
5935         } },
5936         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5937                 [ 0] = RCAR_GP_PIN(1, 28),      /* CLKOUT */
5938                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
5939                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N */
5940                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
5941                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
5942                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
5943                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
5944                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
5945                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
5946                 [ 9] = PIN_NUMBER('C', 1),      /* PRESETOUT# */
5947                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
5948                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
5949                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
5950                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
5951                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
5952                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
5953                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
5954                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
5955                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
5956                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
5957                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
5958                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
5959                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
5960                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
5961                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
5962                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
5963                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
5964                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
5965                 [28] = RCAR_GP_PIN(7,  2),      /* GP7_02 */
5966                 [29] = RCAR_GP_PIN(7,  3),      /* GP7_03 */
5967                 [30] = PIN_A_NUMBER('P', 7),    /* DU_DOTCLKIN0 */
5968                 [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
5969         } },
5970         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5971                 [ 0] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN2 */
5972                 [ 1] = PIN_NONE,
5973                 [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST */
5974                 [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
5975                 [ 4] = PIN_A_NUMBER('R', 26),   /* TRST# */
5976                 [ 5] = PIN_A_NUMBER('T', 27),   /* TCK */
5977                 [ 6] = PIN_A_NUMBER('R', 30),   /* TMS */
5978                 [ 7] = PIN_A_NUMBER('R', 29),   /* TDI */
5979                 [ 8] = PIN_NONE,
5980                 [ 9] = PIN_A_NUMBER('T', 30),   /* ASEBRK */
5981                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
5982                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
5983                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
5984                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
5985                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
5986                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
5987                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
5988                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
5989                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
5990                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
5991                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
5992                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
5993                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
5994                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
5995                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
5996                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
5997                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
5998                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
5999                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
6000                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
6001                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
6002                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
6003         } },
6004         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6005                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
6006                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
6007                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
6008                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
6009                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
6010                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
6011                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
6012                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
6013                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
6014                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
6015                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
6016                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
6017                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
6018                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
6019                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
6020                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
6021                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N */
6022                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
6023                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
6024                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
6025                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N */
6026                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
6027                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
6028                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
6029                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
6030                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
6031                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
6032                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
6033                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
6034                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
6035                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
6036                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
6037         } },
6038         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6039                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
6040                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
6041                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
6042                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
6043                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
6044                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
6045                 [ 6] = PIN_NUMBER('H', 37),     /* MLB_REF */
6046                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
6047                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
6048                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
6049                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
6050                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
6051                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
6052                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
6053                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
6054                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
6055                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
6056                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
6057                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
6058                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
6059                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
6060                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
6061                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
6062                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
6063                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
6064                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
6065                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
6066                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
6067                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
6068                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
6069                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
6070                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
6071         } },
6072         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6073                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
6074                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
6075                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
6076                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
6077                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
6078                 [ 5] = RCAR_GP_PIN(6, 30),      /* GP6_30 */
6079                 [ 6] = RCAR_GP_PIN(6, 31),      /* GP6_31 */
6080                 [ 7] = PIN_NONE,
6081                 [ 8] = PIN_NONE,
6082                 [ 9] = PIN_NONE,
6083                 [10] = PIN_NONE,
6084                 [11] = PIN_NONE,
6085                 [12] = PIN_NONE,
6086                 [13] = PIN_NONE,
6087                 [14] = PIN_NONE,
6088                 [15] = PIN_NONE,
6089                 [16] = PIN_NONE,
6090                 [17] = PIN_NONE,
6091                 [18] = PIN_NONE,
6092                 [19] = PIN_NONE,
6093                 [20] = PIN_NONE,
6094                 [21] = PIN_NONE,
6095                 [22] = PIN_NONE,
6096                 [23] = PIN_NONE,
6097                 [24] = PIN_NONE,
6098                 [25] = PIN_NONE,
6099                 [26] = PIN_NONE,
6100                 [27] = PIN_NONE,
6101                 [28] = PIN_NONE,
6102                 [29] = PIN_NONE,
6103                 [30] = PIN_NONE,
6104                 [31] = PIN_NONE,
6105         } },
6106         { /* sentinel */ },
6107 };
6108
6109 static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
6110                                             unsigned int pin)
6111 {
6112         const struct pinmux_bias_reg *reg;
6113         unsigned int bit;
6114
6115         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6116         if (!reg)
6117                 return PIN_CONFIG_BIAS_DISABLE;
6118
6119         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6120                 return PIN_CONFIG_BIAS_DISABLE;
6121         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6122                 return PIN_CONFIG_BIAS_PULL_UP;
6123         else
6124                 return PIN_CONFIG_BIAS_PULL_DOWN;
6125 }
6126
6127 static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6128                                    unsigned int bias)
6129 {
6130         const struct pinmux_bias_reg *reg;
6131         u32 enable, updown;
6132         unsigned int bit;
6133
6134         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6135         if (!reg)
6136                 return;
6137
6138         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6139         if (bias != PIN_CONFIG_BIAS_DISABLE)
6140                 enable |= BIT(bit);
6141
6142         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6143         if (bias == PIN_CONFIG_BIAS_PULL_UP)
6144                 updown |= BIT(bit);
6145
6146         sh_pfc_write(pfc, reg->pud, updown);
6147         sh_pfc_write(pfc, reg->puen, enable);
6148 }
6149
6150 static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
6151         .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
6152         .get_bias = r8a7796_pinmux_get_bias,
6153         .set_bias = r8a7796_pinmux_set_bias,
6154 };
6155
6156 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
6157 const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
6158         .name = "r8a774a1_pfc",
6159         .ops = &r8a7796_pinmux_ops,
6160         .unlock_reg = 0xe6060000, /* PMMR */
6161
6162         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6163
6164         .pins = pinmux_pins,
6165         .nr_pins = ARRAY_SIZE(pinmux_pins),
6166         .groups = pinmux_groups.common,
6167         .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6168         .functions = pinmux_functions.common,
6169         .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6170
6171         .cfg_regs = pinmux_config_regs,
6172         .drive_regs = pinmux_drive_regs,
6173         .bias_regs = pinmux_bias_regs,
6174         .ioctrl_regs = pinmux_ioctrl_regs,
6175
6176         .pinmux_data = pinmux_data,
6177         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6178 };
6179 #endif
6180
6181 #ifdef CONFIG_PINCTRL_PFC_R8A7796
6182 const struct sh_pfc_soc_info r8a7796_pinmux_info = {
6183         .name = "r8a77960_pfc",
6184         .ops = &r8a7796_pinmux_ops,
6185         .unlock_reg = 0xe6060000, /* PMMR */
6186
6187         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6188
6189         .pins = pinmux_pins,
6190         .nr_pins = ARRAY_SIZE(pinmux_pins),
6191         .groups = pinmux_groups.common,
6192         .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6193                 ARRAY_SIZE(pinmux_groups.automotive),
6194         .functions = pinmux_functions.common,
6195         .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6196                 ARRAY_SIZE(pinmux_functions.automotive),
6197
6198         .cfg_regs = pinmux_config_regs,
6199         .drive_regs = pinmux_drive_regs,
6200         .bias_regs = pinmux_bias_regs,
6201         .ioctrl_regs = pinmux_ioctrl_regs,
6202
6203         .pinmux_data = pinmux_data,
6204         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6205 };
6206 #endif