1 // SPDX-License-Identifier: GPL-2.0
3 * R8A7795 ES2.0+ processor support - PFC hardware block.
5 * Copyright (C) 2015-2016 Renesas Electronics Corporation
11 #include <dm/pinctrl.h>
12 #include <linux/kernel.h>
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
17 SH_PFC_PIN_CFG_PULL_UP | \
18 SH_PFC_PIN_CFG_PULL_DOWN)
20 #define CPU_ALL_PORT(fn, sfx) \
21 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
30 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
34 * F_() : just information
35 * FM() : macro for FN_xxx / xxx_MARK
39 #define GPSR0_15 F_(D15, IP7_11_8)
40 #define GPSR0_14 F_(D14, IP7_7_4)
41 #define GPSR0_13 F_(D13, IP7_3_0)
42 #define GPSR0_12 F_(D12, IP6_31_28)
43 #define GPSR0_11 F_(D11, IP6_27_24)
44 #define GPSR0_10 F_(D10, IP6_23_20)
45 #define GPSR0_9 F_(D9, IP6_19_16)
46 #define GPSR0_8 F_(D8, IP6_15_12)
47 #define GPSR0_7 F_(D7, IP6_11_8)
48 #define GPSR0_6 F_(D6, IP6_7_4)
49 #define GPSR0_5 F_(D5, IP6_3_0)
50 #define GPSR0_4 F_(D4, IP5_31_28)
51 #define GPSR0_3 F_(D3, IP5_27_24)
52 #define GPSR0_2 F_(D2, IP5_23_20)
53 #define GPSR0_1 F_(D1, IP5_19_16)
54 #define GPSR0_0 F_(D0, IP5_15_12)
57 #define GPSR1_28 FM(CLKOUT)
58 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
59 #define GPSR1_26 F_(WE1_N, IP5_7_4)
60 #define GPSR1_25 F_(WE0_N, IP5_3_0)
61 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
62 #define GPSR1_23 F_(RD_N, IP4_27_24)
63 #define GPSR1_22 F_(BS_N, IP4_23_20)
64 #define GPSR1_21 F_(CS1_N, IP4_19_16)
65 #define GPSR1_20 F_(CS0_N, IP4_15_12)
66 #define GPSR1_19 F_(A19, IP4_11_8)
67 #define GPSR1_18 F_(A18, IP4_7_4)
68 #define GPSR1_17 F_(A17, IP4_3_0)
69 #define GPSR1_16 F_(A16, IP3_31_28)
70 #define GPSR1_15 F_(A15, IP3_27_24)
71 #define GPSR1_14 F_(A14, IP3_23_20)
72 #define GPSR1_13 F_(A13, IP3_19_16)
73 #define GPSR1_12 F_(A12, IP3_15_12)
74 #define GPSR1_11 F_(A11, IP3_11_8)
75 #define GPSR1_10 F_(A10, IP3_7_4)
76 #define GPSR1_9 F_(A9, IP3_3_0)
77 #define GPSR1_8 F_(A8, IP2_31_28)
78 #define GPSR1_7 F_(A7, IP2_27_24)
79 #define GPSR1_6 F_(A6, IP2_23_20)
80 #define GPSR1_5 F_(A5, IP2_19_16)
81 #define GPSR1_4 F_(A4, IP2_15_12)
82 #define GPSR1_3 F_(A3, IP2_11_8)
83 #define GPSR1_2 F_(A2, IP2_7_4)
84 #define GPSR1_1 F_(A1, IP2_3_0)
85 #define GPSR1_0 F_(A0, IP1_31_28)
88 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
89 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
90 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
91 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
92 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
93 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
94 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
95 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
96 #define GPSR2_6 F_(PWM0, IP1_19_16)
97 #define GPSR2_5 F_(IRQ5, IP1_15_12)
98 #define GPSR2_4 F_(IRQ4, IP1_11_8)
99 #define GPSR2_3 F_(IRQ3, IP1_7_4)
100 #define GPSR2_2 F_(IRQ2, IP1_3_0)
101 #define GPSR2_1 F_(IRQ1, IP0_31_28)
102 #define GPSR2_0 F_(IRQ0, IP0_27_24)
105 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
106 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
107 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
108 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
109 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
110 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
111 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
112 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
113 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
114 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
115 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
116 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
117 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
118 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
119 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
120 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
123 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
124 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
125 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
126 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
127 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
128 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
129 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
130 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
131 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
132 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
133 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
134 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
135 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
136 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
137 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
138 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
139 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
140 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
143 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
144 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
145 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
146 #define GPSR5_22 FM(MSIOF0_RXD)
147 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
148 #define GPSR5_20 FM(MSIOF0_TXD)
149 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
150 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
151 #define GPSR5_17 FM(MSIOF0_SCK)
152 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
153 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
154 #define GPSR5_14 F_(HTX0, IP13_19_16)
155 #define GPSR5_13 F_(HRX0, IP13_15_12)
156 #define GPSR5_12 F_(HSCK0, IP13_11_8)
157 #define GPSR5_11 F_(RX2_A, IP13_7_4)
158 #define GPSR5_10 F_(TX2_A, IP13_3_0)
159 #define GPSR5_9 F_(SCK2, IP12_31_28)
160 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
161 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
162 #define GPSR5_6 F_(TX1_A, IP12_19_16)
163 #define GPSR5_5 F_(RX1_A, IP12_15_12)
164 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
165 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
166 #define GPSR5_2 F_(TX0, IP12_3_0)
167 #define GPSR5_1 F_(RX0, IP11_31_28)
168 #define GPSR5_0 F_(SCK0, IP11_27_24)
171 #define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
172 #define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
173 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
174 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
175 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
176 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
177 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
178 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
179 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
180 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
181 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
182 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
183 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
184 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
185 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
186 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
187 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
188 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
189 #define GPSR6_13 FM(SSI_SDATA5)
190 #define GPSR6_12 FM(SSI_WS5)
191 #define GPSR6_11 FM(SSI_SCK5)
192 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
193 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
194 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
195 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
196 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
197 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
198 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
199 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
200 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
201 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
202 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
205 #define GPSR7_3 FM(HDMI1_CEC)
206 #define GPSR7_2 FM(HDMI0_CEC)
207 #define GPSR7_1 FM(AVS2)
208 #define GPSR7_0 FM(AVS1)
211 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
212 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
233 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
308 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
329 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
338 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
358 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
359 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
360 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
361 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
362 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
364 #define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
366 #define PINMUX_GPSR \
374 GPSR1_25 GPSR5_25 GPSR6_25 \
375 GPSR1_24 GPSR5_24 GPSR6_24 \
376 GPSR1_23 GPSR5_23 GPSR6_23 \
377 GPSR1_22 GPSR5_22 GPSR6_22 \
378 GPSR1_21 GPSR5_21 GPSR6_21 \
379 GPSR1_20 GPSR5_20 GPSR6_20 \
380 GPSR1_19 GPSR5_19 GPSR6_19 \
381 GPSR1_18 GPSR5_18 GPSR6_18 \
382 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
383 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
384 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
385 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
386 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
387 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
388 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
389 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
390 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
391 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
392 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
393 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
394 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
395 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
396 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
397 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
398 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
399 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
401 #define PINMUX_IPSR \
403 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
404 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
405 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
406 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
407 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
408 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
409 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
410 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
412 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
413 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
414 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
415 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
416 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
417 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
418 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
419 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
421 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
422 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
423 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
424 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
425 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
426 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
427 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
428 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
430 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
431 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
432 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
433 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
434 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
435 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
436 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
437 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
439 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
440 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
441 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
442 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
443 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
444 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
445 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
446 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
448 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
449 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
450 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
451 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
452 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
453 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
454 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
455 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
456 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
457 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
458 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
459 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
460 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
461 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
462 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
463 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
464 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
465 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
466 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
468 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
469 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
470 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
471 #define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
472 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
473 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
474 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
475 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
476 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
477 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
478 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
479 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
480 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
481 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
482 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
483 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
484 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
485 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
486 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
487 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
488 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
489 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
490 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
492 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
493 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
494 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
495 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
496 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
497 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
498 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
499 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
500 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
501 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
502 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
503 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
504 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
506 #define PINMUX_MOD_SELS \
508 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
510 MOD_SEL1_29_28_27 MOD_SEL2_29 \
511 MOD_SEL0_28_27 MOD_SEL2_28_27 \
512 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
513 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
514 MOD_SEL0_23 MOD_SEL1_23_22_21 \
516 MOD_SEL0_21 MOD_SEL2_21 \
517 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
518 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
519 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
521 MOD_SEL0_16 MOD_SEL1_16 \
525 MOD_SEL0_12 MOD_SEL1_12 \
526 MOD_SEL0_11 MOD_SEL1_11 \
527 MOD_SEL0_10 MOD_SEL1_10 \
528 MOD_SEL0_9_8 MOD_SEL1_9 \
531 MOD_SEL0_5 MOD_SEL1_5 \
532 MOD_SEL0_4_3 MOD_SEL1_4 \
536 MOD_SEL1_0 MOD_SEL2_0
539 * These pins are not able to be muxed but have other properties
540 * that can be set, such as drive-strength or pull-up/pull-down enable.
542 #define PINMUX_STATIC \
543 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
544 FM(QSPI0_IO2) FM(QSPI0_IO3) \
545 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
546 FM(QSPI1_IO2) FM(QSPI1_IO3) \
547 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
548 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
549 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
550 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
552 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
553 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
563 #define FM(x) FN_##x,
564 PINMUX_FUNCTION_BEGIN,
574 #define FM(x) x##_MARK,
585 static const u16 pinmux_data[] = {
586 PINMUX_DATA_GP_ALL(),
590 PINMUX_SINGLE(CLKOUT),
591 PINMUX_SINGLE(HDMI0_CEC),
592 PINMUX_SINGLE(HDMI1_CEC),
593 PINMUX_SINGLE(I2C_SEL_0_1),
594 PINMUX_SINGLE(I2C_SEL_3_1),
595 PINMUX_SINGLE(I2C_SEL_5_1),
596 PINMUX_SINGLE(MSIOF0_RXD),
597 PINMUX_SINGLE(MSIOF0_SCK),
598 PINMUX_SINGLE(MSIOF0_TXD),
599 PINMUX_SINGLE(SSI_SCK5),
600 PINMUX_SINGLE(SSI_SDATA5),
601 PINMUX_SINGLE(SSI_WS5),
604 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
605 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
607 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
608 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
609 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
611 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
612 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
613 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
615 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
616 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
617 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
619 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
620 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
621 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
622 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
624 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
625 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
626 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
628 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
629 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
630 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
631 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
632 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
633 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
636 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
637 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
638 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
639 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
640 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
645 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
646 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
647 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
648 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
649 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
650 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
652 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
653 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
654 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
655 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
656 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
657 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
659 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
660 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
661 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
662 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
663 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
664 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
666 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
667 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
668 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
669 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
670 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
671 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
672 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
674 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
675 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
676 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
677 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
679 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
680 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
681 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
682 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
684 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
685 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
686 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
688 PINMUX_IPSR_GPSR(IP1_31_28, A0),
689 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
690 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
691 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
692 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
693 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
696 PINMUX_IPSR_GPSR(IP2_3_0, A1),
697 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
698 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
699 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
700 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
701 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
703 PINMUX_IPSR_GPSR(IP2_7_4, A2),
704 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
705 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
706 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
707 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
708 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
710 PINMUX_IPSR_GPSR(IP2_11_8, A3),
711 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
712 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
713 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
714 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
715 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
717 PINMUX_IPSR_GPSR(IP2_15_12, A4),
718 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
719 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
720 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
721 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
722 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
724 PINMUX_IPSR_GPSR(IP2_19_16, A5),
725 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
726 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
727 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
728 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
729 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
730 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
732 PINMUX_IPSR_GPSR(IP2_23_20, A6),
733 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
734 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
735 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
736 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
737 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
738 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
740 PINMUX_IPSR_GPSR(IP2_27_24, A7),
741 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
742 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
743 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
744 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
745 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
746 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
748 PINMUX_IPSR_GPSR(IP2_31_28, A8),
749 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
750 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
751 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
752 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
753 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
754 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
757 PINMUX_IPSR_GPSR(IP3_3_0, A9),
758 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
759 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
760 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
762 PINMUX_IPSR_GPSR(IP3_7_4, A10),
763 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
764 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
765 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
767 PINMUX_IPSR_GPSR(IP3_11_8, A11),
768 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
769 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
770 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
771 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
772 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
773 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
774 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
775 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
777 PINMUX_IPSR_GPSR(IP3_15_12, A12),
778 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
779 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
780 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
781 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
782 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
784 PINMUX_IPSR_GPSR(IP3_19_16, A13),
785 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
786 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
787 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
788 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
789 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
791 PINMUX_IPSR_GPSR(IP3_23_20, A14),
792 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
793 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
794 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
795 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
796 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
798 PINMUX_IPSR_GPSR(IP3_27_24, A15),
799 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
800 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
801 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
802 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
803 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
805 PINMUX_IPSR_GPSR(IP3_31_28, A16),
806 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
807 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
808 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
811 PINMUX_IPSR_GPSR(IP4_3_0, A17),
812 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
813 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
814 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
816 PINMUX_IPSR_GPSR(IP4_7_4, A18),
817 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
818 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
819 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
821 PINMUX_IPSR_GPSR(IP4_11_8, A19),
822 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
823 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
824 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
826 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
827 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
829 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
830 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
831 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
833 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
834 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
835 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
836 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
837 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
838 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
839 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
840 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
842 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
843 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
844 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
845 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
846 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
847 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
849 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
850 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
851 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
852 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
853 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
854 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
857 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
858 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
859 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
860 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
861 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
862 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
863 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
865 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
866 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
867 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
868 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
869 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
870 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
871 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
872 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
874 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
875 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
876 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
877 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
879 PINMUX_IPSR_GPSR(IP5_15_12, D0),
880 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
881 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
882 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
883 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
885 PINMUX_IPSR_GPSR(IP5_19_16, D1),
886 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
887 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
888 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
889 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
891 PINMUX_IPSR_GPSR(IP5_23_20, D2),
892 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
893 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
894 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
896 PINMUX_IPSR_GPSR(IP5_27_24, D3),
897 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
898 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
899 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
901 PINMUX_IPSR_GPSR(IP5_31_28, D4),
902 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
903 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
904 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
907 PINMUX_IPSR_GPSR(IP6_3_0, D5),
908 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
909 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
910 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
912 PINMUX_IPSR_GPSR(IP6_7_4, D6),
913 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
914 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
915 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
917 PINMUX_IPSR_GPSR(IP6_11_8, D7),
918 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
919 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
920 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
922 PINMUX_IPSR_GPSR(IP6_15_12, D8),
923 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
924 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
925 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
926 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
927 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
929 PINMUX_IPSR_GPSR(IP6_19_16, D9),
930 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
931 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
932 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
933 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
935 PINMUX_IPSR_GPSR(IP6_23_20, D10),
936 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
937 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
938 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
939 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
940 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
941 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
943 PINMUX_IPSR_GPSR(IP6_27_24, D11),
944 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
945 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
946 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
947 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
948 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
949 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
951 PINMUX_IPSR_GPSR(IP6_31_28, D12),
952 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
953 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
954 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
955 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
956 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
959 PINMUX_IPSR_GPSR(IP7_3_0, D13),
960 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
961 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
962 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
963 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
964 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
966 PINMUX_IPSR_GPSR(IP7_7_4, D14),
967 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
968 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
969 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
970 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
971 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
972 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
974 PINMUX_IPSR_GPSR(IP7_11_8, D15),
975 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
976 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
977 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
978 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
979 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
980 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
982 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
983 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
984 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
986 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
987 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
988 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
990 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
991 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
992 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
993 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
995 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
996 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
998 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1001 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1002 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1003 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1004 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1006 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1007 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1008 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1009 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1011 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1012 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1013 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1015 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1016 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1017 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
1018 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1019 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1021 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1022 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1023 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1024 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
1025 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1026 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1028 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1029 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1030 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1031 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
1032 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1033 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1035 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1036 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1037 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1038 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
1039 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1040 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1042 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1043 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1044 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1045 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
1046 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1047 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1050 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1051 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1053 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1054 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1056 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1057 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1059 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1060 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1062 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1063 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1065 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1066 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1068 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1069 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1070 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1072 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1073 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1076 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1077 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1079 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1080 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1082 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1083 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1085 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1086 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1088 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1089 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1091 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1092 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1093 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1095 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1096 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1097 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1099 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1100 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1101 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1104 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1105 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1106 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1108 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1109 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1111 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1112 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1113 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1115 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1116 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1118 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1119 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1121 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1122 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1124 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1125 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1126 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1127 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1128 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1129 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1130 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1131 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1132 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1133 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1135 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1136 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1137 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1138 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1139 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1142 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1143 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1144 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1145 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1146 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1148 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1149 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1150 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1151 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1152 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1153 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1154 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1155 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1157 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1158 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1159 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1160 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1161 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1162 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1163 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1164 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1166 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1167 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1168 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1169 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1170 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1172 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1174 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1175 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1176 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1178 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1179 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1180 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1181 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1182 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1183 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1184 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1186 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1187 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1188 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1189 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1190 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1191 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1192 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1194 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1195 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1196 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1197 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1198 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1199 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1200 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1203 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1204 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1205 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1206 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1207 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1208 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1210 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1211 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1212 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1213 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1214 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1215 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1217 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1218 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1219 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1220 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1221 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1222 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1223 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1224 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1226 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1227 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1228 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1229 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1230 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1231 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1233 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1234 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1235 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1236 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1237 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1238 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1240 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1241 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1242 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1243 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1244 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1245 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1246 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1247 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1249 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1250 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1251 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1252 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1253 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1254 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1255 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1257 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1258 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1259 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1260 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1263 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1264 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1265 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
1266 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1267 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1268 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1269 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1270 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
1272 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1273 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1274 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1275 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1276 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1277 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1278 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1279 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1281 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1282 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1283 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1285 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1286 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1287 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1288 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1290 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1291 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1292 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1294 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1295 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1297 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1298 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1300 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1301 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1304 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1306 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1307 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1309 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1310 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1311 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1313 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1314 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1315 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1316 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1318 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1319 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1320 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1321 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1322 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1323 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1324 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1326 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1327 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1328 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1329 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1330 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1331 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1332 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1334 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1335 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1336 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1337 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1338 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1339 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1340 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1342 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1343 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1344 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1345 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1346 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1347 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1348 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1351 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1352 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1353 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1355 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1356 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1357 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1359 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1360 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1361 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1363 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1364 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1365 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1366 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1367 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1368 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1369 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1371 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1372 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1373 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1374 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1375 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1376 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1377 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1379 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1380 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1381 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1382 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1383 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1384 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1385 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1386 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1388 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1389 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1390 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1391 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1392 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1393 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1394 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1396 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1397 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1398 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1399 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1400 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1401 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1402 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1403 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1406 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1407 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1409 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1410 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1411 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1412 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1413 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
1415 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1416 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1417 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1418 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1419 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1420 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1421 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1423 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1424 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1425 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1426 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1427 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1428 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1430 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1431 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1432 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1433 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1434 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1435 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1436 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1437 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1438 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1440 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1441 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1442 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1443 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1444 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1445 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1446 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1447 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1448 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1450 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1451 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1452 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1453 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1454 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1455 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1456 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1457 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1458 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1459 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1460 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1462 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1463 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1464 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1465 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1466 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1467 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1468 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1469 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1470 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1473 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
1474 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1475 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1476 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1477 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1478 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1479 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1480 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1481 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1483 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
1484 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1485 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1486 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1487 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1488 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1489 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1490 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1491 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1494 * Static pins can not be muxed between different functions but
1495 * still needs a mark entry in the pinmux list. Add each static
1496 * pin to the list without an associated function. The sh-pfc
1497 * core will do the right thing and skip trying to mux then pin
1498 * while still applying configuration to it
1500 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1506 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1507 * Physical layout rows: A - AW, cols: 1 - 39.
1509 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1510 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1511 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1512 #define PIN_NONE U16_MAX
1514 static const struct sh_pfc_pin pinmux_pins[] = {
1515 PINMUX_GPIO_GP_ALL(),
1518 * Pins not associated with a GPIO port.
1520 * The pin positions are different between different r8a7795
1521 * packages, all that is needed for the pfc driver is a unique
1522 * number for each pin. To this end use the pin layout from
1523 * R-Car H3SiP to calculate a unique number for each pin.
1525 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1526 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1527 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1528 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1529 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1530 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1531 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1570 /* - AUDIO CLOCK ------------------------------------------------------------ */
1571 static const unsigned int audio_clk_a_a_pins[] = {
1575 static const unsigned int audio_clk_a_a_mux[] = {
1578 static const unsigned int audio_clk_a_b_pins[] = {
1582 static const unsigned int audio_clk_a_b_mux[] = {
1585 static const unsigned int audio_clk_a_c_pins[] = {
1589 static const unsigned int audio_clk_a_c_mux[] = {
1592 static const unsigned int audio_clk_b_a_pins[] = {
1596 static const unsigned int audio_clk_b_a_mux[] = {
1599 static const unsigned int audio_clk_b_b_pins[] = {
1603 static const unsigned int audio_clk_b_b_mux[] = {
1606 static const unsigned int audio_clk_c_a_pins[] = {
1610 static const unsigned int audio_clk_c_a_mux[] = {
1613 static const unsigned int audio_clk_c_b_pins[] = {
1617 static const unsigned int audio_clk_c_b_mux[] = {
1620 static const unsigned int audio_clkout_a_pins[] = {
1624 static const unsigned int audio_clkout_a_mux[] = {
1625 AUDIO_CLKOUT_A_MARK,
1627 static const unsigned int audio_clkout_b_pins[] = {
1631 static const unsigned int audio_clkout_b_mux[] = {
1632 AUDIO_CLKOUT_B_MARK,
1634 static const unsigned int audio_clkout_c_pins[] = {
1638 static const unsigned int audio_clkout_c_mux[] = {
1639 AUDIO_CLKOUT_C_MARK,
1641 static const unsigned int audio_clkout_d_pins[] = {
1645 static const unsigned int audio_clkout_d_mux[] = {
1646 AUDIO_CLKOUT_D_MARK,
1648 static const unsigned int audio_clkout1_a_pins[] = {
1652 static const unsigned int audio_clkout1_a_mux[] = {
1653 AUDIO_CLKOUT1_A_MARK,
1655 static const unsigned int audio_clkout1_b_pins[] = {
1659 static const unsigned int audio_clkout1_b_mux[] = {
1660 AUDIO_CLKOUT1_B_MARK,
1662 static const unsigned int audio_clkout2_a_pins[] = {
1666 static const unsigned int audio_clkout2_a_mux[] = {
1667 AUDIO_CLKOUT2_A_MARK,
1669 static const unsigned int audio_clkout2_b_pins[] = {
1673 static const unsigned int audio_clkout2_b_mux[] = {
1674 AUDIO_CLKOUT2_B_MARK,
1676 static const unsigned int audio_clkout3_a_pins[] = {
1680 static const unsigned int audio_clkout3_a_mux[] = {
1681 AUDIO_CLKOUT3_A_MARK,
1683 static const unsigned int audio_clkout3_b_pins[] = {
1687 static const unsigned int audio_clkout3_b_mux[] = {
1688 AUDIO_CLKOUT3_B_MARK,
1691 /* - EtherAVB --------------------------------------------------------------- */
1692 static const unsigned int avb_link_pins[] = {
1696 static const unsigned int avb_link_mux[] = {
1699 static const unsigned int avb_magic_pins[] = {
1703 static const unsigned int avb_magic_mux[] = {
1706 static const unsigned int avb_phy_int_pins[] = {
1710 static const unsigned int avb_phy_int_mux[] = {
1713 static const unsigned int avb_mdio_pins[] = {
1714 /* AVB_MDC, AVB_MDIO */
1715 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1717 static const unsigned int avb_mdio_mux[] = {
1718 AVB_MDC_MARK, AVB_MDIO_MARK,
1720 static const unsigned int avb_mii_pins[] = {
1722 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1723 * AVB_TD1, AVB_TD2, AVB_TD3,
1724 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1725 * AVB_RD1, AVB_RD2, AVB_RD3,
1728 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1729 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1730 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1731 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1732 PIN_NUMBER('A', 12),
1735 static const unsigned int avb_mii_mux[] = {
1736 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1737 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1738 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1739 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1742 static const unsigned int avb_avtp_pps_pins[] = {
1746 static const unsigned int avb_avtp_pps_mux[] = {
1749 static const unsigned int avb_avtp_match_a_pins[] = {
1750 /* AVB_AVTP_MATCH_A */
1753 static const unsigned int avb_avtp_match_a_mux[] = {
1754 AVB_AVTP_MATCH_A_MARK,
1756 static const unsigned int avb_avtp_capture_a_pins[] = {
1757 /* AVB_AVTP_CAPTURE_A */
1760 static const unsigned int avb_avtp_capture_a_mux[] = {
1761 AVB_AVTP_CAPTURE_A_MARK,
1763 static const unsigned int avb_avtp_match_b_pins[] = {
1764 /* AVB_AVTP_MATCH_B */
1767 static const unsigned int avb_avtp_match_b_mux[] = {
1768 AVB_AVTP_MATCH_B_MARK,
1770 static const unsigned int avb_avtp_capture_b_pins[] = {
1771 /* AVB_AVTP_CAPTURE_B */
1774 static const unsigned int avb_avtp_capture_b_mux[] = {
1775 AVB_AVTP_CAPTURE_B_MARK,
1778 /* - CAN ------------------------------------------------------------------ */
1779 static const unsigned int can0_data_a_pins[] = {
1781 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1783 static const unsigned int can0_data_a_mux[] = {
1784 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1786 static const unsigned int can0_data_b_pins[] = {
1788 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1790 static const unsigned int can0_data_b_mux[] = {
1791 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1793 static const unsigned int can1_data_pins[] = {
1795 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1797 static const unsigned int can1_data_mux[] = {
1798 CAN1_TX_MARK, CAN1_RX_MARK,
1801 /* - CAN Clock -------------------------------------------------------------- */
1802 static const unsigned int can_clk_pins[] = {
1806 static const unsigned int can_clk_mux[] = {
1810 /* - CAN FD --------------------------------------------------------------- */
1811 static const unsigned int canfd0_data_a_pins[] = {
1813 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1815 static const unsigned int canfd0_data_a_mux[] = {
1816 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1818 static const unsigned int canfd0_data_b_pins[] = {
1820 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1822 static const unsigned int canfd0_data_b_mux[] = {
1823 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1825 static const unsigned int canfd1_data_pins[] = {
1827 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1829 static const unsigned int canfd1_data_mux[] = {
1830 CANFD1_TX_MARK, CANFD1_RX_MARK,
1833 /* - DRIF0 --------------------------------------------------------------- */
1834 static const unsigned int drif0_ctrl_a_pins[] = {
1836 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1838 static const unsigned int drif0_ctrl_a_mux[] = {
1839 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1841 static const unsigned int drif0_data0_a_pins[] = {
1845 static const unsigned int drif0_data0_a_mux[] = {
1848 static const unsigned int drif0_data1_a_pins[] = {
1852 static const unsigned int drif0_data1_a_mux[] = {
1855 static const unsigned int drif0_ctrl_b_pins[] = {
1857 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1859 static const unsigned int drif0_ctrl_b_mux[] = {
1860 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1862 static const unsigned int drif0_data0_b_pins[] = {
1866 static const unsigned int drif0_data0_b_mux[] = {
1869 static const unsigned int drif0_data1_b_pins[] = {
1873 static const unsigned int drif0_data1_b_mux[] = {
1876 static const unsigned int drif0_ctrl_c_pins[] = {
1878 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1880 static const unsigned int drif0_ctrl_c_mux[] = {
1881 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1883 static const unsigned int drif0_data0_c_pins[] = {
1887 static const unsigned int drif0_data0_c_mux[] = {
1890 static const unsigned int drif0_data1_c_pins[] = {
1894 static const unsigned int drif0_data1_c_mux[] = {
1897 /* - DRIF1 --------------------------------------------------------------- */
1898 static const unsigned int drif1_ctrl_a_pins[] = {
1900 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1902 static const unsigned int drif1_ctrl_a_mux[] = {
1903 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1905 static const unsigned int drif1_data0_a_pins[] = {
1909 static const unsigned int drif1_data0_a_mux[] = {
1912 static const unsigned int drif1_data1_a_pins[] = {
1916 static const unsigned int drif1_data1_a_mux[] = {
1919 static const unsigned int drif1_ctrl_b_pins[] = {
1921 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1923 static const unsigned int drif1_ctrl_b_mux[] = {
1924 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1926 static const unsigned int drif1_data0_b_pins[] = {
1930 static const unsigned int drif1_data0_b_mux[] = {
1933 static const unsigned int drif1_data1_b_pins[] = {
1937 static const unsigned int drif1_data1_b_mux[] = {
1940 static const unsigned int drif1_ctrl_c_pins[] = {
1942 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1944 static const unsigned int drif1_ctrl_c_mux[] = {
1945 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1947 static const unsigned int drif1_data0_c_pins[] = {
1951 static const unsigned int drif1_data0_c_mux[] = {
1954 static const unsigned int drif1_data1_c_pins[] = {
1958 static const unsigned int drif1_data1_c_mux[] = {
1961 /* - DRIF2 --------------------------------------------------------------- */
1962 static const unsigned int drif2_ctrl_a_pins[] = {
1964 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1966 static const unsigned int drif2_ctrl_a_mux[] = {
1967 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1969 static const unsigned int drif2_data0_a_pins[] = {
1973 static const unsigned int drif2_data0_a_mux[] = {
1976 static const unsigned int drif2_data1_a_pins[] = {
1980 static const unsigned int drif2_data1_a_mux[] = {
1983 static const unsigned int drif2_ctrl_b_pins[] = {
1985 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1987 static const unsigned int drif2_ctrl_b_mux[] = {
1988 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1990 static const unsigned int drif2_data0_b_pins[] = {
1994 static const unsigned int drif2_data0_b_mux[] = {
1997 static const unsigned int drif2_data1_b_pins[] = {
2001 static const unsigned int drif2_data1_b_mux[] = {
2004 /* - DRIF3 --------------------------------------------------------------- */
2005 static const unsigned int drif3_ctrl_a_pins[] = {
2007 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2009 static const unsigned int drif3_ctrl_a_mux[] = {
2010 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2012 static const unsigned int drif3_data0_a_pins[] = {
2016 static const unsigned int drif3_data0_a_mux[] = {
2019 static const unsigned int drif3_data1_a_pins[] = {
2023 static const unsigned int drif3_data1_a_mux[] = {
2026 static const unsigned int drif3_ctrl_b_pins[] = {
2028 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2030 static const unsigned int drif3_ctrl_b_mux[] = {
2031 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2033 static const unsigned int drif3_data0_b_pins[] = {
2037 static const unsigned int drif3_data0_b_mux[] = {
2040 static const unsigned int drif3_data1_b_pins[] = {
2044 static const unsigned int drif3_data1_b_mux[] = {
2048 /* - DU --------------------------------------------------------------------- */
2049 static const unsigned int du_rgb666_pins[] = {
2050 /* R[7:2], G[7:2], B[7:2] */
2051 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2052 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2053 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2054 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2055 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2056 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2058 static const unsigned int du_rgb666_mux[] = {
2059 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2060 DU_DR3_MARK, DU_DR2_MARK,
2061 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2062 DU_DG3_MARK, DU_DG2_MARK,
2063 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2064 DU_DB3_MARK, DU_DB2_MARK,
2066 static const unsigned int du_rgb888_pins[] = {
2067 /* R[7:0], G[7:0], B[7:0] */
2068 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2069 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2070 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2071 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2072 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2073 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2074 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2075 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2076 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2078 static const unsigned int du_rgb888_mux[] = {
2079 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2080 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2081 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2082 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2083 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2084 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2086 static const unsigned int du_clk_out_0_pins[] = {
2090 static const unsigned int du_clk_out_0_mux[] = {
2093 static const unsigned int du_clk_out_1_pins[] = {
2097 static const unsigned int du_clk_out_1_mux[] = {
2100 static const unsigned int du_sync_pins[] = {
2101 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2102 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2104 static const unsigned int du_sync_mux[] = {
2105 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2107 static const unsigned int du_oddf_pins[] = {
2108 /* EXDISP/EXODDF/EXCDE */
2111 static const unsigned int du_oddf_mux[] = {
2112 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2114 static const unsigned int du_cde_pins[] = {
2118 static const unsigned int du_cde_mux[] = {
2121 static const unsigned int du_disp_pins[] = {
2125 static const unsigned int du_disp_mux[] = {
2129 /* - HDMI ------------------------------------------------------------------- */
2130 static const unsigned int hdmi0_cec_pins[] = {
2134 static const unsigned int hdmi0_cec_mux[] = {
2137 static const unsigned int hdmi1_cec_pins[] = {
2141 static const unsigned int hdmi1_cec_mux[] = {
2145 /* - HSCIF0 ----------------------------------------------------------------- */
2146 static const unsigned int hscif0_data_pins[] = {
2148 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2150 static const unsigned int hscif0_data_mux[] = {
2151 HRX0_MARK, HTX0_MARK,
2153 static const unsigned int hscif0_clk_pins[] = {
2157 static const unsigned int hscif0_clk_mux[] = {
2160 static const unsigned int hscif0_ctrl_pins[] = {
2162 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2164 static const unsigned int hscif0_ctrl_mux[] = {
2165 HRTS0_N_MARK, HCTS0_N_MARK,
2167 /* - HSCIF1 ----------------------------------------------------------------- */
2168 static const unsigned int hscif1_data_a_pins[] = {
2170 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2172 static const unsigned int hscif1_data_a_mux[] = {
2173 HRX1_A_MARK, HTX1_A_MARK,
2175 static const unsigned int hscif1_clk_a_pins[] = {
2179 static const unsigned int hscif1_clk_a_mux[] = {
2182 static const unsigned int hscif1_ctrl_a_pins[] = {
2184 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2186 static const unsigned int hscif1_ctrl_a_mux[] = {
2187 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2190 static const unsigned int hscif1_data_b_pins[] = {
2192 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2194 static const unsigned int hscif1_data_b_mux[] = {
2195 HRX1_B_MARK, HTX1_B_MARK,
2197 static const unsigned int hscif1_clk_b_pins[] = {
2201 static const unsigned int hscif1_clk_b_mux[] = {
2204 static const unsigned int hscif1_ctrl_b_pins[] = {
2206 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2208 static const unsigned int hscif1_ctrl_b_mux[] = {
2209 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2211 /* - HSCIF2 ----------------------------------------------------------------- */
2212 static const unsigned int hscif2_data_a_pins[] = {
2214 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2216 static const unsigned int hscif2_data_a_mux[] = {
2217 HRX2_A_MARK, HTX2_A_MARK,
2219 static const unsigned int hscif2_clk_a_pins[] = {
2223 static const unsigned int hscif2_clk_a_mux[] = {
2226 static const unsigned int hscif2_ctrl_a_pins[] = {
2228 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2230 static const unsigned int hscif2_ctrl_a_mux[] = {
2231 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2234 static const unsigned int hscif2_data_b_pins[] = {
2236 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2238 static const unsigned int hscif2_data_b_mux[] = {
2239 HRX2_B_MARK, HTX2_B_MARK,
2241 static const unsigned int hscif2_clk_b_pins[] = {
2245 static const unsigned int hscif2_clk_b_mux[] = {
2248 static const unsigned int hscif2_ctrl_b_pins[] = {
2250 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2252 static const unsigned int hscif2_ctrl_b_mux[] = {
2253 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2256 static const unsigned int hscif2_data_c_pins[] = {
2258 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2260 static const unsigned int hscif2_data_c_mux[] = {
2261 HRX2_C_MARK, HTX2_C_MARK,
2263 static const unsigned int hscif2_clk_c_pins[] = {
2267 static const unsigned int hscif2_clk_c_mux[] = {
2270 static const unsigned int hscif2_ctrl_c_pins[] = {
2272 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2274 static const unsigned int hscif2_ctrl_c_mux[] = {
2275 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2277 /* - HSCIF3 ----------------------------------------------------------------- */
2278 static const unsigned int hscif3_data_a_pins[] = {
2280 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2282 static const unsigned int hscif3_data_a_mux[] = {
2283 HRX3_A_MARK, HTX3_A_MARK,
2285 static const unsigned int hscif3_clk_pins[] = {
2289 static const unsigned int hscif3_clk_mux[] = {
2292 static const unsigned int hscif3_ctrl_pins[] = {
2294 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2296 static const unsigned int hscif3_ctrl_mux[] = {
2297 HRTS3_N_MARK, HCTS3_N_MARK,
2300 static const unsigned int hscif3_data_b_pins[] = {
2302 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2304 static const unsigned int hscif3_data_b_mux[] = {
2305 HRX3_B_MARK, HTX3_B_MARK,
2307 static const unsigned int hscif3_data_c_pins[] = {
2309 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2311 static const unsigned int hscif3_data_c_mux[] = {
2312 HRX3_C_MARK, HTX3_C_MARK,
2314 static const unsigned int hscif3_data_d_pins[] = {
2316 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2318 static const unsigned int hscif3_data_d_mux[] = {
2319 HRX3_D_MARK, HTX3_D_MARK,
2321 /* - HSCIF4 ----------------------------------------------------------------- */
2322 static const unsigned int hscif4_data_a_pins[] = {
2324 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2326 static const unsigned int hscif4_data_a_mux[] = {
2327 HRX4_A_MARK, HTX4_A_MARK,
2329 static const unsigned int hscif4_clk_pins[] = {
2333 static const unsigned int hscif4_clk_mux[] = {
2336 static const unsigned int hscif4_ctrl_pins[] = {
2338 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2340 static const unsigned int hscif4_ctrl_mux[] = {
2341 HRTS4_N_MARK, HCTS4_N_MARK,
2344 static const unsigned int hscif4_data_b_pins[] = {
2346 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2348 static const unsigned int hscif4_data_b_mux[] = {
2349 HRX4_B_MARK, HTX4_B_MARK,
2352 /* - I2C -------------------------------------------------------------------- */
2353 static const unsigned int i2c1_a_pins[] = {
2355 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2357 static const unsigned int i2c1_a_mux[] = {
2358 SDA1_A_MARK, SCL1_A_MARK,
2360 static const unsigned int i2c1_b_pins[] = {
2362 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2364 static const unsigned int i2c1_b_mux[] = {
2365 SDA1_B_MARK, SCL1_B_MARK,
2367 static const unsigned int i2c2_a_pins[] = {
2369 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2371 static const unsigned int i2c2_a_mux[] = {
2372 SDA2_A_MARK, SCL2_A_MARK,
2374 static const unsigned int i2c2_b_pins[] = {
2376 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2378 static const unsigned int i2c2_b_mux[] = {
2379 SDA2_B_MARK, SCL2_B_MARK,
2381 static const unsigned int i2c6_a_pins[] = {
2383 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2385 static const unsigned int i2c6_a_mux[] = {
2386 SDA6_A_MARK, SCL6_A_MARK,
2388 static const unsigned int i2c6_b_pins[] = {
2390 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2392 static const unsigned int i2c6_b_mux[] = {
2393 SDA6_B_MARK, SCL6_B_MARK,
2395 static const unsigned int i2c6_c_pins[] = {
2397 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2399 static const unsigned int i2c6_c_mux[] = {
2400 SDA6_C_MARK, SCL6_C_MARK,
2403 /* - INTC-EX ---------------------------------------------------------------- */
2404 static const unsigned int intc_ex_irq0_pins[] = {
2408 static const unsigned int intc_ex_irq0_mux[] = {
2411 static const unsigned int intc_ex_irq1_pins[] = {
2415 static const unsigned int intc_ex_irq1_mux[] = {
2418 static const unsigned int intc_ex_irq2_pins[] = {
2422 static const unsigned int intc_ex_irq2_mux[] = {
2425 static const unsigned int intc_ex_irq3_pins[] = {
2429 static const unsigned int intc_ex_irq3_mux[] = {
2432 static const unsigned int intc_ex_irq4_pins[] = {
2436 static const unsigned int intc_ex_irq4_mux[] = {
2439 static const unsigned int intc_ex_irq5_pins[] = {
2443 static const unsigned int intc_ex_irq5_mux[] = {
2447 /* - MSIOF0 ----------------------------------------------------------------- */
2448 static const unsigned int msiof0_clk_pins[] = {
2452 static const unsigned int msiof0_clk_mux[] = {
2455 static const unsigned int msiof0_sync_pins[] = {
2459 static const unsigned int msiof0_sync_mux[] = {
2462 static const unsigned int msiof0_ss1_pins[] = {
2466 static const unsigned int msiof0_ss1_mux[] = {
2469 static const unsigned int msiof0_ss2_pins[] = {
2473 static const unsigned int msiof0_ss2_mux[] = {
2476 static const unsigned int msiof0_txd_pins[] = {
2480 static const unsigned int msiof0_txd_mux[] = {
2483 static const unsigned int msiof0_rxd_pins[] = {
2487 static const unsigned int msiof0_rxd_mux[] = {
2490 /* - MSIOF1 ----------------------------------------------------------------- */
2491 static const unsigned int msiof1_clk_a_pins[] = {
2495 static const unsigned int msiof1_clk_a_mux[] = {
2498 static const unsigned int msiof1_sync_a_pins[] = {
2502 static const unsigned int msiof1_sync_a_mux[] = {
2505 static const unsigned int msiof1_ss1_a_pins[] = {
2509 static const unsigned int msiof1_ss1_a_mux[] = {
2512 static const unsigned int msiof1_ss2_a_pins[] = {
2516 static const unsigned int msiof1_ss2_a_mux[] = {
2519 static const unsigned int msiof1_txd_a_pins[] = {
2523 static const unsigned int msiof1_txd_a_mux[] = {
2526 static const unsigned int msiof1_rxd_a_pins[] = {
2530 static const unsigned int msiof1_rxd_a_mux[] = {
2533 static const unsigned int msiof1_clk_b_pins[] = {
2537 static const unsigned int msiof1_clk_b_mux[] = {
2540 static const unsigned int msiof1_sync_b_pins[] = {
2544 static const unsigned int msiof1_sync_b_mux[] = {
2547 static const unsigned int msiof1_ss1_b_pins[] = {
2551 static const unsigned int msiof1_ss1_b_mux[] = {
2554 static const unsigned int msiof1_ss2_b_pins[] = {
2558 static const unsigned int msiof1_ss2_b_mux[] = {
2561 static const unsigned int msiof1_txd_b_pins[] = {
2565 static const unsigned int msiof1_txd_b_mux[] = {
2568 static const unsigned int msiof1_rxd_b_pins[] = {
2572 static const unsigned int msiof1_rxd_b_mux[] = {
2575 static const unsigned int msiof1_clk_c_pins[] = {
2579 static const unsigned int msiof1_clk_c_mux[] = {
2582 static const unsigned int msiof1_sync_c_pins[] = {
2586 static const unsigned int msiof1_sync_c_mux[] = {
2589 static const unsigned int msiof1_ss1_c_pins[] = {
2593 static const unsigned int msiof1_ss1_c_mux[] = {
2596 static const unsigned int msiof1_ss2_c_pins[] = {
2600 static const unsigned int msiof1_ss2_c_mux[] = {
2603 static const unsigned int msiof1_txd_c_pins[] = {
2607 static const unsigned int msiof1_txd_c_mux[] = {
2610 static const unsigned int msiof1_rxd_c_pins[] = {
2614 static const unsigned int msiof1_rxd_c_mux[] = {
2617 static const unsigned int msiof1_clk_d_pins[] = {
2621 static const unsigned int msiof1_clk_d_mux[] = {
2624 static const unsigned int msiof1_sync_d_pins[] = {
2628 static const unsigned int msiof1_sync_d_mux[] = {
2631 static const unsigned int msiof1_ss1_d_pins[] = {
2635 static const unsigned int msiof1_ss1_d_mux[] = {
2638 static const unsigned int msiof1_ss2_d_pins[] = {
2642 static const unsigned int msiof1_ss2_d_mux[] = {
2645 static const unsigned int msiof1_txd_d_pins[] = {
2649 static const unsigned int msiof1_txd_d_mux[] = {
2652 static const unsigned int msiof1_rxd_d_pins[] = {
2656 static const unsigned int msiof1_rxd_d_mux[] = {
2659 static const unsigned int msiof1_clk_e_pins[] = {
2663 static const unsigned int msiof1_clk_e_mux[] = {
2666 static const unsigned int msiof1_sync_e_pins[] = {
2670 static const unsigned int msiof1_sync_e_mux[] = {
2673 static const unsigned int msiof1_ss1_e_pins[] = {
2677 static const unsigned int msiof1_ss1_e_mux[] = {
2680 static const unsigned int msiof1_ss2_e_pins[] = {
2684 static const unsigned int msiof1_ss2_e_mux[] = {
2687 static const unsigned int msiof1_txd_e_pins[] = {
2691 static const unsigned int msiof1_txd_e_mux[] = {
2694 static const unsigned int msiof1_rxd_e_pins[] = {
2698 static const unsigned int msiof1_rxd_e_mux[] = {
2701 static const unsigned int msiof1_clk_f_pins[] = {
2705 static const unsigned int msiof1_clk_f_mux[] = {
2708 static const unsigned int msiof1_sync_f_pins[] = {
2712 static const unsigned int msiof1_sync_f_mux[] = {
2715 static const unsigned int msiof1_ss1_f_pins[] = {
2719 static const unsigned int msiof1_ss1_f_mux[] = {
2722 static const unsigned int msiof1_ss2_f_pins[] = {
2726 static const unsigned int msiof1_ss2_f_mux[] = {
2729 static const unsigned int msiof1_txd_f_pins[] = {
2733 static const unsigned int msiof1_txd_f_mux[] = {
2736 static const unsigned int msiof1_rxd_f_pins[] = {
2740 static const unsigned int msiof1_rxd_f_mux[] = {
2743 static const unsigned int msiof1_clk_g_pins[] = {
2747 static const unsigned int msiof1_clk_g_mux[] = {
2750 static const unsigned int msiof1_sync_g_pins[] = {
2754 static const unsigned int msiof1_sync_g_mux[] = {
2757 static const unsigned int msiof1_ss1_g_pins[] = {
2761 static const unsigned int msiof1_ss1_g_mux[] = {
2764 static const unsigned int msiof1_ss2_g_pins[] = {
2768 static const unsigned int msiof1_ss2_g_mux[] = {
2771 static const unsigned int msiof1_txd_g_pins[] = {
2775 static const unsigned int msiof1_txd_g_mux[] = {
2778 static const unsigned int msiof1_rxd_g_pins[] = {
2782 static const unsigned int msiof1_rxd_g_mux[] = {
2785 /* - MSIOF2 ----------------------------------------------------------------- */
2786 static const unsigned int msiof2_clk_a_pins[] = {
2790 static const unsigned int msiof2_clk_a_mux[] = {
2793 static const unsigned int msiof2_sync_a_pins[] = {
2797 static const unsigned int msiof2_sync_a_mux[] = {
2800 static const unsigned int msiof2_ss1_a_pins[] = {
2804 static const unsigned int msiof2_ss1_a_mux[] = {
2807 static const unsigned int msiof2_ss2_a_pins[] = {
2811 static const unsigned int msiof2_ss2_a_mux[] = {
2814 static const unsigned int msiof2_txd_a_pins[] = {
2818 static const unsigned int msiof2_txd_a_mux[] = {
2821 static const unsigned int msiof2_rxd_a_pins[] = {
2825 static const unsigned int msiof2_rxd_a_mux[] = {
2828 static const unsigned int msiof2_clk_b_pins[] = {
2832 static const unsigned int msiof2_clk_b_mux[] = {
2835 static const unsigned int msiof2_sync_b_pins[] = {
2839 static const unsigned int msiof2_sync_b_mux[] = {
2842 static const unsigned int msiof2_ss1_b_pins[] = {
2846 static const unsigned int msiof2_ss1_b_mux[] = {
2849 static const unsigned int msiof2_ss2_b_pins[] = {
2853 static const unsigned int msiof2_ss2_b_mux[] = {
2856 static const unsigned int msiof2_txd_b_pins[] = {
2860 static const unsigned int msiof2_txd_b_mux[] = {
2863 static const unsigned int msiof2_rxd_b_pins[] = {
2867 static const unsigned int msiof2_rxd_b_mux[] = {
2870 static const unsigned int msiof2_clk_c_pins[] = {
2874 static const unsigned int msiof2_clk_c_mux[] = {
2877 static const unsigned int msiof2_sync_c_pins[] = {
2881 static const unsigned int msiof2_sync_c_mux[] = {
2884 static const unsigned int msiof2_ss1_c_pins[] = {
2888 static const unsigned int msiof2_ss1_c_mux[] = {
2891 static const unsigned int msiof2_ss2_c_pins[] = {
2895 static const unsigned int msiof2_ss2_c_mux[] = {
2898 static const unsigned int msiof2_txd_c_pins[] = {
2902 static const unsigned int msiof2_txd_c_mux[] = {
2905 static const unsigned int msiof2_rxd_c_pins[] = {
2909 static const unsigned int msiof2_rxd_c_mux[] = {
2912 static const unsigned int msiof2_clk_d_pins[] = {
2916 static const unsigned int msiof2_clk_d_mux[] = {
2919 static const unsigned int msiof2_sync_d_pins[] = {
2923 static const unsigned int msiof2_sync_d_mux[] = {
2926 static const unsigned int msiof2_ss1_d_pins[] = {
2930 static const unsigned int msiof2_ss1_d_mux[] = {
2933 static const unsigned int msiof2_ss2_d_pins[] = {
2937 static const unsigned int msiof2_ss2_d_mux[] = {
2940 static const unsigned int msiof2_txd_d_pins[] = {
2944 static const unsigned int msiof2_txd_d_mux[] = {
2947 static const unsigned int msiof2_rxd_d_pins[] = {
2951 static const unsigned int msiof2_rxd_d_mux[] = {
2954 /* - MSIOF3 ----------------------------------------------------------------- */
2955 static const unsigned int msiof3_clk_a_pins[] = {
2959 static const unsigned int msiof3_clk_a_mux[] = {
2962 static const unsigned int msiof3_sync_a_pins[] = {
2966 static const unsigned int msiof3_sync_a_mux[] = {
2969 static const unsigned int msiof3_ss1_a_pins[] = {
2973 static const unsigned int msiof3_ss1_a_mux[] = {
2976 static const unsigned int msiof3_ss2_a_pins[] = {
2980 static const unsigned int msiof3_ss2_a_mux[] = {
2983 static const unsigned int msiof3_txd_a_pins[] = {
2987 static const unsigned int msiof3_txd_a_mux[] = {
2990 static const unsigned int msiof3_rxd_a_pins[] = {
2994 static const unsigned int msiof3_rxd_a_mux[] = {
2997 static const unsigned int msiof3_clk_b_pins[] = {
3001 static const unsigned int msiof3_clk_b_mux[] = {
3004 static const unsigned int msiof3_sync_b_pins[] = {
3008 static const unsigned int msiof3_sync_b_mux[] = {
3011 static const unsigned int msiof3_ss1_b_pins[] = {
3015 static const unsigned int msiof3_ss1_b_mux[] = {
3018 static const unsigned int msiof3_ss2_b_pins[] = {
3022 static const unsigned int msiof3_ss2_b_mux[] = {
3025 static const unsigned int msiof3_txd_b_pins[] = {
3029 static const unsigned int msiof3_txd_b_mux[] = {
3032 static const unsigned int msiof3_rxd_b_pins[] = {
3036 static const unsigned int msiof3_rxd_b_mux[] = {
3039 static const unsigned int msiof3_clk_c_pins[] = {
3043 static const unsigned int msiof3_clk_c_mux[] = {
3046 static const unsigned int msiof3_sync_c_pins[] = {
3050 static const unsigned int msiof3_sync_c_mux[] = {
3053 static const unsigned int msiof3_txd_c_pins[] = {
3057 static const unsigned int msiof3_txd_c_mux[] = {
3060 static const unsigned int msiof3_rxd_c_pins[] = {
3064 static const unsigned int msiof3_rxd_c_mux[] = {
3067 static const unsigned int msiof3_clk_d_pins[] = {
3071 static const unsigned int msiof3_clk_d_mux[] = {
3074 static const unsigned int msiof3_sync_d_pins[] = {
3078 static const unsigned int msiof3_sync_d_mux[] = {
3081 static const unsigned int msiof3_ss1_d_pins[] = {
3085 static const unsigned int msiof3_ss1_d_mux[] = {
3088 static const unsigned int msiof3_txd_d_pins[] = {
3092 static const unsigned int msiof3_txd_d_mux[] = {
3095 static const unsigned int msiof3_rxd_d_pins[] = {
3099 static const unsigned int msiof3_rxd_d_mux[] = {
3102 static const unsigned int msiof3_clk_e_pins[] = {
3106 static const unsigned int msiof3_clk_e_mux[] = {
3109 static const unsigned int msiof3_sync_e_pins[] = {
3113 static const unsigned int msiof3_sync_e_mux[] = {
3116 static const unsigned int msiof3_ss1_e_pins[] = {
3120 static const unsigned int msiof3_ss1_e_mux[] = {
3123 static const unsigned int msiof3_ss2_e_pins[] = {
3127 static const unsigned int msiof3_ss2_e_mux[] = {
3130 static const unsigned int msiof3_txd_e_pins[] = {
3134 static const unsigned int msiof3_txd_e_mux[] = {
3137 static const unsigned int msiof3_rxd_e_pins[] = {
3141 static const unsigned int msiof3_rxd_e_mux[] = {
3145 /* - PWM0 --------------------------------------------------------------------*/
3146 static const unsigned int pwm0_pins[] = {
3150 static const unsigned int pwm0_mux[] = {
3153 /* - PWM1 --------------------------------------------------------------------*/
3154 static const unsigned int pwm1_a_pins[] = {
3158 static const unsigned int pwm1_a_mux[] = {
3161 static const unsigned int pwm1_b_pins[] = {
3165 static const unsigned int pwm1_b_mux[] = {
3168 /* - PWM2 --------------------------------------------------------------------*/
3169 static const unsigned int pwm2_a_pins[] = {
3173 static const unsigned int pwm2_a_mux[] = {
3176 static const unsigned int pwm2_b_pins[] = {
3180 static const unsigned int pwm2_b_mux[] = {
3183 /* - PWM3 --------------------------------------------------------------------*/
3184 static const unsigned int pwm3_a_pins[] = {
3188 static const unsigned int pwm3_a_mux[] = {
3191 static const unsigned int pwm3_b_pins[] = {
3195 static const unsigned int pwm3_b_mux[] = {
3198 /* - PWM4 --------------------------------------------------------------------*/
3199 static const unsigned int pwm4_a_pins[] = {
3203 static const unsigned int pwm4_a_mux[] = {
3206 static const unsigned int pwm4_b_pins[] = {
3210 static const unsigned int pwm4_b_mux[] = {
3213 /* - PWM5 --------------------------------------------------------------------*/
3214 static const unsigned int pwm5_a_pins[] = {
3218 static const unsigned int pwm5_a_mux[] = {
3221 static const unsigned int pwm5_b_pins[] = {
3225 static const unsigned int pwm5_b_mux[] = {
3228 /* - PWM6 --------------------------------------------------------------------*/
3229 static const unsigned int pwm6_a_pins[] = {
3233 static const unsigned int pwm6_a_mux[] = {
3236 static const unsigned int pwm6_b_pins[] = {
3240 static const unsigned int pwm6_b_mux[] = {
3244 /* - SATA --------------------------------------------------------------------*/
3245 static const unsigned int sata0_devslp_a_pins[] = {
3249 static const unsigned int sata0_devslp_a_mux[] = {
3252 static const unsigned int sata0_devslp_b_pins[] = {
3256 static const unsigned int sata0_devslp_b_mux[] = {
3260 /* - SCIF0 ------------------------------------------------------------------ */
3261 static const unsigned int scif0_data_pins[] = {
3263 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3265 static const unsigned int scif0_data_mux[] = {
3268 static const unsigned int scif0_clk_pins[] = {
3272 static const unsigned int scif0_clk_mux[] = {
3275 static const unsigned int scif0_ctrl_pins[] = {
3277 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3279 static const unsigned int scif0_ctrl_mux[] = {
3280 RTS0_N_MARK, CTS0_N_MARK,
3282 /* - SCIF1 ------------------------------------------------------------------ */
3283 static const unsigned int scif1_data_a_pins[] = {
3285 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3287 static const unsigned int scif1_data_a_mux[] = {
3288 RX1_A_MARK, TX1_A_MARK,
3290 static const unsigned int scif1_clk_pins[] = {
3294 static const unsigned int scif1_clk_mux[] = {
3297 static const unsigned int scif1_ctrl_pins[] = {
3299 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3301 static const unsigned int scif1_ctrl_mux[] = {
3302 RTS1_N_MARK, CTS1_N_MARK,
3305 static const unsigned int scif1_data_b_pins[] = {
3307 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3309 static const unsigned int scif1_data_b_mux[] = {
3310 RX1_B_MARK, TX1_B_MARK,
3312 /* - SCIF2 ------------------------------------------------------------------ */
3313 static const unsigned int scif2_data_a_pins[] = {
3315 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3317 static const unsigned int scif2_data_a_mux[] = {
3318 RX2_A_MARK, TX2_A_MARK,
3320 static const unsigned int scif2_clk_pins[] = {
3324 static const unsigned int scif2_clk_mux[] = {
3327 static const unsigned int scif2_data_b_pins[] = {
3329 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3331 static const unsigned int scif2_data_b_mux[] = {
3332 RX2_B_MARK, TX2_B_MARK,
3334 /* - SCIF3 ------------------------------------------------------------------ */
3335 static const unsigned int scif3_data_a_pins[] = {
3337 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3339 static const unsigned int scif3_data_a_mux[] = {
3340 RX3_A_MARK, TX3_A_MARK,
3342 static const unsigned int scif3_clk_pins[] = {
3346 static const unsigned int scif3_clk_mux[] = {
3349 static const unsigned int scif3_ctrl_pins[] = {
3351 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3353 static const unsigned int scif3_ctrl_mux[] = {
3354 RTS3_N_MARK, CTS3_N_MARK,
3356 static const unsigned int scif3_data_b_pins[] = {
3358 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3360 static const unsigned int scif3_data_b_mux[] = {
3361 RX3_B_MARK, TX3_B_MARK,
3363 /* - SCIF4 ------------------------------------------------------------------ */
3364 static const unsigned int scif4_data_a_pins[] = {
3366 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3368 static const unsigned int scif4_data_a_mux[] = {
3369 RX4_A_MARK, TX4_A_MARK,
3371 static const unsigned int scif4_clk_a_pins[] = {
3375 static const unsigned int scif4_clk_a_mux[] = {
3378 static const unsigned int scif4_ctrl_a_pins[] = {
3380 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3382 static const unsigned int scif4_ctrl_a_mux[] = {
3383 RTS4_N_A_MARK, CTS4_N_A_MARK,
3385 static const unsigned int scif4_data_b_pins[] = {
3387 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3389 static const unsigned int scif4_data_b_mux[] = {
3390 RX4_B_MARK, TX4_B_MARK,
3392 static const unsigned int scif4_clk_b_pins[] = {
3396 static const unsigned int scif4_clk_b_mux[] = {
3399 static const unsigned int scif4_ctrl_b_pins[] = {
3401 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3403 static const unsigned int scif4_ctrl_b_mux[] = {
3404 RTS4_N_B_MARK, CTS4_N_B_MARK,
3406 static const unsigned int scif4_data_c_pins[] = {
3408 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3410 static const unsigned int scif4_data_c_mux[] = {
3411 RX4_C_MARK, TX4_C_MARK,
3413 static const unsigned int scif4_clk_c_pins[] = {
3417 static const unsigned int scif4_clk_c_mux[] = {
3420 static const unsigned int scif4_ctrl_c_pins[] = {
3422 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3424 static const unsigned int scif4_ctrl_c_mux[] = {
3425 RTS4_N_C_MARK, CTS4_N_C_MARK,
3427 /* - SCIF5 ------------------------------------------------------------------ */
3428 static const unsigned int scif5_data_a_pins[] = {
3430 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3432 static const unsigned int scif5_data_a_mux[] = {
3433 RX5_A_MARK, TX5_A_MARK,
3435 static const unsigned int scif5_clk_a_pins[] = {
3439 static const unsigned int scif5_clk_a_mux[] = {
3442 static const unsigned int scif5_data_b_pins[] = {
3444 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3446 static const unsigned int scif5_data_b_mux[] = {
3447 RX5_B_MARK, TX5_B_MARK,
3449 static const unsigned int scif5_clk_b_pins[] = {
3453 static const unsigned int scif5_clk_b_mux[] = {
3457 /* - SCIF Clock ------------------------------------------------------------- */
3458 static const unsigned int scif_clk_a_pins[] = {
3462 static const unsigned int scif_clk_a_mux[] = {
3465 static const unsigned int scif_clk_b_pins[] = {
3469 static const unsigned int scif_clk_b_mux[] = {
3473 /* - SDHI0 ------------------------------------------------------------------ */
3474 static const unsigned int sdhi0_data1_pins[] = {
3478 static const unsigned int sdhi0_data1_mux[] = {
3481 static const unsigned int sdhi0_data4_pins[] = {
3483 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3484 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3486 static const unsigned int sdhi0_data4_mux[] = {
3487 SD0_DAT0_MARK, SD0_DAT1_MARK,
3488 SD0_DAT2_MARK, SD0_DAT3_MARK,
3490 static const unsigned int sdhi0_ctrl_pins[] = {
3492 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3494 static const unsigned int sdhi0_ctrl_mux[] = {
3495 SD0_CLK_MARK, SD0_CMD_MARK,
3497 static const unsigned int sdhi0_cd_pins[] = {
3501 static const unsigned int sdhi0_cd_mux[] = {
3504 static const unsigned int sdhi0_wp_pins[] = {
3508 static const unsigned int sdhi0_wp_mux[] = {
3511 /* - SDHI1 ------------------------------------------------------------------ */
3512 static const unsigned int sdhi1_data1_pins[] = {
3516 static const unsigned int sdhi1_data1_mux[] = {
3519 static const unsigned int sdhi1_data4_pins[] = {
3521 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3522 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3524 static const unsigned int sdhi1_data4_mux[] = {
3525 SD1_DAT0_MARK, SD1_DAT1_MARK,
3526 SD1_DAT2_MARK, SD1_DAT3_MARK,
3528 static const unsigned int sdhi1_ctrl_pins[] = {
3530 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3532 static const unsigned int sdhi1_ctrl_mux[] = {
3533 SD1_CLK_MARK, SD1_CMD_MARK,
3535 static const unsigned int sdhi1_cd_pins[] = {
3539 static const unsigned int sdhi1_cd_mux[] = {
3542 static const unsigned int sdhi1_wp_pins[] = {
3546 static const unsigned int sdhi1_wp_mux[] = {
3549 /* - SDHI2 ------------------------------------------------------------------ */
3550 static const unsigned int sdhi2_data1_pins[] = {
3554 static const unsigned int sdhi2_data1_mux[] = {
3557 static const unsigned int sdhi2_data4_pins[] = {
3559 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3560 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3562 static const unsigned int sdhi2_data4_mux[] = {
3563 SD2_DAT0_MARK, SD2_DAT1_MARK,
3564 SD2_DAT2_MARK, SD2_DAT3_MARK,
3566 static const unsigned int sdhi2_data8_pins[] = {
3568 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3569 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3570 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3571 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3573 static const unsigned int sdhi2_data8_mux[] = {
3574 SD2_DAT0_MARK, SD2_DAT1_MARK,
3575 SD2_DAT2_MARK, SD2_DAT3_MARK,
3576 SD2_DAT4_MARK, SD2_DAT5_MARK,
3577 SD2_DAT6_MARK, SD2_DAT7_MARK,
3579 static const unsigned int sdhi2_ctrl_pins[] = {
3581 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3583 static const unsigned int sdhi2_ctrl_mux[] = {
3584 SD2_CLK_MARK, SD2_CMD_MARK,
3586 static const unsigned int sdhi2_cd_a_pins[] = {
3590 static const unsigned int sdhi2_cd_a_mux[] = {
3593 static const unsigned int sdhi2_cd_b_pins[] = {
3597 static const unsigned int sdhi2_cd_b_mux[] = {
3600 static const unsigned int sdhi2_wp_a_pins[] = {
3604 static const unsigned int sdhi2_wp_a_mux[] = {
3607 static const unsigned int sdhi2_wp_b_pins[] = {
3611 static const unsigned int sdhi2_wp_b_mux[] = {
3614 static const unsigned int sdhi2_ds_pins[] = {
3618 static const unsigned int sdhi2_ds_mux[] = {
3621 /* - SDHI3 ------------------------------------------------------------------ */
3622 static const unsigned int sdhi3_data1_pins[] = {
3626 static const unsigned int sdhi3_data1_mux[] = {
3629 static const unsigned int sdhi3_data4_pins[] = {
3631 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3632 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3634 static const unsigned int sdhi3_data4_mux[] = {
3635 SD3_DAT0_MARK, SD3_DAT1_MARK,
3636 SD3_DAT2_MARK, SD3_DAT3_MARK,
3638 static const unsigned int sdhi3_data8_pins[] = {
3640 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3641 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3642 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3643 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3645 static const unsigned int sdhi3_data8_mux[] = {
3646 SD3_DAT0_MARK, SD3_DAT1_MARK,
3647 SD3_DAT2_MARK, SD3_DAT3_MARK,
3648 SD3_DAT4_MARK, SD3_DAT5_MARK,
3649 SD3_DAT6_MARK, SD3_DAT7_MARK,
3651 static const unsigned int sdhi3_ctrl_pins[] = {
3653 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3655 static const unsigned int sdhi3_ctrl_mux[] = {
3656 SD3_CLK_MARK, SD3_CMD_MARK,
3658 static const unsigned int sdhi3_cd_pins[] = {
3662 static const unsigned int sdhi3_cd_mux[] = {
3665 static const unsigned int sdhi3_wp_pins[] = {
3669 static const unsigned int sdhi3_wp_mux[] = {
3672 static const unsigned int sdhi3_ds_pins[] = {
3676 static const unsigned int sdhi3_ds_mux[] = {
3680 /* - SSI -------------------------------------------------------------------- */
3681 static const unsigned int ssi0_data_pins[] = {
3685 static const unsigned int ssi0_data_mux[] = {
3688 static const unsigned int ssi01239_ctrl_pins[] = {
3690 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3692 static const unsigned int ssi01239_ctrl_mux[] = {
3693 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3695 static const unsigned int ssi1_data_a_pins[] = {
3699 static const unsigned int ssi1_data_a_mux[] = {
3702 static const unsigned int ssi1_data_b_pins[] = {
3706 static const unsigned int ssi1_data_b_mux[] = {
3709 static const unsigned int ssi1_ctrl_a_pins[] = {
3711 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3713 static const unsigned int ssi1_ctrl_a_mux[] = {
3714 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3716 static const unsigned int ssi1_ctrl_b_pins[] = {
3718 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3720 static const unsigned int ssi1_ctrl_b_mux[] = {
3721 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3723 static const unsigned int ssi2_data_a_pins[] = {
3727 static const unsigned int ssi2_data_a_mux[] = {
3730 static const unsigned int ssi2_data_b_pins[] = {
3734 static const unsigned int ssi2_data_b_mux[] = {
3737 static const unsigned int ssi2_ctrl_a_pins[] = {
3739 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3741 static const unsigned int ssi2_ctrl_a_mux[] = {
3742 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3744 static const unsigned int ssi2_ctrl_b_pins[] = {
3746 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3748 static const unsigned int ssi2_ctrl_b_mux[] = {
3749 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3751 static const unsigned int ssi3_data_pins[] = {
3755 static const unsigned int ssi3_data_mux[] = {
3758 static const unsigned int ssi349_ctrl_pins[] = {
3760 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3762 static const unsigned int ssi349_ctrl_mux[] = {
3763 SSI_SCK349_MARK, SSI_WS349_MARK,
3765 static const unsigned int ssi4_data_pins[] = {
3769 static const unsigned int ssi4_data_mux[] = {
3772 static const unsigned int ssi4_ctrl_pins[] = {
3774 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3776 static const unsigned int ssi4_ctrl_mux[] = {
3777 SSI_SCK4_MARK, SSI_WS4_MARK,
3779 static const unsigned int ssi5_data_pins[] = {
3783 static const unsigned int ssi5_data_mux[] = {
3786 static const unsigned int ssi5_ctrl_pins[] = {
3788 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3790 static const unsigned int ssi5_ctrl_mux[] = {
3791 SSI_SCK5_MARK, SSI_WS5_MARK,
3793 static const unsigned int ssi6_data_pins[] = {
3797 static const unsigned int ssi6_data_mux[] = {
3800 static const unsigned int ssi6_ctrl_pins[] = {
3802 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3804 static const unsigned int ssi6_ctrl_mux[] = {
3805 SSI_SCK6_MARK, SSI_WS6_MARK,
3807 static const unsigned int ssi7_data_pins[] = {
3811 static const unsigned int ssi7_data_mux[] = {
3814 static const unsigned int ssi78_ctrl_pins[] = {
3816 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3818 static const unsigned int ssi78_ctrl_mux[] = {
3819 SSI_SCK78_MARK, SSI_WS78_MARK,
3821 static const unsigned int ssi8_data_pins[] = {
3825 static const unsigned int ssi8_data_mux[] = {
3828 static const unsigned int ssi9_data_a_pins[] = {
3832 static const unsigned int ssi9_data_a_mux[] = {
3835 static const unsigned int ssi9_data_b_pins[] = {
3839 static const unsigned int ssi9_data_b_mux[] = {
3842 static const unsigned int ssi9_ctrl_a_pins[] = {
3844 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3846 static const unsigned int ssi9_ctrl_a_mux[] = {
3847 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3849 static const unsigned int ssi9_ctrl_b_pins[] = {
3851 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3853 static const unsigned int ssi9_ctrl_b_mux[] = {
3854 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3857 /* - TMU -------------------------------------------------------------------- */
3858 static const unsigned int tmu_tclk1_a_pins[] = {
3862 static const unsigned int tmu_tclk1_a_mux[] = {
3865 static const unsigned int tmu_tclk1_b_pins[] = {
3869 static const unsigned int tmu_tclk1_b_mux[] = {
3872 static const unsigned int tmu_tclk2_a_pins[] = {
3876 static const unsigned int tmu_tclk2_a_mux[] = {
3879 static const unsigned int tmu_tclk2_b_pins[] = {
3883 static const unsigned int tmu_tclk2_b_mux[] = {
3887 /* - USB0 ------------------------------------------------------------------- */
3888 static const unsigned int usb0_pins[] = {
3890 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3892 static const unsigned int usb0_mux[] = {
3893 USB0_PWEN_MARK, USB0_OVC_MARK,
3895 /* - USB1 ------------------------------------------------------------------- */
3896 static const unsigned int usb1_pins[] = {
3898 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3900 static const unsigned int usb1_mux[] = {
3901 USB1_PWEN_MARK, USB1_OVC_MARK,
3903 /* - USB2 ------------------------------------------------------------------- */
3904 static const unsigned int usb2_pins[] = {
3906 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3908 static const unsigned int usb2_mux[] = {
3909 USB2_PWEN_MARK, USB2_OVC_MARK,
3911 /* - USB2_CH3 --------------------------------------------------------------- */
3912 static const unsigned int usb2_ch3_pins[] = {
3914 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3916 static const unsigned int usb2_ch3_mux[] = {
3917 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3920 /* - USB30 ------------------------------------------------------------------ */
3921 static const unsigned int usb30_pins[] = {
3923 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3925 static const unsigned int usb30_mux[] = {
3926 USB30_PWEN_MARK, USB30_OVC_MARK,
3929 /* - VIN4 ------------------------------------------------------------------- */
3930 static const unsigned int vin4_data18_a_pins[] = {
3931 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3932 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3933 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3934 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3935 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3936 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3937 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3938 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3939 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3941 static const unsigned int vin4_data18_a_mux[] = {
3942 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3943 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3944 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3945 VI4_DATA10_MARK, VI4_DATA11_MARK,
3946 VI4_DATA12_MARK, VI4_DATA13_MARK,
3947 VI4_DATA14_MARK, VI4_DATA15_MARK,
3948 VI4_DATA18_MARK, VI4_DATA19_MARK,
3949 VI4_DATA20_MARK, VI4_DATA21_MARK,
3950 VI4_DATA22_MARK, VI4_DATA23_MARK,
3952 static const unsigned int vin4_data18_b_pins[] = {
3953 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3954 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3955 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3956 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3957 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3958 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3959 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3960 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3961 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3963 static const unsigned int vin4_data18_b_mux[] = {
3964 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3965 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3966 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3967 VI4_DATA10_MARK, VI4_DATA11_MARK,
3968 VI4_DATA12_MARK, VI4_DATA13_MARK,
3969 VI4_DATA14_MARK, VI4_DATA15_MARK,
3970 VI4_DATA18_MARK, VI4_DATA19_MARK,
3971 VI4_DATA20_MARK, VI4_DATA21_MARK,
3972 VI4_DATA22_MARK, VI4_DATA23_MARK,
3974 static const union vin_data vin4_data_a_pins = {
3976 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3977 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3978 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3979 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3980 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3981 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3982 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3983 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3984 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3985 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3986 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3987 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3990 static const union vin_data vin4_data_a_mux = {
3992 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3993 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3994 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3995 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3996 VI4_DATA8_MARK, VI4_DATA9_MARK,
3997 VI4_DATA10_MARK, VI4_DATA11_MARK,
3998 VI4_DATA12_MARK, VI4_DATA13_MARK,
3999 VI4_DATA14_MARK, VI4_DATA15_MARK,
4000 VI4_DATA16_MARK, VI4_DATA17_MARK,
4001 VI4_DATA18_MARK, VI4_DATA19_MARK,
4002 VI4_DATA20_MARK, VI4_DATA21_MARK,
4003 VI4_DATA22_MARK, VI4_DATA23_MARK,
4006 static const union vin_data vin4_data_b_pins = {
4008 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4009 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4010 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4011 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4012 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4013 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4014 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4015 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4016 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4017 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4018 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4019 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4022 static const union vin_data vin4_data_b_mux = {
4024 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4025 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4026 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4027 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4028 VI4_DATA8_MARK, VI4_DATA9_MARK,
4029 VI4_DATA10_MARK, VI4_DATA11_MARK,
4030 VI4_DATA12_MARK, VI4_DATA13_MARK,
4031 VI4_DATA14_MARK, VI4_DATA15_MARK,
4032 VI4_DATA16_MARK, VI4_DATA17_MARK,
4033 VI4_DATA18_MARK, VI4_DATA19_MARK,
4034 VI4_DATA20_MARK, VI4_DATA21_MARK,
4035 VI4_DATA22_MARK, VI4_DATA23_MARK,
4038 static const unsigned int vin4_sync_pins[] = {
4039 /* HSYNC#, VSYNC# */
4040 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4042 static const unsigned int vin4_sync_mux[] = {
4043 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4045 static const unsigned int vin4_field_pins[] = {
4049 static const unsigned int vin4_field_mux[] = {
4052 static const unsigned int vin4_clkenb_pins[] = {
4056 static const unsigned int vin4_clkenb_mux[] = {
4059 static const unsigned int vin4_clk_pins[] = {
4063 static const unsigned int vin4_clk_mux[] = {
4067 /* - VIN5 ------------------------------------------------------------------- */
4068 static const unsigned int vin5_data8_pins[] = {
4069 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4070 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4071 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4072 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4074 static const unsigned int vin5_data8_mux[] = {
4075 VI5_DATA0_MARK, VI5_DATA1_MARK,
4076 VI5_DATA2_MARK, VI5_DATA3_MARK,
4077 VI5_DATA4_MARK, VI5_DATA5_MARK,
4078 VI5_DATA6_MARK, VI5_DATA7_MARK,
4080 static const unsigned int vin5_data10_pins[] = {
4081 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4082 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4083 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4084 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4085 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4087 static const unsigned int vin5_data10_mux[] = {
4088 VI5_DATA0_MARK, VI5_DATA1_MARK,
4089 VI5_DATA2_MARK, VI5_DATA3_MARK,
4090 VI5_DATA4_MARK, VI5_DATA5_MARK,
4091 VI5_DATA6_MARK, VI5_DATA7_MARK,
4092 VI5_DATA8_MARK, VI5_DATA9_MARK,
4094 static const unsigned int vin5_data12_pins[] = {
4095 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4096 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4097 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4098 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4099 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4100 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4102 static const unsigned int vin5_data12_mux[] = {
4103 VI5_DATA0_MARK, VI5_DATA1_MARK,
4104 VI5_DATA2_MARK, VI5_DATA3_MARK,
4105 VI5_DATA4_MARK, VI5_DATA5_MARK,
4106 VI5_DATA6_MARK, VI5_DATA7_MARK,
4107 VI5_DATA8_MARK, VI5_DATA9_MARK,
4108 VI5_DATA10_MARK, VI5_DATA11_MARK,
4110 static const unsigned int vin5_data16_pins[] = {
4111 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4112 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4113 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4114 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4115 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4116 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4117 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4118 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4120 static const unsigned int vin5_data16_mux[] = {
4121 VI5_DATA0_MARK, VI5_DATA1_MARK,
4122 VI5_DATA2_MARK, VI5_DATA3_MARK,
4123 VI5_DATA4_MARK, VI5_DATA5_MARK,
4124 VI5_DATA6_MARK, VI5_DATA7_MARK,
4125 VI5_DATA8_MARK, VI5_DATA9_MARK,
4126 VI5_DATA10_MARK, VI5_DATA11_MARK,
4127 VI5_DATA12_MARK, VI5_DATA13_MARK,
4128 VI5_DATA14_MARK, VI5_DATA15_MARK,
4130 static const unsigned int vin5_sync_pins[] = {
4131 /* HSYNC#, VSYNC# */
4132 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4134 static const unsigned int vin5_sync_mux[] = {
4135 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4137 static const unsigned int vin5_field_pins[] = {
4140 static const unsigned int vin5_field_mux[] = {
4144 static const unsigned int vin5_clkenb_pins[] = {
4147 static const unsigned int vin5_clkenb_mux[] = {
4151 static const unsigned int vin5_clk_pins[] = {
4154 static const unsigned int vin5_clk_mux[] = {
4159 static const struct sh_pfc_pin_group pinmux_groups[] = {
4160 SH_PFC_PIN_GROUP(audio_clk_a_a),
4161 SH_PFC_PIN_GROUP(audio_clk_a_b),
4162 SH_PFC_PIN_GROUP(audio_clk_a_c),
4163 SH_PFC_PIN_GROUP(audio_clk_b_a),
4164 SH_PFC_PIN_GROUP(audio_clk_b_b),
4165 SH_PFC_PIN_GROUP(audio_clk_c_a),
4166 SH_PFC_PIN_GROUP(audio_clk_c_b),
4167 SH_PFC_PIN_GROUP(audio_clkout_a),
4168 SH_PFC_PIN_GROUP(audio_clkout_b),
4169 SH_PFC_PIN_GROUP(audio_clkout_c),
4170 SH_PFC_PIN_GROUP(audio_clkout_d),
4171 SH_PFC_PIN_GROUP(audio_clkout1_a),
4172 SH_PFC_PIN_GROUP(audio_clkout1_b),
4173 SH_PFC_PIN_GROUP(audio_clkout2_a),
4174 SH_PFC_PIN_GROUP(audio_clkout2_b),
4175 SH_PFC_PIN_GROUP(audio_clkout3_a),
4176 SH_PFC_PIN_GROUP(audio_clkout3_b),
4177 SH_PFC_PIN_GROUP(avb_link),
4178 SH_PFC_PIN_GROUP(avb_magic),
4179 SH_PFC_PIN_GROUP(avb_phy_int),
4180 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4181 SH_PFC_PIN_GROUP(avb_mdio),
4182 SH_PFC_PIN_GROUP(avb_mii),
4183 SH_PFC_PIN_GROUP(avb_avtp_pps),
4184 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4185 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4186 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4187 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4188 SH_PFC_PIN_GROUP(can0_data_a),
4189 SH_PFC_PIN_GROUP(can0_data_b),
4190 SH_PFC_PIN_GROUP(can1_data),
4191 SH_PFC_PIN_GROUP(can_clk),
4192 SH_PFC_PIN_GROUP(canfd0_data_a),
4193 SH_PFC_PIN_GROUP(canfd0_data_b),
4194 SH_PFC_PIN_GROUP(canfd1_data),
4195 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4196 SH_PFC_PIN_GROUP(drif0_data0_a),
4197 SH_PFC_PIN_GROUP(drif0_data1_a),
4198 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4199 SH_PFC_PIN_GROUP(drif0_data0_b),
4200 SH_PFC_PIN_GROUP(drif0_data1_b),
4201 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4202 SH_PFC_PIN_GROUP(drif0_data0_c),
4203 SH_PFC_PIN_GROUP(drif0_data1_c),
4204 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4205 SH_PFC_PIN_GROUP(drif1_data0_a),
4206 SH_PFC_PIN_GROUP(drif1_data1_a),
4207 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4208 SH_PFC_PIN_GROUP(drif1_data0_b),
4209 SH_PFC_PIN_GROUP(drif1_data1_b),
4210 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4211 SH_PFC_PIN_GROUP(drif1_data0_c),
4212 SH_PFC_PIN_GROUP(drif1_data1_c),
4213 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4214 SH_PFC_PIN_GROUP(drif2_data0_a),
4215 SH_PFC_PIN_GROUP(drif2_data1_a),
4216 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4217 SH_PFC_PIN_GROUP(drif2_data0_b),
4218 SH_PFC_PIN_GROUP(drif2_data1_b),
4219 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4220 SH_PFC_PIN_GROUP(drif3_data0_a),
4221 SH_PFC_PIN_GROUP(drif3_data1_a),
4222 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4223 SH_PFC_PIN_GROUP(drif3_data0_b),
4224 SH_PFC_PIN_GROUP(drif3_data1_b),
4225 SH_PFC_PIN_GROUP(du_rgb666),
4226 SH_PFC_PIN_GROUP(du_rgb888),
4227 SH_PFC_PIN_GROUP(du_clk_out_0),
4228 SH_PFC_PIN_GROUP(du_clk_out_1),
4229 SH_PFC_PIN_GROUP(du_sync),
4230 SH_PFC_PIN_GROUP(du_oddf),
4231 SH_PFC_PIN_GROUP(du_cde),
4232 SH_PFC_PIN_GROUP(du_disp),
4233 SH_PFC_PIN_GROUP(hdmi0_cec),
4234 SH_PFC_PIN_GROUP(hdmi1_cec),
4235 SH_PFC_PIN_GROUP(hscif0_data),
4236 SH_PFC_PIN_GROUP(hscif0_clk),
4237 SH_PFC_PIN_GROUP(hscif0_ctrl),
4238 SH_PFC_PIN_GROUP(hscif1_data_a),
4239 SH_PFC_PIN_GROUP(hscif1_clk_a),
4240 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4241 SH_PFC_PIN_GROUP(hscif1_data_b),
4242 SH_PFC_PIN_GROUP(hscif1_clk_b),
4243 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4244 SH_PFC_PIN_GROUP(hscif2_data_a),
4245 SH_PFC_PIN_GROUP(hscif2_clk_a),
4246 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4247 SH_PFC_PIN_GROUP(hscif2_data_b),
4248 SH_PFC_PIN_GROUP(hscif2_clk_b),
4249 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4250 SH_PFC_PIN_GROUP(hscif2_data_c),
4251 SH_PFC_PIN_GROUP(hscif2_clk_c),
4252 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4253 SH_PFC_PIN_GROUP(hscif3_data_a),
4254 SH_PFC_PIN_GROUP(hscif3_clk),
4255 SH_PFC_PIN_GROUP(hscif3_ctrl),
4256 SH_PFC_PIN_GROUP(hscif3_data_b),
4257 SH_PFC_PIN_GROUP(hscif3_data_c),
4258 SH_PFC_PIN_GROUP(hscif3_data_d),
4259 SH_PFC_PIN_GROUP(hscif4_data_a),
4260 SH_PFC_PIN_GROUP(hscif4_clk),
4261 SH_PFC_PIN_GROUP(hscif4_ctrl),
4262 SH_PFC_PIN_GROUP(hscif4_data_b),
4263 SH_PFC_PIN_GROUP(i2c1_a),
4264 SH_PFC_PIN_GROUP(i2c1_b),
4265 SH_PFC_PIN_GROUP(i2c2_a),
4266 SH_PFC_PIN_GROUP(i2c2_b),
4267 SH_PFC_PIN_GROUP(i2c6_a),
4268 SH_PFC_PIN_GROUP(i2c6_b),
4269 SH_PFC_PIN_GROUP(i2c6_c),
4270 SH_PFC_PIN_GROUP(intc_ex_irq0),
4271 SH_PFC_PIN_GROUP(intc_ex_irq1),
4272 SH_PFC_PIN_GROUP(intc_ex_irq2),
4273 SH_PFC_PIN_GROUP(intc_ex_irq3),
4274 SH_PFC_PIN_GROUP(intc_ex_irq4),
4275 SH_PFC_PIN_GROUP(intc_ex_irq5),
4276 SH_PFC_PIN_GROUP(msiof0_clk),
4277 SH_PFC_PIN_GROUP(msiof0_sync),
4278 SH_PFC_PIN_GROUP(msiof0_ss1),
4279 SH_PFC_PIN_GROUP(msiof0_ss2),
4280 SH_PFC_PIN_GROUP(msiof0_txd),
4281 SH_PFC_PIN_GROUP(msiof0_rxd),
4282 SH_PFC_PIN_GROUP(msiof1_clk_a),
4283 SH_PFC_PIN_GROUP(msiof1_sync_a),
4284 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4285 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4286 SH_PFC_PIN_GROUP(msiof1_txd_a),
4287 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4288 SH_PFC_PIN_GROUP(msiof1_clk_b),
4289 SH_PFC_PIN_GROUP(msiof1_sync_b),
4290 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4291 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4292 SH_PFC_PIN_GROUP(msiof1_txd_b),
4293 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4294 SH_PFC_PIN_GROUP(msiof1_clk_c),
4295 SH_PFC_PIN_GROUP(msiof1_sync_c),
4296 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4297 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4298 SH_PFC_PIN_GROUP(msiof1_txd_c),
4299 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4300 SH_PFC_PIN_GROUP(msiof1_clk_d),
4301 SH_PFC_PIN_GROUP(msiof1_sync_d),
4302 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4303 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4304 SH_PFC_PIN_GROUP(msiof1_txd_d),
4305 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4306 SH_PFC_PIN_GROUP(msiof1_clk_e),
4307 SH_PFC_PIN_GROUP(msiof1_sync_e),
4308 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4309 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4310 SH_PFC_PIN_GROUP(msiof1_txd_e),
4311 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4312 SH_PFC_PIN_GROUP(msiof1_clk_f),
4313 SH_PFC_PIN_GROUP(msiof1_sync_f),
4314 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4315 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4316 SH_PFC_PIN_GROUP(msiof1_txd_f),
4317 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4318 SH_PFC_PIN_GROUP(msiof1_clk_g),
4319 SH_PFC_PIN_GROUP(msiof1_sync_g),
4320 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4321 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4322 SH_PFC_PIN_GROUP(msiof1_txd_g),
4323 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4324 SH_PFC_PIN_GROUP(msiof2_clk_a),
4325 SH_PFC_PIN_GROUP(msiof2_sync_a),
4326 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4327 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4328 SH_PFC_PIN_GROUP(msiof2_txd_a),
4329 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4330 SH_PFC_PIN_GROUP(msiof2_clk_b),
4331 SH_PFC_PIN_GROUP(msiof2_sync_b),
4332 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4333 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4334 SH_PFC_PIN_GROUP(msiof2_txd_b),
4335 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4336 SH_PFC_PIN_GROUP(msiof2_clk_c),
4337 SH_PFC_PIN_GROUP(msiof2_sync_c),
4338 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4339 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4340 SH_PFC_PIN_GROUP(msiof2_txd_c),
4341 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4342 SH_PFC_PIN_GROUP(msiof2_clk_d),
4343 SH_PFC_PIN_GROUP(msiof2_sync_d),
4344 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4345 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4346 SH_PFC_PIN_GROUP(msiof2_txd_d),
4347 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4348 SH_PFC_PIN_GROUP(msiof3_clk_a),
4349 SH_PFC_PIN_GROUP(msiof3_sync_a),
4350 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4351 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4352 SH_PFC_PIN_GROUP(msiof3_txd_a),
4353 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4354 SH_PFC_PIN_GROUP(msiof3_clk_b),
4355 SH_PFC_PIN_GROUP(msiof3_sync_b),
4356 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4357 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4358 SH_PFC_PIN_GROUP(msiof3_txd_b),
4359 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4360 SH_PFC_PIN_GROUP(msiof3_clk_c),
4361 SH_PFC_PIN_GROUP(msiof3_sync_c),
4362 SH_PFC_PIN_GROUP(msiof3_txd_c),
4363 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4364 SH_PFC_PIN_GROUP(msiof3_clk_d),
4365 SH_PFC_PIN_GROUP(msiof3_sync_d),
4366 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4367 SH_PFC_PIN_GROUP(msiof3_txd_d),
4368 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4369 SH_PFC_PIN_GROUP(msiof3_clk_e),
4370 SH_PFC_PIN_GROUP(msiof3_sync_e),
4371 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4372 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4373 SH_PFC_PIN_GROUP(msiof3_txd_e),
4374 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4375 SH_PFC_PIN_GROUP(pwm0),
4376 SH_PFC_PIN_GROUP(pwm1_a),
4377 SH_PFC_PIN_GROUP(pwm1_b),
4378 SH_PFC_PIN_GROUP(pwm2_a),
4379 SH_PFC_PIN_GROUP(pwm2_b),
4380 SH_PFC_PIN_GROUP(pwm3_a),
4381 SH_PFC_PIN_GROUP(pwm3_b),
4382 SH_PFC_PIN_GROUP(pwm4_a),
4383 SH_PFC_PIN_GROUP(pwm4_b),
4384 SH_PFC_PIN_GROUP(pwm5_a),
4385 SH_PFC_PIN_GROUP(pwm5_b),
4386 SH_PFC_PIN_GROUP(pwm6_a),
4387 SH_PFC_PIN_GROUP(pwm6_b),
4388 SH_PFC_PIN_GROUP(sata0_devslp_a),
4389 SH_PFC_PIN_GROUP(sata0_devslp_b),
4390 SH_PFC_PIN_GROUP(scif0_data),
4391 SH_PFC_PIN_GROUP(scif0_clk),
4392 SH_PFC_PIN_GROUP(scif0_ctrl),
4393 SH_PFC_PIN_GROUP(scif1_data_a),
4394 SH_PFC_PIN_GROUP(scif1_clk),
4395 SH_PFC_PIN_GROUP(scif1_ctrl),
4396 SH_PFC_PIN_GROUP(scif1_data_b),
4397 SH_PFC_PIN_GROUP(scif2_data_a),
4398 SH_PFC_PIN_GROUP(scif2_clk),
4399 SH_PFC_PIN_GROUP(scif2_data_b),
4400 SH_PFC_PIN_GROUP(scif3_data_a),
4401 SH_PFC_PIN_GROUP(scif3_clk),
4402 SH_PFC_PIN_GROUP(scif3_ctrl),
4403 SH_PFC_PIN_GROUP(scif3_data_b),
4404 SH_PFC_PIN_GROUP(scif4_data_a),
4405 SH_PFC_PIN_GROUP(scif4_clk_a),
4406 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4407 SH_PFC_PIN_GROUP(scif4_data_b),
4408 SH_PFC_PIN_GROUP(scif4_clk_b),
4409 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4410 SH_PFC_PIN_GROUP(scif4_data_c),
4411 SH_PFC_PIN_GROUP(scif4_clk_c),
4412 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4413 SH_PFC_PIN_GROUP(scif5_data_a),
4414 SH_PFC_PIN_GROUP(scif5_clk_a),
4415 SH_PFC_PIN_GROUP(scif5_data_b),
4416 SH_PFC_PIN_GROUP(scif5_clk_b),
4417 SH_PFC_PIN_GROUP(scif_clk_a),
4418 SH_PFC_PIN_GROUP(scif_clk_b),
4419 SH_PFC_PIN_GROUP(sdhi0_data1),
4420 SH_PFC_PIN_GROUP(sdhi0_data4),
4421 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4422 SH_PFC_PIN_GROUP(sdhi0_cd),
4423 SH_PFC_PIN_GROUP(sdhi0_wp),
4424 SH_PFC_PIN_GROUP(sdhi1_data1),
4425 SH_PFC_PIN_GROUP(sdhi1_data4),
4426 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4427 SH_PFC_PIN_GROUP(sdhi1_cd),
4428 SH_PFC_PIN_GROUP(sdhi1_wp),
4429 SH_PFC_PIN_GROUP(sdhi2_data1),
4430 SH_PFC_PIN_GROUP(sdhi2_data4),
4431 SH_PFC_PIN_GROUP(sdhi2_data8),
4432 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4433 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4434 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4435 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4436 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4437 SH_PFC_PIN_GROUP(sdhi2_ds),
4438 SH_PFC_PIN_GROUP(sdhi3_data1),
4439 SH_PFC_PIN_GROUP(sdhi3_data4),
4440 SH_PFC_PIN_GROUP(sdhi3_data8),
4441 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4442 SH_PFC_PIN_GROUP(sdhi3_cd),
4443 SH_PFC_PIN_GROUP(sdhi3_wp),
4444 SH_PFC_PIN_GROUP(sdhi3_ds),
4445 SH_PFC_PIN_GROUP(ssi0_data),
4446 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4447 SH_PFC_PIN_GROUP(ssi1_data_a),
4448 SH_PFC_PIN_GROUP(ssi1_data_b),
4449 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4450 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4451 SH_PFC_PIN_GROUP(ssi2_data_a),
4452 SH_PFC_PIN_GROUP(ssi2_data_b),
4453 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4454 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4455 SH_PFC_PIN_GROUP(ssi3_data),
4456 SH_PFC_PIN_GROUP(ssi349_ctrl),
4457 SH_PFC_PIN_GROUP(ssi4_data),
4458 SH_PFC_PIN_GROUP(ssi4_ctrl),
4459 SH_PFC_PIN_GROUP(ssi5_data),
4460 SH_PFC_PIN_GROUP(ssi5_ctrl),
4461 SH_PFC_PIN_GROUP(ssi6_data),
4462 SH_PFC_PIN_GROUP(ssi6_ctrl),
4463 SH_PFC_PIN_GROUP(ssi7_data),
4464 SH_PFC_PIN_GROUP(ssi78_ctrl),
4465 SH_PFC_PIN_GROUP(ssi8_data),
4466 SH_PFC_PIN_GROUP(ssi9_data_a),
4467 SH_PFC_PIN_GROUP(ssi9_data_b),
4468 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4469 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4470 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4471 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4472 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4473 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4474 SH_PFC_PIN_GROUP(usb0),
4475 SH_PFC_PIN_GROUP(usb1),
4476 SH_PFC_PIN_GROUP(usb2),
4477 SH_PFC_PIN_GROUP(usb2_ch3),
4478 SH_PFC_PIN_GROUP(usb30),
4479 VIN_DATA_PIN_GROUP(vin4_data_a, 8),
4480 VIN_DATA_PIN_GROUP(vin4_data_a, 10),
4481 VIN_DATA_PIN_GROUP(vin4_data_a, 12),
4482 VIN_DATA_PIN_GROUP(vin4_data_a, 16),
4483 SH_PFC_PIN_GROUP(vin4_data18_a),
4484 VIN_DATA_PIN_GROUP(vin4_data_a, 20),
4485 VIN_DATA_PIN_GROUP(vin4_data_a, 24),
4486 VIN_DATA_PIN_GROUP(vin4_data_b, 8),
4487 VIN_DATA_PIN_GROUP(vin4_data_b, 10),
4488 VIN_DATA_PIN_GROUP(vin4_data_b, 12),
4489 VIN_DATA_PIN_GROUP(vin4_data_b, 16),
4490 SH_PFC_PIN_GROUP(vin4_data18_b),
4491 VIN_DATA_PIN_GROUP(vin4_data_b, 20),
4492 VIN_DATA_PIN_GROUP(vin4_data_b, 24),
4493 SH_PFC_PIN_GROUP(vin4_sync),
4494 SH_PFC_PIN_GROUP(vin4_field),
4495 SH_PFC_PIN_GROUP(vin4_clkenb),
4496 SH_PFC_PIN_GROUP(vin4_clk),
4497 SH_PFC_PIN_GROUP(vin5_data8),
4498 SH_PFC_PIN_GROUP(vin5_data10),
4499 SH_PFC_PIN_GROUP(vin5_data12),
4500 SH_PFC_PIN_GROUP(vin5_data16),
4501 SH_PFC_PIN_GROUP(vin5_sync),
4502 SH_PFC_PIN_GROUP(vin5_field),
4503 SH_PFC_PIN_GROUP(vin5_clkenb),
4504 SH_PFC_PIN_GROUP(vin5_clk),
4507 static const char * const audio_clk_groups[] = {
4527 static const char * const avb_groups[] = {
4531 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4536 "avb_avtp_capture_a",
4538 "avb_avtp_capture_b",
4541 static const char * const can0_groups[] = {
4546 static const char * const can1_groups[] = {
4550 static const char * const can_clk_groups[] = {
4554 static const char * const canfd0_groups[] = {
4559 static const char * const canfd1_groups[] = {
4563 static const char * const drif0_groups[] = {
4575 static const char * const drif1_groups[] = {
4587 static const char * const drif2_groups[] = {
4596 static const char * const drif3_groups[] = {
4605 static const char * const du_groups[] = {
4616 static const char * const hdmi0_groups[] = {
4620 static const char * const hdmi1_groups[] = {
4624 static const char * const hscif0_groups[] = {
4630 static const char * const hscif1_groups[] = {
4639 static const char * const hscif2_groups[] = {
4651 static const char * const hscif3_groups[] = {
4660 static const char * const hscif4_groups[] = {
4667 static const char * const i2c1_groups[] = {
4672 static const char * const i2c2_groups[] = {
4677 static const char * const i2c6_groups[] = {
4683 static const char * const intc_ex_groups[] = {
4692 static const char * const msiof0_groups[] = {
4701 static const char * const msiof1_groups[] = {
4746 static const char * const msiof2_groups[] = {
4773 static const char * const msiof3_groups[] = {
4803 static const char * const pwm0_groups[] = {
4807 static const char * const pwm1_groups[] = {
4812 static const char * const pwm2_groups[] = {
4817 static const char * const pwm3_groups[] = {
4822 static const char * const pwm4_groups[] = {
4827 static const char * const pwm5_groups[] = {
4832 static const char * const pwm6_groups[] = {
4837 static const char * const sata0_groups[] = {
4842 static const char * const scif0_groups[] = {
4848 static const char * const scif1_groups[] = {
4855 static const char * const scif2_groups[] = {
4861 static const char * const scif3_groups[] = {
4868 static const char * const scif4_groups[] = {
4880 static const char * const scif5_groups[] = {
4887 static const char * const scif_clk_groups[] = {
4892 static const char * const sdhi0_groups[] = {
4900 static const char * const sdhi1_groups[] = {
4908 static const char * const sdhi2_groups[] = {
4920 static const char * const sdhi3_groups[] = {
4930 static const char * const ssi_groups[] = {
4958 static const char * const tmu_groups[] = {
4965 static const char * const usb0_groups[] = {
4969 static const char * const usb1_groups[] = {
4973 static const char * const usb2_groups[] = {
4977 static const char * const usb2_ch3_groups[] = {
4981 static const char * const usb30_groups[] = {
4985 static const char * const vin4_groups[] = {
5006 static const char * const vin5_groups[] = {
5017 static const struct sh_pfc_function pinmux_functions[] = {
5018 SH_PFC_FUNCTION(audio_clk),
5019 SH_PFC_FUNCTION(avb),
5020 SH_PFC_FUNCTION(can0),
5021 SH_PFC_FUNCTION(can1),
5022 SH_PFC_FUNCTION(can_clk),
5023 SH_PFC_FUNCTION(canfd0),
5024 SH_PFC_FUNCTION(canfd1),
5025 SH_PFC_FUNCTION(drif0),
5026 SH_PFC_FUNCTION(drif1),
5027 SH_PFC_FUNCTION(drif2),
5028 SH_PFC_FUNCTION(drif3),
5029 SH_PFC_FUNCTION(du),
5030 SH_PFC_FUNCTION(hdmi0),
5031 SH_PFC_FUNCTION(hdmi1),
5032 SH_PFC_FUNCTION(hscif0),
5033 SH_PFC_FUNCTION(hscif1),
5034 SH_PFC_FUNCTION(hscif2),
5035 SH_PFC_FUNCTION(hscif3),
5036 SH_PFC_FUNCTION(hscif4),
5037 SH_PFC_FUNCTION(i2c1),
5038 SH_PFC_FUNCTION(i2c2),
5039 SH_PFC_FUNCTION(i2c6),
5040 SH_PFC_FUNCTION(intc_ex),
5041 SH_PFC_FUNCTION(msiof0),
5042 SH_PFC_FUNCTION(msiof1),
5043 SH_PFC_FUNCTION(msiof2),
5044 SH_PFC_FUNCTION(msiof3),
5045 SH_PFC_FUNCTION(pwm0),
5046 SH_PFC_FUNCTION(pwm1),
5047 SH_PFC_FUNCTION(pwm2),
5048 SH_PFC_FUNCTION(pwm3),
5049 SH_PFC_FUNCTION(pwm4),
5050 SH_PFC_FUNCTION(pwm5),
5051 SH_PFC_FUNCTION(pwm6),
5052 SH_PFC_FUNCTION(sata0),
5053 SH_PFC_FUNCTION(scif0),
5054 SH_PFC_FUNCTION(scif1),
5055 SH_PFC_FUNCTION(scif2),
5056 SH_PFC_FUNCTION(scif3),
5057 SH_PFC_FUNCTION(scif4),
5058 SH_PFC_FUNCTION(scif5),
5059 SH_PFC_FUNCTION(scif_clk),
5060 SH_PFC_FUNCTION(sdhi0),
5061 SH_PFC_FUNCTION(sdhi1),
5062 SH_PFC_FUNCTION(sdhi2),
5063 SH_PFC_FUNCTION(sdhi3),
5064 SH_PFC_FUNCTION(ssi),
5065 SH_PFC_FUNCTION(tmu),
5066 SH_PFC_FUNCTION(usb0),
5067 SH_PFC_FUNCTION(usb1),
5068 SH_PFC_FUNCTION(usb2),
5069 SH_PFC_FUNCTION(usb2_ch3),
5070 SH_PFC_FUNCTION(usb30),
5071 SH_PFC_FUNCTION(vin4),
5072 SH_PFC_FUNCTION(vin5),
5075 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5076 #define F_(x, y) FN_##y
5077 #define FM(x) FN_##x
5078 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
5095 GP_0_15_FN, GPSR0_15,
5096 GP_0_14_FN, GPSR0_14,
5097 GP_0_13_FN, GPSR0_13,
5098 GP_0_12_FN, GPSR0_12,
5099 GP_0_11_FN, GPSR0_11,
5100 GP_0_10_FN, GPSR0_10,
5110 GP_0_0_FN, GPSR0_0, }
5112 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
5116 GP_1_28_FN, GPSR1_28,
5117 GP_1_27_FN, GPSR1_27,
5118 GP_1_26_FN, GPSR1_26,
5119 GP_1_25_FN, GPSR1_25,
5120 GP_1_24_FN, GPSR1_24,
5121 GP_1_23_FN, GPSR1_23,
5122 GP_1_22_FN, GPSR1_22,
5123 GP_1_21_FN, GPSR1_21,
5124 GP_1_20_FN, GPSR1_20,
5125 GP_1_19_FN, GPSR1_19,
5126 GP_1_18_FN, GPSR1_18,
5127 GP_1_17_FN, GPSR1_17,
5128 GP_1_16_FN, GPSR1_16,
5129 GP_1_15_FN, GPSR1_15,
5130 GP_1_14_FN, GPSR1_14,
5131 GP_1_13_FN, GPSR1_13,
5132 GP_1_12_FN, GPSR1_12,
5133 GP_1_11_FN, GPSR1_11,
5134 GP_1_10_FN, GPSR1_10,
5144 GP_1_0_FN, GPSR1_0, }
5146 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
5164 GP_2_14_FN, GPSR2_14,
5165 GP_2_13_FN, GPSR2_13,
5166 GP_2_12_FN, GPSR2_12,
5167 GP_2_11_FN, GPSR2_11,
5168 GP_2_10_FN, GPSR2_10,
5178 GP_2_0_FN, GPSR2_0, }
5180 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
5197 GP_3_15_FN, GPSR3_15,
5198 GP_3_14_FN, GPSR3_14,
5199 GP_3_13_FN, GPSR3_13,
5200 GP_3_12_FN, GPSR3_12,
5201 GP_3_11_FN, GPSR3_11,
5202 GP_3_10_FN, GPSR3_10,
5212 GP_3_0_FN, GPSR3_0, }
5214 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
5229 GP_4_17_FN, GPSR4_17,
5230 GP_4_16_FN, GPSR4_16,
5231 GP_4_15_FN, GPSR4_15,
5232 GP_4_14_FN, GPSR4_14,
5233 GP_4_13_FN, GPSR4_13,
5234 GP_4_12_FN, GPSR4_12,
5235 GP_4_11_FN, GPSR4_11,
5236 GP_4_10_FN, GPSR4_10,
5246 GP_4_0_FN, GPSR4_0, }
5248 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
5255 GP_5_25_FN, GPSR5_25,
5256 GP_5_24_FN, GPSR5_24,
5257 GP_5_23_FN, GPSR5_23,
5258 GP_5_22_FN, GPSR5_22,
5259 GP_5_21_FN, GPSR5_21,
5260 GP_5_20_FN, GPSR5_20,
5261 GP_5_19_FN, GPSR5_19,
5262 GP_5_18_FN, GPSR5_18,
5263 GP_5_17_FN, GPSR5_17,
5264 GP_5_16_FN, GPSR5_16,
5265 GP_5_15_FN, GPSR5_15,
5266 GP_5_14_FN, GPSR5_14,
5267 GP_5_13_FN, GPSR5_13,
5268 GP_5_12_FN, GPSR5_12,
5269 GP_5_11_FN, GPSR5_11,
5270 GP_5_10_FN, GPSR5_10,
5280 GP_5_0_FN, GPSR5_0, }
5282 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
5283 GP_6_31_FN, GPSR6_31,
5284 GP_6_30_FN, GPSR6_30,
5285 GP_6_29_FN, GPSR6_29,
5286 GP_6_28_FN, GPSR6_28,
5287 GP_6_27_FN, GPSR6_27,
5288 GP_6_26_FN, GPSR6_26,
5289 GP_6_25_FN, GPSR6_25,
5290 GP_6_24_FN, GPSR6_24,
5291 GP_6_23_FN, GPSR6_23,
5292 GP_6_22_FN, GPSR6_22,
5293 GP_6_21_FN, GPSR6_21,
5294 GP_6_20_FN, GPSR6_20,
5295 GP_6_19_FN, GPSR6_19,
5296 GP_6_18_FN, GPSR6_18,
5297 GP_6_17_FN, GPSR6_17,
5298 GP_6_16_FN, GPSR6_16,
5299 GP_6_15_FN, GPSR6_15,
5300 GP_6_14_FN, GPSR6_14,
5301 GP_6_13_FN, GPSR6_13,
5302 GP_6_12_FN, GPSR6_12,
5303 GP_6_11_FN, GPSR6_11,
5304 GP_6_10_FN, GPSR6_10,
5314 GP_6_0_FN, GPSR6_0, }
5316 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
5348 GP_7_0_FN, GPSR7_0, }
5354 #define FM(x) FN_##x,
5355 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5365 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5375 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5385 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5395 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5405 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5415 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5425 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5430 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5435 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5445 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5455 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5465 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5475 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5485 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5495 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5505 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5515 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5525 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5535 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5536 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5537 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5538 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5539 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5540 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5541 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5549 #define FM(x) FN_##x,
5550 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5551 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5552 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5563 0, 0, /* RESERVED 15 */
5572 /* RESERVED 2, 1, 0 */
5573 0, 0, 0, 0, 0, 0, 0, 0 }
5575 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5576 2, 3, 1, 2, 3, 1, 1, 2, 1,
5577 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5593 0, 0, 0, 0, /* RESERVED 8, 7 */
5602 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5603 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5620 /* RESERVED 15, 14, 13, 12 */
5621 0, 0, 0, 0, 0, 0, 0, 0,
5622 0, 0, 0, 0, 0, 0, 0, 0,
5623 /* RESERVED 11, 10, 9, 8 */
5624 0, 0, 0, 0, 0, 0, 0, 0,
5625 0, 0, 0, 0, 0, 0, 0, 0,
5626 /* RESERVED 7, 6, 5, 4 */
5627 0, 0, 0, 0, 0, 0, 0, 0,
5628 0, 0, 0, 0, 0, 0, 0, 0,
5629 /* RESERVED 3, 2, 1 */
5630 0, 0, 0, 0, 0, 0, 0, 0,
5636 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5637 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5638 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5639 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5640 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5641 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5642 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5643 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5644 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5645 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5647 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5648 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5649 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5650 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5651 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5652 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5653 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5654 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5655 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5657 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5658 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5659 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5660 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5661 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5662 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5663 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5664 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5665 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5667 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5668 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5669 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5670 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5671 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5672 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5673 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5674 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5675 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5677 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5678 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5679 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5680 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5681 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5682 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5683 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5684 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5685 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5687 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5688 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5689 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5690 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5691 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5692 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5693 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5694 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5695 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5697 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5698 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5699 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5700 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5701 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5702 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5703 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5704 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5705 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5707 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5708 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5709 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5710 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5711 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5712 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5713 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5714 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5715 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5717 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5718 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5719 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5720 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5721 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5722 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5723 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5724 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5725 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5727 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5728 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5729 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5730 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5731 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5732 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5733 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5734 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5735 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5737 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5738 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5739 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5740 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5741 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5742 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5743 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5744 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5745 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5747 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5748 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5749 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5750 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5751 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5752 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5753 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
5754 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5755 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5757 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5758 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5759 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5760 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5761 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5763 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5764 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5765 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5766 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5767 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5768 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5769 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5770 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5771 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5773 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5774 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5775 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5776 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5777 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5778 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5779 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5780 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5781 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5783 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5784 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5785 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5786 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5787 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5788 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5789 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5790 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5791 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5793 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5794 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5795 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5796 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5797 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5798 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5799 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5800 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5801 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5803 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5804 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5805 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5806 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5807 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5808 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5809 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5810 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5811 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5813 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5814 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5815 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5816 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5817 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5818 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5819 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5820 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5821 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5823 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5824 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5825 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5826 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5827 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5828 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5829 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5830 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5831 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5833 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5834 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5835 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5836 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5837 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5838 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5839 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5840 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5841 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5843 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5844 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5845 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5846 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5847 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5848 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5849 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5850 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5851 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5853 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5854 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5855 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5856 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5857 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5858 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5859 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5860 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5861 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5863 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5864 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5865 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5866 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5867 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5868 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5869 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5870 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5871 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5873 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5874 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5875 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5876 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5877 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5878 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5879 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
5880 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
5889 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5890 [POCCTRL] = { 0xe6060380, },
5894 static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5898 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5900 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5903 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5904 bit = (pin & 0x1f) + 12;
5909 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5910 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5911 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5912 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5913 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5914 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5915 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5916 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5917 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5918 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5919 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5920 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5921 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5922 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5923 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5924 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5925 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5926 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5927 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5928 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5929 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5930 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5931 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5932 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5933 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5934 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5935 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5936 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5937 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5938 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5939 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5940 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5941 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5942 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5944 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5945 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5946 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5947 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5948 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5949 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5950 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5951 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5952 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5953 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5954 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5955 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5956 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5957 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5958 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5959 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5960 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5961 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5962 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5963 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5964 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5965 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5966 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5967 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5968 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5969 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5970 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5971 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5972 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5973 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5974 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5975 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5976 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5978 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5979 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5980 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5981 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5982 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5983 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5984 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5985 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5986 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5987 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5988 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5989 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5990 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5991 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5992 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5993 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5994 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5995 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5996 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5997 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5998 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5999 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6000 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6001 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6002 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6003 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6004 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6005 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6006 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
6007 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
6008 [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
6009 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
6010 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
6012 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6013 [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
6014 [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
6015 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
6016 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
6017 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
6018 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
6019 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
6020 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
6022 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
6023 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6024 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6025 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6026 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6027 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6028 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6029 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6030 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6031 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6032 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6033 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6034 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6035 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6036 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6037 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6038 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6039 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6040 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6041 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6042 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6043 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6044 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6046 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6047 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6048 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6049 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6050 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6051 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6052 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6053 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6054 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6055 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6056 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6057 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6058 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6059 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6060 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6061 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6062 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6063 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6064 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6065 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6066 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6067 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6068 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6069 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6070 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6071 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6072 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6073 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6074 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6075 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6076 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6077 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6078 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6080 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6081 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6082 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6083 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6084 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6085 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6086 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6087 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6088 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6089 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6090 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6091 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6092 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6093 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6094 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6095 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6096 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6097 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6098 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6099 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6100 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6101 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6102 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6103 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6104 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6105 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6106 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6107 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6108 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6109 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6110 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6111 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6112 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6114 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6115 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6116 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6117 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6118 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6119 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6120 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
6121 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
6151 static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
6154 const struct pinmux_bias_reg *reg;
6157 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6159 return PIN_CONFIG_BIAS_DISABLE;
6161 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6162 return PIN_CONFIG_BIAS_DISABLE;
6163 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6164 return PIN_CONFIG_BIAS_PULL_UP;
6166 return PIN_CONFIG_BIAS_PULL_DOWN;
6169 static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6172 const struct pinmux_bias_reg *reg;
6176 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6180 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6181 if (bias != PIN_CONFIG_BIAS_DISABLE)
6184 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6185 if (bias == PIN_CONFIG_BIAS_PULL_UP)
6188 sh_pfc_write(pfc, reg->pud, updown);
6189 sh_pfc_write(pfc, reg->puen, enable);
6192 static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
6193 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
6194 .get_bias = r8a7795_pinmux_get_bias,
6195 .set_bias = r8a7795_pinmux_set_bias,
6198 const struct sh_pfc_soc_info r8a7795_pinmux_info = {
6199 .name = "r8a77951_pfc",
6200 .ops = &r8a7795_pinmux_ops,
6201 .unlock_reg = 0xe6060000, /* PMMR */
6203 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6205 .pins = pinmux_pins,
6206 .nr_pins = ARRAY_SIZE(pinmux_pins),
6207 .groups = pinmux_groups,
6208 .nr_groups = ARRAY_SIZE(pinmux_groups),
6209 .functions = pinmux_functions,
6210 .nr_functions = ARRAY_SIZE(pinmux_functions),
6212 .cfg_regs = pinmux_config_regs,
6213 .drive_regs = pinmux_drive_regs,
6214 .bias_regs = pinmux_bias_regs,
6215 .ioctrl_regs = pinmux_ioctrl_regs,
6217 .pinmux_data = pinmux_data,
6218 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
projects / platform / kernel / u-boot.git / blob