drivers/pinctrl/renesas/pfc-r8a7795.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A7795 ES2.0+ processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2015-2017 Renesas Electronics Corporation
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <dm/pinctrl.h>
  12 #include <linux/kernel.h>
  13
  14 #include "sh_pfc.h"
  15
  16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  17                    SH_PFC_PIN_CFG_PULL_UP | \
  18                    SH_PFC_PIN_CFG_PULL_DOWN)
  19
  20 #define CPU_ALL_PORT(fn, sfx)                                           \
  21         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  22         PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
  23         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  24         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  25         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  26         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  27         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  28         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  29         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  30         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  31         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  32         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  33 /*
  34  * F_() : just information
  35  * FM() : macro for FN_xxx / xxx_MARK
  36  */
  37
  38 /* GPSR0 */
  39 #define GPSR0_15        F_(D15,                 IP7_11_8)
  40 #define GPSR0_14        F_(D14,                 IP7_7_4)
  41 #define GPSR0_13        F_(D13,                 IP7_3_0)
  42 #define GPSR0_12        F_(D12,                 IP6_31_28)
  43 #define GPSR0_11        F_(D11,                 IP6_27_24)
  44 #define GPSR0_10        F_(D10,                 IP6_23_20)
  45 #define GPSR0_9         F_(D9,                  IP6_19_16)
  46 #define GPSR0_8         F_(D8,                  IP6_15_12)
  47 #define GPSR0_7         F_(D7,                  IP6_11_8)
  48 #define GPSR0_6         F_(D6,                  IP6_7_4)
  49 #define GPSR0_5         F_(D5,                  IP6_3_0)
  50 #define GPSR0_4         F_(D4,                  IP5_31_28)
  51 #define GPSR0_3         F_(D3,                  IP5_27_24)
  52 #define GPSR0_2         F_(D2,                  IP5_23_20)
  53 #define GPSR0_1         F_(D1,                  IP5_19_16)
  54 #define GPSR0_0         F_(D0,                  IP5_15_12)
  55
  56 /* GPSR1 */
  57 #define GPSR1_28        FM(CLKOUT)
  58 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  59 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  60 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  61 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  62 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  63 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  64 #define GPSR1_21        F_(CS1_N,               IP4_19_16)
  65 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  66 #define GPSR1_19        F_(A19,                 IP4_11_8)
  67 #define GPSR1_18        F_(A18,                 IP4_7_4)
  68 #define GPSR1_17        F_(A17,                 IP4_3_0)
  69 #define GPSR1_16        F_(A16,                 IP3_31_28)
  70 #define GPSR1_15        F_(A15,                 IP3_27_24)
  71 #define GPSR1_14        F_(A14,                 IP3_23_20)
  72 #define GPSR1_13        F_(A13,                 IP3_19_16)
  73 #define GPSR1_12        F_(A12,                 IP3_15_12)
  74 #define GPSR1_11        F_(A11,                 IP3_11_8)
  75 #define GPSR1_10        F_(A10,                 IP3_7_4)
  76 #define GPSR1_9         F_(A9,                  IP3_3_0)
  77 #define GPSR1_8         F_(A8,                  IP2_31_28)
  78 #define GPSR1_7         F_(A7,                  IP2_27_24)
  79 #define GPSR1_6         F_(A6,                  IP2_23_20)
  80 #define GPSR1_5         F_(A5,                  IP2_19_16)
  81 #define GPSR1_4         F_(A4,                  IP2_15_12)
  82 #define GPSR1_3         F_(A3,                  IP2_11_8)
  83 #define GPSR1_2         F_(A2,                  IP2_7_4)
  84 #define GPSR1_1         F_(A1,                  IP2_3_0)
  85 #define GPSR1_0         F_(A0,                  IP1_31_28)
  86
  87 /* GPSR2 */
  88 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  89 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  90 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  91 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  92 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
  93 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
  94 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
  95 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
  96 #define GPSR2_6         F_(PWM0,                IP1_19_16)
  97 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
  98 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
  99 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
 100 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
 101 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
 102 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
 103
 104 /* GPSR3 */
 105 #define GPSR3_15        F_(SD1_WP,              IP11_23_20)
 106 #define GPSR3_14        F_(SD1_CD,              IP11_19_16)
 107 #define GPSR3_13        F_(SD0_WP,              IP11_15_12)
 108 #define GPSR3_12        F_(SD0_CD,              IP11_11_8)
 109 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 110 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 111 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 112 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 113 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 114 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 115 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 116 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 117 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 118 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 119 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 120 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 121
 122 /* GPSR4 */
 123 #define GPSR4_17        F_(SD3_DS,              IP11_7_4)
 124 #define GPSR4_16        F_(SD3_DAT7,            IP11_3_0)
 125 #define GPSR4_15        F_(SD3_DAT6,            IP10_31_28)
 126 #define GPSR4_14        F_(SD3_DAT5,            IP10_27_24)
 127 #define GPSR4_13        F_(SD3_DAT4,            IP10_23_20)
 128 #define GPSR4_12        F_(SD3_DAT3,            IP10_19_16)
 129 #define GPSR4_11        F_(SD3_DAT2,            IP10_15_12)
 130 #define GPSR4_10        F_(SD3_DAT1,            IP10_11_8)
 131 #define GPSR4_9         F_(SD3_DAT0,            IP10_7_4)
 132 #define GPSR4_8         F_(SD3_CMD,             IP10_3_0)
 133 #define GPSR4_7         F_(SD3_CLK,             IP9_31_28)
 134 #define GPSR4_6         F_(SD2_DS,              IP9_27_24)
 135 #define GPSR4_5         F_(SD2_DAT3,            IP9_23_20)
 136 #define GPSR4_4         F_(SD2_DAT2,            IP9_19_16)
 137 #define GPSR4_3         F_(SD2_DAT1,            IP9_15_12)
 138 #define GPSR4_2         F_(SD2_DAT0,            IP9_11_8)
 139 #define GPSR4_1         F_(SD2_CMD,             IP9_7_4)
 140 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 141
 142 /* GPSR5 */
 143 #define GPSR5_25        F_(MLB_DAT,             IP14_19_16)
 144 #define GPSR5_24        F_(MLB_SIG,             IP14_15_12)
 145 #define GPSR5_23        F_(MLB_CLK,             IP14_11_8)
 146 #define GPSR5_22        FM(MSIOF0_RXD)
 147 #define GPSR5_21        F_(MSIOF0_SS2,          IP14_7_4)
 148 #define GPSR5_20        FM(MSIOF0_TXD)
 149 #define GPSR5_19        F_(MSIOF0_SS1,          IP14_3_0)
 150 #define GPSR5_18        F_(MSIOF0_SYNC,         IP13_31_28)
 151 #define GPSR5_17        FM(MSIOF0_SCK)
 152 #define GPSR5_16        F_(HRTS0_N,             IP13_27_24)
 153 #define GPSR5_15        F_(HCTS0_N,             IP13_23_20)
 154 #define GPSR5_14        F_(HTX0,                IP13_19_16)
 155 #define GPSR5_13        F_(HRX0,                IP13_15_12)
 156 #define GPSR5_12        F_(HSCK0,               IP13_11_8)
 157 #define GPSR5_11        F_(RX2_A,               IP13_7_4)
 158 #define GPSR5_10        F_(TX2_A,               IP13_3_0)
 159 #define GPSR5_9         F_(SCK2,                IP12_31_28)
 160 #define GPSR5_8         F_(RTS1_N,              IP12_27_24)
 161 #define GPSR5_7         F_(CTS1_N,              IP12_23_20)
 162 #define GPSR5_6         F_(TX1_A,               IP12_19_16)
 163 #define GPSR5_5         F_(RX1_A,               IP12_15_12)
 164 #define GPSR5_4         F_(RTS0_N,              IP12_11_8)
 165 #define GPSR5_3         F_(CTS0_N,              IP12_7_4)
 166 #define GPSR5_2         F_(TX0,                 IP12_3_0)
 167 #define GPSR5_1         F_(RX0,                 IP11_31_28)
 168 #define GPSR5_0         F_(SCK0,                IP11_27_24)
 169
 170 /* GPSR6 */
 171 #define GPSR6_31        F_(USB2_CH3_OVC,        IP18_7_4)
 172 #define GPSR6_30        F_(USB2_CH3_PWEN,       IP18_3_0)
 173 #define GPSR6_29        F_(USB30_OVC,           IP17_31_28)
 174 #define GPSR6_28        F_(USB30_PWEN,          IP17_27_24)
 175 #define GPSR6_27        F_(USB1_OVC,            IP17_23_20)
 176 #define GPSR6_26        F_(USB1_PWEN,           IP17_19_16)
 177 #define GPSR6_25        F_(USB0_OVC,            IP17_15_12)
 178 #define GPSR6_24        F_(USB0_PWEN,           IP17_11_8)
 179 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP17_7_4)
 180 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP17_3_0)
 181 #define GPSR6_21        F_(SSI_SDATA9_A,        IP16_31_28)
 182 #define GPSR6_20        F_(SSI_SDATA8,          IP16_27_24)
 183 #define GPSR6_19        F_(SSI_SDATA7,          IP16_23_20)
 184 #define GPSR6_18        F_(SSI_WS78,            IP16_19_16)
 185 #define GPSR6_17        F_(SSI_SCK78,           IP16_15_12)
 186 #define GPSR6_16        F_(SSI_SDATA6,          IP16_11_8)
 187 #define GPSR6_15        F_(SSI_WS6,             IP16_7_4)
 188 #define GPSR6_14        F_(SSI_SCK6,            IP16_3_0)
 189 #define GPSR6_13        FM(SSI_SDATA5)
 190 #define GPSR6_12        FM(SSI_WS5)
 191 #define GPSR6_11        FM(SSI_SCK5)
 192 #define GPSR6_10        F_(SSI_SDATA4,          IP15_31_28)
 193 #define GPSR6_9         F_(SSI_WS4,             IP15_27_24)
 194 #define GPSR6_8         F_(SSI_SCK4,            IP15_23_20)
 195 #define GPSR6_7         F_(SSI_SDATA3,          IP15_19_16)
 196 #define GPSR6_6         F_(SSI_WS349,           IP15_15_12)
 197 #define GPSR6_5         F_(SSI_SCK349,          IP15_11_8)
 198 #define GPSR6_4         F_(SSI_SDATA2_A,        IP15_7_4)
 199 #define GPSR6_3         F_(SSI_SDATA1_A,        IP15_3_0)
 200 #define GPSR6_2         F_(SSI_SDATA0,          IP14_31_28)
 201 #define GPSR6_1         F_(SSI_WS01239,         IP14_27_24)
 202 #define GPSR6_0         F_(SSI_SCK01239,                IP14_23_20)
 203
 204 /* GPSR7 */
 205 #define GPSR7_3         FM(HDMI1_CEC)
 206 #define GPSR7_2         FM(HDMI0_CEC)
 207 #define GPSR7_1         FM(AVS2)
 208 #define GPSR7_0         FM(AVS1)
 209
 210
 211 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 212 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 213 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 214 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 215 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 216 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        FM(FSCLKST2_N_A) F_(0, 0)               F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 217 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 218 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         FM(MSIOF3_SS2_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         FM(MSIOF3_SS1_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SYNC_E) F_(0, 0)              FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   F_(0, 0)                FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SCK_E) F_(0, 0)               FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    F_(0, 0)                FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_RXD_E) F_(0, 0)               FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    F_(0, 0)                FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)               FM(MSIOF3_TXD_E) F_(0, 0)               FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        F_(0, 0)                FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        F_(0, 0)                FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 229 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 231
 232 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 233 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_B)                    F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 244 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 245 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 246 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 247 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP4_19_16       FM(CS1_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N)                      FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_C)    FM(DU_DR3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274
 275 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 276 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 277 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 278 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       FM(NFCE_N_B)                    F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        FM(NFWP_N_B)                    F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        FM(NFDATA14_B)                  F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        FM(NFDATA15_B)                  F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        FM(NFRB_N_B)                    F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        FM(NFDATA8)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP9_7_4         FM(SD2_CMD)             F_(0, 0)        FM(NFDATA9)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP9_11_8        FM(SD2_DAT0)            F_(0, 0)        FM(NFDATA10)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP9_15_12       FM(SD2_DAT1)            F_(0, 0)        FM(NFDATA11)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP9_19_16       FM(SD2_DAT2)            F_(0, 0)        FM(NFDATA12)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP9_23_20       FM(SD2_DAT3)            F_(0, 0)        FM(NFDATA13)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP9_27_24       FM(SD2_DS)              F_(0, 0)        FM(NFALE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP9_31_28       FM(SD3_CLK)             F_(0, 0)        FM(NFWE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP10_3_0        FM(SD3_CMD)             F_(0, 0)        FM(NFRE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP10_7_4        FM(SD3_DAT0)            F_(0, 0)        FM(NFDATA0)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP10_11_8       FM(SD3_DAT1)            F_(0, 0)        FM(NFDATA1)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP10_15_12      FM(SD3_DAT2)            F_(0, 0)        FM(NFDATA2)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP10_19_16      FM(SD3_DAT3)            F_(0, 0)        FM(NFDATA3)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP10_23_20      FM(SD3_DAT4)            FM(SD2_CD_A)    FM(NFDATA4)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP10_27_24      FM(SD3_DAT5)            FM(SD2_WP_A)    FM(NFDATA5)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP10_31_28      FM(SD3_DAT6)            FM(SD3_CD)      FM(NFDATA6)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP11_3_0        FM(SD3_DAT7)            FM(SD3_WP)      FM(NFDATA7)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP11_7_4        FM(SD3_DS)              F_(0, 0)        FM(NFCLE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP11_11_8       FM(SD0_CD)              F_(0, 0)        FM(NFDATA14_A)          F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306
 307 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 308 #define IP11_15_12      FM(SD0_WP)              F_(0, 0)        FM(NFDATA15_A)          F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP11_19_16      FM(SD1_CD)              F_(0, 0)        FM(NFRB_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310 #define IP11_23_20      FM(SD1_WP)              F_(0, 0)        FM(NFCE_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311 #define IP11_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     FM(SCK5_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312 #define IP11_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 313 #define IP12_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 314 #define IP12_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315 #define IP12_11_8       FM(RTS0_N)              FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316 #define IP12_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317 #define IP12_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318 #define IP12_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319 #define IP12_27_24      FM(RTS1_N)              FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320 #define IP12_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP13_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP13_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP13_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        FM(RX5_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP13_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP13_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP13_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP13_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP13_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        FM(TX5_B)       F_(0, 0)        F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
 329 #define IP14_3_0        FM(MSIOF0_SS1)          FM(RX5_A)       FM(NFWP_N_A)            FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP14_7_4        FM(MSIOF0_SS2)          FM(TX5_A)       FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP14_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP14_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333 #define IP14_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334 #define IP14_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 335 #define IP14_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336
 337 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 338 #define IP14_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP15_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340 #define IP15_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341 #define IP15_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342 #define IP15_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 343 #define IP15_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 344 #define IP15_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP15_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP15_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP16_3_0        FM(SSI_SCK6)            FM(USB2_PWEN)   F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP16_7_4        FM(SSI_WS6)             FM(USB2_OVC)    F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP16_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP16_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP16_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352 #define IP16_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353 #define IP16_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354 #define IP16_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5_A)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355 #define IP17_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(CC5_OSCOUT)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 356 #define IP17_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 357 #define IP17_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
 358 #define IP17_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
 359 #define IP17_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
 360 #define IP17_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
 361 #define IP17_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 362 #define IP17_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_N)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 363 #define IP18_3_0        FM(USB2_CH3_PWEN)       F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
 364 #define IP18_7_4        FM(USB2_CH3_OVC)        F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
 365
 366 #define PINMUX_GPSR     \
 367 \
 368                                                                                                 GPSR6_31 \
 369                                                                                                 GPSR6_30 \
 370                                                                                                 GPSR6_29 \
 371                 GPSR1_28                                                                        GPSR6_28 \
 372                 GPSR1_27                                                                        GPSR6_27 \
 373                 GPSR1_26                                                                        GPSR6_26 \
 374                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 375                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 376                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 377                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 378                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 379                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 380                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 381                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 382                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 383                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 384 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 385 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 386 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 387 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 388 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 389 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 390 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 391 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 392 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 393 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 394 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 395 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 396 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 397 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 398 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 399 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 400
 401 #define PINMUX_IPSR                             \
 402 \
 403 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 404 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 405 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 406 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 407 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 408 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 409 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 410 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 411 \
 412 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 413 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 414 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 415 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12 \
 416 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 417 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 418 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 419 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 420 \
 421 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 422 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 423 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 424 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 425 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 426 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 427 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 428 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 429 \
 430 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 431 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 432 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 433 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 434 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 435 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 436 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 437 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 438 \
 439 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0        FM(IP18_3_0)    IP18_3_0 \
 440 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4        FM(IP18_7_4)    IP18_7_4 \
 441 FM(IP16_11_8)   IP16_11_8       FM(IP17_11_8)   IP17_11_8 \
 442 FM(IP16_15_12)  IP16_15_12      FM(IP17_15_12)  IP17_15_12 \
 443 FM(IP16_19_16)  IP16_19_16      FM(IP17_19_16)  IP17_19_16 \
 444 FM(IP16_23_20)  IP16_23_20      FM(IP17_23_20)  IP17_23_20 \
 445 FM(IP16_27_24)  IP16_27_24      FM(IP17_27_24)  IP17_27_24 \
 446 FM(IP16_31_28)  IP16_31_28      FM(IP17_31_28)  IP17_31_28
 447
 448 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 449 #define MOD_SEL0_31_30_29       FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)        FM(SEL_MSIOF3_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 450 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 451 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 452 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 453 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 454 #define MOD_SEL0_21             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 455 #define MOD_SEL0_20             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 456 #define MOD_SEL0_19             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 457 #define MOD_SEL0_18_17          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 458 #define MOD_SEL0_16             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 459 #define MOD_SEL0_14_13          FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)        FM(SEL_HSCIF2_2)        F_(0, 0)
 460 #define MOD_SEL0_12             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 461 #define MOD_SEL0_11             FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 462 #define MOD_SEL0_10             FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 463 #define MOD_SEL0_9_8            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 464 #define MOD_SEL0_7_6            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 465 #define MOD_SEL0_5              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 466 #define MOD_SEL0_4_3            FM(SEL_ADG_A_0)         FM(SEL_ADG_A_1)         FM(SEL_ADG_A_2)         FM(SEL_ADG_A_3)
 467
 468 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 469 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 470 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 471 #define MOD_SEL1_26             FM(SEL_TIMER_TMU1_0)    FM(SEL_TIMER_TMU1_1)
 472 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 473 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 474 #define MOD_SEL1_20             FM(SEL_SSI1_0)          FM(SEL_SSI1_1)
 475 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 476 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 477 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 478 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 479 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 480 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 481 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 482 #define MOD_SEL1_10             FM(SEL_SCIF_0)          FM(SEL_SCIF_1)
 483 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 484 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 485 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 486 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 487 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 488 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 489 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 490 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 491
 492 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */
 493 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 494 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 495 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 496 #define MOD_SEL2_28_27          FM(SEL_FM_0)            FM(SEL_FM_1)            FM(SEL_FM_2)            FM(SEL_FM_3)
 497 #define MOD_SEL2_26             FM(SEL_SCIF5_0)         FM(SEL_SCIF5_1)
 498 #define MOD_SEL2_25_24_23       FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)
 499 #define MOD_SEL2_21             FM(SEL_SSI2_0)          FM(SEL_SSI2_1)
 500 #define MOD_SEL2_20             FM(SEL_SSI9_0)          FM(SEL_SSI9_1)
 501 #define MOD_SEL2_19             FM(SEL_TIMER_TMU2_0)    FM(SEL_TIMER_TMU2_1)
 502 #define MOD_SEL2_18             FM(SEL_ADG_B_0)         FM(SEL_ADG_B_1)
 503 #define MOD_SEL2_17             FM(SEL_ADG_C_0)         FM(SEL_ADG_C_1)
 504 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 505
 506 #define PINMUX_MOD_SELS \
 507 \
 508 MOD_SEL0_31_30_29       MOD_SEL1_31_30          MOD_SEL2_31 \
 509                                                 MOD_SEL2_30 \
 510                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 511 MOD_SEL0_28_27                                  MOD_SEL2_28_27 \
 512 MOD_SEL0_26_25_24       MOD_SEL1_26             MOD_SEL2_26 \
 513                         MOD_SEL1_25_24          MOD_SEL2_25_24_23 \
 514 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 515 MOD_SEL0_22 \
 516 MOD_SEL0_21                                     MOD_SEL2_21 \
 517 MOD_SEL0_20             MOD_SEL1_20             MOD_SEL2_20 \
 518 MOD_SEL0_19             MOD_SEL1_19             MOD_SEL2_19 \
 519 MOD_SEL0_18_17          MOD_SEL1_18_17          MOD_SEL2_18 \
 520                                                 MOD_SEL2_17 \
 521 MOD_SEL0_16             MOD_SEL1_16 \
 522                         MOD_SEL1_15_14 \
 523 MOD_SEL0_14_13 \
 524                         MOD_SEL1_13 \
 525 MOD_SEL0_12             MOD_SEL1_12 \
 526 MOD_SEL0_11             MOD_SEL1_11 \
 527 MOD_SEL0_10             MOD_SEL1_10 \
 528 MOD_SEL0_9_8            MOD_SEL1_9 \
 529 MOD_SEL0_7_6 \
 530                         MOD_SEL1_6 \
 531 MOD_SEL0_5              MOD_SEL1_5 \
 532 MOD_SEL0_4_3            MOD_SEL1_4 \
 533                         MOD_SEL1_3 \
 534                         MOD_SEL1_2 \
 535                         MOD_SEL1_1 \
 536                         MOD_SEL1_0              MOD_SEL2_0
 537
 538 /*
 539  * These pins are not able to be muxed but have other properties
 540  * that can be set, such as drive-strength or pull-up/pull-down enable.
 541  */
 542 #define PINMUX_STATIC \
 543         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 544         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 545         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 546         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 547         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 548         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 549         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 550         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 551         FM(PRESETOUT) \
 552         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
 553         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 554
 555 #define PINMUX_PHYS \
 556         FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
 557
 558 enum {
 559         PINMUX_RESERVED = 0,
 560
 561         PINMUX_DATA_BEGIN,
 562         GP_ALL(DATA),
 563         PINMUX_DATA_END,
 564
 565 #define F_(x, y)
 566 #define FM(x)   FN_##x,
 567         PINMUX_FUNCTION_BEGIN,
 568         GP_ALL(FN),
 569         PINMUX_GPSR
 570         PINMUX_IPSR
 571         PINMUX_MOD_SELS
 572         PINMUX_FUNCTION_END,
 573 #undef F_
 574 #undef FM
 575
 576 #define F_(x, y)
 577 #define FM(x)   x##_MARK,
 578         PINMUX_MARK_BEGIN,
 579         PINMUX_GPSR
 580         PINMUX_IPSR
 581         PINMUX_MOD_SELS
 582         PINMUX_STATIC
 583         PINMUX_PHYS
 584         PINMUX_MARK_END,
 585 #undef F_
 586 #undef FM
 587 };
 588
 589 static const u16 pinmux_data[] = {
 590         PINMUX_DATA_GP_ALL(),
 591
 592         PINMUX_SINGLE(AVS1),
 593         PINMUX_SINGLE(AVS2),
 594         PINMUX_SINGLE(CLKOUT),
 595         PINMUX_SINGLE(HDMI0_CEC),
 596         PINMUX_SINGLE(HDMI1_CEC),
 597         PINMUX_SINGLE(MSIOF0_RXD),
 598         PINMUX_SINGLE(MSIOF0_SCK),
 599         PINMUX_SINGLE(MSIOF0_TXD),
 600         PINMUX_SINGLE(SSI_SCK5),
 601         PINMUX_SINGLE(SSI_SDATA5),
 602         PINMUX_SINGLE(SSI_WS5),
 603
 604         /* IPSR0 */
 605         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 606         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 607
 608         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 609         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 610         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 611
 612         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 613         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 614         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 615
 616         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 617         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 618         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 619
 620         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,      I2C_SEL_5_0,    SEL_ETHERAVB_0),
 621         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,          I2C_SEL_5_0,    SEL_MSIOF2_2),
 622         PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,              I2C_SEL_5_0,    SEL_SCIF4_0),
 623         PINMUX_IPSR_MSEL(IP0_19_16,     FSCLKST2_N_A,           I2C_SEL_5_0),
 624         PINMUX_IPSR_PHYS(IP0_19_16,     SCL5,                   I2C_SEL_5_1),
 625
 626         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,    I2C_SEL_5_0,    SEL_ETHERAVB_0),
 627         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,          I2C_SEL_5_0,    SEL_MSIOF2_2),
 628         PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A,              I2C_SEL_5_0,    SEL_SCIF4_0),
 629         PINMUX_IPSR_PHYS(IP0_23_20,     SDA5,                   I2C_SEL_5_1),
 630
 631         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 632         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 633         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 634         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 635         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 636         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 637         PINMUX_IPSR_MSEL(IP0_27_24,     MSIOF3_SS2_E,           SEL_MSIOF3_4),
 638
 639         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 640         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 641         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 642         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 643         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 644         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 645         PINMUX_IPSR_MSEL(IP0_31_28,     MSIOF3_SS1_E,           SEL_MSIOF3_4),
 646
 647         /* IPSR1 */
 648         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 649         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 650         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 651         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 652         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 653         PINMUX_IPSR_MSEL(IP1_3_0,       MSIOF3_SYNC_E,          SEL_MSIOF3_4),
 654
 655         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 656         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 657         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 658         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 659         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 660         PINMUX_IPSR_MSEL(IP1_7_4,       MSIOF3_SCK_E,           SEL_MSIOF3_4),
 661
 662         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 663         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 664         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 665         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 666         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 667         PINMUX_IPSR_MSEL(IP1_11_8,      MSIOF3_RXD_E,           SEL_MSIOF3_4),
 668
 669         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 670         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 671         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 672         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 673         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 674         PINMUX_IPSR_GPSR(IP1_15_12,     FSCLKST2_N_B),
 675         PINMUX_IPSR_MSEL(IP1_15_12,     MSIOF3_TXD_E,           SEL_MSIOF3_4),
 676
 677         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 678         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 679         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 680         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 681
 682         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,                I2C_SEL_3_0,    SEL_PWM1_0),
 683         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,                I2C_SEL_3_0,    SEL_HSCIF3_3),
 684         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,           I2C_SEL_3_0,    SEL_VIN4_1),
 685         PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,                I2C_SEL_3_0,    SEL_IEBUS_1),
 686         PINMUX_IPSR_PHYS(IP0_23_20,     SCL3,                   I2C_SEL_3_1),
 687
 688         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,                I2C_SEL_3_0,    SEL_PWM2_0),
 689         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,                I2C_SEL_3_0,    SEL_HSCIF3_3),
 690         PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,                I2C_SEL_3_0,    SEL_IEBUS_1),
 691         PINMUX_IPSR_PHYS(IP1_27_24,     SDA3,                   I2C_SEL_3_1),
 692
 693         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 694         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 695         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 696         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 697         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 698         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 699
 700         /* IPSR2 */
 701         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 702         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 703         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 704         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 705         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 706         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 707
 708         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 709         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 710         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 711         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 712         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 713         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 714
 715         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 716         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 717         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 718         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 719         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 720         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 721
 722         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 723         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 724         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 725         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 726         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 727         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 728
 729         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 730         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 731         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 732         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 733         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 734         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 735         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 736
 737         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 738         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 739         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 740         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 741         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 742         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 743         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 744
 745         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 746         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 747         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 748         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 749         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 750         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 751         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 752
 753         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 754         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 755         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 756         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 757         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 758         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 759         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 760
 761         /* IPSR3 */
 762         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 763         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 764         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 765         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 766
 767         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 768         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 769         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_B,               SEL_SCIF4_1),
 770         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 771
 772         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 773         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 774         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 775         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 776         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 777         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 778         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 779         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 780         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 781
 782         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 783         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 784         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 785         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 786         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 787         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 788
 789         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 790         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 791         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 792         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 793         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 794         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 795
 796         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 797         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 798         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 799         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 800         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 801         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 802
 803         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 804         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 805         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 806         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 807         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 808         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 809
 810         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 811         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 812         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 813         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 814
 815         /* IPSR4 */
 816         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 817         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 818         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 819         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 820
 821         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 822         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 823         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 824         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 825
 826         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 827         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 828         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 829         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 830
 831         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 832         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 833
 834         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N),
 835         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 836         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 837
 838         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 839         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 840         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 841         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 842         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 843         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 844         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 845         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 846
 847         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 848         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 849         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 850         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 851         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 852         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 853
 854         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 855         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 856         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 857         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 858         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 859         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 860
 861         /* IPSR5 */
 862         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 863         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 864         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 865         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 866         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 867         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 868         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 869
 870         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 871         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 872         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N),
 873         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 874         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 875         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 876         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 877         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 878
 879         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 880         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 881         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 882         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 883
 884         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 885         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 886         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 887         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 888         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 889
 890         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 891         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 892         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 893         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 894         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 895
 896         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 897         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 898         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 899         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 900
 901         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 902         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 903         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 904         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 905
 906         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 907         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 908         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 909         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 910
 911         /* IPSR6 */
 912         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 913         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 914         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 915         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 916
 917         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 918         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 919         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 920         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 921
 922         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 923         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 924         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 925         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 926
 927         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 928         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 929         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 930         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 931         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 932         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 933
 934         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 935         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 936         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 937         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 938         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 939
 940         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 941         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 942         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 943         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 944         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 945         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 946         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 947
 948         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 949         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 950         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 951         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 952         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 953         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_C,               SEL_SCIF4_2),
 954         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 955
 956         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 957         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 958         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 959         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 960         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 961         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 962
 963         /* IPSR7 */
 964         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 965         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 966         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 967         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 968         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 969         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 970
 971         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 972         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 973         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 974         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 975         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 976         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 977         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 978
 979         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 980         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 981         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 982         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 983         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 984         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 985         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 986
 987         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 988         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 989         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 990
 991         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 992         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 993         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 994
 995         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
 996         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
 997         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
 998         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
 999
1000         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
1001         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
1002         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
1003         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
1004
1005         /* IPSR8 */
1006         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
1007         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
1008         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
1009         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1010
1011         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1012         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1013         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1014         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1015
1016         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1017         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1018         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1019
1020         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1021         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1022         PINMUX_IPSR_GPSR(IP8_15_12,     NFCE_N_B),
1023         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1024         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1025
1026         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1027         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1028         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1029         PINMUX_IPSR_GPSR(IP8_19_16,     NFWP_N_B),
1030         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1031         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1032
1033         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1034         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1035         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1036         PINMUX_IPSR_GPSR(IP8_23_20,     NFDATA14_B),
1037         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1038         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1039
1040         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1041         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1042         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1043         PINMUX_IPSR_GPSR(IP8_27_24,     NFDATA15_B),
1044         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1045         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1046
1047         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1048         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1049         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1050         PINMUX_IPSR_GPSR(IP8_31_28,     NFRB_N_B),
1051         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1052         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1053
1054         /* IPSR9 */
1055         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1056         PINMUX_IPSR_GPSR(IP9_3_0,       NFDATA8),
1057
1058         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_CMD),
1059         PINMUX_IPSR_GPSR(IP9_7_4,       NFDATA9),
1060
1061         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT0),
1062         PINMUX_IPSR_GPSR(IP9_11_8,      NFDATA10),
1063
1064         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT1),
1065         PINMUX_IPSR_GPSR(IP9_15_12,     NFDATA11),
1066
1067         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT2),
1068         PINMUX_IPSR_GPSR(IP9_19_16,     NFDATA12),
1069
1070         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DAT3),
1071         PINMUX_IPSR_GPSR(IP9_23_20,     NFDATA13),
1072
1073         PINMUX_IPSR_GPSR(IP9_27_24,     SD2_DS),
1074         PINMUX_IPSR_GPSR(IP9_27_24,     NFALE),
1075         PINMUX_IPSR_GPSR(IP9_27_24,     SATA_DEVSLP_B),
1076
1077         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_CLK),
1078         PINMUX_IPSR_GPSR(IP9_31_28,     NFWE_N),
1079
1080         /* IPSR10 */
1081         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CMD),
1082         PINMUX_IPSR_GPSR(IP10_3_0,      NFRE_N),
1083
1084         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT0),
1085         PINMUX_IPSR_GPSR(IP10_7_4,      NFDATA0),
1086
1087         PINMUX_IPSR_GPSR(IP10_11_8,     SD3_DAT1),
1088         PINMUX_IPSR_GPSR(IP10_11_8,     NFDATA1),
1089
1090         PINMUX_IPSR_GPSR(IP10_15_12,    SD3_DAT2),
1091         PINMUX_IPSR_GPSR(IP10_15_12,    NFDATA2),
1092
1093         PINMUX_IPSR_GPSR(IP10_19_16,    SD3_DAT3),
1094         PINMUX_IPSR_GPSR(IP10_19_16,    NFDATA3),
1095
1096         PINMUX_IPSR_GPSR(IP10_23_20,    SD3_DAT4),
1097         PINMUX_IPSR_MSEL(IP10_23_20,    SD2_CD_A,               SEL_SDHI2_0),
1098         PINMUX_IPSR_GPSR(IP10_23_20,    NFDATA4),
1099
1100         PINMUX_IPSR_GPSR(IP10_27_24,    SD3_DAT5),
1101         PINMUX_IPSR_MSEL(IP10_27_24,    SD2_WP_A,               SEL_SDHI2_0),
1102         PINMUX_IPSR_GPSR(IP10_27_24,    NFDATA5),
1103
1104         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_DAT6),
1105         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_CD),
1106         PINMUX_IPSR_GPSR(IP10_31_28,    NFDATA6),
1107
1108         /* IPSR11 */
1109         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_DAT7),
1110         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_WP),
1111         PINMUX_IPSR_GPSR(IP11_3_0,      NFDATA7),
1112
1113         PINMUX_IPSR_GPSR(IP11_7_4,      SD3_DS),
1114         PINMUX_IPSR_GPSR(IP11_7_4,      NFCLE),
1115
1116         PINMUX_IPSR_GPSR(IP11_11_8,     SD0_CD),
1117         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_B,                 SEL_I2C2_1),
1118         PINMUX_IPSR_MSEL(IP11_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1119
1120         PINMUX_IPSR_GPSR(IP11_15_12,    SD0_WP),
1121         PINMUX_IPSR_MSEL(IP11_15_12,    SDA2_B,                 SEL_I2C2_1),
1122
1123         PINMUX_IPSR_MSEL(IP11_19_16,    SD1_CD,                 I2C_SEL_0_0),
1124         PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B,           I2C_SEL_0_0,    SEL_SIMCARD_1),
1125         PINMUX_IPSR_PHYS(IP11_19_16,    SCL0,                   I2C_SEL_0_1),
1126
1127         PINMUX_IPSR_MSEL(IP11_23_20,    SD1_WP,                 I2C_SEL_0_0),
1128         PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B,             I2C_SEL_0_0,    SEL_SIMCARD_1),
1129         PINMUX_IPSR_PHYS(IP11_23_20,    SDA0,                   I2C_SEL_0_1),
1130
1131         PINMUX_IPSR_GPSR(IP11_27_24,    SCK0),
1132         PINMUX_IPSR_MSEL(IP11_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1133         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1134         PINMUX_IPSR_MSEL(IP11_27_24,    AUDIO_CLKC_B,           SEL_ADG_C_1),
1135         PINMUX_IPSR_MSEL(IP11_27_24,    SDA2_A,                 SEL_I2C2_0),
1136         PINMUX_IPSR_MSEL(IP11_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1137         PINMUX_IPSR_MSEL(IP11_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1138         PINMUX_IPSR_MSEL(IP11_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1139         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS2),
1140         PINMUX_IPSR_MSEL(IP11_27_24,    SCK5_B,                 SEL_SCIF5_1),
1141
1142         PINMUX_IPSR_GPSR(IP11_31_28,    RX0),
1143         PINMUX_IPSR_MSEL(IP11_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1144         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1145         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1146         PINMUX_IPSR_MSEL(IP11_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1147
1148         /* IPSR12 */
1149         PINMUX_IPSR_GPSR(IP12_3_0,      TX0),
1150         PINMUX_IPSR_MSEL(IP12_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1151         PINMUX_IPSR_MSEL(IP12_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1152         PINMUX_IPSR_MSEL(IP12_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1153         PINMUX_IPSR_MSEL(IP12_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1154
1155         PINMUX_IPSR_GPSR(IP12_7_4,      CTS0_N),
1156         PINMUX_IPSR_MSEL(IP12_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1157         PINMUX_IPSR_MSEL(IP12_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1158         PINMUX_IPSR_MSEL(IP12_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1159         PINMUX_IPSR_MSEL(IP12_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1160         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1161         PINMUX_IPSR_GPSR(IP12_7_4,      AUDIO_CLKOUT_C),
1162         PINMUX_IPSR_GPSR(IP12_7_4,      ADICS_SAMP),
1163
1164         PINMUX_IPSR_GPSR(IP12_11_8,     RTS0_N),
1165         PINMUX_IPSR_MSEL(IP12_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1166         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1167         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKA_B,           SEL_ADG_A_1),
1168         PINMUX_IPSR_MSEL(IP12_11_8,     SCL2_A,                 SEL_I2C2_0),
1169         PINMUX_IPSR_MSEL(IP12_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1170         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1171         PINMUX_IPSR_GPSR(IP12_11_8,     ADICHS1),
1172
1173         PINMUX_IPSR_MSEL(IP12_15_12,    RX1_A,                  SEL_SCIF1_0),
1174         PINMUX_IPSR_MSEL(IP12_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1175         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1176         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1177         PINMUX_IPSR_MSEL(IP12_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1178
1179         PINMUX_IPSR_MSEL(IP12_19_16,    TX1_A,                  SEL_SCIF1_0),
1180         PINMUX_IPSR_MSEL(IP12_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1181         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1182         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1183         PINMUX_IPSR_MSEL(IP12_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1184
1185         PINMUX_IPSR_GPSR(IP12_23_20,    CTS1_N),
1186         PINMUX_IPSR_MSEL(IP12_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1187         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1188         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1189         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1190         PINMUX_IPSR_MSEL(IP12_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1191         PINMUX_IPSR_GPSR(IP12_23_20,    ADIDATA),
1192
1193         PINMUX_IPSR_GPSR(IP12_27_24,    RTS1_N),
1194         PINMUX_IPSR_MSEL(IP12_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1195         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1196         PINMUX_IPSR_MSEL(IP12_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1197         PINMUX_IPSR_MSEL(IP12_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1198         PINMUX_IPSR_MSEL(IP12_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1199         PINMUX_IPSR_GPSR(IP12_27_24,    ADICHS0),
1200
1201         PINMUX_IPSR_GPSR(IP12_31_28,    SCK2),
1202         PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,             SEL_SCIF_1),
1203         PINMUX_IPSR_MSEL(IP12_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1204         PINMUX_IPSR_MSEL(IP12_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1205         PINMUX_IPSR_MSEL(IP12_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1206         PINMUX_IPSR_MSEL(IP12_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1207         PINMUX_IPSR_GPSR(IP12_31_28,    ADICLK),
1208
1209         /* IPSR13 */
1210         PINMUX_IPSR_MSEL(IP13_3_0,      TX2_A,                  SEL_SCIF2_0),
1211         PINMUX_IPSR_MSEL(IP13_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1212         PINMUX_IPSR_MSEL(IP13_3_0,      SCL1_A,                 SEL_I2C1_0),
1213         PINMUX_IPSR_MSEL(IP13_3_0,      FMCLK_A,                SEL_FM_0),
1214         PINMUX_IPSR_MSEL(IP13_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1215         PINMUX_IPSR_GPSR(IP13_3_0,      FSO_CFE_0_N),
1216
1217         PINMUX_IPSR_MSEL(IP13_7_4,      RX2_A,                  SEL_SCIF2_0),
1218         PINMUX_IPSR_MSEL(IP13_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1219         PINMUX_IPSR_MSEL(IP13_7_4,      SDA1_A,                 SEL_I2C1_0),
1220         PINMUX_IPSR_MSEL(IP13_7_4,      FMIN_A,                 SEL_FM_0),
1221         PINMUX_IPSR_MSEL(IP13_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1222         PINMUX_IPSR_GPSR(IP13_7_4,      FSO_CFE_1_N),
1223
1224         PINMUX_IPSR_GPSR(IP13_11_8,     HSCK0),
1225         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1226         PINMUX_IPSR_MSEL(IP13_11_8,     AUDIO_CLKB_A,           SEL_ADG_B_0),
1227         PINMUX_IPSR_MSEL(IP13_11_8,     SSI_SDATA1_B,           SEL_SSI1_1),
1228         PINMUX_IPSR_MSEL(IP13_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1229         PINMUX_IPSR_MSEL(IP13_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1230         PINMUX_IPSR_MSEL(IP13_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1231         PINMUX_IPSR_MSEL(IP13_11_8,     RX5_B,                  SEL_SCIF5_1),
1232
1233         PINMUX_IPSR_GPSR(IP13_15_12,    HRX0),
1234         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1235         PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,           SEL_SSI2_1),
1236         PINMUX_IPSR_MSEL(IP13_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1237         PINMUX_IPSR_MSEL(IP13_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1238         PINMUX_IPSR_MSEL(IP13_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1239
1240         PINMUX_IPSR_GPSR(IP13_19_16,    HTX0),
1241         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1242         PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,           SEL_SSI9_1),
1243         PINMUX_IPSR_MSEL(IP13_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1244         PINMUX_IPSR_MSEL(IP13_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1245         PINMUX_IPSR_MSEL(IP13_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1246
1247         PINMUX_IPSR_GPSR(IP13_23_20,    HCTS0_N),
1248         PINMUX_IPSR_MSEL(IP13_23_20,    RX2_B,                  SEL_SCIF2_1),
1249         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1250         PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,             SEL_SSI9_0),
1251         PINMUX_IPSR_MSEL(IP13_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1252         PINMUX_IPSR_MSEL(IP13_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1253         PINMUX_IPSR_MSEL(IP13_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1254         PINMUX_IPSR_GPSR(IP13_23_20,    AUDIO_CLKOUT1_A),
1255
1256         PINMUX_IPSR_GPSR(IP13_27_24,    HRTS0_N),
1257         PINMUX_IPSR_MSEL(IP13_27_24,    TX2_B,                  SEL_SCIF2_1),
1258         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1259         PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,              SEL_SSI9_0),
1260         PINMUX_IPSR_MSEL(IP13_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1261         PINMUX_IPSR_MSEL(IP13_27_24,    BPFCLK_A,               SEL_FM_0),
1262         PINMUX_IPSR_GPSR(IP13_27_24,    AUDIO_CLKOUT2_A),
1263
1264         PINMUX_IPSR_GPSR(IP13_31_28,    MSIOF0_SYNC),
1265         PINMUX_IPSR_GPSR(IP13_31_28,    AUDIO_CLKOUT_A),
1266         PINMUX_IPSR_MSEL(IP13_31_28,    TX5_B,                  SEL_SCIF5_1),
1267         PINMUX_IPSR_MSEL(IP13_31_28,    BPFCLK_D,               SEL_FM_3),
1268
1269         /* IPSR14 */
1270         PINMUX_IPSR_GPSR(IP14_3_0,      MSIOF0_SS1),
1271         PINMUX_IPSR_MSEL(IP14_3_0,      RX5_A,                  SEL_SCIF5_0),
1272         PINMUX_IPSR_GPSR(IP14_3_0,      NFWP_N_A),
1273         PINMUX_IPSR_MSEL(IP14_3_0,      AUDIO_CLKA_C,           SEL_ADG_A_2),
1274         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SCK2_A,             SEL_SSI2_0),
1275         PINMUX_IPSR_MSEL(IP14_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1276         PINMUX_IPSR_GPSR(IP14_3_0,      AUDIO_CLKOUT3_A),
1277         PINMUX_IPSR_MSEL(IP14_3_0,      TCLK1_B,                SEL_TIMER_TMU1_1),
1278
1279         PINMUX_IPSR_GPSR(IP14_7_4,      MSIOF0_SS2),
1280         PINMUX_IPSR_MSEL(IP14_7_4,      TX5_A,                  SEL_SCIF5_0),
1281         PINMUX_IPSR_MSEL(IP14_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1282         PINMUX_IPSR_MSEL(IP14_7_4,      AUDIO_CLKC_A,           SEL_ADG_C_0),
1283         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_WS2_A,              SEL_SSI2_0),
1284         PINMUX_IPSR_MSEL(IP14_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1285         PINMUX_IPSR_GPSR(IP14_7_4,      AUDIO_CLKOUT_D),
1286         PINMUX_IPSR_MSEL(IP14_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1287
1288         PINMUX_IPSR_GPSR(IP14_11_8,     MLB_CLK),
1289         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1290         PINMUX_IPSR_MSEL(IP14_11_8,     SCL1_B,                 SEL_I2C1_1),
1291
1292         PINMUX_IPSR_GPSR(IP14_15_12,    MLB_SIG),
1293         PINMUX_IPSR_MSEL(IP14_15_12,    RX1_B,                  SEL_SCIF1_1),
1294         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1295         PINMUX_IPSR_MSEL(IP14_15_12,    SDA1_B,                 SEL_I2C1_1),
1296
1297         PINMUX_IPSR_GPSR(IP14_19_16,    MLB_DAT),
1298         PINMUX_IPSR_MSEL(IP14_19_16,    TX1_B,                  SEL_SCIF1_1),
1299         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1300
1301         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK01239),
1302         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1303
1304         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS01239),
1305         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1306
1307         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA0),
1308         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1309
1310         /* IPSR15 */
1311         PINMUX_IPSR_MSEL(IP15_3_0,      SSI_SDATA1_A,           SEL_SSI1_0),
1312
1313         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SDATA2_A,           SEL_SSI2_0),
1314         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SCK1_B,             SEL_SSI1_1),
1315
1316         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SCK349),
1317         PINMUX_IPSR_MSEL(IP15_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1318         PINMUX_IPSR_MSEL(IP15_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1319
1320         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_WS349),
1321         PINMUX_IPSR_MSEL(IP15_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1322         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1323         PINMUX_IPSR_MSEL(IP15_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1324
1325         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_SDATA3),
1326         PINMUX_IPSR_MSEL(IP15_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1327         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1328         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1329         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1330         PINMUX_IPSR_MSEL(IP15_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1331         PINMUX_IPSR_MSEL(IP15_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1332
1333         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SCK4),
1334         PINMUX_IPSR_MSEL(IP15_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1335         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1336         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1337         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1338         PINMUX_IPSR_MSEL(IP15_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1339         PINMUX_IPSR_MSEL(IP15_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1340
1341         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_WS4),
1342         PINMUX_IPSR_MSEL(IP15_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1343         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1344         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1345         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1346         PINMUX_IPSR_MSEL(IP15_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1347         PINMUX_IPSR_MSEL(IP15_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1348
1349         PINMUX_IPSR_GPSR(IP15_31_28,    SSI_SDATA4),
1350         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1351         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1352         PINMUX_IPSR_MSEL(IP15_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1353         PINMUX_IPSR_MSEL(IP15_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1354         PINMUX_IPSR_MSEL(IP15_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1355         PINMUX_IPSR_MSEL(IP15_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1356
1357         /* IPSR16 */
1358         PINMUX_IPSR_GPSR(IP16_3_0,      SSI_SCK6),
1359         PINMUX_IPSR_GPSR(IP16_3_0,      USB2_PWEN),
1360         PINMUX_IPSR_MSEL(IP16_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1361
1362         PINMUX_IPSR_GPSR(IP16_7_4,      SSI_WS6),
1363         PINMUX_IPSR_GPSR(IP16_7_4,      USB2_OVC),
1364         PINMUX_IPSR_MSEL(IP16_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1365
1366         PINMUX_IPSR_GPSR(IP16_11_8,     SSI_SDATA6),
1367         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1368         PINMUX_IPSR_GPSR(IP16_11_8,     SATA_DEVSLP_A),
1369
1370         PINMUX_IPSR_GPSR(IP16_15_12,    SSI_SCK78),
1371         PINMUX_IPSR_MSEL(IP16_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1372         PINMUX_IPSR_MSEL(IP16_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1373         PINMUX_IPSR_MSEL(IP16_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1374         PINMUX_IPSR_MSEL(IP16_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1375         PINMUX_IPSR_MSEL(IP16_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1376         PINMUX_IPSR_MSEL(IP16_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1377
1378         PINMUX_IPSR_GPSR(IP16_19_16,    SSI_WS78),
1379         PINMUX_IPSR_MSEL(IP16_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1380         PINMUX_IPSR_MSEL(IP16_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1381         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1382         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1383         PINMUX_IPSR_MSEL(IP16_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1384         PINMUX_IPSR_MSEL(IP16_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1385
1386         PINMUX_IPSR_GPSR(IP16_23_20,    SSI_SDATA7),
1387         PINMUX_IPSR_MSEL(IP16_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1388         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1389         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1390         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1391         PINMUX_IPSR_MSEL(IP16_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1392         PINMUX_IPSR_MSEL(IP16_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1393         PINMUX_IPSR_MSEL(IP16_23_20,    TCLK2_A,                SEL_TIMER_TMU2_0),
1394
1395         PINMUX_IPSR_GPSR(IP16_27_24,    SSI_SDATA8),
1396         PINMUX_IPSR_MSEL(IP16_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1397         PINMUX_IPSR_MSEL(IP16_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1398         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1399         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1400         PINMUX_IPSR_MSEL(IP16_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1401         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1402
1403         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,           SEL_SSI9_0),
1404         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1405         PINMUX_IPSR_MSEL(IP16_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1406         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1407         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,              SEL_SSI1_1),
1408         PINMUX_IPSR_GPSR(IP16_31_28,    SCK1),
1409         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1410         PINMUX_IPSR_MSEL(IP16_31_28,    SCK5_A,                 SEL_SCIF5_0),
1411
1412         /* IPSR17 */
1413         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKA_A,           SEL_ADG_A_0),
1414         PINMUX_IPSR_GPSR(IP17_3_0,      CC5_OSCOUT),
1415
1416         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKB_B,           SEL_ADG_B_1),
1417         PINMUX_IPSR_MSEL(IP17_7_4,      SCIF_CLK_A,             SEL_SCIF_0),
1418         PINMUX_IPSR_MSEL(IP17_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1419         PINMUX_IPSR_MSEL(IP17_7_4,      REMOCON_A,              SEL_REMOCON_0),
1420         PINMUX_IPSR_MSEL(IP17_7_4,      TCLK1_A,                SEL_TIMER_TMU1_0),
1421
1422         PINMUX_IPSR_GPSR(IP17_11_8,     USB0_PWEN),
1423         PINMUX_IPSR_MSEL(IP17_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1424         PINMUX_IPSR_MSEL(IP17_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1425         PINMUX_IPSR_MSEL(IP17_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1426         PINMUX_IPSR_MSEL(IP17_11_8,     BPFCLK_B,               SEL_FM_1),
1427         PINMUX_IPSR_MSEL(IP17_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1428         PINMUX_IPSR_MSEL(IP17_11_8,     HSCK2_C,                SEL_HSCIF2_2),
1429
1430         PINMUX_IPSR_GPSR(IP17_15_12,    USB0_OVC),
1431         PINMUX_IPSR_MSEL(IP17_15_12,    SIM0_D_C,               SEL_SIMCARD_2),
1432         PINMUX_IPSR_MSEL(IP17_15_12,    TS_SDAT1_D,             SEL_TSIF1_3),
1433         PINMUX_IPSR_MSEL(IP17_15_12,    STP_ISD_1_D,            SEL_SSP1_1_3),
1434         PINMUX_IPSR_MSEL(IP17_15_12,    RIF3_SYNC_B,            SEL_DRIF3_1),
1435         PINMUX_IPSR_MSEL(IP17_15_12,    HRX2_C,                 SEL_HSCIF2_2),
1436
1437         PINMUX_IPSR_GPSR(IP17_19_16,    USB1_PWEN),
1438         PINMUX_IPSR_MSEL(IP17_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1439         PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,             SEL_SSI1_0),
1440         PINMUX_IPSR_MSEL(IP17_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1441         PINMUX_IPSR_MSEL(IP17_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1442         PINMUX_IPSR_MSEL(IP17_19_16,    FMCLK_B,                SEL_FM_1),
1443         PINMUX_IPSR_MSEL(IP17_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1444         PINMUX_IPSR_MSEL(IP17_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1445         PINMUX_IPSR_MSEL(IP17_19_16,    HTX2_C,                 SEL_HSCIF2_2),
1446
1447         PINMUX_IPSR_GPSR(IP17_23_20,    USB1_OVC),
1448         PINMUX_IPSR_MSEL(IP17_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1449         PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,              SEL_SSI1_0),
1450         PINMUX_IPSR_MSEL(IP17_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1451         PINMUX_IPSR_MSEL(IP17_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1452         PINMUX_IPSR_MSEL(IP17_23_20,    FMIN_B,                 SEL_FM_1),
1453         PINMUX_IPSR_MSEL(IP17_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1454         PINMUX_IPSR_MSEL(IP17_23_20,    REMOCON_B,              SEL_REMOCON_1),
1455         PINMUX_IPSR_MSEL(IP17_23_20,    HCTS2_N_C,              SEL_HSCIF2_2),
1456
1457         PINMUX_IPSR_GPSR(IP17_27_24,    USB30_PWEN),
1458         PINMUX_IPSR_GPSR(IP17_27_24,    AUDIO_CLKOUT_B),
1459         PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,             SEL_SSI2_1),
1460         PINMUX_IPSR_MSEL(IP17_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1461         PINMUX_IPSR_MSEL(IP17_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1462         PINMUX_IPSR_MSEL(IP17_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1463         PINMUX_IPSR_MSEL(IP17_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1464         PINMUX_IPSR_MSEL(IP17_27_24,    TCLK2_B,                SEL_TIMER_TMU2_1),
1465         PINMUX_IPSR_GPSR(IP17_27_24,    TPU0TO0),
1466         PINMUX_IPSR_MSEL(IP17_27_24,    BPFCLK_C,               SEL_FM_2),
1467         PINMUX_IPSR_MSEL(IP17_27_24,    HRTS2_N_C,              SEL_HSCIF2_2),
1468
1469         PINMUX_IPSR_GPSR(IP17_31_28,    USB30_OVC),
1470         PINMUX_IPSR_GPSR(IP17_31_28,    AUDIO_CLKOUT1_B),
1471         PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,              SEL_SSI2_1),
1472         PINMUX_IPSR_MSEL(IP17_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1473         PINMUX_IPSR_MSEL(IP17_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1474         PINMUX_IPSR_MSEL(IP17_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1475         PINMUX_IPSR_MSEL(IP17_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1476         PINMUX_IPSR_GPSR(IP17_31_28,    FSO_TOE_N),
1477         PINMUX_IPSR_GPSR(IP17_31_28,    TPU0TO1),
1478
1479         /* IPSR18 */
1480         PINMUX_IPSR_GPSR(IP18_3_0,      USB2_CH3_PWEN),
1481         PINMUX_IPSR_GPSR(IP18_3_0,      AUDIO_CLKOUT2_B),
1482         PINMUX_IPSR_MSEL(IP18_3_0,      SSI_SCK9_B,             SEL_SSI9_1),
1483         PINMUX_IPSR_MSEL(IP18_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1484         PINMUX_IPSR_MSEL(IP18_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1485         PINMUX_IPSR_MSEL(IP18_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1486         PINMUX_IPSR_GPSR(IP18_3_0,      TPU0TO2),
1487         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_C,                SEL_FM_2),
1488         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_D,                SEL_FM_3),
1489
1490         PINMUX_IPSR_GPSR(IP18_7_4,      USB2_CH3_OVC),
1491         PINMUX_IPSR_GPSR(IP18_7_4,      AUDIO_CLKOUT3_B),
1492         PINMUX_IPSR_MSEL(IP18_7_4,      SSI_WS9_B,              SEL_SSI9_1),
1493         PINMUX_IPSR_MSEL(IP18_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1494         PINMUX_IPSR_MSEL(IP18_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1495         PINMUX_IPSR_MSEL(IP18_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1496         PINMUX_IPSR_GPSR(IP18_7_4,      TPU0TO3),
1497         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_C,                 SEL_FM_2),
1498         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_D,                 SEL_FM_3),
1499
1500 /*
1501  * Static pins can not be muxed between different functions but
1502  * still need mark entries in the pinmux list. Add each static
1503  * pin to the list without an associated function. The sh-pfc
1504  * core will do the right thing and skip trying to mux the pin
1505  * while still applying configuration to it.
1506  */
1507 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1508         PINMUX_STATIC
1509 #undef FM
1510 };
1511
1512 /*
1513  * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1514  * Physical layout rows: A - AW, cols: 1 - 39.
1515  */
1516 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1517 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1518 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1519 #define PIN_NONE U16_MAX
1520
1521 static const struct sh_pfc_pin pinmux_pins[] = {
1522         PINMUX_GPIO_GP_ALL(),
1523
1524         /*
1525          * Pins not associated with a GPIO port.
1526          *
1527          * The pin positions are different between different r8a7795
1528          * packages, all that is needed for the pfc driver is a unique
1529          * number for each pin. To this end use the pin layout from
1530          * R-Car H3SiP to calculate a unique number for each pin.
1531          */
1532         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1533         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1534         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1535         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1536         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1537         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1538         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1539         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1540         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1541         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1542         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1543         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1544         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1545         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1546         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1547         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1548         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1549         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1550         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1551         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1552         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1553         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1554         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1555         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1556         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1557         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1558         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1559         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1560         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1561         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1562         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1563         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1564         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1565         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1566         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1567         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  7, DU_DOTCLKIN2, CFG_FLAGS),
1568         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN3, CFG_FLAGS),
1569         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1570         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1572         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1573         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1574         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1575 };
1576
1577 /* - AUDIO CLOCK ------------------------------------------------------------ */
1578 static const unsigned int audio_clk_a_a_pins[] = {
1579         /* CLK A */
1580         RCAR_GP_PIN(6, 22),
1581 };
1582 static const unsigned int audio_clk_a_a_mux[] = {
1583         AUDIO_CLKA_A_MARK,
1584 };
1585 static const unsigned int audio_clk_a_b_pins[] = {
1586         /* CLK A */
1587         RCAR_GP_PIN(5, 4),
1588 };
1589 static const unsigned int audio_clk_a_b_mux[] = {
1590         AUDIO_CLKA_B_MARK,
1591 };
1592 static const unsigned int audio_clk_a_c_pins[] = {
1593         /* CLK A */
1594         RCAR_GP_PIN(5, 19),
1595 };
1596 static const unsigned int audio_clk_a_c_mux[] = {
1597         AUDIO_CLKA_C_MARK,
1598 };
1599 static const unsigned int audio_clk_b_a_pins[] = {
1600         /* CLK B */
1601         RCAR_GP_PIN(5, 12),
1602 };
1603 static const unsigned int audio_clk_b_a_mux[] = {
1604         AUDIO_CLKB_A_MARK,
1605 };
1606 static const unsigned int audio_clk_b_b_pins[] = {
1607         /* CLK B */
1608         RCAR_GP_PIN(6, 23),
1609 };
1610 static const unsigned int audio_clk_b_b_mux[] = {
1611         AUDIO_CLKB_B_MARK,
1612 };
1613 static const unsigned int audio_clk_c_a_pins[] = {
1614         /* CLK C */
1615         RCAR_GP_PIN(5, 21),
1616 };
1617 static const unsigned int audio_clk_c_a_mux[] = {
1618         AUDIO_CLKC_A_MARK,
1619 };
1620 static const unsigned int audio_clk_c_b_pins[] = {
1621         /* CLK C */
1622         RCAR_GP_PIN(5, 0),
1623 };
1624 static const unsigned int audio_clk_c_b_mux[] = {
1625         AUDIO_CLKC_B_MARK,
1626 };
1627 static const unsigned int audio_clkout_a_pins[] = {
1628         /* CLKOUT */
1629         RCAR_GP_PIN(5, 18),
1630 };
1631 static const unsigned int audio_clkout_a_mux[] = {
1632         AUDIO_CLKOUT_A_MARK,
1633 };
1634 static const unsigned int audio_clkout_b_pins[] = {
1635         /* CLKOUT */
1636         RCAR_GP_PIN(6, 28),
1637 };
1638 static const unsigned int audio_clkout_b_mux[] = {
1639         AUDIO_CLKOUT_B_MARK,
1640 };
1641 static const unsigned int audio_clkout_c_pins[] = {
1642         /* CLKOUT */
1643         RCAR_GP_PIN(5, 3),
1644 };
1645 static const unsigned int audio_clkout_c_mux[] = {
1646         AUDIO_CLKOUT_C_MARK,
1647 };
1648 static const unsigned int audio_clkout_d_pins[] = {
1649         /* CLKOUT */
1650         RCAR_GP_PIN(5, 21),
1651 };
1652 static const unsigned int audio_clkout_d_mux[] = {
1653         AUDIO_CLKOUT_D_MARK,
1654 };
1655 static const unsigned int audio_clkout1_a_pins[] = {
1656         /* CLKOUT1 */
1657         RCAR_GP_PIN(5, 15),
1658 };
1659 static const unsigned int audio_clkout1_a_mux[] = {
1660         AUDIO_CLKOUT1_A_MARK,
1661 };
1662 static const unsigned int audio_clkout1_b_pins[] = {
1663         /* CLKOUT1 */
1664         RCAR_GP_PIN(6, 29),
1665 };
1666 static const unsigned int audio_clkout1_b_mux[] = {
1667         AUDIO_CLKOUT1_B_MARK,
1668 };
1669 static const unsigned int audio_clkout2_a_pins[] = {
1670         /* CLKOUT2 */
1671         RCAR_GP_PIN(5, 16),
1672 };
1673 static const unsigned int audio_clkout2_a_mux[] = {
1674         AUDIO_CLKOUT2_A_MARK,
1675 };
1676 static const unsigned int audio_clkout2_b_pins[] = {
1677         /* CLKOUT2 */
1678         RCAR_GP_PIN(6, 30),
1679 };
1680 static const unsigned int audio_clkout2_b_mux[] = {
1681         AUDIO_CLKOUT2_B_MARK,
1682 };
1683 static const unsigned int audio_clkout3_a_pins[] = {
1684         /* CLKOUT3 */
1685         RCAR_GP_PIN(5, 19),
1686 };
1687 static const unsigned int audio_clkout3_a_mux[] = {
1688         AUDIO_CLKOUT3_A_MARK,
1689 };
1690 static const unsigned int audio_clkout3_b_pins[] = {
1691         /* CLKOUT3 */
1692         RCAR_GP_PIN(6, 31),
1693 };
1694 static const unsigned int audio_clkout3_b_mux[] = {
1695         AUDIO_CLKOUT3_B_MARK,
1696 };
1697
1698 /* - EtherAVB --------------------------------------------------------------- */
1699 static const unsigned int avb_link_pins[] = {
1700         /* AVB_LINK */
1701         RCAR_GP_PIN(2, 12),
1702 };
1703 static const unsigned int avb_link_mux[] = {
1704         AVB_LINK_MARK,
1705 };
1706 static const unsigned int avb_magic_pins[] = {
1707         /* AVB_MAGIC_ */
1708         RCAR_GP_PIN(2, 10),
1709 };
1710 static const unsigned int avb_magic_mux[] = {
1711         AVB_MAGIC_MARK,
1712 };
1713 static const unsigned int avb_phy_int_pins[] = {
1714         /* AVB_PHY_INT */
1715         RCAR_GP_PIN(2, 11),
1716 };
1717 static const unsigned int avb_phy_int_mux[] = {
1718         AVB_PHY_INT_MARK,
1719 };
1720 static const unsigned int avb_mdio_pins[] = {
1721         /* AVB_MDC, AVB_MDIO */
1722         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1723 };
1724 static const unsigned int avb_mdio_mux[] = {
1725         AVB_MDC_MARK, AVB_MDIO_MARK,
1726 };
1727 static const unsigned int avb_mii_pins[] = {
1728         /*
1729          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1730          * AVB_TD1, AVB_TD2, AVB_TD3,
1731          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1732          * AVB_RD1, AVB_RD2, AVB_RD3,
1733          * AVB_TXCREFCLK
1734          */
1735         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1736         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1737         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1738         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1739         PIN_NUMBER('A', 12),
1740
1741 };
1742 static const unsigned int avb_mii_mux[] = {
1743         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1744         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1745         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1746         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1747         AVB_TXCREFCLK_MARK,
1748 };
1749 static const unsigned int avb_avtp_pps_pins[] = {
1750         /* AVB_AVTP_PPS */
1751         RCAR_GP_PIN(2, 6),
1752 };
1753 static const unsigned int avb_avtp_pps_mux[] = {
1754         AVB_AVTP_PPS_MARK,
1755 };
1756 static const unsigned int avb_avtp_match_a_pins[] = {
1757         /* AVB_AVTP_MATCH_A */
1758         RCAR_GP_PIN(2, 13),
1759 };
1760 static const unsigned int avb_avtp_match_a_mux[] = {
1761         AVB_AVTP_MATCH_A_MARK,
1762 };
1763 static const unsigned int avb_avtp_capture_a_pins[] = {
1764         /* AVB_AVTP_CAPTURE_A */
1765         RCAR_GP_PIN(2, 14),
1766 };
1767 static const unsigned int avb_avtp_capture_a_mux[] = {
1768         AVB_AVTP_CAPTURE_A_MARK,
1769 };
1770 static const unsigned int avb_avtp_match_b_pins[] = {
1771         /*  AVB_AVTP_MATCH_B */
1772         RCAR_GP_PIN(1, 8),
1773 };
1774 static const unsigned int avb_avtp_match_b_mux[] = {
1775         AVB_AVTP_MATCH_B_MARK,
1776 };
1777 static const unsigned int avb_avtp_capture_b_pins[] = {
1778         /* AVB_AVTP_CAPTURE_B */
1779         RCAR_GP_PIN(1, 11),
1780 };
1781 static const unsigned int avb_avtp_capture_b_mux[] = {
1782         AVB_AVTP_CAPTURE_B_MARK,
1783 };
1784
1785 /* - CAN ------------------------------------------------------------------ */
1786 static const unsigned int can0_data_a_pins[] = {
1787         /* TX, RX */
1788         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1789 };
1790 static const unsigned int can0_data_a_mux[] = {
1791         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1792 };
1793 static const unsigned int can0_data_b_pins[] = {
1794         /* TX, RX */
1795         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1796 };
1797 static const unsigned int can0_data_b_mux[] = {
1798         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1799 };
1800 static const unsigned int can1_data_pins[] = {
1801         /* TX, RX */
1802         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1803 };
1804 static const unsigned int can1_data_mux[] = {
1805         CAN1_TX_MARK,           CAN1_RX_MARK,
1806 };
1807
1808 /* - CAN Clock -------------------------------------------------------------- */
1809 static const unsigned int can_clk_pins[] = {
1810         /* CLK */
1811         RCAR_GP_PIN(1, 25),
1812 };
1813 static const unsigned int can_clk_mux[] = {
1814         CAN_CLK_MARK,
1815 };
1816
1817 /* - CAN FD --------------------------------------------------------------- */
1818 static const unsigned int canfd0_data_a_pins[] = {
1819         /* TX, RX */
1820         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1821 };
1822 static const unsigned int canfd0_data_a_mux[] = {
1823         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1824 };
1825 static const unsigned int canfd0_data_b_pins[] = {
1826         /* TX, RX */
1827         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1828 };
1829 static const unsigned int canfd0_data_b_mux[] = {
1830         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1831 };
1832 static const unsigned int canfd1_data_pins[] = {
1833         /* TX, RX */
1834         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1835 };
1836 static const unsigned int canfd1_data_mux[] = {
1837         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1838 };
1839
1840 /* - DRIF0 --------------------------------------------------------------- */
1841 static const unsigned int drif0_ctrl_a_pins[] = {
1842         /* CLK, SYNC */
1843         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1844 };
1845 static const unsigned int drif0_ctrl_a_mux[] = {
1846         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1847 };
1848 static const unsigned int drif0_data0_a_pins[] = {
1849         /* D0 */
1850         RCAR_GP_PIN(6, 10),
1851 };
1852 static const unsigned int drif0_data0_a_mux[] = {
1853         RIF0_D0_A_MARK,
1854 };
1855 static const unsigned int drif0_data1_a_pins[] = {
1856         /* D1 */
1857         RCAR_GP_PIN(6, 7),
1858 };
1859 static const unsigned int drif0_data1_a_mux[] = {
1860         RIF0_D1_A_MARK,
1861 };
1862 static const unsigned int drif0_ctrl_b_pins[] = {
1863         /* CLK, SYNC */
1864         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1865 };
1866 static const unsigned int drif0_ctrl_b_mux[] = {
1867         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1868 };
1869 static const unsigned int drif0_data0_b_pins[] = {
1870         /* D0 */
1871         RCAR_GP_PIN(5, 1),
1872 };
1873 static const unsigned int drif0_data0_b_mux[] = {
1874         RIF0_D0_B_MARK,
1875 };
1876 static const unsigned int drif0_data1_b_pins[] = {
1877         /* D1 */
1878         RCAR_GP_PIN(5, 2),
1879 };
1880 static const unsigned int drif0_data1_b_mux[] = {
1881         RIF0_D1_B_MARK,
1882 };
1883 static const unsigned int drif0_ctrl_c_pins[] = {
1884         /* CLK, SYNC */
1885         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1886 };
1887 static const unsigned int drif0_ctrl_c_mux[] = {
1888         RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1889 };
1890 static const unsigned int drif0_data0_c_pins[] = {
1891         /* D0 */
1892         RCAR_GP_PIN(5, 13),
1893 };
1894 static const unsigned int drif0_data0_c_mux[] = {
1895         RIF0_D0_C_MARK,
1896 };
1897 static const unsigned int drif0_data1_c_pins[] = {
1898         /* D1 */
1899         RCAR_GP_PIN(5, 14),
1900 };
1901 static const unsigned int drif0_data1_c_mux[] = {
1902         RIF0_D1_C_MARK,
1903 };
1904 /* - DRIF1 --------------------------------------------------------------- */
1905 static const unsigned int drif1_ctrl_a_pins[] = {
1906         /* CLK, SYNC */
1907         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1908 };
1909 static const unsigned int drif1_ctrl_a_mux[] = {
1910         RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1911 };
1912 static const unsigned int drif1_data0_a_pins[] = {
1913         /* D0 */
1914         RCAR_GP_PIN(6, 19),
1915 };
1916 static const unsigned int drif1_data0_a_mux[] = {
1917         RIF1_D0_A_MARK,
1918 };
1919 static const unsigned int drif1_data1_a_pins[] = {
1920         /* D1 */
1921         RCAR_GP_PIN(6, 20),
1922 };
1923 static const unsigned int drif1_data1_a_mux[] = {
1924         RIF1_D1_A_MARK,
1925 };
1926 static const unsigned int drif1_ctrl_b_pins[] = {
1927         /* CLK, SYNC */
1928         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1929 };
1930 static const unsigned int drif1_ctrl_b_mux[] = {
1931         RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1932 };
1933 static const unsigned int drif1_data0_b_pins[] = {
1934         /* D0 */
1935         RCAR_GP_PIN(5, 7),
1936 };
1937 static const unsigned int drif1_data0_b_mux[] = {
1938         RIF1_D0_B_MARK,
1939 };
1940 static const unsigned int drif1_data1_b_pins[] = {
1941         /* D1 */
1942         RCAR_GP_PIN(5, 8),
1943 };
1944 static const unsigned int drif1_data1_b_mux[] = {
1945         RIF1_D1_B_MARK,
1946 };
1947 static const unsigned int drif1_ctrl_c_pins[] = {
1948         /* CLK, SYNC */
1949         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1950 };
1951 static const unsigned int drif1_ctrl_c_mux[] = {
1952         RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1953 };
1954 static const unsigned int drif1_data0_c_pins[] = {
1955         /* D0 */
1956         RCAR_GP_PIN(5, 6),
1957 };
1958 static const unsigned int drif1_data0_c_mux[] = {
1959         RIF1_D0_C_MARK,
1960 };
1961 static const unsigned int drif1_data1_c_pins[] = {
1962         /* D1 */
1963         RCAR_GP_PIN(5, 10),
1964 };
1965 static const unsigned int drif1_data1_c_mux[] = {
1966         RIF1_D1_C_MARK,
1967 };
1968 /* - DRIF2 --------------------------------------------------------------- */
1969 static const unsigned int drif2_ctrl_a_pins[] = {
1970         /* CLK, SYNC */
1971         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1972 };
1973 static const unsigned int drif2_ctrl_a_mux[] = {
1974         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1975 };
1976 static const unsigned int drif2_data0_a_pins[] = {
1977         /* D0 */
1978         RCAR_GP_PIN(6, 7),
1979 };
1980 static const unsigned int drif2_data0_a_mux[] = {
1981         RIF2_D0_A_MARK,
1982 };
1983 static const unsigned int drif2_data1_a_pins[] = {
1984         /* D1 */
1985         RCAR_GP_PIN(6, 10),
1986 };
1987 static const unsigned int drif2_data1_a_mux[] = {
1988         RIF2_D1_A_MARK,
1989 };
1990 static const unsigned int drif2_ctrl_b_pins[] = {
1991         /* CLK, SYNC */
1992         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1993 };
1994 static const unsigned int drif2_ctrl_b_mux[] = {
1995         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1996 };
1997 static const unsigned int drif2_data0_b_pins[] = {
1998         /* D0 */
1999         RCAR_GP_PIN(6, 30),
2000 };
2001 static const unsigned int drif2_data0_b_mux[] = {
2002         RIF2_D0_B_MARK,
2003 };
2004 static const unsigned int drif2_data1_b_pins[] = {
2005         /* D1 */
2006         RCAR_GP_PIN(6, 31),
2007 };
2008 static const unsigned int drif2_data1_b_mux[] = {
2009         RIF2_D1_B_MARK,
2010 };
2011 /* - DRIF3 --------------------------------------------------------------- */
2012 static const unsigned int drif3_ctrl_a_pins[] = {
2013         /* CLK, SYNC */
2014         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2015 };
2016 static const unsigned int drif3_ctrl_a_mux[] = {
2017         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2018 };
2019 static const unsigned int drif3_data0_a_pins[] = {
2020         /* D0 */
2021         RCAR_GP_PIN(6, 19),
2022 };
2023 static const unsigned int drif3_data0_a_mux[] = {
2024         RIF3_D0_A_MARK,
2025 };
2026 static const unsigned int drif3_data1_a_pins[] = {
2027         /* D1 */
2028         RCAR_GP_PIN(6, 20),
2029 };
2030 static const unsigned int drif3_data1_a_mux[] = {
2031         RIF3_D1_A_MARK,
2032 };
2033 static const unsigned int drif3_ctrl_b_pins[] = {
2034         /* CLK, SYNC */
2035         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2036 };
2037 static const unsigned int drif3_ctrl_b_mux[] = {
2038         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2039 };
2040 static const unsigned int drif3_data0_b_pins[] = {
2041         /* D0 */
2042         RCAR_GP_PIN(6, 28),
2043 };
2044 static const unsigned int drif3_data0_b_mux[] = {
2045         RIF3_D0_B_MARK,
2046 };
2047 static const unsigned int drif3_data1_b_pins[] = {
2048         /* D1 */
2049         RCAR_GP_PIN(6, 29),
2050 };
2051 static const unsigned int drif3_data1_b_mux[] = {
2052         RIF3_D1_B_MARK,
2053 };
2054
2055 /* - DU --------------------------------------------------------------------- */
2056 static const unsigned int du_rgb666_pins[] = {
2057         /* R[7:2], G[7:2], B[7:2] */
2058         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2059         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2060         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2061         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2062         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2063         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2064 };
2065 static const unsigned int du_rgb666_mux[] = {
2066         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2067         DU_DR3_MARK, DU_DR2_MARK,
2068         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2069         DU_DG3_MARK, DU_DG2_MARK,
2070         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2071         DU_DB3_MARK, DU_DB2_MARK,
2072 };
2073 static const unsigned int du_rgb888_pins[] = {
2074         /* R[7:0], G[7:0], B[7:0] */
2075         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2076         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2077         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2078         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2079         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2080         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2081         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2082         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2083         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2084 };
2085 static const unsigned int du_rgb888_mux[] = {
2086         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2087         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2088         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2089         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2090         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2091         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2092 };
2093 static const unsigned int du_clk_out_0_pins[] = {
2094         /* CLKOUT */
2095         RCAR_GP_PIN(1, 27),
2096 };
2097 static const unsigned int du_clk_out_0_mux[] = {
2098         DU_DOTCLKOUT0_MARK
2099 };
2100 static const unsigned int du_clk_out_1_pins[] = {
2101         /* CLKOUT */
2102         RCAR_GP_PIN(2, 3),
2103 };
2104 static const unsigned int du_clk_out_1_mux[] = {
2105         DU_DOTCLKOUT1_MARK
2106 };
2107 static const unsigned int du_sync_pins[] = {
2108         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2109         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2110 };
2111 static const unsigned int du_sync_mux[] = {
2112         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2113 };
2114 static const unsigned int du_oddf_pins[] = {
2115         /* EXDISP/EXODDF/EXCDE */
2116         RCAR_GP_PIN(2, 2),
2117 };
2118 static const unsigned int du_oddf_mux[] = {
2119         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2120 };
2121 static const unsigned int du_cde_pins[] = {
2122         /* CDE */
2123         RCAR_GP_PIN(2, 0),
2124 };
2125 static const unsigned int du_cde_mux[] = {
2126         DU_CDE_MARK,
2127 };
2128 static const unsigned int du_disp_pins[] = {
2129         /* DISP */
2130         RCAR_GP_PIN(2, 1),
2131 };
2132 static const unsigned int du_disp_mux[] = {
2133         DU_DISP_MARK,
2134 };
2135
2136 /* - HDMI ------------------------------------------------------------------- */
2137 static const unsigned int hdmi0_cec_pins[] = {
2138         /* HDMI0_CEC */
2139         RCAR_GP_PIN(7, 2),
2140 };
2141 static const unsigned int hdmi0_cec_mux[] = {
2142         HDMI0_CEC_MARK,
2143 };
2144 static const unsigned int hdmi1_cec_pins[] = {
2145         /* HDMI1_CEC */
2146         RCAR_GP_PIN(7, 3),
2147 };
2148 static const unsigned int hdmi1_cec_mux[] = {
2149         HDMI1_CEC_MARK,
2150 };
2151
2152 /* - HSCIF0 ----------------------------------------------------------------- */
2153 static const unsigned int hscif0_data_pins[] = {
2154         /* RX, TX */
2155         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2156 };
2157 static const unsigned int hscif0_data_mux[] = {
2158         HRX0_MARK, HTX0_MARK,
2159 };
2160 static const unsigned int hscif0_clk_pins[] = {
2161         /* SCK */
2162         RCAR_GP_PIN(5, 12),
2163 };
2164 static const unsigned int hscif0_clk_mux[] = {
2165         HSCK0_MARK,
2166 };
2167 static const unsigned int hscif0_ctrl_pins[] = {
2168         /* RTS, CTS */
2169         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2170 };
2171 static const unsigned int hscif0_ctrl_mux[] = {
2172         HRTS0_N_MARK, HCTS0_N_MARK,
2173 };
2174 /* - HSCIF1 ----------------------------------------------------------------- */
2175 static const unsigned int hscif1_data_a_pins[] = {
2176         /* RX, TX */
2177         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2178 };
2179 static const unsigned int hscif1_data_a_mux[] = {
2180         HRX1_A_MARK, HTX1_A_MARK,
2181 };
2182 static const unsigned int hscif1_clk_a_pins[] = {
2183         /* SCK */
2184         RCAR_GP_PIN(6, 21),
2185 };
2186 static const unsigned int hscif1_clk_a_mux[] = {
2187         HSCK1_A_MARK,
2188 };
2189 static const unsigned int hscif1_ctrl_a_pins[] = {
2190         /* RTS, CTS */
2191         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2192 };
2193 static const unsigned int hscif1_ctrl_a_mux[] = {
2194         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2195 };
2196
2197 static const unsigned int hscif1_data_b_pins[] = {
2198         /* RX, TX */
2199         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2200 };
2201 static const unsigned int hscif1_data_b_mux[] = {
2202         HRX1_B_MARK, HTX1_B_MARK,
2203 };
2204 static const unsigned int hscif1_clk_b_pins[] = {
2205         /* SCK */
2206         RCAR_GP_PIN(5, 0),
2207 };
2208 static const unsigned int hscif1_clk_b_mux[] = {
2209         HSCK1_B_MARK,
2210 };
2211 static const unsigned int hscif1_ctrl_b_pins[] = {
2212         /* RTS, CTS */
2213         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2214 };
2215 static const unsigned int hscif1_ctrl_b_mux[] = {
2216         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2217 };
2218 /* - HSCIF2 ----------------------------------------------------------------- */
2219 static const unsigned int hscif2_data_a_pins[] = {
2220         /* RX, TX */
2221         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2222 };
2223 static const unsigned int hscif2_data_a_mux[] = {
2224         HRX2_A_MARK, HTX2_A_MARK,
2225 };
2226 static const unsigned int hscif2_clk_a_pins[] = {
2227         /* SCK */
2228         RCAR_GP_PIN(6, 10),
2229 };
2230 static const unsigned int hscif2_clk_a_mux[] = {
2231         HSCK2_A_MARK,
2232 };
2233 static const unsigned int hscif2_ctrl_a_pins[] = {
2234         /* RTS, CTS */
2235         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2236 };
2237 static const unsigned int hscif2_ctrl_a_mux[] = {
2238         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2239 };
2240
2241 static const unsigned int hscif2_data_b_pins[] = {
2242         /* RX, TX */
2243         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2244 };
2245 static const unsigned int hscif2_data_b_mux[] = {
2246         HRX2_B_MARK, HTX2_B_MARK,
2247 };
2248 static const unsigned int hscif2_clk_b_pins[] = {
2249         /* SCK */
2250         RCAR_GP_PIN(6, 21),
2251 };
2252 static const unsigned int hscif2_clk_b_mux[] = {
2253         HSCK2_B_MARK,
2254 };
2255 static const unsigned int hscif2_ctrl_b_pins[] = {
2256         /* RTS, CTS */
2257         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2258 };
2259 static const unsigned int hscif2_ctrl_b_mux[] = {
2260         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2261 };
2262
2263 static const unsigned int hscif2_data_c_pins[] = {
2264         /* RX, TX */
2265         RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2266 };
2267 static const unsigned int hscif2_data_c_mux[] = {
2268         HRX2_C_MARK, HTX2_C_MARK,
2269 };
2270 static const unsigned int hscif2_clk_c_pins[] = {
2271         /* SCK */
2272         RCAR_GP_PIN(6, 24),
2273 };
2274 static const unsigned int hscif2_clk_c_mux[] = {
2275         HSCK2_C_MARK,
2276 };
2277 static const unsigned int hscif2_ctrl_c_pins[] = {
2278         /* RTS, CTS */
2279         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2280 };
2281 static const unsigned int hscif2_ctrl_c_mux[] = {
2282         HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2283 };
2284 /* - HSCIF3 ----------------------------------------------------------------- */
2285 static const unsigned int hscif3_data_a_pins[] = {
2286         /* RX, TX */
2287         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2288 };
2289 static const unsigned int hscif3_data_a_mux[] = {
2290         HRX3_A_MARK, HTX3_A_MARK,
2291 };
2292 static const unsigned int hscif3_clk_pins[] = {
2293         /* SCK */
2294         RCAR_GP_PIN(1, 22),
2295 };
2296 static const unsigned int hscif3_clk_mux[] = {
2297         HSCK3_MARK,
2298 };
2299 static const unsigned int hscif3_ctrl_pins[] = {
2300         /* RTS, CTS */
2301         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2302 };
2303 static const unsigned int hscif3_ctrl_mux[] = {
2304         HRTS3_N_MARK, HCTS3_N_MARK,
2305 };
2306
2307 static const unsigned int hscif3_data_b_pins[] = {
2308         /* RX, TX */
2309         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2310 };
2311 static const unsigned int hscif3_data_b_mux[] = {
2312         HRX3_B_MARK, HTX3_B_MARK,
2313 };
2314 static const unsigned int hscif3_data_c_pins[] = {
2315         /* RX, TX */
2316         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2317 };
2318 static const unsigned int hscif3_data_c_mux[] = {
2319         HRX3_C_MARK, HTX3_C_MARK,
2320 };
2321 static const unsigned int hscif3_data_d_pins[] = {
2322         /* RX, TX */
2323         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2324 };
2325 static const unsigned int hscif3_data_d_mux[] = {
2326         HRX3_D_MARK, HTX3_D_MARK,
2327 };
2328 /* - HSCIF4 ----------------------------------------------------------------- */
2329 static const unsigned int hscif4_data_a_pins[] = {
2330         /* RX, TX */
2331         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2332 };
2333 static const unsigned int hscif4_data_a_mux[] = {
2334         HRX4_A_MARK, HTX4_A_MARK,
2335 };
2336 static const unsigned int hscif4_clk_pins[] = {
2337         /* SCK */
2338         RCAR_GP_PIN(1, 11),
2339 };
2340 static const unsigned int hscif4_clk_mux[] = {
2341         HSCK4_MARK,
2342 };
2343 static const unsigned int hscif4_ctrl_pins[] = {
2344         /* RTS, CTS */
2345         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2346 };
2347 static const unsigned int hscif4_ctrl_mux[] = {
2348         HRTS4_N_MARK, HCTS4_N_MARK,
2349 };
2350
2351 static const unsigned int hscif4_data_b_pins[] = {
2352         /* RX, TX */
2353         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2354 };
2355 static const unsigned int hscif4_data_b_mux[] = {
2356         HRX4_B_MARK, HTX4_B_MARK,
2357 };
2358
2359 /* - I2C -------------------------------------------------------------------- */
2360 static const unsigned int i2c0_pins[] = {
2361         /* SCL, SDA */
2362         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2363 };
2364
2365 static const unsigned int i2c0_mux[] = {
2366         SCL0_MARK, SDA0_MARK,
2367 };
2368
2369 static const unsigned int i2c1_a_pins[] = {
2370         /* SDA, SCL */
2371         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2372 };
2373 static const unsigned int i2c1_a_mux[] = {
2374         SDA1_A_MARK, SCL1_A_MARK,
2375 };
2376 static const unsigned int i2c1_b_pins[] = {
2377         /* SDA, SCL */
2378         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2379 };
2380 static const unsigned int i2c1_b_mux[] = {
2381         SDA1_B_MARK, SCL1_B_MARK,
2382 };
2383 static const unsigned int i2c2_a_pins[] = {
2384         /* SDA, SCL */
2385         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2386 };
2387 static const unsigned int i2c2_a_mux[] = {
2388         SDA2_A_MARK, SCL2_A_MARK,
2389 };
2390 static const unsigned int i2c2_b_pins[] = {
2391         /* SDA, SCL */
2392         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2393 };
2394 static const unsigned int i2c2_b_mux[] = {
2395         SDA2_B_MARK, SCL2_B_MARK,
2396 };
2397
2398 static const unsigned int i2c3_pins[] = {
2399         /* SCL, SDA */
2400         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2401 };
2402
2403 static const unsigned int i2c3_mux[] = {
2404         SCL3_MARK, SDA3_MARK,
2405 };
2406
2407 static const unsigned int i2c5_pins[] = {
2408         /* SCL, SDA */
2409         RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2410 };
2411
2412 static const unsigned int i2c5_mux[] = {
2413         SCL5_MARK, SDA5_MARK,
2414 };
2415
2416 static const unsigned int i2c6_a_pins[] = {
2417         /* SDA, SCL */
2418         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2419 };
2420 static const unsigned int i2c6_a_mux[] = {
2421         SDA6_A_MARK, SCL6_A_MARK,
2422 };
2423 static const unsigned int i2c6_b_pins[] = {
2424         /* SDA, SCL */
2425         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2426 };
2427 static const unsigned int i2c6_b_mux[] = {
2428         SDA6_B_MARK, SCL6_B_MARK,
2429 };
2430 static const unsigned int i2c6_c_pins[] = {
2431         /* SDA, SCL */
2432         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2433 };
2434 static const unsigned int i2c6_c_mux[] = {
2435         SDA6_C_MARK, SCL6_C_MARK,
2436 };
2437
2438 /* - INTC-EX ---------------------------------------------------------------- */
2439 static const unsigned int intc_ex_irq0_pins[] = {
2440         /* IRQ0 */
2441         RCAR_GP_PIN(2, 0),
2442 };
2443 static const unsigned int intc_ex_irq0_mux[] = {
2444         IRQ0_MARK,
2445 };
2446 static const unsigned int intc_ex_irq1_pins[] = {
2447         /* IRQ1 */
2448         RCAR_GP_PIN(2, 1),
2449 };
2450 static const unsigned int intc_ex_irq1_mux[] = {
2451         IRQ1_MARK,
2452 };
2453 static const unsigned int intc_ex_irq2_pins[] = {
2454         /* IRQ2 */
2455         RCAR_GP_PIN(2, 2),
2456 };
2457 static const unsigned int intc_ex_irq2_mux[] = {
2458         IRQ2_MARK,
2459 };
2460 static const unsigned int intc_ex_irq3_pins[] = {
2461         /* IRQ3 */
2462         RCAR_GP_PIN(2, 3),
2463 };
2464 static const unsigned int intc_ex_irq3_mux[] = {
2465         IRQ3_MARK,
2466 };
2467 static const unsigned int intc_ex_irq4_pins[] = {
2468         /* IRQ4 */
2469         RCAR_GP_PIN(2, 4),
2470 };
2471 static const unsigned int intc_ex_irq4_mux[] = {
2472         IRQ4_MARK,
2473 };
2474 static const unsigned int intc_ex_irq5_pins[] = {
2475         /* IRQ5 */
2476         RCAR_GP_PIN(2, 5),
2477 };
2478 static const unsigned int intc_ex_irq5_mux[] = {
2479         IRQ5_MARK,
2480 };
2481
2482 /* - MSIOF0 ----------------------------------------------------------------- */
2483 static const unsigned int msiof0_clk_pins[] = {
2484         /* SCK */
2485         RCAR_GP_PIN(5, 17),
2486 };
2487 static const unsigned int msiof0_clk_mux[] = {
2488         MSIOF0_SCK_MARK,
2489 };
2490 static const unsigned int msiof0_sync_pins[] = {
2491         /* SYNC */
2492         RCAR_GP_PIN(5, 18),
2493 };
2494 static const unsigned int msiof0_sync_mux[] = {
2495         MSIOF0_SYNC_MARK,
2496 };
2497 static const unsigned int msiof0_ss1_pins[] = {
2498         /* SS1 */
2499         RCAR_GP_PIN(5, 19),
2500 };
2501 static const unsigned int msiof0_ss1_mux[] = {
2502         MSIOF0_SS1_MARK,
2503 };
2504 static const unsigned int msiof0_ss2_pins[] = {
2505         /* SS2 */
2506         RCAR_GP_PIN(5, 21),
2507 };
2508 static const unsigned int msiof0_ss2_mux[] = {
2509         MSIOF0_SS2_MARK,
2510 };
2511 static const unsigned int msiof0_txd_pins[] = {
2512         /* TXD */
2513         RCAR_GP_PIN(5, 20),
2514 };
2515 static const unsigned int msiof0_txd_mux[] = {
2516         MSIOF0_TXD_MARK,
2517 };
2518 static const unsigned int msiof0_rxd_pins[] = {
2519         /* RXD */
2520         RCAR_GP_PIN(5, 22),
2521 };
2522 static const unsigned int msiof0_rxd_mux[] = {
2523         MSIOF0_RXD_MARK,
2524 };
2525 /* - MSIOF1 ----------------------------------------------------------------- */
2526 static const unsigned int msiof1_clk_a_pins[] = {
2527         /* SCK */
2528         RCAR_GP_PIN(6, 8),
2529 };
2530 static const unsigned int msiof1_clk_a_mux[] = {
2531         MSIOF1_SCK_A_MARK,
2532 };
2533 static const unsigned int msiof1_sync_a_pins[] = {
2534         /* SYNC */
2535         RCAR_GP_PIN(6, 9),
2536 };
2537 static const unsigned int msiof1_sync_a_mux[] = {
2538         MSIOF1_SYNC_A_MARK,
2539 };
2540 static const unsigned int msiof1_ss1_a_pins[] = {
2541         /* SS1 */
2542         RCAR_GP_PIN(6, 5),
2543 };
2544 static const unsigned int msiof1_ss1_a_mux[] = {
2545         MSIOF1_SS1_A_MARK,
2546 };
2547 static const unsigned int msiof1_ss2_a_pins[] = {
2548         /* SS2 */
2549         RCAR_GP_PIN(6, 6),
2550 };
2551 static const unsigned int msiof1_ss2_a_mux[] = {
2552         MSIOF1_SS2_A_MARK,
2553 };
2554 static const unsigned int msiof1_txd_a_pins[] = {
2555         /* TXD */
2556         RCAR_GP_PIN(6, 7),
2557 };
2558 static const unsigned int msiof1_txd_a_mux[] = {
2559         MSIOF1_TXD_A_MARK,
2560 };
2561 static const unsigned int msiof1_rxd_a_pins[] = {
2562         /* RXD */
2563         RCAR_GP_PIN(6, 10),
2564 };
2565 static const unsigned int msiof1_rxd_a_mux[] = {
2566         MSIOF1_RXD_A_MARK,
2567 };
2568 static const unsigned int msiof1_clk_b_pins[] = {
2569         /* SCK */
2570         RCAR_GP_PIN(5, 9),
2571 };
2572 static const unsigned int msiof1_clk_b_mux[] = {
2573         MSIOF1_SCK_B_MARK,
2574 };
2575 static const unsigned int msiof1_sync_b_pins[] = {
2576         /* SYNC */
2577         RCAR_GP_PIN(5, 3),
2578 };
2579 static const unsigned int msiof1_sync_b_mux[] = {
2580         MSIOF1_SYNC_B_MARK,
2581 };
2582 static const unsigned int msiof1_ss1_b_pins[] = {
2583         /* SS1 */
2584         RCAR_GP_PIN(5, 4),
2585 };
2586 static const unsigned int msiof1_ss1_b_mux[] = {
2587         MSIOF1_SS1_B_MARK,
2588 };
2589 static const unsigned int msiof1_ss2_b_pins[] = {
2590         /* SS2 */
2591         RCAR_GP_PIN(5, 0),
2592 };
2593 static const unsigned int msiof1_ss2_b_mux[] = {
2594         MSIOF1_SS2_B_MARK,
2595 };
2596 static const unsigned int msiof1_txd_b_pins[] = {
2597         /* TXD */
2598         RCAR_GP_PIN(5, 8),
2599 };
2600 static const unsigned int msiof1_txd_b_mux[] = {
2601         MSIOF1_TXD_B_MARK,
2602 };
2603 static const unsigned int msiof1_rxd_b_pins[] = {
2604         /* RXD */
2605         RCAR_GP_PIN(5, 7),
2606 };
2607 static const unsigned int msiof1_rxd_b_mux[] = {
2608         MSIOF1_RXD_B_MARK,
2609 };
2610 static const unsigned int msiof1_clk_c_pins[] = {
2611         /* SCK */
2612         RCAR_GP_PIN(6, 17),
2613 };
2614 static const unsigned int msiof1_clk_c_mux[] = {
2615         MSIOF1_SCK_C_MARK,
2616 };
2617 static const unsigned int msiof1_sync_c_pins[] = {
2618         /* SYNC */
2619         RCAR_GP_PIN(6, 18),
2620 };
2621 static const unsigned int msiof1_sync_c_mux[] = {
2622         MSIOF1_SYNC_C_MARK,
2623 };
2624 static const unsigned int msiof1_ss1_c_pins[] = {
2625         /* SS1 */
2626         RCAR_GP_PIN(6, 21),
2627 };
2628 static const unsigned int msiof1_ss1_c_mux[] = {
2629         MSIOF1_SS1_C_MARK,
2630 };
2631 static const unsigned int msiof1_ss2_c_pins[] = {
2632         /* SS2 */
2633         RCAR_GP_PIN(6, 27),
2634 };
2635 static const unsigned int msiof1_ss2_c_mux[] = {
2636         MSIOF1_SS2_C_MARK,
2637 };
2638 static const unsigned int msiof1_txd_c_pins[] = {
2639         /* TXD */
2640         RCAR_GP_PIN(6, 20),
2641 };
2642 static const unsigned int msiof1_txd_c_mux[] = {
2643         MSIOF1_TXD_C_MARK,
2644 };
2645 static const unsigned int msiof1_rxd_c_pins[] = {
2646         /* RXD */
2647         RCAR_GP_PIN(6, 19),
2648 };
2649 static const unsigned int msiof1_rxd_c_mux[] = {
2650         MSIOF1_RXD_C_MARK,
2651 };
2652 static const unsigned int msiof1_clk_d_pins[] = {
2653         /* SCK */
2654         RCAR_GP_PIN(5, 12),
2655 };
2656 static const unsigned int msiof1_clk_d_mux[] = {
2657         MSIOF1_SCK_D_MARK,
2658 };
2659 static const unsigned int msiof1_sync_d_pins[] = {
2660         /* SYNC */
2661         RCAR_GP_PIN(5, 15),
2662 };
2663 static const unsigned int msiof1_sync_d_mux[] = {
2664         MSIOF1_SYNC_D_MARK,
2665 };
2666 static const unsigned int msiof1_ss1_d_pins[] = {
2667         /* SS1 */
2668         RCAR_GP_PIN(5, 16),
2669 };
2670 static const unsigned int msiof1_ss1_d_mux[] = {
2671         MSIOF1_SS1_D_MARK,
2672 };
2673 static const unsigned int msiof1_ss2_d_pins[] = {
2674         /* SS2 */
2675         RCAR_GP_PIN(5, 21),
2676 };
2677 static const unsigned int msiof1_ss2_d_mux[] = {
2678         MSIOF1_SS2_D_MARK,
2679 };
2680 static const unsigned int msiof1_txd_d_pins[] = {
2681         /* TXD */
2682         RCAR_GP_PIN(5, 14),
2683 };
2684 static const unsigned int msiof1_txd_d_mux[] = {
2685         MSIOF1_TXD_D_MARK,
2686 };
2687 static const unsigned int msiof1_rxd_d_pins[] = {
2688         /* RXD */
2689         RCAR_GP_PIN(5, 13),
2690 };
2691 static const unsigned int msiof1_rxd_d_mux[] = {
2692         MSIOF1_RXD_D_MARK,
2693 };
2694 static const unsigned int msiof1_clk_e_pins[] = {
2695         /* SCK */
2696         RCAR_GP_PIN(3, 0),
2697 };
2698 static const unsigned int msiof1_clk_e_mux[] = {
2699         MSIOF1_SCK_E_MARK,
2700 };
2701 static const unsigned int msiof1_sync_e_pins[] = {
2702         /* SYNC */
2703         RCAR_GP_PIN(3, 1),
2704 };
2705 static const unsigned int msiof1_sync_e_mux[] = {
2706         MSIOF1_SYNC_E_MARK,
2707 };
2708 static const unsigned int msiof1_ss1_e_pins[] = {
2709         /* SS1 */
2710         RCAR_GP_PIN(3, 4),
2711 };
2712 static const unsigned int msiof1_ss1_e_mux[] = {
2713         MSIOF1_SS1_E_MARK,
2714 };
2715 static const unsigned int msiof1_ss2_e_pins[] = {
2716         /* SS2 */
2717         RCAR_GP_PIN(3, 5),
2718 };
2719 static const unsigned int msiof1_ss2_e_mux[] = {
2720         MSIOF1_SS2_E_MARK,
2721 };
2722 static const unsigned int msiof1_txd_e_pins[] = {
2723         /* TXD */
2724         RCAR_GP_PIN(3, 3),
2725 };
2726 static const unsigned int msiof1_txd_e_mux[] = {
2727         MSIOF1_TXD_E_MARK,
2728 };
2729 static const unsigned int msiof1_rxd_e_pins[] = {
2730         /* RXD */
2731         RCAR_GP_PIN(3, 2),
2732 };
2733 static const unsigned int msiof1_rxd_e_mux[] = {
2734         MSIOF1_RXD_E_MARK,
2735 };
2736 static const unsigned int msiof1_clk_f_pins[] = {
2737         /* SCK */
2738         RCAR_GP_PIN(5, 23),
2739 };
2740 static const unsigned int msiof1_clk_f_mux[] = {
2741         MSIOF1_SCK_F_MARK,
2742 };
2743 static const unsigned int msiof1_sync_f_pins[] = {
2744         /* SYNC */
2745         RCAR_GP_PIN(5, 24),
2746 };
2747 static const unsigned int msiof1_sync_f_mux[] = {
2748         MSIOF1_SYNC_F_MARK,
2749 };
2750 static const unsigned int msiof1_ss1_f_pins[] = {
2751         /* SS1 */
2752         RCAR_GP_PIN(6, 1),
2753 };
2754 static const unsigned int msiof1_ss1_f_mux[] = {
2755         MSIOF1_SS1_F_MARK,
2756 };
2757 static const unsigned int msiof1_ss2_f_pins[] = {
2758         /* SS2 */
2759         RCAR_GP_PIN(6, 2),
2760 };
2761 static const unsigned int msiof1_ss2_f_mux[] = {
2762         MSIOF1_SS2_F_MARK,
2763 };
2764 static const unsigned int msiof1_txd_f_pins[] = {
2765         /* TXD */
2766         RCAR_GP_PIN(6, 0),
2767 };
2768 static const unsigned int msiof1_txd_f_mux[] = {
2769         MSIOF1_TXD_F_MARK,
2770 };
2771 static const unsigned int msiof1_rxd_f_pins[] = {
2772         /* RXD */
2773         RCAR_GP_PIN(5, 25),
2774 };
2775 static const unsigned int msiof1_rxd_f_mux[] = {
2776         MSIOF1_RXD_F_MARK,
2777 };
2778 static const unsigned int msiof1_clk_g_pins[] = {
2779         /* SCK */
2780         RCAR_GP_PIN(3, 6),
2781 };
2782 static const unsigned int msiof1_clk_g_mux[] = {
2783         MSIOF1_SCK_G_MARK,
2784 };
2785 static const unsigned int msiof1_sync_g_pins[] = {
2786         /* SYNC */
2787         RCAR_GP_PIN(3, 7),
2788 };
2789 static const unsigned int msiof1_sync_g_mux[] = {
2790         MSIOF1_SYNC_G_MARK,
2791 };
2792 static const unsigned int msiof1_ss1_g_pins[] = {
2793         /* SS1 */
2794         RCAR_GP_PIN(3, 10),
2795 };
2796 static const unsigned int msiof1_ss1_g_mux[] = {
2797         MSIOF1_SS1_G_MARK,
2798 };
2799 static const unsigned int msiof1_ss2_g_pins[] = {
2800         /* SS2 */
2801         RCAR_GP_PIN(3, 11),
2802 };
2803 static const unsigned int msiof1_ss2_g_mux[] = {
2804         MSIOF1_SS2_G_MARK,
2805 };
2806 static const unsigned int msiof1_txd_g_pins[] = {
2807         /* TXD */
2808         RCAR_GP_PIN(3, 9),
2809 };
2810 static const unsigned int msiof1_txd_g_mux[] = {
2811         MSIOF1_TXD_G_MARK,
2812 };
2813 static const unsigned int msiof1_rxd_g_pins[] = {
2814         /* RXD */
2815         RCAR_GP_PIN(3, 8),
2816 };
2817 static const unsigned int msiof1_rxd_g_mux[] = {
2818         MSIOF1_RXD_G_MARK,
2819 };
2820 /* - MSIOF2 ----------------------------------------------------------------- */
2821 static const unsigned int msiof2_clk_a_pins[] = {
2822         /* SCK */
2823         RCAR_GP_PIN(1, 9),
2824 };
2825 static const unsigned int msiof2_clk_a_mux[] = {
2826         MSIOF2_SCK_A_MARK,
2827 };
2828 static const unsigned int msiof2_sync_a_pins[] = {
2829         /* SYNC */
2830         RCAR_GP_PIN(1, 8),
2831 };
2832 static const unsigned int msiof2_sync_a_mux[] = {
2833         MSIOF2_SYNC_A_MARK,
2834 };
2835 static const unsigned int msiof2_ss1_a_pins[] = {
2836         /* SS1 */
2837         RCAR_GP_PIN(1, 6),
2838 };
2839 static const unsigned int msiof2_ss1_a_mux[] = {
2840         MSIOF2_SS1_A_MARK,
2841 };
2842 static const unsigned int msiof2_ss2_a_pins[] = {
2843         /* SS2 */
2844         RCAR_GP_PIN(1, 7),
2845 };
2846 static const unsigned int msiof2_ss2_a_mux[] = {
2847         MSIOF2_SS2_A_MARK,
2848 };
2849 static const unsigned int msiof2_txd_a_pins[] = {
2850         /* TXD */
2851         RCAR_GP_PIN(1, 11),
2852 };
2853 static const unsigned int msiof2_txd_a_mux[] = {
2854         MSIOF2_TXD_A_MARK,
2855 };
2856 static const unsigned int msiof2_rxd_a_pins[] = {
2857         /* RXD */
2858         RCAR_GP_PIN(1, 10),
2859 };
2860 static const unsigned int msiof2_rxd_a_mux[] = {
2861         MSIOF2_RXD_A_MARK,
2862 };
2863 static const unsigned int msiof2_clk_b_pins[] = {
2864         /* SCK */
2865         RCAR_GP_PIN(0, 4),
2866 };
2867 static const unsigned int msiof2_clk_b_mux[] = {
2868         MSIOF2_SCK_B_MARK,
2869 };
2870 static const unsigned int msiof2_sync_b_pins[] = {
2871         /* SYNC */
2872         RCAR_GP_PIN(0, 5),
2873 };
2874 static const unsigned int msiof2_sync_b_mux[] = {
2875         MSIOF2_SYNC_B_MARK,
2876 };
2877 static const unsigned int msiof2_ss1_b_pins[] = {
2878         /* SS1 */
2879         RCAR_GP_PIN(0, 0),
2880 };
2881 static const unsigned int msiof2_ss1_b_mux[] = {
2882         MSIOF2_SS1_B_MARK,
2883 };
2884 static const unsigned int msiof2_ss2_b_pins[] = {
2885         /* SS2 */
2886         RCAR_GP_PIN(0, 1),
2887 };
2888 static const unsigned int msiof2_ss2_b_mux[] = {
2889         MSIOF2_SS2_B_MARK,
2890 };
2891 static const unsigned int msiof2_txd_b_pins[] = {
2892         /* TXD */
2893         RCAR_GP_PIN(0, 7),
2894 };
2895 static const unsigned int msiof2_txd_b_mux[] = {
2896         MSIOF2_TXD_B_MARK,
2897 };
2898 static const unsigned int msiof2_rxd_b_pins[] = {
2899         /* RXD */
2900         RCAR_GP_PIN(0, 6),
2901 };
2902 static const unsigned int msiof2_rxd_b_mux[] = {
2903         MSIOF2_RXD_B_MARK,
2904 };
2905 static const unsigned int msiof2_clk_c_pins[] = {
2906         /* SCK */
2907         RCAR_GP_PIN(2, 12),
2908 };
2909 static const unsigned int msiof2_clk_c_mux[] = {
2910         MSIOF2_SCK_C_MARK,
2911 };
2912 static const unsigned int msiof2_sync_c_pins[] = {
2913         /* SYNC */
2914         RCAR_GP_PIN(2, 11),
2915 };
2916 static const unsigned int msiof2_sync_c_mux[] = {
2917         MSIOF2_SYNC_C_MARK,
2918 };
2919 static const unsigned int msiof2_ss1_c_pins[] = {
2920         /* SS1 */
2921         RCAR_GP_PIN(2, 10),
2922 };
2923 static const unsigned int msiof2_ss1_c_mux[] = {
2924         MSIOF2_SS1_C_MARK,
2925 };
2926 static const unsigned int msiof2_ss2_c_pins[] = {
2927         /* SS2 */
2928         RCAR_GP_PIN(2, 9),
2929 };
2930 static const unsigned int msiof2_ss2_c_mux[] = {
2931         MSIOF2_SS2_C_MARK,
2932 };
2933 static const unsigned int msiof2_txd_c_pins[] = {
2934         /* TXD */
2935         RCAR_GP_PIN(2, 14),
2936 };
2937 static const unsigned int msiof2_txd_c_mux[] = {
2938         MSIOF2_TXD_C_MARK,
2939 };
2940 static const unsigned int msiof2_rxd_c_pins[] = {
2941         /* RXD */
2942         RCAR_GP_PIN(2, 13),
2943 };
2944 static const unsigned int msiof2_rxd_c_mux[] = {
2945         MSIOF2_RXD_C_MARK,
2946 };
2947 static const unsigned int msiof2_clk_d_pins[] = {
2948         /* SCK */
2949         RCAR_GP_PIN(0, 8),
2950 };
2951 static const unsigned int msiof2_clk_d_mux[] = {
2952         MSIOF2_SCK_D_MARK,
2953 };
2954 static const unsigned int msiof2_sync_d_pins[] = {
2955         /* SYNC */
2956         RCAR_GP_PIN(0, 9),
2957 };
2958 static const unsigned int msiof2_sync_d_mux[] = {
2959         MSIOF2_SYNC_D_MARK,
2960 };
2961 static const unsigned int msiof2_ss1_d_pins[] = {
2962         /* SS1 */
2963         RCAR_GP_PIN(0, 12),
2964 };
2965 static const unsigned int msiof2_ss1_d_mux[] = {
2966         MSIOF2_SS1_D_MARK,
2967 };
2968 static const unsigned int msiof2_ss2_d_pins[] = {
2969         /* SS2 */
2970         RCAR_GP_PIN(0, 13),
2971 };
2972 static const unsigned int msiof2_ss2_d_mux[] = {
2973         MSIOF2_SS2_D_MARK,
2974 };
2975 static const unsigned int msiof2_txd_d_pins[] = {
2976         /* TXD */
2977         RCAR_GP_PIN(0, 11),
2978 };
2979 static const unsigned int msiof2_txd_d_mux[] = {
2980         MSIOF2_TXD_D_MARK,
2981 };
2982 static const unsigned int msiof2_rxd_d_pins[] = {
2983         /* RXD */
2984         RCAR_GP_PIN(0, 10),
2985 };
2986 static const unsigned int msiof2_rxd_d_mux[] = {
2987         MSIOF2_RXD_D_MARK,
2988 };
2989 /* - MSIOF3 ----------------------------------------------------------------- */
2990 static const unsigned int msiof3_clk_a_pins[] = {
2991         /* SCK */
2992         RCAR_GP_PIN(0, 0),
2993 };
2994 static const unsigned int msiof3_clk_a_mux[] = {
2995         MSIOF3_SCK_A_MARK,
2996 };
2997 static const unsigned int msiof3_sync_a_pins[] = {
2998         /* SYNC */
2999         RCAR_GP_PIN(0, 1),
3000 };
3001 static const unsigned int msiof3_sync_a_mux[] = {
3002         MSIOF3_SYNC_A_MARK,
3003 };
3004 static const unsigned int msiof3_ss1_a_pins[] = {
3005         /* SS1 */
3006         RCAR_GP_PIN(0, 14),
3007 };
3008 static const unsigned int msiof3_ss1_a_mux[] = {
3009         MSIOF3_SS1_A_MARK,
3010 };
3011 static const unsigned int msiof3_ss2_a_pins[] = {
3012         /* SS2 */
3013         RCAR_GP_PIN(0, 15),
3014 };
3015 static const unsigned int msiof3_ss2_a_mux[] = {
3016         MSIOF3_SS2_A_MARK,
3017 };
3018 static const unsigned int msiof3_txd_a_pins[] = {
3019         /* TXD */
3020         RCAR_GP_PIN(0, 3),
3021 };
3022 static const unsigned int msiof3_txd_a_mux[] = {
3023         MSIOF3_TXD_A_MARK,
3024 };
3025 static const unsigned int msiof3_rxd_a_pins[] = {
3026         /* RXD */
3027         RCAR_GP_PIN(0, 2),
3028 };
3029 static const unsigned int msiof3_rxd_a_mux[] = {
3030         MSIOF3_RXD_A_MARK,
3031 };
3032 static const unsigned int msiof3_clk_b_pins[] = {
3033         /* SCK */
3034         RCAR_GP_PIN(1, 2),
3035 };
3036 static const unsigned int msiof3_clk_b_mux[] = {
3037         MSIOF3_SCK_B_MARK,
3038 };
3039 static const unsigned int msiof3_sync_b_pins[] = {
3040         /* SYNC */
3041         RCAR_GP_PIN(1, 0),
3042 };
3043 static const unsigned int msiof3_sync_b_mux[] = {
3044         MSIOF3_SYNC_B_MARK,
3045 };
3046 static const unsigned int msiof3_ss1_b_pins[] = {
3047         /* SS1 */
3048         RCAR_GP_PIN(1, 4),
3049 };
3050 static const unsigned int msiof3_ss1_b_mux[] = {
3051         MSIOF3_SS1_B_MARK,
3052 };
3053 static const unsigned int msiof3_ss2_b_pins[] = {
3054         /* SS2 */
3055         RCAR_GP_PIN(1, 5),
3056 };
3057 static const unsigned int msiof3_ss2_b_mux[] = {
3058         MSIOF3_SS2_B_MARK,
3059 };
3060 static const unsigned int msiof3_txd_b_pins[] = {
3061         /* TXD */
3062         RCAR_GP_PIN(1, 1),
3063 };
3064 static const unsigned int msiof3_txd_b_mux[] = {
3065         MSIOF3_TXD_B_MARK,
3066 };
3067 static const unsigned int msiof3_rxd_b_pins[] = {
3068         /* RXD */
3069         RCAR_GP_PIN(1, 3),
3070 };
3071 static const unsigned int msiof3_rxd_b_mux[] = {
3072         MSIOF3_RXD_B_MARK,
3073 };
3074 static const unsigned int msiof3_clk_c_pins[] = {
3075         /* SCK */
3076         RCAR_GP_PIN(1, 12),
3077 };
3078 static const unsigned int msiof3_clk_c_mux[] = {
3079         MSIOF3_SCK_C_MARK,
3080 };
3081 static const unsigned int msiof3_sync_c_pins[] = {
3082         /* SYNC */
3083         RCAR_GP_PIN(1, 13),
3084 };
3085 static const unsigned int msiof3_sync_c_mux[] = {
3086         MSIOF3_SYNC_C_MARK,
3087 };
3088 static const unsigned int msiof3_txd_c_pins[] = {
3089         /* TXD */
3090         RCAR_GP_PIN(1, 15),
3091 };
3092 static const unsigned int msiof3_txd_c_mux[] = {
3093         MSIOF3_TXD_C_MARK,
3094 };
3095 static const unsigned int msiof3_rxd_c_pins[] = {
3096         /* RXD */
3097         RCAR_GP_PIN(1, 14),
3098 };
3099 static const unsigned int msiof3_rxd_c_mux[] = {
3100         MSIOF3_RXD_C_MARK,
3101 };
3102 static const unsigned int msiof3_clk_d_pins[] = {
3103         /* SCK */
3104         RCAR_GP_PIN(1, 22),
3105 };
3106 static const unsigned int msiof3_clk_d_mux[] = {
3107         MSIOF3_SCK_D_MARK,
3108 };
3109 static const unsigned int msiof3_sync_d_pins[] = {
3110         /* SYNC */
3111         RCAR_GP_PIN(1, 23),
3112 };
3113 static const unsigned int msiof3_sync_d_mux[] = {
3114         MSIOF3_SYNC_D_MARK,
3115 };
3116 static const unsigned int msiof3_ss1_d_pins[] = {
3117         /* SS1 */
3118         RCAR_GP_PIN(1, 26),
3119 };
3120 static const unsigned int msiof3_ss1_d_mux[] = {
3121         MSIOF3_SS1_D_MARK,
3122 };
3123 static const unsigned int msiof3_txd_d_pins[] = {
3124         /* TXD */
3125         RCAR_GP_PIN(1, 25),
3126 };
3127 static const unsigned int msiof3_txd_d_mux[] = {
3128         MSIOF3_TXD_D_MARK,
3129 };
3130 static const unsigned int msiof3_rxd_d_pins[] = {
3131         /* RXD */
3132         RCAR_GP_PIN(1, 24),
3133 };
3134 static const unsigned int msiof3_rxd_d_mux[] = {
3135         MSIOF3_RXD_D_MARK,
3136 };
3137 static const unsigned int msiof3_clk_e_pins[] = {
3138         /* SCK */
3139         RCAR_GP_PIN(2, 3),
3140 };
3141 static const unsigned int msiof3_clk_e_mux[] = {
3142         MSIOF3_SCK_E_MARK,
3143 };
3144 static const unsigned int msiof3_sync_e_pins[] = {
3145         /* SYNC */
3146         RCAR_GP_PIN(2, 2),
3147 };
3148 static const unsigned int msiof3_sync_e_mux[] = {
3149         MSIOF3_SYNC_E_MARK,
3150 };
3151 static const unsigned int msiof3_ss1_e_pins[] = {
3152         /* SS1 */
3153         RCAR_GP_PIN(2, 1),
3154 };
3155 static const unsigned int msiof3_ss1_e_mux[] = {
3156         MSIOF3_SS1_E_MARK,
3157 };
3158 static const unsigned int msiof3_ss2_e_pins[] = {
3159         /* SS2 */
3160         RCAR_GP_PIN(2, 0),
3161 };
3162 static const unsigned int msiof3_ss2_e_mux[] = {
3163         MSIOF3_SS2_E_MARK,
3164 };
3165 static const unsigned int msiof3_txd_e_pins[] = {
3166         /* TXD */
3167         RCAR_GP_PIN(2, 5),
3168 };
3169 static const unsigned int msiof3_txd_e_mux[] = {
3170         MSIOF3_TXD_E_MARK,
3171 };
3172 static const unsigned int msiof3_rxd_e_pins[] = {
3173         /* RXD */
3174         RCAR_GP_PIN(2, 4),
3175 };
3176 static const unsigned int msiof3_rxd_e_mux[] = {
3177         MSIOF3_RXD_E_MARK,
3178 };
3179
3180 /* - PWM0 --------------------------------------------------------------------*/
3181 static const unsigned int pwm0_pins[] = {
3182         /* PWM */
3183         RCAR_GP_PIN(2, 6),
3184 };
3185 static const unsigned int pwm0_mux[] = {
3186         PWM0_MARK,
3187 };
3188 /* - PWM1 --------------------------------------------------------------------*/
3189 static const unsigned int pwm1_a_pins[] = {
3190         /* PWM */
3191         RCAR_GP_PIN(2, 7),
3192 };
3193 static const unsigned int pwm1_a_mux[] = {
3194         PWM1_A_MARK,
3195 };
3196 static const unsigned int pwm1_b_pins[] = {
3197         /* PWM */
3198         RCAR_GP_PIN(1, 8),
3199 };
3200 static const unsigned int pwm1_b_mux[] = {
3201         PWM1_B_MARK,
3202 };
3203 /* - PWM2 --------------------------------------------------------------------*/
3204 static const unsigned int pwm2_a_pins[] = {
3205         /* PWM */
3206         RCAR_GP_PIN(2, 8),
3207 };
3208 static const unsigned int pwm2_a_mux[] = {
3209         PWM2_A_MARK,
3210 };
3211 static const unsigned int pwm2_b_pins[] = {
3212         /* PWM */
3213         RCAR_GP_PIN(1, 11),
3214 };
3215 static const unsigned int pwm2_b_mux[] = {
3216         PWM2_B_MARK,
3217 };
3218 /* - PWM3 --------------------------------------------------------------------*/
3219 static const unsigned int pwm3_a_pins[] = {
3220         /* PWM */
3221         RCAR_GP_PIN(1, 0),
3222 };
3223 static const unsigned int pwm3_a_mux[] = {
3224         PWM3_A_MARK,
3225 };
3226 static const unsigned int pwm3_b_pins[] = {
3227         /* PWM */
3228         RCAR_GP_PIN(2, 2),
3229 };
3230 static const unsigned int pwm3_b_mux[] = {
3231         PWM3_B_MARK,
3232 };
3233 /* - PWM4 --------------------------------------------------------------------*/
3234 static const unsigned int pwm4_a_pins[] = {
3235         /* PWM */
3236         RCAR_GP_PIN(1, 1),
3237 };
3238 static const unsigned int pwm4_a_mux[] = {
3239         PWM4_A_MARK,
3240 };
3241 static const unsigned int pwm4_b_pins[] = {
3242         /* PWM */
3243         RCAR_GP_PIN(2, 3),
3244 };
3245 static const unsigned int pwm4_b_mux[] = {
3246         PWM4_B_MARK,
3247 };
3248 /* - PWM5 --------------------------------------------------------------------*/
3249 static const unsigned int pwm5_a_pins[] = {
3250         /* PWM */
3251         RCAR_GP_PIN(1, 2),
3252 };
3253 static const unsigned int pwm5_a_mux[] = {
3254         PWM5_A_MARK,
3255 };
3256 static const unsigned int pwm5_b_pins[] = {
3257         /* PWM */
3258         RCAR_GP_PIN(2, 4),
3259 };
3260 static const unsigned int pwm5_b_mux[] = {
3261         PWM5_B_MARK,
3262 };
3263 /* - PWM6 --------------------------------------------------------------------*/
3264 static const unsigned int pwm6_a_pins[] = {
3265         /* PWM */
3266         RCAR_GP_PIN(1, 3),
3267 };
3268 static const unsigned int pwm6_a_mux[] = {
3269         PWM6_A_MARK,
3270 };
3271 static const unsigned int pwm6_b_pins[] = {
3272         /* PWM */
3273         RCAR_GP_PIN(2, 5),
3274 };
3275 static const unsigned int pwm6_b_mux[] = {
3276         PWM6_B_MARK,
3277 };
3278
3279 /* - SATA --------------------------------------------------------------------*/
3280 static const unsigned int sata0_devslp_a_pins[] = {
3281         /* DEVSLP */
3282         RCAR_GP_PIN(6, 16),
3283 };
3284 static const unsigned int sata0_devslp_a_mux[] = {
3285         SATA_DEVSLP_A_MARK,
3286 };
3287 static const unsigned int sata0_devslp_b_pins[] = {
3288         /* DEVSLP */
3289         RCAR_GP_PIN(4, 6),
3290 };
3291 static const unsigned int sata0_devslp_b_mux[] = {
3292         SATA_DEVSLP_B_MARK,
3293 };
3294
3295 /* - SCIF0 ------------------------------------------------------------------ */
3296 static const unsigned int scif0_data_pins[] = {
3297         /* RX, TX */
3298         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3299 };
3300 static const unsigned int scif0_data_mux[] = {
3301         RX0_MARK, TX0_MARK,
3302 };
3303 static const unsigned int scif0_clk_pins[] = {
3304         /* SCK */
3305         RCAR_GP_PIN(5, 0),
3306 };
3307 static const unsigned int scif0_clk_mux[] = {
3308         SCK0_MARK,
3309 };
3310 static const unsigned int scif0_ctrl_pins[] = {
3311         /* RTS, CTS */
3312         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3313 };
3314 static const unsigned int scif0_ctrl_mux[] = {
3315         RTS0_N_MARK, CTS0_N_MARK,
3316 };
3317 /* - SCIF1 ------------------------------------------------------------------ */
3318 static const unsigned int scif1_data_a_pins[] = {
3319         /* RX, TX */
3320         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3321 };
3322 static const unsigned int scif1_data_a_mux[] = {
3323         RX1_A_MARK, TX1_A_MARK,
3324 };
3325 static const unsigned int scif1_clk_pins[] = {
3326         /* SCK */
3327         RCAR_GP_PIN(6, 21),
3328 };
3329 static const unsigned int scif1_clk_mux[] = {
3330         SCK1_MARK,
3331 };
3332 static const unsigned int scif1_ctrl_pins[] = {
3333         /* RTS, CTS */
3334         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3335 };
3336 static const unsigned int scif1_ctrl_mux[] = {
3337         RTS1_N_MARK, CTS1_N_MARK,
3338 };
3339
3340 static const unsigned int scif1_data_b_pins[] = {
3341         /* RX, TX */
3342         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3343 };
3344 static const unsigned int scif1_data_b_mux[] = {
3345         RX1_B_MARK, TX1_B_MARK,
3346 };
3347 /* - SCIF2 ------------------------------------------------------------------ */
3348 static const unsigned int scif2_data_a_pins[] = {
3349         /* RX, TX */
3350         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3351 };
3352 static const unsigned int scif2_data_a_mux[] = {
3353         RX2_A_MARK, TX2_A_MARK,
3354 };
3355 static const unsigned int scif2_clk_pins[] = {
3356         /* SCK */
3357         RCAR_GP_PIN(5, 9),
3358 };
3359 static const unsigned int scif2_clk_mux[] = {
3360         SCK2_MARK,
3361 };
3362 static const unsigned int scif2_data_b_pins[] = {
3363         /* RX, TX */
3364         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3365 };
3366 static const unsigned int scif2_data_b_mux[] = {
3367         RX2_B_MARK, TX2_B_MARK,
3368 };
3369 /* - SCIF3 ------------------------------------------------------------------ */
3370 static const unsigned int scif3_data_a_pins[] = {
3371         /* RX, TX */
3372         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3373 };
3374 static const unsigned int scif3_data_a_mux[] = {
3375         RX3_A_MARK, TX3_A_MARK,
3376 };
3377 static const unsigned int scif3_clk_pins[] = {
3378         /* SCK */
3379         RCAR_GP_PIN(1, 22),
3380 };
3381 static const unsigned int scif3_clk_mux[] = {
3382         SCK3_MARK,
3383 };
3384 static const unsigned int scif3_ctrl_pins[] = {
3385         /* RTS, CTS */
3386         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3387 };
3388 static const unsigned int scif3_ctrl_mux[] = {
3389         RTS3_N_MARK, CTS3_N_MARK,
3390 };
3391 static const unsigned int scif3_data_b_pins[] = {
3392         /* RX, TX */
3393         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3394 };
3395 static const unsigned int scif3_data_b_mux[] = {
3396         RX3_B_MARK, TX3_B_MARK,
3397 };
3398 /* - SCIF4 ------------------------------------------------------------------ */
3399 static const unsigned int scif4_data_a_pins[] = {
3400         /* RX, TX */
3401         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3402 };
3403 static const unsigned int scif4_data_a_mux[] = {
3404         RX4_A_MARK, TX4_A_MARK,
3405 };
3406 static const unsigned int scif4_clk_a_pins[] = {
3407         /* SCK */
3408         RCAR_GP_PIN(2, 10),
3409 };
3410 static const unsigned int scif4_clk_a_mux[] = {
3411         SCK4_A_MARK,
3412 };
3413 static const unsigned int scif4_ctrl_a_pins[] = {
3414         /* RTS, CTS */
3415         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3416 };
3417 static const unsigned int scif4_ctrl_a_mux[] = {
3418         RTS4_N_A_MARK, CTS4_N_A_MARK,
3419 };
3420 static const unsigned int scif4_data_b_pins[] = {
3421         /* RX, TX */
3422         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3423 };
3424 static const unsigned int scif4_data_b_mux[] = {
3425         RX4_B_MARK, TX4_B_MARK,
3426 };
3427 static const unsigned int scif4_clk_b_pins[] = {
3428         /* SCK */
3429         RCAR_GP_PIN(1, 5),
3430 };
3431 static const unsigned int scif4_clk_b_mux[] = {
3432         SCK4_B_MARK,
3433 };
3434 static const unsigned int scif4_ctrl_b_pins[] = {
3435         /* RTS, CTS */
3436         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3437 };
3438 static const unsigned int scif4_ctrl_b_mux[] = {
3439         RTS4_N_B_MARK, CTS4_N_B_MARK,
3440 };
3441 static const unsigned int scif4_data_c_pins[] = {
3442         /* RX, TX */
3443         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3444 };
3445 static const unsigned int scif4_data_c_mux[] = {
3446         RX4_C_MARK, TX4_C_MARK,
3447 };
3448 static const unsigned int scif4_clk_c_pins[] = {
3449         /* SCK */
3450         RCAR_GP_PIN(0, 8),
3451 };
3452 static const unsigned int scif4_clk_c_mux[] = {
3453         SCK4_C_MARK,
3454 };
3455 static const unsigned int scif4_ctrl_c_pins[] = {
3456         /* RTS, CTS */
3457         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3458 };
3459 static const unsigned int scif4_ctrl_c_mux[] = {
3460         RTS4_N_C_MARK, CTS4_N_C_MARK,
3461 };
3462 /* - SCIF5 ------------------------------------------------------------------ */
3463 static const unsigned int scif5_data_a_pins[] = {
3464         /* RX, TX */
3465         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3466 };
3467 static const unsigned int scif5_data_a_mux[] = {
3468         RX5_A_MARK, TX5_A_MARK,
3469 };
3470 static const unsigned int scif5_clk_a_pins[] = {
3471         /* SCK */
3472         RCAR_GP_PIN(6, 21),
3473 };
3474 static const unsigned int scif5_clk_a_mux[] = {
3475         SCK5_A_MARK,
3476 };
3477 static const unsigned int scif5_data_b_pins[] = {
3478         /* RX, TX */
3479         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3480 };
3481 static const unsigned int scif5_data_b_mux[] = {
3482         RX5_B_MARK, TX5_B_MARK,
3483 };
3484 static const unsigned int scif5_clk_b_pins[] = {
3485         /* SCK */
3486         RCAR_GP_PIN(5, 0),
3487 };
3488 static const unsigned int scif5_clk_b_mux[] = {
3489         SCK5_B_MARK,
3490 };
3491
3492 /* - SCIF Clock ------------------------------------------------------------- */
3493 static const unsigned int scif_clk_a_pins[] = {
3494         /* SCIF_CLK */
3495         RCAR_GP_PIN(6, 23),
3496 };
3497 static const unsigned int scif_clk_a_mux[] = {
3498         SCIF_CLK_A_MARK,
3499 };
3500 static const unsigned int scif_clk_b_pins[] = {
3501         /* SCIF_CLK */
3502         RCAR_GP_PIN(5, 9),
3503 };
3504 static const unsigned int scif_clk_b_mux[] = {
3505         SCIF_CLK_B_MARK,
3506 };
3507
3508 /* - SDHI0 ------------------------------------------------------------------ */
3509 static const unsigned int sdhi0_data1_pins[] = {
3510         /* D0 */
3511         RCAR_GP_PIN(3, 2),
3512 };
3513 static const unsigned int sdhi0_data1_mux[] = {
3514         SD0_DAT0_MARK,
3515 };
3516 static const unsigned int sdhi0_data4_pins[] = {
3517         /* D[0:3] */
3518         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3519         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3520 };
3521 static const unsigned int sdhi0_data4_mux[] = {
3522         SD0_DAT0_MARK, SD0_DAT1_MARK,
3523         SD0_DAT2_MARK, SD0_DAT3_MARK,
3524 };
3525 static const unsigned int sdhi0_ctrl_pins[] = {
3526         /* CLK, CMD */
3527         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3528 };
3529 static const unsigned int sdhi0_ctrl_mux[] = {
3530         SD0_CLK_MARK, SD0_CMD_MARK,
3531 };
3532 static const unsigned int sdhi0_cd_pins[] = {
3533         /* CD */
3534         RCAR_GP_PIN(3, 12),
3535 };
3536 static const unsigned int sdhi0_cd_mux[] = {
3537         SD0_CD_MARK,
3538 };
3539 static const unsigned int sdhi0_wp_pins[] = {
3540         /* WP */
3541         RCAR_GP_PIN(3, 13),
3542 };
3543 static const unsigned int sdhi0_wp_mux[] = {
3544         SD0_WP_MARK,
3545 };
3546 /* - SDHI1 ------------------------------------------------------------------ */
3547 static const unsigned int sdhi1_data1_pins[] = {
3548         /* D0 */
3549         RCAR_GP_PIN(3, 8),
3550 };
3551 static const unsigned int sdhi1_data1_mux[] = {
3552         SD1_DAT0_MARK,
3553 };
3554 static const unsigned int sdhi1_data4_pins[] = {
3555         /* D[0:3] */
3556         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3557         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3558 };
3559 static const unsigned int sdhi1_data4_mux[] = {
3560         SD1_DAT0_MARK, SD1_DAT1_MARK,
3561         SD1_DAT2_MARK, SD1_DAT3_MARK,
3562 };
3563 static const unsigned int sdhi1_ctrl_pins[] = {
3564         /* CLK, CMD */
3565         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3566 };
3567 static const unsigned int sdhi1_ctrl_mux[] = {
3568         SD1_CLK_MARK, SD1_CMD_MARK,
3569 };
3570 static const unsigned int sdhi1_cd_pins[] = {
3571         /* CD */
3572         RCAR_GP_PIN(3, 14),
3573 };
3574 static const unsigned int sdhi1_cd_mux[] = {
3575         SD1_CD_MARK,
3576 };
3577 static const unsigned int sdhi1_wp_pins[] = {
3578         /* WP */
3579         RCAR_GP_PIN(3, 15),
3580 };
3581 static const unsigned int sdhi1_wp_mux[] = {
3582         SD1_WP_MARK,
3583 };
3584 /* - SDHI2 ------------------------------------------------------------------ */
3585 static const unsigned int sdhi2_data1_pins[] = {
3586         /* D0 */
3587         RCAR_GP_PIN(4, 2),
3588 };
3589 static const unsigned int sdhi2_data1_mux[] = {
3590         SD2_DAT0_MARK,
3591 };
3592 static const unsigned int sdhi2_data4_pins[] = {
3593         /* D[0:3] */
3594         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3595         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3596 };
3597 static const unsigned int sdhi2_data4_mux[] = {
3598         SD2_DAT0_MARK, SD2_DAT1_MARK,
3599         SD2_DAT2_MARK, SD2_DAT3_MARK,
3600 };
3601 static const unsigned int sdhi2_data8_pins[] = {
3602         /* D[0:7] */
3603         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3604         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3605         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3606         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3607 };
3608 static const unsigned int sdhi2_data8_mux[] = {
3609         SD2_DAT0_MARK, SD2_DAT1_MARK,
3610         SD2_DAT2_MARK, SD2_DAT3_MARK,
3611         SD2_DAT4_MARK, SD2_DAT5_MARK,
3612         SD2_DAT6_MARK, SD2_DAT7_MARK,
3613 };
3614 static const unsigned int sdhi2_ctrl_pins[] = {
3615         /* CLK, CMD */
3616         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3617 };
3618 static const unsigned int sdhi2_ctrl_mux[] = {
3619         SD2_CLK_MARK, SD2_CMD_MARK,
3620 };
3621 static const unsigned int sdhi2_cd_a_pins[] = {
3622         /* CD */
3623         RCAR_GP_PIN(4, 13),
3624 };
3625 static const unsigned int sdhi2_cd_a_mux[] = {
3626         SD2_CD_A_MARK,
3627 };
3628 static const unsigned int sdhi2_cd_b_pins[] = {
3629         /* CD */
3630         RCAR_GP_PIN(5, 10),
3631 };
3632 static const unsigned int sdhi2_cd_b_mux[] = {
3633         SD2_CD_B_MARK,
3634 };
3635 static const unsigned int sdhi2_wp_a_pins[] = {
3636         /* WP */
3637         RCAR_GP_PIN(4, 14),
3638 };
3639 static const unsigned int sdhi2_wp_a_mux[] = {
3640         SD2_WP_A_MARK,
3641 };
3642 static const unsigned int sdhi2_wp_b_pins[] = {
3643         /* WP */
3644         RCAR_GP_PIN(5, 11),
3645 };
3646 static const unsigned int sdhi2_wp_b_mux[] = {
3647         SD2_WP_B_MARK,
3648 };
3649 static const unsigned int sdhi2_ds_pins[] = {
3650         /* DS */
3651         RCAR_GP_PIN(4, 6),
3652 };
3653 static const unsigned int sdhi2_ds_mux[] = {
3654         SD2_DS_MARK,
3655 };
3656 /* - SDHI3 ------------------------------------------------------------------ */
3657 static const unsigned int sdhi3_data1_pins[] = {
3658         /* D0 */
3659         RCAR_GP_PIN(4, 9),
3660 };
3661 static const unsigned int sdhi3_data1_mux[] = {
3662         SD3_DAT0_MARK,
3663 };
3664 static const unsigned int sdhi3_data4_pins[] = {
3665         /* D[0:3] */
3666         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3667         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3668 };
3669 static const unsigned int sdhi3_data4_mux[] = {
3670         SD3_DAT0_MARK, SD3_DAT1_MARK,
3671         SD3_DAT2_MARK, SD3_DAT3_MARK,
3672 };
3673 static const unsigned int sdhi3_data8_pins[] = {
3674         /* D[0:7] */
3675         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3676         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3677         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3678         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3679 };
3680 static const unsigned int sdhi3_data8_mux[] = {
3681         SD3_DAT0_MARK, SD3_DAT1_MARK,
3682         SD3_DAT2_MARK, SD3_DAT3_MARK,
3683         SD3_DAT4_MARK, SD3_DAT5_MARK,
3684         SD3_DAT6_MARK, SD3_DAT7_MARK,
3685 };
3686 static const unsigned int sdhi3_ctrl_pins[] = {
3687         /* CLK, CMD */
3688         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3689 };
3690 static const unsigned int sdhi3_ctrl_mux[] = {
3691         SD3_CLK_MARK, SD3_CMD_MARK,
3692 };
3693 static const unsigned int sdhi3_cd_pins[] = {
3694         /* CD */
3695         RCAR_GP_PIN(4, 15),
3696 };
3697 static const unsigned int sdhi3_cd_mux[] = {
3698         SD3_CD_MARK,
3699 };
3700 static const unsigned int sdhi3_wp_pins[] = {
3701         /* WP */
3702         RCAR_GP_PIN(4, 16),
3703 };
3704 static const unsigned int sdhi3_wp_mux[] = {
3705         SD3_WP_MARK,
3706 };
3707 static const unsigned int sdhi3_ds_pins[] = {
3708         /* DS */
3709         RCAR_GP_PIN(4, 17),
3710 };
3711 static const unsigned int sdhi3_ds_mux[] = {
3712         SD3_DS_MARK,
3713 };
3714
3715 /* - SSI -------------------------------------------------------------------- */
3716 static const unsigned int ssi0_data_pins[] = {
3717         /* SDATA */
3718         RCAR_GP_PIN(6, 2),
3719 };
3720 static const unsigned int ssi0_data_mux[] = {
3721         SSI_SDATA0_MARK,
3722 };
3723 static const unsigned int ssi01239_ctrl_pins[] = {
3724         /* SCK, WS */
3725         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3726 };
3727 static const unsigned int ssi01239_ctrl_mux[] = {
3728         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3729 };
3730 static const unsigned int ssi1_data_a_pins[] = {
3731         /* SDATA */
3732         RCAR_GP_PIN(6, 3),
3733 };
3734 static const unsigned int ssi1_data_a_mux[] = {
3735         SSI_SDATA1_A_MARK,
3736 };
3737 static const unsigned int ssi1_data_b_pins[] = {
3738         /* SDATA */
3739         RCAR_GP_PIN(5, 12),
3740 };
3741 static const unsigned int ssi1_data_b_mux[] = {
3742         SSI_SDATA1_B_MARK,
3743 };
3744 static const unsigned int ssi1_ctrl_a_pins[] = {
3745         /* SCK, WS */
3746         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3747 };
3748 static const unsigned int ssi1_ctrl_a_mux[] = {
3749         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3750 };
3751 static const unsigned int ssi1_ctrl_b_pins[] = {
3752         /* SCK, WS */
3753         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3754 };
3755 static const unsigned int ssi1_ctrl_b_mux[] = {
3756         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3757 };
3758 static const unsigned int ssi2_data_a_pins[] = {
3759         /* SDATA */
3760         RCAR_GP_PIN(6, 4),
3761 };
3762 static const unsigned int ssi2_data_a_mux[] = {
3763         SSI_SDATA2_A_MARK,
3764 };
3765 static const unsigned int ssi2_data_b_pins[] = {
3766         /* SDATA */
3767         RCAR_GP_PIN(5, 13),
3768 };
3769 static const unsigned int ssi2_data_b_mux[] = {
3770         SSI_SDATA2_B_MARK,
3771 };
3772 static const unsigned int ssi2_ctrl_a_pins[] = {
3773         /* SCK, WS */
3774         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3775 };
3776 static const unsigned int ssi2_ctrl_a_mux[] = {
3777         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3778 };
3779 static const unsigned int ssi2_ctrl_b_pins[] = {
3780         /* SCK, WS */
3781         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3782 };
3783 static const unsigned int ssi2_ctrl_b_mux[] = {
3784         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3785 };
3786 static const unsigned int ssi3_data_pins[] = {
3787         /* SDATA */
3788         RCAR_GP_PIN(6, 7),
3789 };
3790 static const unsigned int ssi3_data_mux[] = {
3791         SSI_SDATA3_MARK,
3792 };
3793 static const unsigned int ssi349_ctrl_pins[] = {
3794         /* SCK, WS */
3795         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3796 };
3797 static const unsigned int ssi349_ctrl_mux[] = {
3798         SSI_SCK349_MARK, SSI_WS349_MARK,
3799 };
3800 static const unsigned int ssi4_data_pins[] = {
3801         /* SDATA */
3802         RCAR_GP_PIN(6, 10),
3803 };
3804 static const unsigned int ssi4_data_mux[] = {
3805         SSI_SDATA4_MARK,
3806 };
3807 static const unsigned int ssi4_ctrl_pins[] = {
3808         /* SCK, WS */
3809         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3810 };
3811 static const unsigned int ssi4_ctrl_mux[] = {
3812         SSI_SCK4_MARK, SSI_WS4_MARK,
3813 };
3814 static const unsigned int ssi5_data_pins[] = {
3815         /* SDATA */
3816         RCAR_GP_PIN(6, 13),
3817 };
3818 static const unsigned int ssi5_data_mux[] = {
3819         SSI_SDATA5_MARK,
3820 };
3821 static const unsigned int ssi5_ctrl_pins[] = {
3822         /* SCK, WS */
3823         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3824 };
3825 static const unsigned int ssi5_ctrl_mux[] = {
3826         SSI_SCK5_MARK, SSI_WS5_MARK,
3827 };
3828 static const unsigned int ssi6_data_pins[] = {
3829         /* SDATA */
3830         RCAR_GP_PIN(6, 16),
3831 };
3832 static const unsigned int ssi6_data_mux[] = {
3833         SSI_SDATA6_MARK,
3834 };
3835 static const unsigned int ssi6_ctrl_pins[] = {
3836         /* SCK, WS */
3837         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3838 };
3839 static const unsigned int ssi6_ctrl_mux[] = {
3840         SSI_SCK6_MARK, SSI_WS6_MARK,
3841 };
3842 static const unsigned int ssi7_data_pins[] = {
3843         /* SDATA */
3844         RCAR_GP_PIN(6, 19),
3845 };
3846 static const unsigned int ssi7_data_mux[] = {
3847         SSI_SDATA7_MARK,
3848 };
3849 static const unsigned int ssi78_ctrl_pins[] = {
3850         /* SCK, WS */
3851         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3852 };
3853 static const unsigned int ssi78_ctrl_mux[] = {
3854         SSI_SCK78_MARK, SSI_WS78_MARK,
3855 };
3856 static const unsigned int ssi8_data_pins[] = {
3857         /* SDATA */
3858         RCAR_GP_PIN(6, 20),
3859 };
3860 static const unsigned int ssi8_data_mux[] = {
3861         SSI_SDATA8_MARK,
3862 };
3863 static const unsigned int ssi9_data_a_pins[] = {
3864         /* SDATA */
3865         RCAR_GP_PIN(6, 21),
3866 };
3867 static const unsigned int ssi9_data_a_mux[] = {
3868         SSI_SDATA9_A_MARK,
3869 };
3870 static const unsigned int ssi9_data_b_pins[] = {
3871         /* SDATA */
3872         RCAR_GP_PIN(5, 14),
3873 };
3874 static const unsigned int ssi9_data_b_mux[] = {
3875         SSI_SDATA9_B_MARK,
3876 };
3877 static const unsigned int ssi9_ctrl_a_pins[] = {
3878         /* SCK, WS */
3879         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3880 };
3881 static const unsigned int ssi9_ctrl_a_mux[] = {
3882         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3883 };
3884 static const unsigned int ssi9_ctrl_b_pins[] = {
3885         /* SCK, WS */
3886         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3887 };
3888 static const unsigned int ssi9_ctrl_b_mux[] = {
3889         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3890 };
3891
3892 /* - TMU -------------------------------------------------------------------- */
3893 static const unsigned int tmu_tclk1_a_pins[] = {
3894         /* TCLK */
3895         RCAR_GP_PIN(6, 23),
3896 };
3897 static const unsigned int tmu_tclk1_a_mux[] = {
3898         TCLK1_A_MARK,
3899 };
3900 static const unsigned int tmu_tclk1_b_pins[] = {
3901         /* TCLK */
3902         RCAR_GP_PIN(5, 19),
3903 };
3904 static const unsigned int tmu_tclk1_b_mux[] = {
3905         TCLK1_B_MARK,
3906 };
3907 static const unsigned int tmu_tclk2_a_pins[] = {
3908         /* TCLK */
3909         RCAR_GP_PIN(6, 19),
3910 };
3911 static const unsigned int tmu_tclk2_a_mux[] = {
3912         TCLK2_A_MARK,
3913 };
3914 static const unsigned int tmu_tclk2_b_pins[] = {
3915         /* TCLK */
3916         RCAR_GP_PIN(6, 28),
3917 };
3918 static const unsigned int tmu_tclk2_b_mux[] = {
3919         TCLK2_B_MARK,
3920 };
3921
3922 /* - USB0 ------------------------------------------------------------------- */
3923 static const unsigned int usb0_pins[] = {
3924         /* PWEN, OVC */
3925         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3926 };
3927 static const unsigned int usb0_mux[] = {
3928         USB0_PWEN_MARK, USB0_OVC_MARK,
3929 };
3930 /* - USB1 ------------------------------------------------------------------- */
3931 static const unsigned int usb1_pins[] = {
3932         /* PWEN, OVC */
3933         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3934 };
3935 static const unsigned int usb1_mux[] = {
3936         USB1_PWEN_MARK, USB1_OVC_MARK,
3937 };
3938 /* - USB2 ------------------------------------------------------------------- */
3939 static const unsigned int usb2_pins[] = {
3940         /* PWEN, OVC */
3941         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3942 };
3943 static const unsigned int usb2_mux[] = {
3944         USB2_PWEN_MARK, USB2_OVC_MARK,
3945 };
3946 /* - USB2_CH3 --------------------------------------------------------------- */
3947 static const unsigned int usb2_ch3_pins[] = {
3948         /* PWEN, OVC */
3949         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3950 };
3951 static const unsigned int usb2_ch3_mux[] = {
3952         USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3953 };
3954
3955 /* - USB30 ------------------------------------------------------------------ */
3956 static const unsigned int usb30_pins[] = {
3957         /* PWEN, OVC */
3958         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3959 };
3960 static const unsigned int usb30_mux[] = {
3961         USB30_PWEN_MARK, USB30_OVC_MARK,
3962 };
3963
3964 /* - VIN4 ------------------------------------------------------------------- */
3965 static const unsigned int vin4_data18_a_pins[] = {
3966         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3967         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3968         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3969         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3970         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3971         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3972         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3973         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3974         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3975 };
3976 static const unsigned int vin4_data18_a_mux[] = {
3977         VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3978         VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3979         VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3980         VI4_DATA10_MARK, VI4_DATA11_MARK,
3981         VI4_DATA12_MARK, VI4_DATA13_MARK,
3982         VI4_DATA14_MARK, VI4_DATA15_MARK,
3983         VI4_DATA18_MARK, VI4_DATA19_MARK,
3984         VI4_DATA20_MARK, VI4_DATA21_MARK,
3985         VI4_DATA22_MARK, VI4_DATA23_MARK,
3986 };
3987 static const unsigned int vin4_data18_b_pins[] = {
3988         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3989         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3990         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3991         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3992         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3993         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3994         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3995         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3996         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3997 };
3998 static const unsigned int vin4_data18_b_mux[] = {
3999         VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4000         VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4001         VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4002         VI4_DATA10_MARK, VI4_DATA11_MARK,
4003         VI4_DATA12_MARK, VI4_DATA13_MARK,
4004         VI4_DATA14_MARK, VI4_DATA15_MARK,
4005         VI4_DATA18_MARK, VI4_DATA19_MARK,
4006         VI4_DATA20_MARK, VI4_DATA21_MARK,
4007         VI4_DATA22_MARK, VI4_DATA23_MARK,
4008 };
4009 static const union vin_data vin4_data_a_pins = {
4010         .data24 = {
4011                 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4012                 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4013                 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4014                 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4015                 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4016                 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4017                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4018                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4019                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4020                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4021                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4022                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4023         },
4024 };
4025 static const union vin_data vin4_data_a_mux = {
4026         .data24 = {
4027                 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4028                 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4029                 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4030                 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4031                 VI4_DATA8_MARK,  VI4_DATA9_MARK,
4032                 VI4_DATA10_MARK, VI4_DATA11_MARK,
4033                 VI4_DATA12_MARK, VI4_DATA13_MARK,
4034                 VI4_DATA14_MARK, VI4_DATA15_MARK,
4035                 VI4_DATA16_MARK, VI4_DATA17_MARK,
4036                 VI4_DATA18_MARK, VI4_DATA19_MARK,
4037                 VI4_DATA20_MARK, VI4_DATA21_MARK,
4038                 VI4_DATA22_MARK, VI4_DATA23_MARK,
4039         },
4040 };
4041 static const union vin_data vin4_data_b_pins = {
4042         .data24 = {
4043                 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4044                 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4045                 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4046                 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4047                 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4048                 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4049                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4050                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4051                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4052                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4053                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4054                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4055         },
4056 };
4057 static const union vin_data vin4_data_b_mux = {
4058         .data24 = {
4059                 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4060                 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4061                 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4062                 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4063                 VI4_DATA8_MARK,  VI4_DATA9_MARK,
4064                 VI4_DATA10_MARK, VI4_DATA11_MARK,
4065                 VI4_DATA12_MARK, VI4_DATA13_MARK,
4066                 VI4_DATA14_MARK, VI4_DATA15_MARK,
4067                 VI4_DATA16_MARK, VI4_DATA17_MARK,
4068                 VI4_DATA18_MARK, VI4_DATA19_MARK,
4069                 VI4_DATA20_MARK, VI4_DATA21_MARK,
4070                 VI4_DATA22_MARK, VI4_DATA23_MARK,
4071         },
4072 };
4073 static const unsigned int vin4_sync_pins[] = {
4074         /* HSYNC#, VSYNC# */
4075         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4076 };
4077 static const unsigned int vin4_sync_mux[] = {
4078         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4079 };
4080 static const unsigned int vin4_field_pins[] = {
4081         /* FIELD */
4082         RCAR_GP_PIN(1, 16),
4083 };
4084 static const unsigned int vin4_field_mux[] = {
4085         VI4_FIELD_MARK,
4086 };
4087 static const unsigned int vin4_clkenb_pins[] = {
4088         /* CLKENB */
4089         RCAR_GP_PIN(1, 19),
4090 };
4091 static const unsigned int vin4_clkenb_mux[] = {
4092         VI4_CLKENB_MARK,
4093 };
4094 static const unsigned int vin4_clk_pins[] = {
4095         /* CLK */
4096         RCAR_GP_PIN(1, 27),
4097 };
4098 static const unsigned int vin4_clk_mux[] = {
4099         VI4_CLK_MARK,
4100 };
4101
4102 /* - VIN5 ------------------------------------------------------------------- */
4103 static const union vin_data16 vin5_data_pins = {
4104         .data16 = {
4105                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4106                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4107                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4108                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4109                 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4110                 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4111                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4112                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4113         },
4114 };
4115 static const union vin_data16 vin5_data_mux = {
4116         .data16 = {
4117                 VI5_DATA0_MARK, VI5_DATA1_MARK,
4118                 VI5_DATA2_MARK, VI5_DATA3_MARK,
4119                 VI5_DATA4_MARK, VI5_DATA5_MARK,
4120                 VI5_DATA6_MARK, VI5_DATA7_MARK,
4121                 VI5_DATA8_MARK,  VI5_DATA9_MARK,
4122                 VI5_DATA10_MARK, VI5_DATA11_MARK,
4123                 VI5_DATA12_MARK, VI5_DATA13_MARK,
4124                 VI5_DATA14_MARK, VI5_DATA15_MARK,
4125         },
4126 };
4127 static const unsigned int vin5_sync_pins[] = {
4128         /* HSYNC#, VSYNC# */
4129         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4130 };
4131 static const unsigned int vin5_sync_mux[] = {
4132         VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4133 };
4134 static const unsigned int vin5_field_pins[] = {
4135         RCAR_GP_PIN(1, 11),
4136 };
4137 static const unsigned int vin5_field_mux[] = {
4138         /* FIELD */
4139         VI5_FIELD_MARK,
4140 };
4141 static const unsigned int vin5_clkenb_pins[] = {
4142         RCAR_GP_PIN(1, 20),
4143 };
4144 static const unsigned int vin5_clkenb_mux[] = {
4145         /* CLKENB */
4146         VI5_CLKENB_MARK,
4147 };
4148 static const unsigned int vin5_clk_pins[] = {
4149         RCAR_GP_PIN(1, 21),
4150 };
4151 static const unsigned int vin5_clk_mux[] = {
4152         /* CLK */
4153         VI5_CLK_MARK,
4154 };
4155
4156 static const struct sh_pfc_pin_group pinmux_groups[] = {
4157         SH_PFC_PIN_GROUP(audio_clk_a_a),
4158         SH_PFC_PIN_GROUP(audio_clk_a_b),
4159         SH_PFC_PIN_GROUP(audio_clk_a_c),
4160         SH_PFC_PIN_GROUP(audio_clk_b_a),
4161         SH_PFC_PIN_GROUP(audio_clk_b_b),
4162         SH_PFC_PIN_GROUP(audio_clk_c_a),
4163         SH_PFC_PIN_GROUP(audio_clk_c_b),
4164         SH_PFC_PIN_GROUP(audio_clkout_a),
4165         SH_PFC_PIN_GROUP(audio_clkout_b),
4166         SH_PFC_PIN_GROUP(audio_clkout_c),
4167         SH_PFC_PIN_GROUP(audio_clkout_d),
4168         SH_PFC_PIN_GROUP(audio_clkout1_a),
4169         SH_PFC_PIN_GROUP(audio_clkout1_b),
4170         SH_PFC_PIN_GROUP(audio_clkout2_a),
4171         SH_PFC_PIN_GROUP(audio_clkout2_b),
4172         SH_PFC_PIN_GROUP(audio_clkout3_a),
4173         SH_PFC_PIN_GROUP(audio_clkout3_b),
4174         SH_PFC_PIN_GROUP(avb_link),
4175         SH_PFC_PIN_GROUP(avb_magic),
4176         SH_PFC_PIN_GROUP(avb_phy_int),
4177         SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),      /* Deprecated */
4178         SH_PFC_PIN_GROUP(avb_mdio),
4179         SH_PFC_PIN_GROUP(avb_mii),
4180         SH_PFC_PIN_GROUP(avb_avtp_pps),
4181         SH_PFC_PIN_GROUP(avb_avtp_match_a),
4182         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4183         SH_PFC_PIN_GROUP(avb_avtp_match_b),
4184         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4185         SH_PFC_PIN_GROUP(can0_data_a),
4186         SH_PFC_PIN_GROUP(can0_data_b),
4187         SH_PFC_PIN_GROUP(can1_data),
4188         SH_PFC_PIN_GROUP(can_clk),
4189         SH_PFC_PIN_GROUP(canfd0_data_a),
4190         SH_PFC_PIN_GROUP(canfd0_data_b),
4191         SH_PFC_PIN_GROUP(canfd1_data),
4192         SH_PFC_PIN_GROUP(drif0_ctrl_a),
4193         SH_PFC_PIN_GROUP(drif0_data0_a),
4194         SH_PFC_PIN_GROUP(drif0_data1_a),
4195         SH_PFC_PIN_GROUP(drif0_ctrl_b),
4196         SH_PFC_PIN_GROUP(drif0_data0_b),
4197         SH_PFC_PIN_GROUP(drif0_data1_b),
4198         SH_PFC_PIN_GROUP(drif0_ctrl_c),
4199         SH_PFC_PIN_GROUP(drif0_data0_c),
4200         SH_PFC_PIN_GROUP(drif0_data1_c),
4201         SH_PFC_PIN_GROUP(drif1_ctrl_a),
4202         SH_PFC_PIN_GROUP(drif1_data0_a),
4203         SH_PFC_PIN_GROUP(drif1_data1_a),
4204         SH_PFC_PIN_GROUP(drif1_ctrl_b),
4205         SH_PFC_PIN_GROUP(drif1_data0_b),
4206         SH_PFC_PIN_GROUP(drif1_data1_b),
4207         SH_PFC_PIN_GROUP(drif1_ctrl_c),
4208         SH_PFC_PIN_GROUP(drif1_data0_c),
4209         SH_PFC_PIN_GROUP(drif1_data1_c),
4210         SH_PFC_PIN_GROUP(drif2_ctrl_a),
4211         SH_PFC_PIN_GROUP(drif2_data0_a),
4212         SH_PFC_PIN_GROUP(drif2_data1_a),
4213         SH_PFC_PIN_GROUP(drif2_ctrl_b),
4214         SH_PFC_PIN_GROUP(drif2_data0_b),
4215         SH_PFC_PIN_GROUP(drif2_data1_b),
4216         SH_PFC_PIN_GROUP(drif3_ctrl_a),
4217         SH_PFC_PIN_GROUP(drif3_data0_a),
4218         SH_PFC_PIN_GROUP(drif3_data1_a),
4219         SH_PFC_PIN_GROUP(drif3_ctrl_b),
4220         SH_PFC_PIN_GROUP(drif3_data0_b),
4221         SH_PFC_PIN_GROUP(drif3_data1_b),
4222         SH_PFC_PIN_GROUP(du_rgb666),
4223         SH_PFC_PIN_GROUP(du_rgb888),
4224         SH_PFC_PIN_GROUP(du_clk_out_0),
4225         SH_PFC_PIN_GROUP(du_clk_out_1),
4226         SH_PFC_PIN_GROUP(du_sync),
4227         SH_PFC_PIN_GROUP(du_oddf),
4228         SH_PFC_PIN_GROUP(du_cde),
4229         SH_PFC_PIN_GROUP(du_disp),
4230         SH_PFC_PIN_GROUP(hdmi0_cec),
4231         SH_PFC_PIN_GROUP(hdmi1_cec),
4232         SH_PFC_PIN_GROUP(hscif0_data),
4233         SH_PFC_PIN_GROUP(hscif0_clk),
4234         SH_PFC_PIN_GROUP(hscif0_ctrl),
4235         SH_PFC_PIN_GROUP(hscif1_data_a),
4236         SH_PFC_PIN_GROUP(hscif1_clk_a),
4237         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4238         SH_PFC_PIN_GROUP(hscif1_data_b),
4239         SH_PFC_PIN_GROUP(hscif1_clk_b),
4240         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4241         SH_PFC_PIN_GROUP(hscif2_data_a),
4242         SH_PFC_PIN_GROUP(hscif2_clk_a),
4243         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4244         SH_PFC_PIN_GROUP(hscif2_data_b),
4245         SH_PFC_PIN_GROUP(hscif2_clk_b),
4246         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4247         SH_PFC_PIN_GROUP(hscif2_data_c),
4248         SH_PFC_PIN_GROUP(hscif2_clk_c),
4249         SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4250         SH_PFC_PIN_GROUP(hscif3_data_a),
4251         SH_PFC_PIN_GROUP(hscif3_clk),
4252         SH_PFC_PIN_GROUP(hscif3_ctrl),
4253         SH_PFC_PIN_GROUP(hscif3_data_b),
4254         SH_PFC_PIN_GROUP(hscif3_data_c),
4255         SH_PFC_PIN_GROUP(hscif3_data_d),
4256         SH_PFC_PIN_GROUP(hscif4_data_a),
4257         SH_PFC_PIN_GROUP(hscif4_clk),
4258         SH_PFC_PIN_GROUP(hscif4_ctrl),
4259         SH_PFC_PIN_GROUP(hscif4_data_b),
4260         SH_PFC_PIN_GROUP(i2c0),
4261         SH_PFC_PIN_GROUP(i2c1_a),
4262         SH_PFC_PIN_GROUP(i2c1_b),
4263         SH_PFC_PIN_GROUP(i2c2_a),
4264         SH_PFC_PIN_GROUP(i2c2_b),
4265         SH_PFC_PIN_GROUP(i2c3),
4266         SH_PFC_PIN_GROUP(i2c5),
4267         SH_PFC_PIN_GROUP(i2c6_a),
4268         SH_PFC_PIN_GROUP(i2c6_b),
4269         SH_PFC_PIN_GROUP(i2c6_c),
4270         SH_PFC_PIN_GROUP(intc_ex_irq0),
4271         SH_PFC_PIN_GROUP(intc_ex_irq1),
4272         SH_PFC_PIN_GROUP(intc_ex_irq2),
4273         SH_PFC_PIN_GROUP(intc_ex_irq3),
4274         SH_PFC_PIN_GROUP(intc_ex_irq4),
4275         SH_PFC_PIN_GROUP(intc_ex_irq5),
4276         SH_PFC_PIN_GROUP(msiof0_clk),
4277         SH_PFC_PIN_GROUP(msiof0_sync),
4278         SH_PFC_PIN_GROUP(msiof0_ss1),
4279         SH_PFC_PIN_GROUP(msiof0_ss2),
4280         SH_PFC_PIN_GROUP(msiof0_txd),
4281         SH_PFC_PIN_GROUP(msiof0_rxd),
4282         SH_PFC_PIN_GROUP(msiof1_clk_a),
4283         SH_PFC_PIN_GROUP(msiof1_sync_a),
4284         SH_PFC_PIN_GROUP(msiof1_ss1_a),
4285         SH_PFC_PIN_GROUP(msiof1_ss2_a),
4286         SH_PFC_PIN_GROUP(msiof1_txd_a),
4287         SH_PFC_PIN_GROUP(msiof1_rxd_a),
4288         SH_PFC_PIN_GROUP(msiof1_clk_b),
4289         SH_PFC_PIN_GROUP(msiof1_sync_b),
4290         SH_PFC_PIN_GROUP(msiof1_ss1_b),
4291         SH_PFC_PIN_GROUP(msiof1_ss2_b),
4292         SH_PFC_PIN_GROUP(msiof1_txd_b),
4293         SH_PFC_PIN_GROUP(msiof1_rxd_b),
4294         SH_PFC_PIN_GROUP(msiof1_clk_c),
4295         SH_PFC_PIN_GROUP(msiof1_sync_c),
4296         SH_PFC_PIN_GROUP(msiof1_ss1_c),
4297         SH_PFC_PIN_GROUP(msiof1_ss2_c),
4298         SH_PFC_PIN_GROUP(msiof1_txd_c),
4299         SH_PFC_PIN_GROUP(msiof1_rxd_c),
4300         SH_PFC_PIN_GROUP(msiof1_clk_d),
4301         SH_PFC_PIN_GROUP(msiof1_sync_d),
4302         SH_PFC_PIN_GROUP(msiof1_ss1_d),
4303         SH_PFC_PIN_GROUP(msiof1_ss2_d),
4304         SH_PFC_PIN_GROUP(msiof1_txd_d),
4305         SH_PFC_PIN_GROUP(msiof1_rxd_d),
4306         SH_PFC_PIN_GROUP(msiof1_clk_e),
4307         SH_PFC_PIN_GROUP(msiof1_sync_e),
4308         SH_PFC_PIN_GROUP(msiof1_ss1_e),
4309         SH_PFC_PIN_GROUP(msiof1_ss2_e),
4310         SH_PFC_PIN_GROUP(msiof1_txd_e),
4311         SH_PFC_PIN_GROUP(msiof1_rxd_e),
4312         SH_PFC_PIN_GROUP(msiof1_clk_f),
4313         SH_PFC_PIN_GROUP(msiof1_sync_f),
4314         SH_PFC_PIN_GROUP(msiof1_ss1_f),
4315         SH_PFC_PIN_GROUP(msiof1_ss2_f),
4316         SH_PFC_PIN_GROUP(msiof1_txd_f),
4317         SH_PFC_PIN_GROUP(msiof1_rxd_f),
4318         SH_PFC_PIN_GROUP(msiof1_clk_g),
4319         SH_PFC_PIN_GROUP(msiof1_sync_g),
4320         SH_PFC_PIN_GROUP(msiof1_ss1_g),
4321         SH_PFC_PIN_GROUP(msiof1_ss2_g),
4322         SH_PFC_PIN_GROUP(msiof1_txd_g),
4323         SH_PFC_PIN_GROUP(msiof1_rxd_g),
4324         SH_PFC_PIN_GROUP(msiof2_clk_a),
4325         SH_PFC_PIN_GROUP(msiof2_sync_a),
4326         SH_PFC_PIN_GROUP(msiof2_ss1_a),
4327         SH_PFC_PIN_GROUP(msiof2_ss2_a),
4328         SH_PFC_PIN_GROUP(msiof2_txd_a),
4329         SH_PFC_PIN_GROUP(msiof2_rxd_a),
4330         SH_PFC_PIN_GROUP(msiof2_clk_b),
4331         SH_PFC_PIN_GROUP(msiof2_sync_b),
4332         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4333         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4334         SH_PFC_PIN_GROUP(msiof2_txd_b),
4335         SH_PFC_PIN_GROUP(msiof2_rxd_b),
4336         SH_PFC_PIN_GROUP(msiof2_clk_c),
4337         SH_PFC_PIN_GROUP(msiof2_sync_c),
4338         SH_PFC_PIN_GROUP(msiof2_ss1_c),
4339         SH_PFC_PIN_GROUP(msiof2_ss2_c),
4340         SH_PFC_PIN_GROUP(msiof2_txd_c),
4341         SH_PFC_PIN_GROUP(msiof2_rxd_c),
4342         SH_PFC_PIN_GROUP(msiof2_clk_d),
4343         SH_PFC_PIN_GROUP(msiof2_sync_d),
4344         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4345         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4346         SH_PFC_PIN_GROUP(msiof2_txd_d),
4347         SH_PFC_PIN_GROUP(msiof2_rxd_d),
4348         SH_PFC_PIN_GROUP(msiof3_clk_a),
4349         SH_PFC_PIN_GROUP(msiof3_sync_a),
4350         SH_PFC_PIN_GROUP(msiof3_ss1_a),
4351         SH_PFC_PIN_GROUP(msiof3_ss2_a),
4352         SH_PFC_PIN_GROUP(msiof3_txd_a),
4353         SH_PFC_PIN_GROUP(msiof3_rxd_a),
4354         SH_PFC_PIN_GROUP(msiof3_clk_b),
4355         SH_PFC_PIN_GROUP(msiof3_sync_b),
4356         SH_PFC_PIN_GROUP(msiof3_ss1_b),
4357         SH_PFC_PIN_GROUP(msiof3_ss2_b),
4358         SH_PFC_PIN_GROUP(msiof3_txd_b),
4359         SH_PFC_PIN_GROUP(msiof3_rxd_b),
4360         SH_PFC_PIN_GROUP(msiof3_clk_c),
4361         SH_PFC_PIN_GROUP(msiof3_sync_c),
4362         SH_PFC_PIN_GROUP(msiof3_txd_c),
4363         SH_PFC_PIN_GROUP(msiof3_rxd_c),
4364         SH_PFC_PIN_GROUP(msiof3_clk_d),
4365         SH_PFC_PIN_GROUP(msiof3_sync_d),
4366         SH_PFC_PIN_GROUP(msiof3_ss1_d),
4367         SH_PFC_PIN_GROUP(msiof3_txd_d),
4368         SH_PFC_PIN_GROUP(msiof3_rxd_d),
4369         SH_PFC_PIN_GROUP(msiof3_clk_e),
4370         SH_PFC_PIN_GROUP(msiof3_sync_e),
4371         SH_PFC_PIN_GROUP(msiof3_ss1_e),
4372         SH_PFC_PIN_GROUP(msiof3_ss2_e),
4373         SH_PFC_PIN_GROUP(msiof3_txd_e),
4374         SH_PFC_PIN_GROUP(msiof3_rxd_e),
4375         SH_PFC_PIN_GROUP(pwm0),
4376         SH_PFC_PIN_GROUP(pwm1_a),
4377         SH_PFC_PIN_GROUP(pwm1_b),
4378         SH_PFC_PIN_GROUP(pwm2_a),
4379         SH_PFC_PIN_GROUP(pwm2_b),
4380         SH_PFC_PIN_GROUP(pwm3_a),
4381         SH_PFC_PIN_GROUP(pwm3_b),
4382         SH_PFC_PIN_GROUP(pwm4_a),
4383         SH_PFC_PIN_GROUP(pwm4_b),
4384         SH_PFC_PIN_GROUP(pwm5_a),
4385         SH_PFC_PIN_GROUP(pwm5_b),
4386         SH_PFC_PIN_GROUP(pwm6_a),
4387         SH_PFC_PIN_GROUP(pwm6_b),
4388         SH_PFC_PIN_GROUP(sata0_devslp_a),
4389         SH_PFC_PIN_GROUP(sata0_devslp_b),
4390         SH_PFC_PIN_GROUP(scif0_data),
4391         SH_PFC_PIN_GROUP(scif0_clk),
4392         SH_PFC_PIN_GROUP(scif0_ctrl),
4393         SH_PFC_PIN_GROUP(scif1_data_a),
4394         SH_PFC_PIN_GROUP(scif1_clk),
4395         SH_PFC_PIN_GROUP(scif1_ctrl),
4396         SH_PFC_PIN_GROUP(scif1_data_b),
4397         SH_PFC_PIN_GROUP(scif2_data_a),
4398         SH_PFC_PIN_GROUP(scif2_clk),
4399         SH_PFC_PIN_GROUP(scif2_data_b),
4400         SH_PFC_PIN_GROUP(scif3_data_a),
4401         SH_PFC_PIN_GROUP(scif3_clk),
4402         SH_PFC_PIN_GROUP(scif3_ctrl),
4403         SH_PFC_PIN_GROUP(scif3_data_b),
4404         SH_PFC_PIN_GROUP(scif4_data_a),
4405         SH_PFC_PIN_GROUP(scif4_clk_a),
4406         SH_PFC_PIN_GROUP(scif4_ctrl_a),
4407         SH_PFC_PIN_GROUP(scif4_data_b),
4408         SH_PFC_PIN_GROUP(scif4_clk_b),
4409         SH_PFC_PIN_GROUP(scif4_ctrl_b),
4410         SH_PFC_PIN_GROUP(scif4_data_c),
4411         SH_PFC_PIN_GROUP(scif4_clk_c),
4412         SH_PFC_PIN_GROUP(scif4_ctrl_c),
4413         SH_PFC_PIN_GROUP(scif5_data_a),
4414         SH_PFC_PIN_GROUP(scif5_clk_a),
4415         SH_PFC_PIN_GROUP(scif5_data_b),
4416         SH_PFC_PIN_GROUP(scif5_clk_b),
4417         SH_PFC_PIN_GROUP(scif_clk_a),
4418         SH_PFC_PIN_GROUP(scif_clk_b),
4419         SH_PFC_PIN_GROUP(sdhi0_data1),
4420         SH_PFC_PIN_GROUP(sdhi0_data4),
4421         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4422         SH_PFC_PIN_GROUP(sdhi0_cd),
4423         SH_PFC_PIN_GROUP(sdhi0_wp),
4424         SH_PFC_PIN_GROUP(sdhi1_data1),
4425         SH_PFC_PIN_GROUP(sdhi1_data4),
4426         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4427         SH_PFC_PIN_GROUP(sdhi1_cd),
4428         SH_PFC_PIN_GROUP(sdhi1_wp),
4429         SH_PFC_PIN_GROUP(sdhi2_data1),
4430         SH_PFC_PIN_GROUP(sdhi2_data4),
4431         SH_PFC_PIN_GROUP(sdhi2_data8),
4432         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4433         SH_PFC_PIN_GROUP(sdhi2_cd_a),
4434         SH_PFC_PIN_GROUP(sdhi2_wp_a),
4435         SH_PFC_PIN_GROUP(sdhi2_cd_b),
4436         SH_PFC_PIN_GROUP(sdhi2_wp_b),
4437         SH_PFC_PIN_GROUP(sdhi2_ds),
4438         SH_PFC_PIN_GROUP(sdhi3_data1),
4439         SH_PFC_PIN_GROUP(sdhi3_data4),
4440         SH_PFC_PIN_GROUP(sdhi3_data8),
4441         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4442         SH_PFC_PIN_GROUP(sdhi3_cd),
4443         SH_PFC_PIN_GROUP(sdhi3_wp),
4444         SH_PFC_PIN_GROUP(sdhi3_ds),
4445         SH_PFC_PIN_GROUP(ssi0_data),
4446         SH_PFC_PIN_GROUP(ssi01239_ctrl),
4447         SH_PFC_PIN_GROUP(ssi1_data_a),
4448         SH_PFC_PIN_GROUP(ssi1_data_b),
4449         SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4450         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4451         SH_PFC_PIN_GROUP(ssi2_data_a),
4452         SH_PFC_PIN_GROUP(ssi2_data_b),
4453         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4454         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4455         SH_PFC_PIN_GROUP(ssi3_data),
4456         SH_PFC_PIN_GROUP(ssi349_ctrl),
4457         SH_PFC_PIN_GROUP(ssi4_data),
4458         SH_PFC_PIN_GROUP(ssi4_ctrl),
4459         SH_PFC_PIN_GROUP(ssi5_data),
4460         SH_PFC_PIN_GROUP(ssi5_ctrl),
4461         SH_PFC_PIN_GROUP(ssi6_data),
4462         SH_PFC_PIN_GROUP(ssi6_ctrl),
4463         SH_PFC_PIN_GROUP(ssi7_data),
4464         SH_PFC_PIN_GROUP(ssi78_ctrl),
4465         SH_PFC_PIN_GROUP(ssi8_data),
4466         SH_PFC_PIN_GROUP(ssi9_data_a),
4467         SH_PFC_PIN_GROUP(ssi9_data_b),
4468         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4469         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4470         SH_PFC_PIN_GROUP(tmu_tclk1_a),
4471         SH_PFC_PIN_GROUP(tmu_tclk1_b),
4472         SH_PFC_PIN_GROUP(tmu_tclk2_a),
4473         SH_PFC_PIN_GROUP(tmu_tclk2_b),
4474         SH_PFC_PIN_GROUP(usb0),
4475         SH_PFC_PIN_GROUP(usb1),
4476         SH_PFC_PIN_GROUP(usb2),
4477         SH_PFC_PIN_GROUP(usb2_ch3),
4478         SH_PFC_PIN_GROUP(usb30),
4479         VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4480         VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4481         VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4482         VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4483         SH_PFC_PIN_GROUP(vin4_data18_a),
4484         VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4485         VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4486         VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4487         VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4488         VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4489         VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4490         SH_PFC_PIN_GROUP(vin4_data18_b),
4491         VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4492         VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4493         SH_PFC_PIN_GROUP(vin4_sync),
4494         SH_PFC_PIN_GROUP(vin4_field),
4495         SH_PFC_PIN_GROUP(vin4_clkenb),
4496         SH_PFC_PIN_GROUP(vin4_clk),
4497         VIN_DATA_PIN_GROUP(vin5_data, 8),
4498         VIN_DATA_PIN_GROUP(vin5_data, 10),
4499         VIN_DATA_PIN_GROUP(vin5_data, 12),
4500         VIN_DATA_PIN_GROUP(vin5_data, 16),
4501         SH_PFC_PIN_GROUP(vin5_sync),
4502         SH_PFC_PIN_GROUP(vin5_field),
4503         SH_PFC_PIN_GROUP(vin5_clkenb),
4504         SH_PFC_PIN_GROUP(vin5_clk),
4505 };
4506
4507 static const char * const audio_clk_groups[] = {
4508         "audio_clk_a_a",
4509         "audio_clk_a_b",
4510         "audio_clk_a_c",
4511         "audio_clk_b_a",
4512         "audio_clk_b_b",
4513         "audio_clk_c_a",
4514         "audio_clk_c_b",
4515         "audio_clkout_a",
4516         "audio_clkout_b",
4517         "audio_clkout_c",
4518         "audio_clkout_d",
4519         "audio_clkout1_a",
4520         "audio_clkout1_b",
4521         "audio_clkout2_a",
4522         "audio_clkout2_b",
4523         "audio_clkout3_a",
4524         "audio_clkout3_b",
4525 };
4526
4527 static const char * const avb_groups[] = {
4528         "avb_link",
4529         "avb_magic",
4530         "avb_phy_int",
4531         "avb_mdc",      /* Deprecated, please use "avb_mdio" instead */
4532         "avb_mdio",
4533         "avb_mii",
4534         "avb_avtp_pps",
4535         "avb_avtp_match_a",
4536         "avb_avtp_capture_a",
4537         "avb_avtp_match_b",
4538         "avb_avtp_capture_b",
4539 };
4540
4541 static const char * const can0_groups[] = {
4542         "can0_data_a",
4543         "can0_data_b",
4544 };
4545
4546 static const char * const can1_groups[] = {
4547         "can1_data",
4548 };
4549
4550 static const char * const can_clk_groups[] = {
4551         "can_clk",
4552 };
4553
4554 static const char * const canfd0_groups[] = {
4555         "canfd0_data_a",
4556         "canfd0_data_b",
4557 };
4558
4559 static const char * const canfd1_groups[] = {
4560         "canfd1_data",
4561 };
4562
4563 static const char * const drif0_groups[] = {
4564         "drif0_ctrl_a",
4565         "drif0_data0_a",
4566         "drif0_data1_a",
4567         "drif0_ctrl_b",
4568         "drif0_data0_b",
4569         "drif0_data1_b",
4570         "drif0_ctrl_c",
4571         "drif0_data0_c",
4572         "drif0_data1_c",
4573 };
4574
4575 static const char * const drif1_groups[] = {
4576         "drif1_ctrl_a",
4577         "drif1_data0_a",
4578         "drif1_data1_a",
4579         "drif1_ctrl_b",
4580         "drif1_data0_b",
4581         "drif1_data1_b",
4582         "drif1_ctrl_c",
4583         "drif1_data0_c",
4584         "drif1_data1_c",
4585 };
4586
4587 static const char * const drif2_groups[] = {
4588         "drif2_ctrl_a",
4589         "drif2_data0_a",
4590         "drif2_data1_a",
4591         "drif2_ctrl_b",
4592         "drif2_data0_b",
4593         "drif2_data1_b",
4594 };
4595
4596 static const char * const drif3_groups[] = {
4597         "drif3_ctrl_a",
4598         "drif3_data0_a",
4599         "drif3_data1_a",
4600         "drif3_ctrl_b",
4601         "drif3_data0_b",
4602         "drif3_data1_b",
4603 };
4604
4605 static const char * const du_groups[] = {
4606         "du_rgb666",
4607         "du_rgb888",
4608         "du_clk_out_0",
4609         "du_clk_out_1",
4610         "du_sync",
4611         "du_oddf",
4612         "du_cde",
4613         "du_disp",
4614 };
4615
4616 static const char * const hdmi0_groups[] = {
4617         "hdmi0_cec",
4618 };
4619
4620 static const char * const hdmi1_groups[] = {
4621         "hdmi1_cec",
4622 };
4623
4624 static const char * const hscif0_groups[] = {
4625         "hscif0_data",
4626         "hscif0_clk",
4627         "hscif0_ctrl",
4628 };
4629
4630 static const char * const hscif1_groups[] = {
4631         "hscif1_data_a",
4632         "hscif1_clk_a",
4633         "hscif1_ctrl_a",
4634         "hscif1_data_b",
4635         "hscif1_clk_b",
4636         "hscif1_ctrl_b",
4637 };
4638
4639 static const char * const hscif2_groups[] = {
4640         "hscif2_data_a",
4641         "hscif2_clk_a",
4642         "hscif2_ctrl_a",
4643         "hscif2_data_b",
4644         "hscif2_clk_b",
4645         "hscif2_ctrl_b",
4646         "hscif2_data_c",
4647         "hscif2_clk_c",
4648         "hscif2_ctrl_c",
4649 };
4650
4651 static const char * const hscif3_groups[] = {
4652         "hscif3_data_a",
4653         "hscif3_clk",
4654         "hscif3_ctrl",
4655         "hscif3_data_b",
4656         "hscif3_data_c",
4657         "hscif3_data_d",
4658 };
4659
4660 static const char * const hscif4_groups[] = {
4661         "hscif4_data_a",
4662         "hscif4_clk",
4663         "hscif4_ctrl",
4664         "hscif4_data_b",
4665 };
4666
4667 static const char * const i2c0_groups[] = {
4668         "i2c0",
4669 };
4670
4671 static const char * const i2c1_groups[] = {
4672         "i2c1_a",
4673         "i2c1_b",
4674 };
4675
4676 static const char * const i2c2_groups[] = {
4677         "i2c2_a",
4678         "i2c2_b",
4679 };
4680
4681 static const char * const i2c3_groups[] = {
4682         "i2c3",
4683 };
4684
4685 static const char * const i2c5_groups[] = {
4686         "i2c5",
4687 };
4688
4689 static const char * const i2c6_groups[] = {
4690         "i2c6_a",
4691         "i2c6_b",
4692         "i2c6_c",
4693 };
4694
4695 static const char * const intc_ex_groups[] = {
4696         "intc_ex_irq0",
4697         "intc_ex_irq1",
4698         "intc_ex_irq2",
4699         "intc_ex_irq3",
4700         "intc_ex_irq4",
4701         "intc_ex_irq5",
4702 };
4703
4704 static const char * const msiof0_groups[] = {
4705         "msiof0_clk",
4706         "msiof0_sync",
4707         "msiof0_ss1",
4708         "msiof0_ss2",
4709         "msiof0_txd",
4710         "msiof0_rxd",
4711 };
4712
4713 static const char * const msiof1_groups[] = {
4714         "msiof1_clk_a",
4715         "msiof1_sync_a",
4716         "msiof1_ss1_a",
4717         "msiof1_ss2_a",
4718         "msiof1_txd_a",
4719         "msiof1_rxd_a",
4720         "msiof1_clk_b",
4721         "msiof1_sync_b",
4722         "msiof1_ss1_b",
4723         "msiof1_ss2_b",
4724         "msiof1_txd_b",
4725         "msiof1_rxd_b",
4726         "msiof1_clk_c",
4727         "msiof1_sync_c",
4728         "msiof1_ss1_c",
4729         "msiof1_ss2_c",
4730         "msiof1_txd_c",
4731         "msiof1_rxd_c",
4732         "msiof1_clk_d",
4733         "msiof1_sync_d",
4734         "msiof1_ss1_d",
4735         "msiof1_ss2_d",
4736         "msiof1_txd_d",
4737         "msiof1_rxd_d",
4738         "msiof1_clk_e",
4739         "msiof1_sync_e",
4740         "msiof1_ss1_e",
4741         "msiof1_ss2_e",
4742         "msiof1_txd_e",
4743         "msiof1_rxd_e",
4744         "msiof1_clk_f",
4745         "msiof1_sync_f",
4746         "msiof1_ss1_f",
4747         "msiof1_ss2_f",
4748         "msiof1_txd_f",
4749         "msiof1_rxd_f",
4750         "msiof1_clk_g",
4751         "msiof1_sync_g",
4752         "msiof1_ss1_g",
4753         "msiof1_ss2_g",
4754         "msiof1_txd_g",
4755         "msiof1_rxd_g",
4756 };
4757
4758 static const char * const msiof2_groups[] = {
4759         "msiof2_clk_a",
4760         "msiof2_sync_a",
4761         "msiof2_ss1_a",
4762         "msiof2_ss2_a",
4763         "msiof2_txd_a",
4764         "msiof2_rxd_a",
4765         "msiof2_clk_b",
4766         "msiof2_sync_b",
4767         "msiof2_ss1_b",
4768         "msiof2_ss2_b",
4769         "msiof2_txd_b",
4770         "msiof2_rxd_b",
4771         "msiof2_clk_c",
4772         "msiof2_sync_c",
4773         "msiof2_ss1_c",
4774         "msiof2_ss2_c",
4775         "msiof2_txd_c",
4776         "msiof2_rxd_c",
4777         "msiof2_clk_d",
4778         "msiof2_sync_d",
4779         "msiof2_ss1_d",
4780         "msiof2_ss2_d",
4781         "msiof2_txd_d",
4782         "msiof2_rxd_d",
4783 };
4784
4785 static const char * const msiof3_groups[] = {
4786         "msiof3_clk_a",
4787         "msiof3_sync_a",
4788         "msiof3_ss1_a",
4789         "msiof3_ss2_a",
4790         "msiof3_txd_a",
4791         "msiof3_rxd_a",
4792         "msiof3_clk_b",
4793         "msiof3_sync_b",
4794         "msiof3_ss1_b",
4795         "msiof3_ss2_b",
4796         "msiof3_txd_b",
4797         "msiof3_rxd_b",
4798         "msiof3_clk_c",
4799         "msiof3_sync_c",
4800         "msiof3_txd_c",
4801         "msiof3_rxd_c",
4802         "msiof3_clk_d",
4803         "msiof3_sync_d",
4804         "msiof3_ss1_d",
4805         "msiof3_txd_d",
4806         "msiof3_rxd_d",
4807         "msiof3_clk_e",
4808         "msiof3_sync_e",
4809         "msiof3_ss1_e",
4810         "msiof3_ss2_e",
4811         "msiof3_txd_e",
4812         "msiof3_rxd_e",
4813 };
4814
4815 static const char * const pwm0_groups[] = {
4816         "pwm0",
4817 };
4818
4819 static const char * const pwm1_groups[] = {
4820         "pwm1_a",
4821         "pwm1_b",
4822 };
4823
4824 static const char * const pwm2_groups[] = {
4825         "pwm2_a",
4826         "pwm2_b",
4827 };
4828
4829 static const char * const pwm3_groups[] = {
4830         "pwm3_a",
4831         "pwm3_b",
4832 };
4833
4834 static const char * const pwm4_groups[] = {
4835         "pwm4_a",
4836         "pwm4_b",
4837 };
4838
4839 static const char * const pwm5_groups[] = {
4840         "pwm5_a",
4841         "pwm5_b",
4842 };
4843
4844 static const char * const pwm6_groups[] = {
4845         "pwm6_a",
4846         "pwm6_b",
4847 };
4848
4849 static const char * const sata0_groups[] = {
4850         "sata0_devslp_a",
4851         "sata0_devslp_b",
4852 };
4853
4854 static const char * const scif0_groups[] = {
4855         "scif0_data",
4856         "scif0_clk",
4857         "scif0_ctrl",
4858 };
4859
4860 static const char * const scif1_groups[] = {
4861         "scif1_data_a",
4862         "scif1_clk",
4863         "scif1_ctrl",
4864         "scif1_data_b",
4865 };
4866
4867 static const char * const scif2_groups[] = {
4868         "scif2_data_a",
4869         "scif2_clk",
4870         "scif2_data_b",
4871 };
4872
4873 static const char * const scif3_groups[] = {
4874         "scif3_data_a",
4875         "scif3_clk",
4876         "scif3_ctrl",
4877         "scif3_data_b",
4878 };
4879
4880 static const char * const scif4_groups[] = {
4881         "scif4_data_a",
4882         "scif4_clk_a",
4883         "scif4_ctrl_a",
4884         "scif4_data_b",
4885         "scif4_clk_b",
4886         "scif4_ctrl_b",
4887         "scif4_data_c",
4888         "scif4_clk_c",
4889         "scif4_ctrl_c",
4890 };
4891
4892 static const char * const scif5_groups[] = {
4893         "scif5_data_a",
4894         "scif5_clk_a",
4895         "scif5_data_b",
4896         "scif5_clk_b",
4897 };
4898
4899 static const char * const scif_clk_groups[] = {
4900         "scif_clk_a",
4901         "scif_clk_b",
4902 };
4903
4904 static const char * const sdhi0_groups[] = {
4905         "sdhi0_data1",
4906         "sdhi0_data4",
4907         "sdhi0_ctrl",
4908         "sdhi0_cd",
4909         "sdhi0_wp",
4910 };
4911
4912 static const char * const sdhi1_groups[] = {
4913         "sdhi1_data1",
4914         "sdhi1_data4",
4915         "sdhi1_ctrl",
4916         "sdhi1_cd",
4917         "sdhi1_wp",
4918 };
4919
4920 static const char * const sdhi2_groups[] = {
4921         "sdhi2_data1",
4922         "sdhi2_data4",
4923         "sdhi2_data8",
4924         "sdhi2_ctrl",
4925         "sdhi2_cd_a",
4926         "sdhi2_wp_a",
4927         "sdhi2_cd_b",
4928         "sdhi2_wp_b",
4929         "sdhi2_ds",
4930 };
4931
4932 static const char * const sdhi3_groups[] = {
4933         "sdhi3_data1",
4934         "sdhi3_data4",
4935         "sdhi3_data8",
4936         "sdhi3_ctrl",
4937         "sdhi3_cd",
4938         "sdhi3_wp",
4939         "sdhi3_ds",
4940 };
4941
4942 static const char * const ssi_groups[] = {
4943         "ssi0_data",
4944         "ssi01239_ctrl",
4945         "ssi1_data_a",
4946         "ssi1_data_b",
4947         "ssi1_ctrl_a",
4948         "ssi1_ctrl_b",
4949         "ssi2_data_a",
4950         "ssi2_data_b",
4951         "ssi2_ctrl_a",
4952         "ssi2_ctrl_b",
4953         "ssi3_data",
4954         "ssi349_ctrl",
4955         "ssi4_data",
4956         "ssi4_ctrl",
4957         "ssi5_data",
4958         "ssi5_ctrl",
4959         "ssi6_data",
4960         "ssi6_ctrl",
4961         "ssi7_data",
4962         "ssi78_ctrl",
4963         "ssi8_data",
4964         "ssi9_data_a",
4965         "ssi9_data_b",
4966         "ssi9_ctrl_a",
4967         "ssi9_ctrl_b",
4968 };
4969
4970 static const char * const tmu_groups[] = {
4971         "tmu_tclk1_a",
4972         "tmu_tclk1_b",
4973         "tmu_tclk2_a",
4974         "tmu_tclk2_b",
4975 };
4976
4977 static const char * const usb0_groups[] = {
4978         "usb0",
4979 };
4980
4981 static const char * const usb1_groups[] = {
4982         "usb1",
4983 };
4984
4985 static const char * const usb2_groups[] = {
4986         "usb2",
4987 };
4988
4989 static const char * const usb2_ch3_groups[] = {
4990         "usb2_ch3",
4991 };
4992
4993 static const char * const usb30_groups[] = {
4994         "usb30",
4995 };
4996
4997 static const char * const vin4_groups[] = {
4998         "vin4_data8_a",
4999         "vin4_data10_a",
5000         "vin4_data12_a",
5001         "vin4_data16_a",
5002         "vin4_data18_a",
5003         "vin4_data20_a",
5004         "vin4_data24_a",
5005         "vin4_data8_b",
5006         "vin4_data10_b",
5007         "vin4_data12_b",
5008         "vin4_data16_b",
5009         "vin4_data18_b",
5010         "vin4_data20_b",
5011         "vin4_data24_b",
5012         "vin4_sync",
5013         "vin4_field",
5014         "vin4_clkenb",
5015         "vin4_clk",
5016 };
5017
5018 static const char * const vin5_groups[] = {
5019         "vin5_data8",
5020         "vin5_data10",
5021         "vin5_data12",
5022         "vin5_data16",
5023         "vin5_sync",
5024         "vin5_field",
5025         "vin5_clkenb",
5026         "vin5_clk",
5027 };
5028
5029 static const struct sh_pfc_function pinmux_functions[] = {
5030         SH_PFC_FUNCTION(audio_clk),
5031         SH_PFC_FUNCTION(avb),
5032         SH_PFC_FUNCTION(can0),
5033         SH_PFC_FUNCTION(can1),
5034         SH_PFC_FUNCTION(can_clk),
5035         SH_PFC_FUNCTION(canfd0),
5036         SH_PFC_FUNCTION(canfd1),
5037         SH_PFC_FUNCTION(drif0),
5038         SH_PFC_FUNCTION(drif1),
5039         SH_PFC_FUNCTION(drif2),
5040         SH_PFC_FUNCTION(drif3),
5041         SH_PFC_FUNCTION(du),
5042         SH_PFC_FUNCTION(hdmi0),
5043         SH_PFC_FUNCTION(hdmi1),
5044         SH_PFC_FUNCTION(hscif0),
5045         SH_PFC_FUNCTION(hscif1),
5046         SH_PFC_FUNCTION(hscif2),
5047         SH_PFC_FUNCTION(hscif3),
5048         SH_PFC_FUNCTION(hscif4),
5049         SH_PFC_FUNCTION(i2c0),
5050         SH_PFC_FUNCTION(i2c1),
5051         SH_PFC_FUNCTION(i2c2),
5052         SH_PFC_FUNCTION(i2c3),
5053         SH_PFC_FUNCTION(i2c5),
5054         SH_PFC_FUNCTION(i2c6),
5055         SH_PFC_FUNCTION(intc_ex),
5056         SH_PFC_FUNCTION(msiof0),
5057         SH_PFC_FUNCTION(msiof1),
5058         SH_PFC_FUNCTION(msiof2),
5059         SH_PFC_FUNCTION(msiof3),
5060         SH_PFC_FUNCTION(pwm0),
5061         SH_PFC_FUNCTION(pwm1),
5062         SH_PFC_FUNCTION(pwm2),
5063         SH_PFC_FUNCTION(pwm3),
5064         SH_PFC_FUNCTION(pwm4),
5065         SH_PFC_FUNCTION(pwm5),
5066         SH_PFC_FUNCTION(pwm6),
5067         SH_PFC_FUNCTION(sata0),
5068         SH_PFC_FUNCTION(scif0),
5069         SH_PFC_FUNCTION(scif1),
5070         SH_PFC_FUNCTION(scif2),
5071         SH_PFC_FUNCTION(scif3),
5072         SH_PFC_FUNCTION(scif4),
5073         SH_PFC_FUNCTION(scif5),
5074         SH_PFC_FUNCTION(scif_clk),
5075         SH_PFC_FUNCTION(sdhi0),
5076         SH_PFC_FUNCTION(sdhi1),
5077         SH_PFC_FUNCTION(sdhi2),
5078         SH_PFC_FUNCTION(sdhi3),
5079         SH_PFC_FUNCTION(ssi),
5080         SH_PFC_FUNCTION(tmu),
5081         SH_PFC_FUNCTION(usb0),
5082         SH_PFC_FUNCTION(usb1),
5083         SH_PFC_FUNCTION(usb2),
5084         SH_PFC_FUNCTION(usb2_ch3),
5085         SH_PFC_FUNCTION(usb30),
5086         SH_PFC_FUNCTION(vin4),
5087         SH_PFC_FUNCTION(vin5),
5088 };
5089
5090 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5091 #define F_(x, y)        FN_##y
5092 #define FM(x)           FN_##x
5093         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
5094                 0, 0,
5095                 0, 0,
5096                 0, 0,
5097                 0, 0,
5098                 0, 0,
5099                 0, 0,
5100                 0, 0,
5101                 0, 0,
5102                 0, 0,
5103                 0, 0,
5104                 0, 0,
5105                 0, 0,
5106                 0, 0,
5107                 0, 0,
5108                 0, 0,
5109                 0, 0,
5110                 GP_0_15_FN,     GPSR0_15,
5111                 GP_0_14_FN,     GPSR0_14,
5112                 GP_0_13_FN,     GPSR0_13,
5113                 GP_0_12_FN,     GPSR0_12,
5114                 GP_0_11_FN,     GPSR0_11,
5115                 GP_0_10_FN,     GPSR0_10,
5116                 GP_0_9_FN,      GPSR0_9,
5117                 GP_0_8_FN,      GPSR0_8,
5118                 GP_0_7_FN,      GPSR0_7,
5119                 GP_0_6_FN,      GPSR0_6,
5120                 GP_0_5_FN,      GPSR0_5,
5121                 GP_0_4_FN,      GPSR0_4,
5122                 GP_0_3_FN,      GPSR0_3,
5123                 GP_0_2_FN,      GPSR0_2,
5124                 GP_0_1_FN,      GPSR0_1,
5125                 GP_0_0_FN,      GPSR0_0, }
5126         },
5127         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
5128                 0, 0,
5129                 0, 0,
5130                 0, 0,
5131                 GP_1_28_FN,     GPSR1_28,
5132                 GP_1_27_FN,     GPSR1_27,
5133                 GP_1_26_FN,     GPSR1_26,
5134                 GP_1_25_FN,     GPSR1_25,
5135                 GP_1_24_FN,     GPSR1_24,
5136                 GP_1_23_FN,     GPSR1_23,
5137                 GP_1_22_FN,     GPSR1_22,
5138                 GP_1_21_FN,     GPSR1_21,
5139                 GP_1_20_FN,     GPSR1_20,
5140                 GP_1_19_FN,     GPSR1_19,
5141                 GP_1_18_FN,     GPSR1_18,
5142                 GP_1_17_FN,     GPSR1_17,
5143                 GP_1_16_FN,     GPSR1_16,
5144                 GP_1_15_FN,     GPSR1_15,
5145                 GP_1_14_FN,     GPSR1_14,
5146                 GP_1_13_FN,     GPSR1_13,
5147                 GP_1_12_FN,     GPSR1_12,
5148                 GP_1_11_FN,     GPSR1_11,
5149                 GP_1_10_FN,     GPSR1_10,
5150                 GP_1_9_FN,      GPSR1_9,
5151                 GP_1_8_FN,      GPSR1_8,
5152                 GP_1_7_FN,      GPSR1_7,
5153                 GP_1_6_FN,      GPSR1_6,
5154                 GP_1_5_FN,      GPSR1_5,
5155                 GP_1_4_FN,      GPSR1_4,
5156                 GP_1_3_FN,      GPSR1_3,
5157                 GP_1_2_FN,      GPSR1_2,
5158                 GP_1_1_FN,      GPSR1_1,
5159                 GP_1_0_FN,      GPSR1_0, }
5160         },
5161         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
5162                 0, 0,
5163                 0, 0,
5164                 0, 0,
5165                 0, 0,
5166                 0, 0,
5167                 0, 0,
5168                 0, 0,
5169                 0, 0,
5170                 0, 0,
5171                 0, 0,
5172                 0, 0,
5173                 0, 0,
5174                 0, 0,
5175                 0, 0,
5176                 0, 0,
5177                 0, 0,
5178                 0, 0,
5179                 GP_2_14_FN,     GPSR2_14,
5180                 GP_2_13_FN,     GPSR2_13,
5181                 GP_2_12_FN,     GPSR2_12,
5182                 GP_2_11_FN,     GPSR2_11,
5183                 GP_2_10_FN,     GPSR2_10,
5184                 GP_2_9_FN,      GPSR2_9,
5185                 GP_2_8_FN,      GPSR2_8,
5186                 GP_2_7_FN,      GPSR2_7,
5187                 GP_2_6_FN,      GPSR2_6,
5188                 GP_2_5_FN,      GPSR2_5,
5189                 GP_2_4_FN,      GPSR2_4,
5190                 GP_2_3_FN,      GPSR2_3,
5191                 GP_2_2_FN,      GPSR2_2,
5192                 GP_2_1_FN,      GPSR2_1,
5193                 GP_2_0_FN,      GPSR2_0, }
5194         },
5195         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
5196                 0, 0,
5197                 0, 0,
5198                 0, 0,
5199                 0, 0,
5200                 0, 0,
5201                 0, 0,
5202                 0, 0,
5203                 0, 0,
5204                 0, 0,
5205                 0, 0,
5206                 0, 0,
5207                 0, 0,
5208                 0, 0,
5209                 0, 0,
5210                 0, 0,
5211                 0, 0,
5212                 GP_3_15_FN,     GPSR3_15,
5213                 GP_3_14_FN,     GPSR3_14,
5214                 GP_3_13_FN,     GPSR3_13,
5215                 GP_3_12_FN,     GPSR3_12,
5216                 GP_3_11_FN,     GPSR3_11,
5217                 GP_3_10_FN,     GPSR3_10,
5218                 GP_3_9_FN,      GPSR3_9,
5219                 GP_3_8_FN,      GPSR3_8,
5220                 GP_3_7_FN,      GPSR3_7,
5221                 GP_3_6_FN,      GPSR3_6,
5222                 GP_3_5_FN,      GPSR3_5,
5223                 GP_3_4_FN,      GPSR3_4,
5224                 GP_3_3_FN,      GPSR3_3,
5225                 GP_3_2_FN,      GPSR3_2,
5226                 GP_3_1_FN,      GPSR3_1,
5227                 GP_3_0_FN,      GPSR3_0, }
5228         },
5229         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
5230                 0, 0,
5231                 0, 0,
5232                 0, 0,
5233                 0, 0,
5234                 0, 0,
5235                 0, 0,
5236                 0, 0,
5237                 0, 0,
5238                 0, 0,
5239                 0, 0,
5240                 0, 0,
5241                 0, 0,
5242                 0, 0,
5243                 0, 0,
5244                 GP_4_17_FN,     GPSR4_17,
5245                 GP_4_16_FN,     GPSR4_16,
5246                 GP_4_15_FN,     GPSR4_15,
5247                 GP_4_14_FN,     GPSR4_14,
5248                 GP_4_13_FN,     GPSR4_13,
5249                 GP_4_12_FN,     GPSR4_12,
5250                 GP_4_11_FN,     GPSR4_11,
5251                 GP_4_10_FN,     GPSR4_10,
5252                 GP_4_9_FN,      GPSR4_9,
5253                 GP_4_8_FN,      GPSR4_8,
5254                 GP_4_7_FN,      GPSR4_7,
5255                 GP_4_6_FN,      GPSR4_6,
5256                 GP_4_5_FN,      GPSR4_5,
5257                 GP_4_4_FN,      GPSR4_4,
5258                 GP_4_3_FN,      GPSR4_3,
5259                 GP_4_2_FN,      GPSR4_2,
5260                 GP_4_1_FN,      GPSR4_1,
5261                 GP_4_0_FN,      GPSR4_0, }
5262         },
5263         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
5264                 0, 0,
5265                 0, 0,
5266                 0, 0,
5267                 0, 0,
5268                 0, 0,
5269                 0, 0,
5270                 GP_5_25_FN,     GPSR5_25,
5271                 GP_5_24_FN,     GPSR5_24,
5272                 GP_5_23_FN,     GPSR5_23,
5273                 GP_5_22_FN,     GPSR5_22,
5274                 GP_5_21_FN,     GPSR5_21,
5275                 GP_5_20_FN,     GPSR5_20,
5276                 GP_5_19_FN,     GPSR5_19,
5277                 GP_5_18_FN,     GPSR5_18,
5278                 GP_5_17_FN,     GPSR5_17,
5279                 GP_5_16_FN,     GPSR5_16,
5280                 GP_5_15_FN,     GPSR5_15,
5281                 GP_5_14_FN,     GPSR5_14,
5282                 GP_5_13_FN,     GPSR5_13,
5283                 GP_5_12_FN,     GPSR5_12,
5284                 GP_5_11_FN,     GPSR5_11,
5285                 GP_5_10_FN,     GPSR5_10,
5286                 GP_5_9_FN,      GPSR5_9,
5287                 GP_5_8_FN,      GPSR5_8,
5288                 GP_5_7_FN,      GPSR5_7,
5289                 GP_5_6_FN,      GPSR5_6,
5290                 GP_5_5_FN,      GPSR5_5,
5291                 GP_5_4_FN,      GPSR5_4,
5292                 GP_5_3_FN,      GPSR5_3,
5293                 GP_5_2_FN,      GPSR5_2,
5294                 GP_5_1_FN,      GPSR5_1,
5295                 GP_5_0_FN,      GPSR5_0, }
5296         },
5297         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
5298                 GP_6_31_FN,     GPSR6_31,
5299                 GP_6_30_FN,     GPSR6_30,
5300                 GP_6_29_FN,     GPSR6_29,
5301                 GP_6_28_FN,     GPSR6_28,
5302                 GP_6_27_FN,     GPSR6_27,
5303                 GP_6_26_FN,     GPSR6_26,
5304                 GP_6_25_FN,     GPSR6_25,
5305                 GP_6_24_FN,     GPSR6_24,
5306                 GP_6_23_FN,     GPSR6_23,
5307                 GP_6_22_FN,     GPSR6_22,
5308                 GP_6_21_FN,     GPSR6_21,
5309                 GP_6_20_FN,     GPSR6_20,
5310                 GP_6_19_FN,     GPSR6_19,
5311                 GP_6_18_FN,     GPSR6_18,
5312                 GP_6_17_FN,     GPSR6_17,
5313                 GP_6_16_FN,     GPSR6_16,
5314                 GP_6_15_FN,     GPSR6_15,
5315                 GP_6_14_FN,     GPSR6_14,
5316                 GP_6_13_FN,     GPSR6_13,
5317                 GP_6_12_FN,     GPSR6_12,
5318                 GP_6_11_FN,     GPSR6_11,
5319                 GP_6_10_FN,     GPSR6_10,
5320                 GP_6_9_FN,      GPSR6_9,
5321                 GP_6_8_FN,      GPSR6_8,
5322                 GP_6_7_FN,      GPSR6_7,
5323                 GP_6_6_FN,      GPSR6_6,
5324                 GP_6_5_FN,      GPSR6_5,
5325                 GP_6_4_FN,      GPSR6_4,
5326                 GP_6_3_FN,      GPSR6_3,
5327                 GP_6_2_FN,      GPSR6_2,
5328                 GP_6_1_FN,      GPSR6_1,
5329                 GP_6_0_FN,      GPSR6_0, }
5330         },
5331         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
5332                 0, 0,
5333                 0, 0,
5334                 0, 0,
5335                 0, 0,
5336                 0, 0,
5337                 0, 0,
5338                 0, 0,
5339                 0, 0,
5340                 0, 0,
5341                 0, 0,
5342                 0, 0,
5343                 0, 0,
5344                 0, 0,
5345                 0, 0,
5346                 0, 0,
5347                 0, 0,
5348                 0, 0,
5349                 0, 0,
5350                 0, 0,
5351                 0, 0,
5352                 0, 0,
5353                 0, 0,
5354                 0, 0,
5355                 0, 0,
5356                 0, 0,
5357                 0, 0,
5358                 0, 0,
5359                 0, 0,
5360                 GP_7_3_FN, GPSR7_3,
5361                 GP_7_2_FN, GPSR7_2,
5362                 GP_7_1_FN, GPSR7_1,
5363                 GP_7_0_FN, GPSR7_0, }
5364         },
5365 #undef F_
5366 #undef FM
5367
5368 #define F_(x, y)        x,
5369 #define FM(x)           FN_##x,
5370         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5371                 IP0_31_28
5372                 IP0_27_24
5373                 IP0_23_20
5374                 IP0_19_16
5375                 IP0_15_12
5376                 IP0_11_8
5377                 IP0_7_4
5378                 IP0_3_0 }
5379         },
5380         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5381                 IP1_31_28
5382                 IP1_27_24
5383                 IP1_23_20
5384                 IP1_19_16
5385                 IP1_15_12
5386                 IP1_11_8
5387                 IP1_7_4
5388                 IP1_3_0 }
5389         },
5390         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5391                 IP2_31_28
5392                 IP2_27_24
5393                 IP2_23_20
5394                 IP2_19_16
5395                 IP2_15_12
5396                 IP2_11_8
5397                 IP2_7_4
5398                 IP2_3_0 }
5399         },
5400         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5401                 IP3_31_28
5402                 IP3_27_24
5403                 IP3_23_20
5404                 IP3_19_16
5405                 IP3_15_12
5406                 IP3_11_8
5407                 IP3_7_4
5408                 IP3_3_0 }
5409         },
5410         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5411                 IP4_31_28
5412                 IP4_27_24
5413                 IP4_23_20
5414                 IP4_19_16
5415                 IP4_15_12
5416                 IP4_11_8
5417                 IP4_7_4
5418                 IP4_3_0 }
5419         },
5420         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5421                 IP5_31_28
5422                 IP5_27_24
5423                 IP5_23_20
5424                 IP5_19_16
5425                 IP5_15_12
5426                 IP5_11_8
5427                 IP5_7_4
5428                 IP5_3_0 }
5429         },
5430         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5431                 IP6_31_28
5432                 IP6_27_24
5433                 IP6_23_20
5434                 IP6_19_16
5435                 IP6_15_12
5436                 IP6_11_8
5437                 IP6_7_4
5438                 IP6_3_0 }
5439         },
5440         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5441                 IP7_31_28
5442                 IP7_27_24
5443                 IP7_23_20
5444                 IP7_19_16
5445                 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5446                 IP7_11_8
5447                 IP7_7_4
5448                 IP7_3_0 }
5449         },
5450         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5451                 IP8_31_28
5452                 IP8_27_24
5453                 IP8_23_20
5454                 IP8_19_16
5455                 IP8_15_12
5456                 IP8_11_8
5457                 IP8_7_4
5458                 IP8_3_0 }
5459         },
5460         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5461                 IP9_31_28
5462                 IP9_27_24
5463                 IP9_23_20
5464                 IP9_19_16
5465                 IP9_15_12
5466                 IP9_11_8
5467                 IP9_7_4
5468                 IP9_3_0 }
5469         },
5470         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5471                 IP10_31_28
5472                 IP10_27_24
5473                 IP10_23_20
5474                 IP10_19_16
5475                 IP10_15_12
5476                 IP10_11_8
5477                 IP10_7_4
5478                 IP10_3_0 }
5479         },
5480         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5481                 IP11_31_28
5482                 IP11_27_24
5483                 IP11_23_20
5484                 IP11_19_16
5485                 IP11_15_12
5486                 IP11_11_8
5487                 IP11_7_4
5488                 IP11_3_0 }
5489         },
5490         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5491                 IP12_31_28
5492                 IP12_27_24
5493                 IP12_23_20
5494                 IP12_19_16
5495                 IP12_15_12
5496                 IP12_11_8
5497                 IP12_7_4
5498                 IP12_3_0 }
5499         },
5500         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5501                 IP13_31_28
5502                 IP13_27_24
5503                 IP13_23_20
5504                 IP13_19_16
5505                 IP13_15_12
5506                 IP13_11_8
5507                 IP13_7_4
5508                 IP13_3_0 }
5509         },
5510         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5511                 IP14_31_28
5512                 IP14_27_24
5513                 IP14_23_20
5514                 IP14_19_16
5515                 IP14_15_12
5516                 IP14_11_8
5517                 IP14_7_4
5518                 IP14_3_0 }
5519         },
5520         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5521                 IP15_31_28
5522                 IP15_27_24
5523                 IP15_23_20
5524                 IP15_19_16
5525                 IP15_15_12
5526                 IP15_11_8
5527                 IP15_7_4
5528                 IP15_3_0 }
5529         },
5530         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5531                 IP16_31_28
5532                 IP16_27_24
5533                 IP16_23_20
5534                 IP16_19_16
5535                 IP16_15_12
5536                 IP16_11_8
5537                 IP16_7_4
5538                 IP16_3_0 }
5539         },
5540         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5541                 IP17_31_28
5542                 IP17_27_24
5543                 IP17_23_20
5544                 IP17_19_16
5545                 IP17_15_12
5546                 IP17_11_8
5547                 IP17_7_4
5548                 IP17_3_0 }
5549         },
5550         { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5551                 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5552                 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5553                 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5554                 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5555                 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5556                 /* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5557                 IP18_7_4
5558                 IP18_3_0 }
5559         },
5560 #undef F_
5561 #undef FM
5562
5563 #define F_(x, y)        x,
5564 #define FM(x)           FN_##x,
5565         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5566                              3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5567                              1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5568                 MOD_SEL0_31_30_29
5569                 MOD_SEL0_28_27
5570                 MOD_SEL0_26_25_24
5571                 MOD_SEL0_23
5572                 MOD_SEL0_22
5573                 MOD_SEL0_21
5574                 MOD_SEL0_20
5575                 MOD_SEL0_19
5576                 MOD_SEL0_18_17
5577                 MOD_SEL0_16
5578                 0, 0, /* RESERVED 15 */
5579                 MOD_SEL0_14_13
5580                 MOD_SEL0_12
5581                 MOD_SEL0_11
5582                 MOD_SEL0_10
5583                 MOD_SEL0_9_8
5584                 MOD_SEL0_7_6
5585                 MOD_SEL0_5
5586                 MOD_SEL0_4_3
5587                 /* RESERVED 2, 1, 0 */
5588                 0, 0, 0, 0, 0, 0, 0, 0 }
5589         },
5590         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5591                              2, 3, 1, 2, 3, 1, 1, 2, 1,
5592                              2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5593                 MOD_SEL1_31_30
5594                 MOD_SEL1_29_28_27
5595                 MOD_SEL1_26
5596                 MOD_SEL1_25_24
5597                 MOD_SEL1_23_22_21
5598                 MOD_SEL1_20
5599                 MOD_SEL1_19
5600                 MOD_SEL1_18_17
5601                 MOD_SEL1_16
5602                 MOD_SEL1_15_14
5603                 MOD_SEL1_13
5604                 MOD_SEL1_12
5605                 MOD_SEL1_11
5606                 MOD_SEL1_10
5607                 MOD_SEL1_9
5608                 0, 0, 0, 0, /* RESERVED 8, 7 */
5609                 MOD_SEL1_6
5610                 MOD_SEL1_5
5611                 MOD_SEL1_4
5612                 MOD_SEL1_3
5613                 MOD_SEL1_2
5614                 MOD_SEL1_1
5615                 MOD_SEL1_0 }
5616         },
5617         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5618                              1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5619                              4, 4, 4, 3, 1) {
5620                 MOD_SEL2_31
5621                 MOD_SEL2_30
5622                 MOD_SEL2_29
5623                 MOD_SEL2_28_27
5624                 MOD_SEL2_26
5625                 MOD_SEL2_25_24_23
5626                 /* RESERVED 22 */
5627                 0, 0,
5628                 MOD_SEL2_21
5629                 MOD_SEL2_20
5630                 MOD_SEL2_19
5631                 MOD_SEL2_18
5632                 MOD_SEL2_17
5633                 /* RESERVED 16 */
5634                 0, 0,
5635                 /* RESERVED 15, 14, 13, 12 */
5636                 0, 0, 0, 0, 0, 0, 0, 0,
5637                 0, 0, 0, 0, 0, 0, 0, 0,
5638                 /* RESERVED 11, 10, 9, 8 */
5639                 0, 0, 0, 0, 0, 0, 0, 0,
5640                 0, 0, 0, 0, 0, 0, 0, 0,
5641                 /* RESERVED 7, 6, 5, 4 */
5642                 0, 0, 0, 0, 0, 0, 0, 0,
5643                 0, 0, 0, 0, 0, 0, 0, 0,
5644                 /* RESERVED 3, 2, 1 */
5645                 0, 0, 0, 0, 0, 0, 0, 0,
5646                 MOD_SEL2_0 }
5647         },
5648         { },
5649 };
5650
5651 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5652         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5653                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5654                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5655                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5656                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5657                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5658                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5659                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5660                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5661         } },
5662         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5663                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5664                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5665                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5666                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5667                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5668                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5669                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5670                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5671         } },
5672         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5673                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5674                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5675                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5676                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5677                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5678                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5679                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5680                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5681         } },
5682         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5683                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5684                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5685                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5686                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5687                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5688                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5689                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5690                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5691         } },
5692         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5693                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5694                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5695                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5696                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5697                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5698                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5699                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5700                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5701         } },
5702         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5703                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5704                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5705                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5706                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5707                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5708                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5709                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5710                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5711         } },
5712         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5713                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5714                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5715                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5716                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5717                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5718                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5719                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5720                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5721         } },
5722         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5723                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5724                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5725                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5726                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5727                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5728                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5729                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5730                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5731         } },
5732         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5733                 { RCAR_GP_PIN(1, 28), 28, 3 },  /* CLKOUT */
5734                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5735                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5736                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5737                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5738                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5739                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5740                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5741         } },
5742         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5743                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5744                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5745                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5746                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5747                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5748                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5749                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5750                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5751         } },
5752         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5753                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5754                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5755                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5756                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5757                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5758                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5759                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5760                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5761         } },
5762         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5763                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5764                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5765                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5766                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5767                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* HDMI0_CEC */
5768                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* HDMI1_CEC */
5769                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5770                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5771         } },
5772         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5773                 { PIN_A_NUMBER('R', 7),  28, 2 },       /* DU_DOTCLKIN2 */
5774                 { PIN_A_NUMBER('R', 8),  24, 2 },       /* DU_DOTCLKIN3 */
5775                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST# */
5776                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5777         } },
5778         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5779                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5780                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5781                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5782                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5783                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5784                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5785                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5786                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5787         } },
5788         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5789                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5790                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5791                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5792                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5793                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5794                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5795                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5796                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5797         } },
5798         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5799                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5800                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5801                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5802                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5803                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5804                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5805                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5806                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5807         } },
5808         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5809                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5810                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5811                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5812                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5813                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5814                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5815                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5816                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5817         } },
5818         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5819                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5820                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5821                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5822                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5823                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5824                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5825                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5826                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5827         } },
5828         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5829                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0 */
5830                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5831                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5832                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5833                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1 */
5834                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5835                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5836                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5837         } },
5838         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5839                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5840                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5841                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5842                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5843                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5844                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5845                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5846                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5847         } },
5848         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5849                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5850                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5851                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5852                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5853                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5854                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5855                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5856                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5857         } },
5858         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5859                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5860                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5861                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5862                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5863                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5864                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5865                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5866                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5867         } },
5868         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5869                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5870                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5871                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5872                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5873                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5874                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5875                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5876                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5877         } },
5878         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5879                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5880                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5881                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5882                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5883                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5884                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5885                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5886                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5887         } },
5888         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5889                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5890                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5891                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5892                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5893                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5894                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* USB2_CH3_PWEN */
5895                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* USB2_CH3_OVC */
5896         } },
5897         { },
5898 };
5899
5900 enum ioctrl_regs {
5901         POCCTRL,
5902 };
5903
5904 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5905         [POCCTRL] = { 0xe6060380, },
5906         { /* sentinel */ },
5907 };
5908
5909 static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5910 {
5911         int bit = -EINVAL;
5912
5913         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5914
5915         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5916                 bit = pin & 0x1f;
5917
5918         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5919                 bit = (pin & 0x1f) + 12;
5920
5921         return bit;
5922 }
5923
5924 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5925         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5926                 [ 0] = PIN_NUMBER('W', 3),      /* QSPI0_SPCLK */
5927                 [ 1] = PIN_A_NUMBER('C', 5),    /* QSPI0_MOSI_IO0 */
5928                 [ 2] = PIN_A_NUMBER('B', 4),    /* QSPI0_MISO_IO1 */
5929                 [ 3] = PIN_NUMBER('Y', 6),      /* QSPI0_IO2 */
5930                 [ 4] = PIN_A_NUMBER('B', 6),    /* QSPI0_IO3 */
5931                 [ 5] = PIN_NUMBER('Y', 3),      /* QSPI0_SSL */
5932                 [ 6] = PIN_NUMBER('V', 3),      /* QSPI1_SPCLK */
5933                 [ 7] = PIN_A_NUMBER('C', 7),    /* QSPI1_MOSI_IO0 */
5934                 [ 8] = PIN_A_NUMBER('E', 5),    /* QSPI1_MISO_IO1 */
5935                 [ 9] = PIN_A_NUMBER('E', 4),    /* QSPI1_IO2 */
5936                 [10] = PIN_A_NUMBER('C', 3),    /* QSPI1_IO3 */
5937                 [11] = PIN_NUMBER('V', 5),      /* QSPI1_SSL */
5938                 [12] = PIN_NUMBER('Y', 7),      /* RPC_INT# */
5939                 [13] = PIN_NUMBER('V', 6),      /* RPC_WP# */
5940                 [14] = PIN_NUMBER('V', 7),      /* RPC_RESET# */
5941                 [15] = PIN_NUMBER('A', 16),     /* AVB_RX_CTL */
5942                 [16] = PIN_NUMBER('B', 19),     /* AVB_RXC */
5943                 [17] = PIN_NUMBER('A', 13),     /* AVB_RD0 */
5944                 [18] = PIN_NUMBER('B', 13),     /* AVB_RD1 */
5945                 [19] = PIN_NUMBER('A', 14),     /* AVB_RD2 */
5946                 [20] = PIN_NUMBER('B', 14),     /* AVB_RD3 */
5947                 [21] = PIN_NUMBER('A', 8),      /* AVB_TX_CTL */
5948                 [22] = PIN_NUMBER('A', 19),     /* AVB_TXC */
5949                 [23] = PIN_NUMBER('A', 18),     /* AVB_TD0 */
5950                 [24] = PIN_NUMBER('B', 18),     /* AVB_TD1 */
5951                 [25] = PIN_NUMBER('A', 17),     /* AVB_TD2 */
5952                 [26] = PIN_NUMBER('B', 17),     /* AVB_TD3 */
5953                 [27] = PIN_NUMBER('A', 12),     /* AVB_TXCREFCLK */
5954                 [28] = PIN_NUMBER('A', 9),      /* AVB_MDIO */
5955                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
5956                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
5957                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
5958         } },
5959         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5960                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
5961                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
5962                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
5963                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
5964                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
5965                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
5966                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
5967                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
5968                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
5969                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
5970                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
5971                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
5972                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
5973                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
5974                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
5975                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
5976                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
5977                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
5978                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
5979                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
5980                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
5981                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
5982                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
5983                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
5984                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
5985                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
5986                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
5987                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
5988                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
5989                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
5990                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
5991                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
5992         } },
5993         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5994                 [ 0] = RCAR_GP_PIN(1, 28),      /* CLKOUT */
5995                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
5996                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N */
5997                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
5998                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
5999                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
6000                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
6001                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
6002                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
6003                 [ 9] = PIN_NUMBER('C', 1),      /* PRESETOUT# */
6004                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
6005                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
6006                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
6007                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
6008                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
6009                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
6010                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
6011                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
6012                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
6013                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
6014                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
6015                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
6016                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
6017                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
6018                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
6019                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
6020                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
6021                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
6022                 [28] = RCAR_GP_PIN(7,  2),      /* HDMI0_CEC */
6023                 [29] = RCAR_GP_PIN(7,  3),      /* HDMI1_CEC */
6024                 [30] = PIN_A_NUMBER('P', 7),    /* DU_DOTCLKIN0 */
6025                 [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
6026         } },
6027         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6028                 [ 0] = PIN_A_NUMBER('R', 7),    /* DU_DOTCLKIN2 */
6029                 [ 1] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN3 */
6030                 [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST# */
6031                 [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
6032                 [ 4] = PIN_A_NUMBER('R', 26),   /* TRST# */
6033                 [ 5] = PIN_A_NUMBER('T', 27),   /* TCK */
6034                 [ 6] = PIN_A_NUMBER('R', 30),   /* TMS */
6035                 [ 7] = PIN_A_NUMBER('R', 29),   /* TDI */
6036                 [ 8] = PIN_NONE,
6037                 [ 9] = PIN_A_NUMBER('T', 30),   /* ASEBRK */
6038                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
6039                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
6040                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
6041                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
6042                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
6043                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
6044                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
6045                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
6046                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
6047                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
6048                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
6049                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
6050                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
6051                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
6052                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
6053                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
6054                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
6055                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
6056                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
6057                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
6058                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
6059                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
6060         } },
6061         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6062                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
6063                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
6064                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
6065                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
6066                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
6067                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
6068                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
6069                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
6070                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
6071                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
6072                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
6073                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
6074                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
6075                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
6076                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
6077                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
6078                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N */
6079                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
6080                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
6081                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
6082                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N */
6083                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
6084                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
6085                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
6086                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
6087                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
6088                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
6089                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
6090                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
6091                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
6092                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
6093                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
6094         } },
6095         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6096                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
6097                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
6098                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
6099                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
6100                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
6101                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
6102                 [ 6] = PIN_NUMBER('H', 37),     /* MLB_REF */
6103                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
6104                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
6105                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
6106                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
6107                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
6108                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
6109                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
6110                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
6111                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
6112                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
6113                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
6114                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
6115                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
6116                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
6117                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
6118                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
6119                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
6120                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
6121                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
6122                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
6123                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
6124                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
6125                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
6126                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
6127                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
6128         } },
6129         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6130                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
6131                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
6132                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
6133                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
6134                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
6135                 [ 5] = RCAR_GP_PIN(6, 30),      /* USB2_CH3_PWEN */
6136                 [ 6] = RCAR_GP_PIN(6, 31),      /* USB2_CH3_OVC */
6137                 [ 7] = PIN_NONE,
6138                 [ 8] = PIN_NONE,
6139                 [ 9] = PIN_NONE,
6140                 [10] = PIN_NONE,
6141                 [11] = PIN_NONE,
6142                 [12] = PIN_NONE,
6143                 [13] = PIN_NONE,
6144                 [14] = PIN_NONE,
6145                 [15] = PIN_NONE,
6146                 [16] = PIN_NONE,
6147                 [17] = PIN_NONE,
6148                 [18] = PIN_NONE,
6149                 [19] = PIN_NONE,
6150                 [20] = PIN_NONE,
6151                 [21] = PIN_NONE,
6152                 [22] = PIN_NONE,
6153                 [23] = PIN_NONE,
6154                 [24] = PIN_NONE,
6155                 [25] = PIN_NONE,
6156                 [26] = PIN_NONE,
6157                 [27] = PIN_NONE,
6158                 [28] = PIN_NONE,
6159                 [29] = PIN_NONE,
6160                 [30] = PIN_NONE,
6161                 [31] = PIN_NONE,
6162         } },
6163         { /* sentinel */ },
6164 };
6165
6166 static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
6167                                             unsigned int pin)
6168 {
6169         const struct pinmux_bias_reg *reg;
6170         unsigned int bit;
6171
6172         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6173         if (!reg)
6174                 return PIN_CONFIG_BIAS_DISABLE;
6175
6176         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6177                 return PIN_CONFIG_BIAS_DISABLE;
6178         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6179                 return PIN_CONFIG_BIAS_PULL_UP;
6180         else
6181                 return PIN_CONFIG_BIAS_PULL_DOWN;
6182 }
6183
6184 static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6185                                    unsigned int bias)
6186 {
6187         const struct pinmux_bias_reg *reg;
6188         u32 enable, updown;
6189         unsigned int bit;
6190
6191         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6192         if (!reg)
6193                 return;
6194
6195         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6196         if (bias != PIN_CONFIG_BIAS_DISABLE)
6197                 enable |= BIT(bit);
6198
6199         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6200         if (bias == PIN_CONFIG_BIAS_PULL_UP)
6201                 updown |= BIT(bit);
6202
6203         sh_pfc_write(pfc, reg->pud, updown);
6204         sh_pfc_write(pfc, reg->puen, enable);
6205 }
6206
6207 static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
6208         .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
6209         .get_bias = r8a7795_pinmux_get_bias,
6210         .set_bias = r8a7795_pinmux_set_bias,
6211 };
6212
6213 const struct sh_pfc_soc_info r8a7795_pinmux_info = {
6214         .name = "r8a77951_pfc",
6215         .ops = &r8a7795_pinmux_ops,
6216         .unlock_reg = 0xe6060000, /* PMMR */
6217
6218         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6219
6220         .pins = pinmux_pins,
6221         .nr_pins = ARRAY_SIZE(pinmux_pins),
6222         .groups = pinmux_groups,
6223         .nr_groups = ARRAY_SIZE(pinmux_groups),
6224         .functions = pinmux_functions,
6225         .nr_functions = ARRAY_SIZE(pinmux_functions),
6226
6227         .cfg_regs = pinmux_config_regs,
6228         .drive_regs = pinmux_drive_regs,
6229         .bias_regs = pinmux_bias_regs,
6230         .ioctrl_regs = pinmux_ioctrl_regs,
6231
6232         .pinmux_data = pinmux_data,
6233         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6234 };