1 // SPDX-License-Identifier: GPL-2.0+
3 * R7S72100 processor support
5 * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
11 #include <dm/pinctrl.h>
13 #include <linux/err.h>
15 #define P(bank) (0x0000 + (bank) * 4)
16 #define PSR(bank) (0x0100 + (bank) * 4)
17 #define PPR(bank) (0x0200 + (bank) * 4)
18 #define PM(bank) (0x0300 + (bank) * 4)
19 #define PMC(bank) (0x0400 + (bank) * 4)
20 #define PFC(bank) (0x0500 + (bank) * 4)
21 #define PFCE(bank) (0x0600 + (bank) * 4)
22 #define PNOT(bank) (0x0700 + (bank) * 4)
23 #define PMSR(bank) (0x0800 + (bank) * 4)
24 #define PMCSR(bank) (0x0900 + (bank) * 4)
25 #define PFCAE(bank) (0x0A00 + (bank) * 4)
26 #define PIBC(bank) (0x4000 + (bank) * 4)
27 #define PBDC(bank) (0x4100 + (bank) * 4)
28 #define PIPC(bank) (0x4200 + (bank) * 4)
30 #define RZA1_PINS_PER_PORT 16
32 DECLARE_GLOBAL_DATA_PTR;
34 struct r7s72100_pfc_platdata {
38 static void r7s72100_pfc_set_function(struct udevice *dev, u16 bank, u16 line,
39 u16 func, u16 inbuf, u16 bidir)
41 struct r7s72100_pfc_platdata *plat = dev_get_platdata(dev);
43 clrsetbits_le16(plat->base + PFCAE(bank), BIT(line),
44 (func & BIT(2)) ? BIT(line) : 0);
45 clrsetbits_le16(plat->base + PFCE(bank), BIT(line),
46 (func & BIT(1)) ? BIT(line) : 0);
47 clrsetbits_le16(plat->base + PFC(bank), BIT(line),
48 (func & BIT(0)) ? BIT(line) : 0);
50 clrsetbits_le16(plat->base + PIBC(bank), BIT(line),
51 inbuf ? BIT(line) : 0);
52 clrsetbits_le16(plat->base + PBDC(bank), BIT(line),
53 bidir ? BIT(line) : 0);
55 setbits_le32(plat->base + PMCSR(bank), BIT(line + 16) | BIT(line));
57 setbits_le16(plat->base + PIPC(bank), BIT(line));
60 static int r7s72100_pfc_set_state(struct udevice *dev, struct udevice *config)
62 const void *blob = gd->fdt_blob;
63 int node = dev_of_offset(config);
68 count = fdtdec_get_int_array_count(blob, node, "pinmux",
69 cells, ARRAY_SIZE(cells));
71 printf("%s: bad pinmux array %d\n", __func__, count);
75 if (count > ARRAY_SIZE(cells)) {
76 printf("%s: unsupported pinmux array count %d\n",
81 for (i = 0 ; i < count; i++) {
82 func = (cells[i] >> 16) & 0xf;
83 if (func == 0 || func > 8) {
84 printf("Invalid cell %i in node %s!\n",
85 count, ofnode_get_name(dev_ofnode(config)));
89 func = (func - 1) & 0x7;
91 bank = (cells[i] / RZA1_PINS_PER_PORT) & 0xff;
92 line = cells[i] % RZA1_PINS_PER_PORT;
95 if (bank == 3 && line == 3 && func == 1)
98 r7s72100_pfc_set_function(dev, bank, line, func, 0, bidir);
104 const struct pinctrl_ops r7s72100_pfc_ops = {
105 .set_state = r7s72100_pfc_set_state,
108 static int r7s72100_pfc_probe(struct udevice *dev)
110 struct r7s72100_pfc_platdata *plat = dev_get_platdata(dev);
111 fdt_addr_t addr_base;
114 addr_base = devfdt_get_addr(dev);
115 if (addr_base == FDT_ADDR_T_NONE)
118 plat->base = (void __iomem *)addr_base;
120 dev_for_each_subnode(node, dev) {
121 struct udevice *cdev;
123 if (!ofnode_read_bool(node, "gpio-controller"))
126 device_bind_driver_to_node(dev, "r7s72100-gpio",
127 ofnode_get_name(node),
134 static const struct udevice_id r7s72100_pfc_match[] = {
135 { .compatible = "renesas,r7s72100-ports" },
139 U_BOOT_DRIVER(r7s72100_pfc) = {
140 .name = "r7s72100_pfc",
141 .id = UCLASS_PINCTRL,
142 .of_match = r7s72100_pfc_match,
143 .probe = r7s72100_pfc_probe,
144 .platdata_auto_alloc_size = sizeof(struct r7s72100_pfc_platdata),
145 .ops = &r7s72100_pfc_ops,