1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013, Sony Mobile Communications AB.
4 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
7 #include <linux/delay.h>
10 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pinctrl/machine.h>
14 #include <linux/pinctrl/pinctrl.h>
15 #include <linux/pinctrl/pinmux.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/slab.h>
19 #include <linux/gpio/driver.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/reboot.h>
24 #include <linux/log2.h>
26 #include <linux/soc/qcom/irq.h>
29 #include "../pinconf.h"
30 #include "pinctrl-msm.h"
31 #include "../pinctrl-utils.h"
33 #define MAX_NR_GPIO 300
34 #define MAX_NR_TILES 4
35 #define PS_HOLD_OFFSET 0x820
38 * struct msm_pinctrl - state for a pinctrl-msm device
39 * @dev: device handle.
40 * @pctrl: pinctrl handle.
41 * @chip: gpiochip handle.
42 * @restart_nb: restart notifier block.
43 * @irq: parent irq for the TLMM irq_chip.
44 * @lock: Spinlock to protect register resources as well
45 * as msm_pinctrl data structures.
46 * @enabled_irqs: Bitmap of currently enabled irqs.
47 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
49 * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller
50 * @soc; Reference to soc_data of platform specific data.
51 * @regs: Base addresses for the TLMM tiles.
55 struct pinctrl_dev *pctrl;
56 struct gpio_chip chip;
57 struct pinctrl_desc desc;
58 struct notifier_block restart_nb;
60 struct irq_chip irq_chip;
65 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
66 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
67 DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO);
69 const struct msm_pinctrl_soc_data *soc;
70 void __iomem *regs[MAX_NR_TILES];
73 #define MSM_ACCESSOR(name) \
74 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
75 const struct msm_pingroup *g) \
77 return readl(pctrl->regs[g->tile] + g->name##_reg); \
79 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
80 const struct msm_pingroup *g) \
82 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
87 MSM_ACCESSOR(intr_cfg)
88 MSM_ACCESSOR(intr_status)
89 MSM_ACCESSOR(intr_target)
91 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
93 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
95 return pctrl->soc->ngroups;
98 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
101 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
103 return pctrl->soc->groups[group].name;
106 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
108 const unsigned **pins,
111 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
113 *pins = pctrl->soc->groups[group].pins;
114 *num_pins = pctrl->soc->groups[group].npins;
118 static const struct pinctrl_ops msm_pinctrl_ops = {
119 .get_groups_count = msm_get_groups_count,
120 .get_group_name = msm_get_group_name,
121 .get_group_pins = msm_get_group_pins,
122 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
123 .dt_free_map = pinctrl_utils_free_map,
126 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
128 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
129 struct gpio_chip *chip = &pctrl->chip;
131 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
134 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
136 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
138 return pctrl->soc->nfunctions;
141 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
144 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
146 return pctrl->soc->functions[function].name;
149 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
151 const char * const **groups,
152 unsigned * const num_groups)
154 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
156 *groups = pctrl->soc->functions[function].groups;
157 *num_groups = pctrl->soc->functions[function].ngroups;
161 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
165 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
166 const struct msm_pingroup *g;
171 g = &pctrl->soc->groups[group];
172 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
174 for (i = 0; i < g->nfuncs; i++) {
175 if (g->funcs[i] == function)
179 if (WARN_ON(i == g->nfuncs))
182 raw_spin_lock_irqsave(&pctrl->lock, flags);
184 val = msm_readl_ctl(pctrl, g);
186 val |= i << g->mux_bit;
187 msm_writel_ctl(val, pctrl, g);
189 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
194 static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
195 struct pinctrl_gpio_range *range,
198 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
199 const struct msm_pingroup *g = &pctrl->soc->groups[offset];
201 /* No funcs? Probably ACPI so can't do anything here */
205 /* For now assume function 0 is GPIO because it always is */
206 return msm_pinmux_set_mux(pctldev, g->funcs[0], offset);
209 static const struct pinmux_ops msm_pinmux_ops = {
210 .request = msm_pinmux_request,
211 .get_functions_count = msm_get_functions_count,
212 .get_function_name = msm_get_function_name,
213 .get_function_groups = msm_get_function_groups,
214 .gpio_request_enable = msm_pinmux_request_gpio,
215 .set_mux = msm_pinmux_set_mux,
218 static int msm_config_reg(struct msm_pinctrl *pctrl,
219 const struct msm_pingroup *g,
225 case PIN_CONFIG_BIAS_DISABLE:
226 case PIN_CONFIG_BIAS_PULL_DOWN:
227 case PIN_CONFIG_BIAS_BUS_HOLD:
228 case PIN_CONFIG_BIAS_PULL_UP:
232 case PIN_CONFIG_DRIVE_STRENGTH:
236 case PIN_CONFIG_OUTPUT:
237 case PIN_CONFIG_INPUT_ENABLE:
248 #define MSM_NO_PULL 0
249 #define MSM_PULL_DOWN 1
251 #define MSM_PULL_UP_NO_KEEPER 2
252 #define MSM_PULL_UP 3
254 static unsigned msm_regval_to_drive(u32 val)
256 return (val + 1) * 2;
259 static int msm_config_group_get(struct pinctrl_dev *pctldev,
261 unsigned long *config)
263 const struct msm_pingroup *g;
264 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
265 unsigned param = pinconf_to_config_param(*config);
272 g = &pctrl->soc->groups[group];
274 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
278 val = msm_readl_ctl(pctrl, g);
279 arg = (val >> bit) & mask;
281 /* Convert register value to pinconf value */
283 case PIN_CONFIG_BIAS_DISABLE:
284 if (arg != MSM_NO_PULL)
288 case PIN_CONFIG_BIAS_PULL_DOWN:
289 if (arg != MSM_PULL_DOWN)
293 case PIN_CONFIG_BIAS_BUS_HOLD:
294 if (pctrl->soc->pull_no_keeper)
297 if (arg != MSM_KEEPER)
301 case PIN_CONFIG_BIAS_PULL_UP:
302 if (pctrl->soc->pull_no_keeper)
303 arg = arg == MSM_PULL_UP_NO_KEEPER;
305 arg = arg == MSM_PULL_UP;
309 case PIN_CONFIG_DRIVE_STRENGTH:
310 arg = msm_regval_to_drive(arg);
312 case PIN_CONFIG_OUTPUT:
313 /* Pin is not output */
317 val = msm_readl_io(pctrl, g);
318 arg = !!(val & BIT(g->in_bit));
320 case PIN_CONFIG_INPUT_ENABLE:
330 *config = pinconf_to_config_packed(param, arg);
335 static int msm_config_group_set(struct pinctrl_dev *pctldev,
337 unsigned long *configs,
338 unsigned num_configs)
340 const struct msm_pingroup *g;
341 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
351 g = &pctrl->soc->groups[group];
353 for (i = 0; i < num_configs; i++) {
354 param = pinconf_to_config_param(configs[i]);
355 arg = pinconf_to_config_argument(configs[i]);
357 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
361 /* Convert pinconf values to register values */
363 case PIN_CONFIG_BIAS_DISABLE:
366 case PIN_CONFIG_BIAS_PULL_DOWN:
369 case PIN_CONFIG_BIAS_BUS_HOLD:
370 if (pctrl->soc->pull_no_keeper)
375 case PIN_CONFIG_BIAS_PULL_UP:
376 if (pctrl->soc->pull_no_keeper)
377 arg = MSM_PULL_UP_NO_KEEPER;
381 case PIN_CONFIG_DRIVE_STRENGTH:
382 /* Check for invalid values */
383 if (arg > 16 || arg < 2 || (arg % 2) != 0)
388 case PIN_CONFIG_OUTPUT:
389 /* set output value */
390 raw_spin_lock_irqsave(&pctrl->lock, flags);
391 val = msm_readl_io(pctrl, g);
393 val |= BIT(g->out_bit);
395 val &= ~BIT(g->out_bit);
396 msm_writel_io(val, pctrl, g);
397 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
402 case PIN_CONFIG_INPUT_ENABLE:
407 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
412 /* Range-check user-supplied value */
414 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
418 raw_spin_lock_irqsave(&pctrl->lock, flags);
419 val = msm_readl_ctl(pctrl, g);
420 val &= ~(mask << bit);
422 msm_writel_ctl(val, pctrl, g);
423 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
429 static const struct pinconf_ops msm_pinconf_ops = {
431 .pin_config_group_get = msm_config_group_get,
432 .pin_config_group_set = msm_config_group_set,
435 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
437 const struct msm_pingroup *g;
438 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
442 g = &pctrl->soc->groups[offset];
444 raw_spin_lock_irqsave(&pctrl->lock, flags);
446 val = msm_readl_ctl(pctrl, g);
447 val &= ~BIT(g->oe_bit);
448 msm_writel_ctl(val, pctrl, g);
450 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
455 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
457 const struct msm_pingroup *g;
458 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
462 g = &pctrl->soc->groups[offset];
464 raw_spin_lock_irqsave(&pctrl->lock, flags);
466 val = msm_readl_io(pctrl, g);
468 val |= BIT(g->out_bit);
470 val &= ~BIT(g->out_bit);
471 msm_writel_io(val, pctrl, g);
473 val = msm_readl_ctl(pctrl, g);
474 val |= BIT(g->oe_bit);
475 msm_writel_ctl(val, pctrl, g);
477 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
482 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
484 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
485 const struct msm_pingroup *g;
488 g = &pctrl->soc->groups[offset];
490 val = msm_readl_ctl(pctrl, g);
492 /* 0 = output, 1 = input */
493 return val & BIT(g->oe_bit) ? 0 : 1;
496 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
498 const struct msm_pingroup *g;
499 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
502 g = &pctrl->soc->groups[offset];
504 val = msm_readl_io(pctrl, g);
505 return !!(val & BIT(g->in_bit));
508 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
510 const struct msm_pingroup *g;
511 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
515 g = &pctrl->soc->groups[offset];
517 raw_spin_lock_irqsave(&pctrl->lock, flags);
519 val = msm_readl_io(pctrl, g);
521 val |= BIT(g->out_bit);
523 val &= ~BIT(g->out_bit);
524 msm_writel_io(val, pctrl, g);
526 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
529 #ifdef CONFIG_DEBUG_FS
530 #include <linux/seq_file.h>
532 static void msm_gpio_dbg_show_one(struct seq_file *s,
533 struct pinctrl_dev *pctldev,
534 struct gpio_chip *chip,
538 const struct msm_pingroup *g;
539 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
547 static const char * const pulls_keeper[] = {
554 static const char * const pulls_no_keeper[] = {
560 if (!gpiochip_line_is_valid(chip, offset))
563 g = &pctrl->soc->groups[offset];
564 ctl_reg = msm_readl_ctl(pctrl, g);
565 io_reg = msm_readl_io(pctrl, g);
567 is_out = !!(ctl_reg & BIT(g->oe_bit));
568 func = (ctl_reg >> g->mux_bit) & 7;
569 drive = (ctl_reg >> g->drv_bit) & 7;
570 pull = (ctl_reg >> g->pull_bit) & 3;
573 val = !!(io_reg & BIT(g->out_bit));
575 val = !!(io_reg & BIT(g->in_bit));
577 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
578 seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
579 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
580 if (pctrl->soc->pull_no_keeper)
581 seq_printf(s, " %s", pulls_no_keeper[pull]);
583 seq_printf(s, " %s", pulls_keeper[pull]);
587 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
589 unsigned gpio = chip->base;
592 for (i = 0; i < chip->ngpio; i++, gpio++)
593 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
597 #define msm_gpio_dbg_show NULL
600 static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
601 unsigned long *valid_mask,
604 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
607 const int *reserved = pctrl->soc->reserved_gpios;
610 /* Driver provided reserved list overrides DT and ACPI */
612 bitmap_fill(valid_mask, ngpios);
613 for (i = 0; reserved[i] >= 0; i++) {
614 if (i >= ngpios || reserved[i] >= ngpios) {
615 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
618 clear_bit(reserved[i], valid_mask);
624 /* The number of GPIOs in the ACPI tables */
625 len = ret = device_property_count_u16(pctrl->dev, "gpios");
632 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
636 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
638 dev_err(pctrl->dev, "could not read list of GPIOs\n");
642 bitmap_zero(valid_mask, ngpios);
643 for (i = 0; i < len; i++)
644 set_bit(tmp[i], valid_mask);
651 static const struct gpio_chip msm_gpio_template = {
652 .direction_input = msm_gpio_direction_input,
653 .direction_output = msm_gpio_direction_output,
654 .get_direction = msm_gpio_get_direction,
657 .request = gpiochip_generic_request,
658 .free = gpiochip_generic_free,
659 .dbg_show = msm_gpio_dbg_show,
662 /* For dual-edge interrupts in software, since some hardware has no
665 * At appropriate moments, this function may be called to flip the polarity
666 * settings of both-edge irq lines to try and catch the next edge.
668 * The attempt is considered successful if:
669 * - the status bit goes high, indicating that an edge was caught, or
670 * - the input value of the gpio doesn't change during the attempt.
671 * If the value changes twice during the process, that would cause the first
672 * test to fail but would force the second, as two opposite
673 * transitions would cause a detection no matter the polarity setting.
675 * The do-loop tries to sledge-hammer closed the timing hole between
676 * the initial value-read and the polarity-write - if the line value changes
677 * during that window, an interrupt is lost, the new polarity setting is
678 * incorrect, and the first success test will fail, causing a retry.
680 * Algorithm comes from Google's msmgpio driver.
682 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
683 const struct msm_pingroup *g,
686 int loop_limit = 100;
687 unsigned val, val2, intstat;
691 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
693 pol = msm_readl_intr_cfg(pctrl, g);
694 pol ^= BIT(g->intr_polarity_bit);
695 msm_writel_intr_cfg(val, pctrl, g);
697 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
698 intstat = msm_readl_intr_status(pctrl, g);
699 if (intstat || (val == val2))
701 } while (loop_limit-- > 0);
702 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
706 static void msm_gpio_irq_mask(struct irq_data *d)
708 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
709 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
710 const struct msm_pingroup *g;
715 irq_chip_mask_parent(d);
717 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
720 g = &pctrl->soc->groups[d->hwirq];
722 raw_spin_lock_irqsave(&pctrl->lock, flags);
724 val = msm_readl_intr_cfg(pctrl, g);
726 * There are two bits that control interrupt forwarding to the CPU. The
727 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be
728 * latched into the interrupt status register when the hardware detects
729 * an irq that it's configured for (either edge for edge type or level
730 * for level type irq). The 'non-raw' status enable bit causes the
731 * hardware to assert the summary interrupt to the CPU if the latched
732 * status bit is set. There's a bug though, the edge detection logic
733 * seems to have a problem where toggling the RAW_STATUS_EN bit may
734 * cause the status bit to latch spuriously when there isn't any edge
735 * so we can't touch that bit for edge type irqs and we have to keep
736 * the bit set anyway so that edges are latched while the line is masked.
738 * To make matters more complicated, leaving the RAW_STATUS_EN bit
739 * enabled all the time causes level interrupts to re-latch into the
740 * status register because the level is still present on the line after
741 * we ack it. We clear the raw status enable bit during mask here and
742 * set the bit on unmask so the interrupt can't latch into the hardware
745 if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
746 val &= ~BIT(g->intr_raw_status_bit);
748 val &= ~BIT(g->intr_enable_bit);
749 msm_writel_intr_cfg(val, pctrl, g);
751 clear_bit(d->hwirq, pctrl->enabled_irqs);
753 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
756 static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear)
758 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
759 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
760 const struct msm_pingroup *g;
765 irq_chip_unmask_parent(d);
767 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
770 g = &pctrl->soc->groups[d->hwirq];
772 raw_spin_lock_irqsave(&pctrl->lock, flags);
776 * clear the interrupt status bit before unmask to avoid
777 * any erroneous interrupts that would have got latched
778 * when the interrupt is not in use.
780 val = msm_readl_intr_status(pctrl, g);
781 val &= ~BIT(g->intr_status_bit);
782 msm_writel_intr_status(val, pctrl, g);
785 val = msm_readl_intr_cfg(pctrl, g);
786 val |= BIT(g->intr_raw_status_bit);
787 val |= BIT(g->intr_enable_bit);
788 msm_writel_intr_cfg(val, pctrl, g);
790 set_bit(d->hwirq, pctrl->enabled_irqs);
792 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
795 static void msm_gpio_irq_enable(struct irq_data *d)
798 * Clear the interrupt that may be pending before we enable
800 * This is especially a problem with the GPIOs routed to the
801 * PDC. These GPIOs are direct-connect interrupts to the GIC.
802 * Disabling the interrupt line at the PDC does not prevent
803 * the interrupt from being latched at the GIC. The state at
804 * GIC needs to be cleared before enabling.
806 if (d->parent_data) {
807 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, 0);
808 irq_chip_enable_parent(d);
811 msm_gpio_irq_clear_unmask(d, true);
814 static void msm_gpio_irq_disable(struct irq_data *d)
816 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
817 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
820 irq_chip_disable_parent(d);
822 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
823 msm_gpio_irq_mask(d);
826 static void msm_gpio_irq_unmask(struct irq_data *d)
828 msm_gpio_irq_clear_unmask(d, false);
831 static void msm_gpio_irq_ack(struct irq_data *d)
833 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
834 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
835 const struct msm_pingroup *g;
839 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
842 g = &pctrl->soc->groups[d->hwirq];
844 raw_spin_lock_irqsave(&pctrl->lock, flags);
846 val = msm_readl_intr_status(pctrl, g);
847 if (g->intr_ack_high)
848 val |= BIT(g->intr_status_bit);
850 val &= ~BIT(g->intr_status_bit);
851 msm_writel_intr_status(val, pctrl, g);
853 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
854 msm_gpio_update_dual_edge_pos(pctrl, g, d);
856 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
859 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
861 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
862 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
863 const struct msm_pingroup *g;
868 irq_chip_set_type_parent(d, type);
870 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
873 g = &pctrl->soc->groups[d->hwirq];
875 raw_spin_lock_irqsave(&pctrl->lock, flags);
878 * For hw without possibility of detecting both edges
880 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
881 set_bit(d->hwirq, pctrl->dual_edge_irqs);
883 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
885 /* Route interrupts to application cpu */
886 val = msm_readl_intr_target(pctrl, g);
887 val &= ~(7 << g->intr_target_bit);
888 val |= g->intr_target_kpss_val << g->intr_target_bit;
889 msm_writel_intr_target(val, pctrl, g);
891 /* Update configuration for gpio.
892 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
893 * internal circuitry of TLMM, toggling the RAW_STATUS
894 * could cause the INTR_STATUS to be set for EDGE interrupts.
896 val = msm_readl_intr_cfg(pctrl, g);
897 val |= BIT(g->intr_raw_status_bit);
898 if (g->intr_detection_width == 2) {
899 val &= ~(3 << g->intr_detection_bit);
900 val &= ~(1 << g->intr_polarity_bit);
902 case IRQ_TYPE_EDGE_RISING:
903 val |= 1 << g->intr_detection_bit;
904 val |= BIT(g->intr_polarity_bit);
906 case IRQ_TYPE_EDGE_FALLING:
907 val |= 2 << g->intr_detection_bit;
908 val |= BIT(g->intr_polarity_bit);
910 case IRQ_TYPE_EDGE_BOTH:
911 val |= 3 << g->intr_detection_bit;
912 val |= BIT(g->intr_polarity_bit);
914 case IRQ_TYPE_LEVEL_LOW:
916 case IRQ_TYPE_LEVEL_HIGH:
917 val |= BIT(g->intr_polarity_bit);
920 } else if (g->intr_detection_width == 1) {
921 val &= ~(1 << g->intr_detection_bit);
922 val &= ~(1 << g->intr_polarity_bit);
924 case IRQ_TYPE_EDGE_RISING:
925 val |= BIT(g->intr_detection_bit);
926 val |= BIT(g->intr_polarity_bit);
928 case IRQ_TYPE_EDGE_FALLING:
929 val |= BIT(g->intr_detection_bit);
931 case IRQ_TYPE_EDGE_BOTH:
932 val |= BIT(g->intr_detection_bit);
933 val |= BIT(g->intr_polarity_bit);
935 case IRQ_TYPE_LEVEL_LOW:
937 case IRQ_TYPE_LEVEL_HIGH:
938 val |= BIT(g->intr_polarity_bit);
944 msm_writel_intr_cfg(val, pctrl, g);
946 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
947 msm_gpio_update_dual_edge_pos(pctrl, g, d);
949 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
951 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
952 irq_set_handler_locked(d, handle_level_irq);
953 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
954 irq_set_handler_locked(d, handle_edge_irq);
959 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
961 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
962 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
965 * While they may not wake up when the TLMM is powered off,
966 * some GPIOs would like to wakeup the system from suspend
967 * when TLMM is powered on. To allow that, enable the GPIO
968 * summary line to be wakeup capable at GIC.
971 irq_chip_set_wake_parent(d, on);
973 irq_set_irq_wake(pctrl->irq, on);
978 static int msm_gpio_irq_reqres(struct irq_data *d)
980 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
981 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
984 if (!try_module_get(gc->owner))
987 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
990 msm_gpio_direction_input(gc, d->hwirq);
992 if (gpiochip_lock_as_irq(gc, d->hwirq)) {
994 "unable to lock HW IRQ %lu for IRQ\n",
1001 module_put(gc->owner);
1005 static void msm_gpio_irq_relres(struct irq_data *d)
1007 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1009 gpiochip_unlock_as_irq(gc, d->hwirq);
1010 module_put(gc->owner);
1013 static void msm_gpio_irq_handler(struct irq_desc *desc)
1015 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1016 const struct msm_pingroup *g;
1017 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1018 struct irq_chip *chip = irq_desc_get_chip(desc);
1024 chained_irq_enter(chip, desc);
1027 * Each pin has it's own IRQ status register, so use
1028 * enabled_irq bitmap to limit the number of reads.
1030 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
1031 g = &pctrl->soc->groups[i];
1032 val = msm_readl_intr_status(pctrl, g);
1033 if (val & BIT(g->intr_status_bit)) {
1034 irq_pin = irq_find_mapping(gc->irq.domain, i);
1035 generic_handle_irq(irq_pin);
1040 /* No interrupts were flagged */
1042 handle_bad_irq(desc);
1044 chained_irq_exit(chip, desc);
1047 static int msm_gpio_wakeirq(struct gpio_chip *gc,
1049 unsigned int child_type,
1050 unsigned int *parent,
1051 unsigned int *parent_type)
1053 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1054 const struct msm_gpio_wakeirq_map *map;
1057 *parent = GPIO_NO_WAKE_IRQ;
1058 *parent_type = IRQ_TYPE_EDGE_RISING;
1060 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {
1061 map = &pctrl->soc->wakeirq_map[i];
1062 if (map->gpio == child) {
1063 *parent = map->wakeirq;
1071 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
1073 if (pctrl->soc->reserved_gpios)
1076 return device_property_count_u16(pctrl->dev, "gpios") > 0;
1079 static int msm_gpio_init(struct msm_pinctrl *pctrl)
1081 struct gpio_chip *chip;
1082 struct gpio_irq_chip *girq;
1084 unsigned gpio, ngpio = pctrl->soc->ngpios;
1085 struct device_node *np;
1088 if (WARN_ON(ngpio > MAX_NR_GPIO))
1091 chip = &pctrl->chip;
1093 chip->ngpio = ngpio;
1094 chip->label = dev_name(pctrl->dev);
1095 chip->parent = pctrl->dev;
1096 chip->owner = THIS_MODULE;
1097 chip->of_node = pctrl->dev->of_node;
1098 if (msm_gpio_needs_valid_mask(pctrl))
1099 chip->init_valid_mask = msm_gpio_init_valid_mask;
1101 pctrl->irq_chip.name = "msmgpio";
1102 pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
1103 pctrl->irq_chip.irq_disable = msm_gpio_irq_disable;
1104 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
1105 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
1106 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
1107 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
1108 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
1109 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
1110 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
1112 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
1114 chip->irq.parent_domain = irq_find_matching_host(np,
1117 if (!chip->irq.parent_domain)
1118 return -EPROBE_DEFER;
1119 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;
1120 pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent;
1122 * Let's skip handling the GPIOs, if the parent irqchip
1123 * is handling the direct connect IRQ of the GPIO.
1125 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain);
1126 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {
1127 gpio = pctrl->soc->wakeirq_map[i].gpio;
1128 set_bit(gpio, pctrl->skip_wake_irqs);
1133 girq->chip = &pctrl->irq_chip;
1134 girq->parent_handler = msm_gpio_irq_handler;
1135 girq->fwnode = pctrl->dev->fwnode;
1136 girq->num_parents = 1;
1137 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
1141 girq->default_type = IRQ_TYPE_NONE;
1142 girq->handler = handle_bad_irq;
1143 girq->parents[0] = pctrl->irq;
1145 ret = gpiochip_add_data(&pctrl->chip, pctrl);
1147 dev_err(pctrl->dev, "Failed register gpiochip\n");
1152 * For DeviceTree-supported systems, the gpio core checks the
1153 * pinctrl's device node for the "gpio-ranges" property.
1154 * If it is present, it takes care of adding the pin ranges
1155 * for the driver. In this case the driver can skip ahead.
1157 * In order to remain compatible with older, existing DeviceTree
1158 * files which don't set the "gpio-ranges" property or systems that
1159 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1161 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
1162 ret = gpiochip_add_pin_range(&pctrl->chip,
1163 dev_name(pctrl->dev), 0, 0, chip->ngpio);
1165 dev_err(pctrl->dev, "Failed to add pin range\n");
1166 gpiochip_remove(&pctrl->chip);
1174 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
1177 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
1179 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
1184 static struct msm_pinctrl *poweroff_pctrl;
1186 static void msm_ps_hold_poweroff(void)
1188 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
1191 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1194 const struct msm_function *func = pctrl->soc->functions;
1196 for (i = 0; i < pctrl->soc->nfunctions; i++)
1197 if (!strcmp(func[i].name, "ps_hold")) {
1198 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
1199 pctrl->restart_nb.priority = 128;
1200 if (register_restart_handler(&pctrl->restart_nb))
1202 "failed to setup restart handler.\n");
1203 poweroff_pctrl = pctrl;
1204 pm_power_off = msm_ps_hold_poweroff;
1209 static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
1211 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1213 return pinctrl_force_sleep(pctrl->pctrl);
1216 static __maybe_unused int msm_pinctrl_resume(struct device *dev)
1218 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1220 return pinctrl_force_default(pctrl->pctrl);
1223 SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
1224 msm_pinctrl_resume);
1226 EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
1228 int msm_pinctrl_probe(struct platform_device *pdev,
1229 const struct msm_pinctrl_soc_data *soc_data)
1231 struct msm_pinctrl *pctrl;
1232 struct resource *res;
1236 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1240 pctrl->dev = &pdev->dev;
1241 pctrl->soc = soc_data;
1242 pctrl->chip = msm_gpio_template;
1244 raw_spin_lock_init(&pctrl->lock);
1246 if (soc_data->tiles) {
1247 for (i = 0; i < soc_data->ntiles; i++) {
1248 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1249 soc_data->tiles[i]);
1250 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1251 if (IS_ERR(pctrl->regs[i]))
1252 return PTR_ERR(pctrl->regs[i]);
1255 pctrl->regs[0] = devm_platform_ioremap_resource(pdev, 0);
1256 if (IS_ERR(pctrl->regs[0]))
1257 return PTR_ERR(pctrl->regs[0]);
1260 msm_pinctrl_setup_pm_reset(pctrl);
1262 pctrl->irq = platform_get_irq(pdev, 0);
1266 pctrl->desc.owner = THIS_MODULE;
1267 pctrl->desc.pctlops = &msm_pinctrl_ops;
1268 pctrl->desc.pmxops = &msm_pinmux_ops;
1269 pctrl->desc.confops = &msm_pinconf_ops;
1270 pctrl->desc.name = dev_name(&pdev->dev);
1271 pctrl->desc.pins = pctrl->soc->pins;
1272 pctrl->desc.npins = pctrl->soc->npins;
1274 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1275 if (IS_ERR(pctrl->pctrl)) {
1276 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1277 return PTR_ERR(pctrl->pctrl);
1280 ret = msm_gpio_init(pctrl);
1284 platform_set_drvdata(pdev, pctrl);
1286 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1290 EXPORT_SYMBOL(msm_pinctrl_probe);
1292 int msm_pinctrl_remove(struct platform_device *pdev)
1294 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1296 gpiochip_remove(&pctrl->chip);
1298 unregister_restart_handler(&pctrl->restart_nb);
1302 EXPORT_SYMBOL(msm_pinctrl_remove);