3 #include <hwspinlock.h>
6 #include <asm/arch/gpio.h>
9 #include <dm/device_compat.h>
11 #include <dm/pinctrl.h>
12 #include <linux/bitops.h>
13 #include <linux/err.h>
14 #include <linux/libfdt.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 #define MAX_PINS_ONE_IP 70
19 #define MODE_BITS_MASK 3
25 struct stm32_pinctrl_priv {
26 struct hwspinlock hws;
28 struct list_head gpio_dev;
31 struct stm32_gpio_bank {
32 struct udevice *gpio_dev;
33 struct list_head list;
36 #ifndef CONFIG_SPL_BUILD
38 static char pin_name[PINNAME_SIZE];
39 #define PINMUX_MODE_COUNT 5
40 static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
48 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
50 struct stm32_gpio_priv *priv = dev_get_priv(dev);
51 struct stm32_gpio_regs *regs = priv->regs;
53 u32 alt_shift = (offset % 8) * 4;
54 u32 alt_index = offset / 8;
56 af = (readl(®s->afr[alt_index]) &
57 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
62 static int stm32_populate_gpio_dev_list(struct udevice *dev)
64 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
65 struct udevice *gpio_dev;
66 struct udevice *child;
67 struct stm32_gpio_bank *gpio_bank;
71 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
72 * a list with all gpio device reference which belongs to the
73 * current pin-controller. This list is used to find pin_name and
76 list_for_each_entry(child, &dev->child_head, sibling_node) {
77 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
82 gpio_bank = malloc(sizeof(*gpio_bank));
84 dev_err(dev, "Not enough memory\n");
88 gpio_bank->gpio_dev = gpio_dev;
89 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
95 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
97 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
98 struct gpio_dev_priv *uc_priv;
99 struct stm32_gpio_bank *gpio_bank;
102 * if get_pins_count has already been executed once on this
103 * pin-controller, no need to run it again
105 if (priv->pinctrl_ngpios)
106 return priv->pinctrl_ngpios;
108 if (list_empty(&priv->gpio_dev))
109 stm32_populate_gpio_dev_list(dev);
111 * walk through all banks to retrieve the pin-controller
114 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
115 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
117 priv->pinctrl_ngpios += uc_priv->gpio_count;
120 return priv->pinctrl_ngpios;
123 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
124 unsigned int selector,
127 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
128 struct stm32_gpio_bank *gpio_bank;
129 struct gpio_dev_priv *uc_priv;
132 if (list_empty(&priv->gpio_dev))
133 stm32_populate_gpio_dev_list(dev);
135 /* look up for the bank which owns the requested pin */
136 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
137 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
139 if (selector < (pin_count + uc_priv->gpio_count)) {
141 * we found the bank, convert pin selector to
144 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
145 selector - pin_count);
146 if (IS_ERR_VALUE(*idx))
149 return gpio_bank->gpio_dev;
151 pin_count += uc_priv->gpio_count;
157 static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
158 unsigned int selector)
160 struct gpio_dev_priv *uc_priv;
161 struct udevice *gpio_dev;
162 unsigned int gpio_idx;
164 /* look up for the bank which owns the requested pin */
165 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
167 snprintf(pin_name, PINNAME_SIZE, "Error");
169 uc_priv = dev_get_uclass_priv(gpio_dev);
171 snprintf(pin_name, PINNAME_SIZE, "%s%d",
179 static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
180 unsigned int selector,
184 struct udevice *gpio_dev;
188 unsigned int gpio_idx;
190 /* look up for the bank which owns the requested pin */
191 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
196 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
198 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
199 selector, gpio_idx, mode);
204 /* should never happen */
207 snprintf(buf, size, "%s", pinmux_mode[mode]);
210 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
211 snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
215 snprintf(buf, size, "%s %s",
216 pinmux_mode[mode], label ? label : "");
225 static int stm32_pinctrl_probe(struct udevice *dev)
227 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
230 INIT_LIST_HEAD(&priv->gpio_dev);
232 /* hwspinlock property is optional, just log the error */
233 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
235 debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
241 static int stm32_gpio_config(struct gpio_desc *desc,
242 const struct stm32_gpio_ctl *ctl)
244 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
245 struct stm32_gpio_regs *regs = priv->regs;
246 struct stm32_pinctrl_priv *ctrl_priv;
250 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
251 ctl->pupd > 2 || ctl->speed > 3)
254 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
255 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
257 dev_err(desc->dev, "HWSpinlock timeout\n");
261 index = (desc->offset & 0x07) * 4;
262 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
265 index = desc->offset * 2;
266 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
268 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
269 ctl->speed << index);
270 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
272 index = desc->offset;
273 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
275 hwspinlock_unlock(&ctrl_priv->hws);
280 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
282 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
283 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
284 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
290 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
297 gpio_ctl->mode = STM32_GPIO_MODE_IN;
300 gpio_ctl->mode = STM32_GPIO_MODE_AF;
301 gpio_ctl->af = gpio_fn - 1;
304 gpio_ctl->mode = STM32_GPIO_MODE_AN;
307 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
311 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
313 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
314 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
316 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
318 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
319 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
320 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
321 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
323 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
325 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
326 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
332 static int stm32_pinctrl_config(int offset)
334 u32 pin_mux[MAX_PINS_ONE_IP];
338 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
339 * usart1) of pin controller phandle "pinctrl-0"
341 fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
342 struct stm32_gpio_dsc gpio_dsc;
343 struct stm32_gpio_ctl gpio_ctl;
346 len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
348 ARRAY_SIZE(pin_mux));
349 debug("%s: no of pinmux entries= %d\n", __func__, len);
352 for (i = 0; i < len; i++) {
353 struct gpio_desc desc;
355 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
356 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
357 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
358 rv = uclass_get_device_by_seq(UCLASS_GPIO,
363 desc.offset = gpio_dsc.pin;
364 rv = stm32_gpio_config(&desc, &gpio_ctl);
365 debug("%s: rv = %d\n\n", __func__, rv);
374 static int stm32_pinctrl_bind(struct udevice *dev)
380 dev_for_each_subnode(node, dev) {
381 debug("%s: bind %s\n", __func__, ofnode_get_name(node));
383 ofnode_get_property(node, "gpio-controller", &ret);
386 /* Get the name of each gpio node */
387 name = ofnode_get_name(node);
391 /* Bind each gpio node */
392 ret = device_bind_driver_to_node(dev, "gpio_stm32",
397 debug("%s: bind %s\n", __func__, name);
403 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
404 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
406 return stm32_pinctrl_config(dev_of_offset(config));
408 #else /* PINCTRL_FULL */
409 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
410 struct udevice *periph)
412 const void *fdt = gd->fdt_blob;
418 list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
422 debug("%s: periph->name = %s\n", __func__, periph->name);
424 size /= sizeof(*list);
425 for (i = 0; i < size; i++) {
426 phandle = fdt32_to_cpu(*list++);
428 config_node = fdt_node_offset_by_phandle(fdt, phandle);
429 if (config_node < 0) {
430 pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
434 ret = stm32_pinctrl_config(config_node);
441 #endif /* PINCTRL_FULL */
443 static struct pinctrl_ops stm32_pinctrl_ops = {
444 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
445 .set_state = stm32_pinctrl_set_state,
446 #else /* PINCTRL_FULL */
447 .set_state_simple = stm32_pinctrl_set_state_simple,
448 #endif /* PINCTRL_FULL */
449 #ifndef CONFIG_SPL_BUILD
450 .get_pin_name = stm32_pinctrl_get_pin_name,
451 .get_pins_count = stm32_pinctrl_get_pins_count,
452 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
456 static const struct udevice_id stm32_pinctrl_ids[] = {
457 { .compatible = "st,stm32f429-pinctrl" },
458 { .compatible = "st,stm32f469-pinctrl" },
459 { .compatible = "st,stm32f746-pinctrl" },
460 { .compatible = "st,stm32f769-pinctrl" },
461 { .compatible = "st,stm32h743-pinctrl" },
462 { .compatible = "st,stm32mp157-pinctrl" },
463 { .compatible = "st,stm32mp157-z-pinctrl" },
467 U_BOOT_DRIVER(pinctrl_stm32) = {
468 .name = "pinctrl_stm32",
469 .id = UCLASS_PINCTRL,
470 .of_match = stm32_pinctrl_ids,
471 .ops = &stm32_pinctrl_ops,
472 .bind = stm32_pinctrl_bind,
473 .probe = stm32_pinctrl_probe,
474 .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),