3 #include <hwspinlock.h>
5 #include <asm/arch/gpio.h>
8 #include <dm/device_compat.h>
10 #include <dm/pinctrl.h>
11 #include <linux/err.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 #define MAX_PINS_ONE_IP 70
16 #define MODE_BITS_MASK 3
22 struct stm32_pinctrl_priv {
23 struct hwspinlock hws;
25 struct list_head gpio_dev;
28 struct stm32_gpio_bank {
29 struct udevice *gpio_dev;
30 struct list_head list;
33 #ifndef CONFIG_SPL_BUILD
35 static char pin_name[PINNAME_SIZE];
36 #define PINMUX_MODE_COUNT 5
37 static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
45 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
47 struct stm32_gpio_priv *priv = dev_get_priv(dev);
48 struct stm32_gpio_regs *regs = priv->regs;
50 u32 alt_shift = (offset % 8) * 4;
51 u32 alt_index = offset / 8;
53 af = (readl(®s->afr[alt_index]) &
54 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
59 static int stm32_populate_gpio_dev_list(struct udevice *dev)
61 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
62 struct udevice *gpio_dev;
63 struct udevice *child;
64 struct stm32_gpio_bank *gpio_bank;
68 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
69 * a list with all gpio device reference which belongs to the
70 * current pin-controller. This list is used to find pin_name and
73 list_for_each_entry(child, &dev->child_head, sibling_node) {
74 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
79 gpio_bank = malloc(sizeof(*gpio_bank));
81 dev_err(dev, "Not enough memory\n");
85 gpio_bank->gpio_dev = gpio_dev;
86 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
92 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
94 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
95 struct gpio_dev_priv *uc_priv;
96 struct stm32_gpio_bank *gpio_bank;
99 * if get_pins_count has already been executed once on this
100 * pin-controller, no need to run it again
102 if (priv->pinctrl_ngpios)
103 return priv->pinctrl_ngpios;
105 if (list_empty(&priv->gpio_dev))
106 stm32_populate_gpio_dev_list(dev);
108 * walk through all banks to retrieve the pin-controller
111 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
112 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
114 priv->pinctrl_ngpios += uc_priv->gpio_count;
117 return priv->pinctrl_ngpios;
120 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
121 unsigned int selector,
124 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
125 struct stm32_gpio_bank *gpio_bank;
126 struct gpio_dev_priv *uc_priv;
129 if (list_empty(&priv->gpio_dev))
130 stm32_populate_gpio_dev_list(dev);
132 /* look up for the bank which owns the requested pin */
133 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
134 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
136 if (selector < (pin_count + uc_priv->gpio_count)) {
138 * we found the bank, convert pin selector to
141 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
142 selector - pin_count);
143 if (IS_ERR_VALUE(*idx))
146 return gpio_bank->gpio_dev;
148 pin_count += uc_priv->gpio_count;
154 static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
155 unsigned int selector)
157 struct gpio_dev_priv *uc_priv;
158 struct udevice *gpio_dev;
159 unsigned int gpio_idx;
161 /* look up for the bank which owns the requested pin */
162 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
164 snprintf(pin_name, PINNAME_SIZE, "Error");
166 uc_priv = dev_get_uclass_priv(gpio_dev);
168 snprintf(pin_name, PINNAME_SIZE, "%s%d",
176 static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
177 unsigned int selector,
181 struct udevice *gpio_dev;
185 unsigned int gpio_idx;
187 /* look up for the bank which owns the requested pin */
188 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
193 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
195 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
196 selector, gpio_idx, mode);
201 /* should never happen */
204 snprintf(buf, size, "%s", pinmux_mode[mode]);
207 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
208 snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
212 snprintf(buf, size, "%s %s",
213 pinmux_mode[mode], label ? label : "");
222 static int stm32_pinctrl_probe(struct udevice *dev)
224 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
227 INIT_LIST_HEAD(&priv->gpio_dev);
229 /* hwspinlock property is optional, just log the error */
230 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
232 debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
238 static int stm32_gpio_config(struct gpio_desc *desc,
239 const struct stm32_gpio_ctl *ctl)
241 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
242 struct stm32_gpio_regs *regs = priv->regs;
243 struct stm32_pinctrl_priv *ctrl_priv;
247 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
248 ctl->pupd > 2 || ctl->speed > 3)
251 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
252 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
254 dev_err(desc->dev, "HWSpinlock timeout\n");
258 index = (desc->offset & 0x07) * 4;
259 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
262 index = desc->offset * 2;
263 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
265 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
266 ctl->speed << index);
267 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
269 index = desc->offset;
270 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
272 hwspinlock_unlock(&ctrl_priv->hws);
277 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
279 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
280 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
281 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
287 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
294 gpio_ctl->mode = STM32_GPIO_MODE_IN;
297 gpio_ctl->mode = STM32_GPIO_MODE_AF;
298 gpio_ctl->af = gpio_fn - 1;
301 gpio_ctl->mode = STM32_GPIO_MODE_AN;
304 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
308 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
310 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
311 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
313 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
315 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
316 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
317 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
318 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
320 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
322 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
323 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
329 static int stm32_pinctrl_config(int offset)
331 u32 pin_mux[MAX_PINS_ONE_IP];
335 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
336 * usart1) of pin controller phandle "pinctrl-0"
338 fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
339 struct stm32_gpio_dsc gpio_dsc;
340 struct stm32_gpio_ctl gpio_ctl;
343 len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
345 ARRAY_SIZE(pin_mux));
346 debug("%s: no of pinmux entries= %d\n", __func__, len);
349 for (i = 0; i < len; i++) {
350 struct gpio_desc desc;
352 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
353 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
354 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
355 rv = uclass_get_device_by_seq(UCLASS_GPIO,
360 desc.offset = gpio_dsc.pin;
361 rv = stm32_gpio_config(&desc, &gpio_ctl);
362 debug("%s: rv = %d\n\n", __func__, rv);
371 static int stm32_pinctrl_bind(struct udevice *dev)
377 dev_for_each_subnode(node, dev) {
378 debug("%s: bind %s\n", __func__, ofnode_get_name(node));
380 ofnode_get_property(node, "gpio-controller", &ret);
383 /* Get the name of each gpio node */
384 name = ofnode_get_name(node);
388 /* Bind each gpio node */
389 ret = device_bind_driver_to_node(dev, "gpio_stm32",
394 debug("%s: bind %s\n", __func__, name);
400 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
401 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
403 return stm32_pinctrl_config(dev_of_offset(config));
405 #else /* PINCTRL_FULL */
406 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
407 struct udevice *periph)
409 const void *fdt = gd->fdt_blob;
415 list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
419 debug("%s: periph->name = %s\n", __func__, periph->name);
421 size /= sizeof(*list);
422 for (i = 0; i < size; i++) {
423 phandle = fdt32_to_cpu(*list++);
425 config_node = fdt_node_offset_by_phandle(fdt, phandle);
426 if (config_node < 0) {
427 pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
431 ret = stm32_pinctrl_config(config_node);
438 #endif /* PINCTRL_FULL */
440 static struct pinctrl_ops stm32_pinctrl_ops = {
441 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
442 .set_state = stm32_pinctrl_set_state,
443 #else /* PINCTRL_FULL */
444 .set_state_simple = stm32_pinctrl_set_state_simple,
445 #endif /* PINCTRL_FULL */
446 #ifndef CONFIG_SPL_BUILD
447 .get_pin_name = stm32_pinctrl_get_pin_name,
448 .get_pins_count = stm32_pinctrl_get_pins_count,
449 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
453 static const struct udevice_id stm32_pinctrl_ids[] = {
454 { .compatible = "st,stm32f429-pinctrl" },
455 { .compatible = "st,stm32f469-pinctrl" },
456 { .compatible = "st,stm32f746-pinctrl" },
457 { .compatible = "st,stm32f769-pinctrl" },
458 { .compatible = "st,stm32h743-pinctrl" },
459 { .compatible = "st,stm32mp157-pinctrl" },
460 { .compatible = "st,stm32mp157-z-pinctrl" },
464 U_BOOT_DRIVER(pinctrl_stm32) = {
465 .name = "pinctrl_stm32",
466 .id = UCLASS_PINCTRL,
467 .of_match = stm32_pinctrl_ids,
468 .ops = &stm32_pinctrl_ops,
469 .bind = stm32_pinctrl_bind,
470 .probe = stm32_pinctrl_probe,
471 .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),