3 #include <hwspinlock.h>
5 #include <asm/arch/gpio.h>
8 #include <dm/device_compat.h>
10 #include <dm/pinctrl.h>
11 #include <linux/err.h>
12 #include <linux/libfdt.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 #define MAX_PINS_ONE_IP 70
17 #define MODE_BITS_MASK 3
23 struct stm32_pinctrl_priv {
24 struct hwspinlock hws;
26 struct list_head gpio_dev;
29 struct stm32_gpio_bank {
30 struct udevice *gpio_dev;
31 struct list_head list;
34 #ifndef CONFIG_SPL_BUILD
36 static char pin_name[PINNAME_SIZE];
37 #define PINMUX_MODE_COUNT 5
38 static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
46 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
48 struct stm32_gpio_priv *priv = dev_get_priv(dev);
49 struct stm32_gpio_regs *regs = priv->regs;
51 u32 alt_shift = (offset % 8) * 4;
52 u32 alt_index = offset / 8;
54 af = (readl(®s->afr[alt_index]) &
55 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
60 static int stm32_populate_gpio_dev_list(struct udevice *dev)
62 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
63 struct udevice *gpio_dev;
64 struct udevice *child;
65 struct stm32_gpio_bank *gpio_bank;
69 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
70 * a list with all gpio device reference which belongs to the
71 * current pin-controller. This list is used to find pin_name and
74 list_for_each_entry(child, &dev->child_head, sibling_node) {
75 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
80 gpio_bank = malloc(sizeof(*gpio_bank));
82 dev_err(dev, "Not enough memory\n");
86 gpio_bank->gpio_dev = gpio_dev;
87 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
93 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
95 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
96 struct gpio_dev_priv *uc_priv;
97 struct stm32_gpio_bank *gpio_bank;
100 * if get_pins_count has already been executed once on this
101 * pin-controller, no need to run it again
103 if (priv->pinctrl_ngpios)
104 return priv->pinctrl_ngpios;
106 if (list_empty(&priv->gpio_dev))
107 stm32_populate_gpio_dev_list(dev);
109 * walk through all banks to retrieve the pin-controller
112 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
113 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
115 priv->pinctrl_ngpios += uc_priv->gpio_count;
118 return priv->pinctrl_ngpios;
121 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
122 unsigned int selector,
125 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
126 struct stm32_gpio_bank *gpio_bank;
127 struct gpio_dev_priv *uc_priv;
130 if (list_empty(&priv->gpio_dev))
131 stm32_populate_gpio_dev_list(dev);
133 /* look up for the bank which owns the requested pin */
134 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
135 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
137 if (selector < (pin_count + uc_priv->gpio_count)) {
139 * we found the bank, convert pin selector to
142 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
143 selector - pin_count);
144 if (IS_ERR_VALUE(*idx))
147 return gpio_bank->gpio_dev;
149 pin_count += uc_priv->gpio_count;
155 static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
156 unsigned int selector)
158 struct gpio_dev_priv *uc_priv;
159 struct udevice *gpio_dev;
160 unsigned int gpio_idx;
162 /* look up for the bank which owns the requested pin */
163 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
165 snprintf(pin_name, PINNAME_SIZE, "Error");
167 uc_priv = dev_get_uclass_priv(gpio_dev);
169 snprintf(pin_name, PINNAME_SIZE, "%s%d",
177 static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
178 unsigned int selector,
182 struct udevice *gpio_dev;
186 unsigned int gpio_idx;
188 /* look up for the bank which owns the requested pin */
189 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
194 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
196 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
197 selector, gpio_idx, mode);
202 /* should never happen */
205 snprintf(buf, size, "%s", pinmux_mode[mode]);
208 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
209 snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
213 snprintf(buf, size, "%s %s",
214 pinmux_mode[mode], label ? label : "");
223 static int stm32_pinctrl_probe(struct udevice *dev)
225 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
228 INIT_LIST_HEAD(&priv->gpio_dev);
230 /* hwspinlock property is optional, just log the error */
231 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
233 debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
239 static int stm32_gpio_config(struct gpio_desc *desc,
240 const struct stm32_gpio_ctl *ctl)
242 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
243 struct stm32_gpio_regs *regs = priv->regs;
244 struct stm32_pinctrl_priv *ctrl_priv;
248 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
249 ctl->pupd > 2 || ctl->speed > 3)
252 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
253 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
255 dev_err(desc->dev, "HWSpinlock timeout\n");
259 index = (desc->offset & 0x07) * 4;
260 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
263 index = desc->offset * 2;
264 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
266 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
267 ctl->speed << index);
268 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
270 index = desc->offset;
271 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
273 hwspinlock_unlock(&ctrl_priv->hws);
278 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
280 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
281 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
282 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
288 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
295 gpio_ctl->mode = STM32_GPIO_MODE_IN;
298 gpio_ctl->mode = STM32_GPIO_MODE_AF;
299 gpio_ctl->af = gpio_fn - 1;
302 gpio_ctl->mode = STM32_GPIO_MODE_AN;
305 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
309 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
311 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
312 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
314 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
316 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
317 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
318 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
319 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
321 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
323 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
324 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
330 static int stm32_pinctrl_config(int offset)
332 u32 pin_mux[MAX_PINS_ONE_IP];
336 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
337 * usart1) of pin controller phandle "pinctrl-0"
339 fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
340 struct stm32_gpio_dsc gpio_dsc;
341 struct stm32_gpio_ctl gpio_ctl;
344 len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
346 ARRAY_SIZE(pin_mux));
347 debug("%s: no of pinmux entries= %d\n", __func__, len);
350 for (i = 0; i < len; i++) {
351 struct gpio_desc desc;
353 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
354 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
355 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
356 rv = uclass_get_device_by_seq(UCLASS_GPIO,
361 desc.offset = gpio_dsc.pin;
362 rv = stm32_gpio_config(&desc, &gpio_ctl);
363 debug("%s: rv = %d\n\n", __func__, rv);
372 static int stm32_pinctrl_bind(struct udevice *dev)
378 dev_for_each_subnode(node, dev) {
379 debug("%s: bind %s\n", __func__, ofnode_get_name(node));
381 ofnode_get_property(node, "gpio-controller", &ret);
384 /* Get the name of each gpio node */
385 name = ofnode_get_name(node);
389 /* Bind each gpio node */
390 ret = device_bind_driver_to_node(dev, "gpio_stm32",
395 debug("%s: bind %s\n", __func__, name);
401 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
402 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
404 return stm32_pinctrl_config(dev_of_offset(config));
406 #else /* PINCTRL_FULL */
407 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
408 struct udevice *periph)
410 const void *fdt = gd->fdt_blob;
416 list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
420 debug("%s: periph->name = %s\n", __func__, periph->name);
422 size /= sizeof(*list);
423 for (i = 0; i < size; i++) {
424 phandle = fdt32_to_cpu(*list++);
426 config_node = fdt_node_offset_by_phandle(fdt, phandle);
427 if (config_node < 0) {
428 pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
432 ret = stm32_pinctrl_config(config_node);
439 #endif /* PINCTRL_FULL */
441 static struct pinctrl_ops stm32_pinctrl_ops = {
442 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
443 .set_state = stm32_pinctrl_set_state,
444 #else /* PINCTRL_FULL */
445 .set_state_simple = stm32_pinctrl_set_state_simple,
446 #endif /* PINCTRL_FULL */
447 #ifndef CONFIG_SPL_BUILD
448 .get_pin_name = stm32_pinctrl_get_pin_name,
449 .get_pins_count = stm32_pinctrl_get_pins_count,
450 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
454 static const struct udevice_id stm32_pinctrl_ids[] = {
455 { .compatible = "st,stm32f429-pinctrl" },
456 { .compatible = "st,stm32f469-pinctrl" },
457 { .compatible = "st,stm32f746-pinctrl" },
458 { .compatible = "st,stm32f769-pinctrl" },
459 { .compatible = "st,stm32h743-pinctrl" },
460 { .compatible = "st,stm32mp157-pinctrl" },
461 { .compatible = "st,stm32mp157-z-pinctrl" },
465 U_BOOT_DRIVER(pinctrl_stm32) = {
466 .name = "pinctrl_stm32",
467 .id = UCLASS_PINCTRL,
468 .of_match = stm32_pinctrl_ids,
469 .ops = &stm32_pinctrl_ops,
470 .bind = stm32_pinctrl_bind,
471 .probe = stm32_pinctrl_probe,
472 .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),