1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017-2020 STMicroelectronics - All Rights Reserved
6 #define LOG_CATEGORY UCLASS_PINCTRL
10 #include <hwspinlock.h>
13 #include <asm/arch/gpio.h>
16 #include <dm/device_compat.h>
18 #include <dm/pinctrl.h>
19 #include <linux/bitops.h>
20 #include <linux/err.h>
21 #include <linux/libfdt.h>
23 #define MAX_PINS_ONE_IP 70
24 #define MODE_BITS_MASK 3
30 struct stm32_pinctrl_priv {
31 struct hwspinlock hws;
33 struct list_head gpio_dev;
36 struct stm32_gpio_bank {
37 struct udevice *gpio_dev;
38 struct list_head list;
41 #ifndef CONFIG_SPL_BUILD
43 static char pin_name[PINNAME_SIZE];
44 #define PINMUX_MODE_COUNT 5
45 static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
53 static const char * const pinmux_bias[] = {
54 [STM32_GPIO_PUPD_NO] = "",
55 [STM32_GPIO_PUPD_UP] = "pull-up",
56 [STM32_GPIO_PUPD_DOWN] = "pull-down",
59 static const char * const pinmux_otype[] = {
60 [STM32_GPIO_OTYPE_PP] = "push-pull",
61 [STM32_GPIO_OTYPE_OD] = "open-drain",
64 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
66 struct stm32_gpio_priv *priv = dev_get_priv(dev);
67 struct stm32_gpio_regs *regs = priv->regs;
69 u32 alt_shift = (offset % 8) * 4;
70 u32 alt_index = offset / 8;
72 af = (readl(®s->afr[alt_index]) &
73 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
78 static int stm32_populate_gpio_dev_list(struct udevice *dev)
80 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
81 struct udevice *gpio_dev;
82 struct udevice *child;
83 struct stm32_gpio_bank *gpio_bank;
87 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
88 * a list with all gpio device reference which belongs to the
89 * current pin-controller. This list is used to find pin_name and
92 list_for_each_entry(child, &dev->child_head, sibling_node) {
93 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
98 gpio_bank = malloc(sizeof(*gpio_bank));
100 dev_err(dev, "Not enough memory\n");
104 gpio_bank->gpio_dev = gpio_dev;
105 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
111 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
113 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
114 struct gpio_dev_priv *uc_priv;
115 struct stm32_gpio_bank *gpio_bank;
118 * if get_pins_count has already been executed once on this
119 * pin-controller, no need to run it again
121 if (priv->pinctrl_ngpios)
122 return priv->pinctrl_ngpios;
124 if (list_empty(&priv->gpio_dev))
125 stm32_populate_gpio_dev_list(dev);
127 * walk through all banks to retrieve the pin-controller
130 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
131 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
133 priv->pinctrl_ngpios += uc_priv->gpio_count;
136 return priv->pinctrl_ngpios;
139 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
140 unsigned int selector,
143 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
144 struct stm32_gpio_bank *gpio_bank;
145 struct gpio_dev_priv *uc_priv;
148 if (list_empty(&priv->gpio_dev))
149 stm32_populate_gpio_dev_list(dev);
151 /* look up for the bank which owns the requested pin */
152 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
153 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
155 if (selector < (pin_count + uc_priv->gpio_count)) {
157 * we found the bank, convert pin selector to
160 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
161 selector - pin_count);
162 if (IS_ERR_VALUE(*idx))
165 return gpio_bank->gpio_dev;
167 pin_count += uc_priv->gpio_count;
173 static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
174 unsigned int selector)
176 struct gpio_dev_priv *uc_priv;
177 struct udevice *gpio_dev;
178 unsigned int gpio_idx;
180 /* look up for the bank which owns the requested pin */
181 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
183 snprintf(pin_name, PINNAME_SIZE, "Error");
185 uc_priv = dev_get_uclass_priv(gpio_dev);
187 snprintf(pin_name, PINNAME_SIZE, "%s%d",
195 static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
196 unsigned int selector,
200 struct udevice *gpio_dev;
201 struct stm32_gpio_priv *priv;
205 unsigned int gpio_idx;
208 /* look up for the bank which owns the requested pin */
209 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
214 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
215 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
216 selector, gpio_idx, mode);
217 priv = dev_get_priv(gpio_dev);
218 pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
219 otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
223 /* should never happen */
226 snprintf(buf, size, "%s", pinmux_mode[mode]);
229 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
230 snprintf(buf, size, "%s %d %s %s", pinmux_mode[mode], af_num,
231 pinmux_otype[otype], pinmux_bias[pupd]);
234 snprintf(buf, size, "%s %s %s %s",
235 pinmux_mode[mode], pinmux_otype[otype],
236 pinmux_bias[pupd], label ? label : "");
239 snprintf(buf, size, "%s %s %s", pinmux_mode[mode],
240 pinmux_bias[pupd], label ? label : "");
249 static int stm32_pinctrl_probe(struct udevice *dev)
251 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
254 INIT_LIST_HEAD(&priv->gpio_dev);
256 /* hwspinlock property is optional, just log the error */
257 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
259 dev_dbg(dev, "hwspinlock_get_by_index may have failed (%d)\n",
265 static int stm32_gpio_config(struct gpio_desc *desc,
266 const struct stm32_gpio_ctl *ctl)
268 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
269 struct stm32_gpio_regs *regs = priv->regs;
270 struct stm32_pinctrl_priv *ctrl_priv;
274 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
275 ctl->pupd > 2 || ctl->speed > 3)
278 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
279 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
281 dev_err(desc->dev, "HWSpinlock timeout\n");
285 index = (desc->offset & 0x07) * 4;
286 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
289 index = desc->offset * 2;
290 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
292 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
293 ctl->speed << index);
294 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
296 index = desc->offset;
297 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
299 hwspinlock_unlock(&ctrl_priv->hws);
304 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
306 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
307 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
308 log_debug("GPIO:port= %d, pin= %d\n", gpio_dsc->port, gpio_dsc->pin);
313 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn,
321 gpio_ctl->mode = STM32_GPIO_MODE_IN;
324 gpio_ctl->mode = STM32_GPIO_MODE_AF;
325 gpio_ctl->af = gpio_fn - 1;
328 gpio_ctl->mode = STM32_GPIO_MODE_AN;
331 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
335 gpio_ctl->speed = ofnode_read_u32_default(node, "slew-rate", 0);
337 if (ofnode_read_bool(node, "drive-open-drain"))
338 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
340 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
342 if (ofnode_read_bool(node, "bias-pull-up"))
343 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
344 else if (ofnode_read_bool(node, "bias-pull-down"))
345 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
347 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
349 log_debug("gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
350 gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
356 static int stm32_pinctrl_config(ofnode node)
358 u32 pin_mux[MAX_PINS_ONE_IP];
363 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
364 * usart1) of pin controller phandle "pinctrl-0"
366 ofnode_for_each_subnode(subnode, node) {
367 struct stm32_gpio_dsc gpio_dsc;
368 struct stm32_gpio_ctl gpio_ctl;
371 rv = ofnode_read_size(subnode, "pinmux");
374 len = rv / sizeof(pin_mux[0]);
375 log_debug("No of pinmux entries= %d\n", len);
376 if (len > MAX_PINS_ONE_IP)
378 rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len);
381 for (i = 0; i < len; i++) {
382 struct gpio_desc desc;
384 log_debug("pinmux = %x\n", *(pin_mux + i));
385 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
386 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode);
387 rv = uclass_get_device_by_seq(UCLASS_GPIO,
392 desc.offset = gpio_dsc.pin;
393 rv = stm32_gpio_config(&desc, &gpio_ctl);
394 log_debug("rv = %d\n\n", rv);
403 static int stm32_pinctrl_bind(struct udevice *dev)
409 dev_for_each_subnode(node, dev) {
410 dev_dbg(dev, "bind %s\n", ofnode_get_name(node));
412 if (!ofnode_is_enabled(node))
415 ofnode_get_property(node, "gpio-controller", &ret);
418 /* Get the name of each gpio node */
419 name = ofnode_get_name(node);
423 /* Bind each gpio node */
424 ret = device_bind_driver_to_node(dev, "gpio_stm32",
429 dev_dbg(dev, "bind %s\n", name);
435 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
436 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
438 return stm32_pinctrl_config(dev_ofnode(config));
440 #else /* PINCTRL_FULL */
441 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
442 struct udevice *periph)
449 list = ofnode_get_property(dev_ofnode(periph), "pinctrl-0", &size);
453 dev_dbg(dev, "periph->name = %s\n", periph->name);
455 size /= sizeof(*list);
456 for (i = 0; i < size; i++) {
457 phandle = fdt32_to_cpu(*list++);
459 config_node = ofnode_get_by_phandle(phandle);
460 if (!ofnode_valid(config_node)) {
462 "prop pinctrl-0 index %d invalid phandle\n", i);
466 ret = stm32_pinctrl_config(config_node);
473 #endif /* PINCTRL_FULL */
475 static struct pinctrl_ops stm32_pinctrl_ops = {
476 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
477 .set_state = stm32_pinctrl_set_state,
478 #else /* PINCTRL_FULL */
479 .set_state_simple = stm32_pinctrl_set_state_simple,
480 #endif /* PINCTRL_FULL */
481 #ifndef CONFIG_SPL_BUILD
482 .get_pin_name = stm32_pinctrl_get_pin_name,
483 .get_pins_count = stm32_pinctrl_get_pins_count,
484 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
488 static const struct udevice_id stm32_pinctrl_ids[] = {
489 { .compatible = "st,stm32f429-pinctrl" },
490 { .compatible = "st,stm32f469-pinctrl" },
491 { .compatible = "st,stm32f746-pinctrl" },
492 { .compatible = "st,stm32f769-pinctrl" },
493 { .compatible = "st,stm32h743-pinctrl" },
494 { .compatible = "st,stm32mp157-pinctrl" },
495 { .compatible = "st,stm32mp157-z-pinctrl" },
499 U_BOOT_DRIVER(pinctrl_stm32) = {
500 .name = "pinctrl_stm32",
501 .id = UCLASS_PINCTRL,
502 .of_match = stm32_pinctrl_ids,
503 .ops = &stm32_pinctrl_ops,
504 .bind = stm32_pinctrl_bind,
505 .probe = stm32_pinctrl_probe,
506 .priv_auto = sizeof(struct stm32_pinctrl_priv),