3 #include <hwspinlock.h>
6 #include <asm/arch/gpio.h>
9 #include <dm/device_compat.h>
11 #include <dm/pinctrl.h>
12 #include <linux/bitops.h>
13 #include <linux/err.h>
14 #include <linux/libfdt.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 #define MAX_PINS_ONE_IP 70
19 #define MODE_BITS_MASK 3
25 struct stm32_pinctrl_priv {
26 struct hwspinlock hws;
28 struct list_head gpio_dev;
31 struct stm32_gpio_bank {
32 struct udevice *gpio_dev;
33 struct list_head list;
36 #ifndef CONFIG_SPL_BUILD
38 static char pin_name[PINNAME_SIZE];
39 #define PINMUX_MODE_COUNT 5
40 static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
48 static const char * const pinmux_output[] = {
49 [STM32_GPIO_PUPD_NO] = "bias-disable",
50 [STM32_GPIO_PUPD_UP] = "bias-pull-up",
51 [STM32_GPIO_PUPD_DOWN] = "bias-pull-down",
54 static const char * const pinmux_input[] = {
55 [STM32_GPIO_OTYPE_PP] = "drive-push-pull",
56 [STM32_GPIO_OTYPE_OD] = "drive-open-drain",
59 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
61 struct stm32_gpio_priv *priv = dev_get_priv(dev);
62 struct stm32_gpio_regs *regs = priv->regs;
64 u32 alt_shift = (offset % 8) * 4;
65 u32 alt_index = offset / 8;
67 af = (readl(®s->afr[alt_index]) &
68 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
73 static int stm32_populate_gpio_dev_list(struct udevice *dev)
75 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
76 struct udevice *gpio_dev;
77 struct udevice *child;
78 struct stm32_gpio_bank *gpio_bank;
82 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
83 * a list with all gpio device reference which belongs to the
84 * current pin-controller. This list is used to find pin_name and
87 list_for_each_entry(child, &dev->child_head, sibling_node) {
88 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
93 gpio_bank = malloc(sizeof(*gpio_bank));
95 dev_err(dev, "Not enough memory\n");
99 gpio_bank->gpio_dev = gpio_dev;
100 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
106 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
108 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
109 struct gpio_dev_priv *uc_priv;
110 struct stm32_gpio_bank *gpio_bank;
113 * if get_pins_count has already been executed once on this
114 * pin-controller, no need to run it again
116 if (priv->pinctrl_ngpios)
117 return priv->pinctrl_ngpios;
119 if (list_empty(&priv->gpio_dev))
120 stm32_populate_gpio_dev_list(dev);
122 * walk through all banks to retrieve the pin-controller
125 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
126 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
128 priv->pinctrl_ngpios += uc_priv->gpio_count;
131 return priv->pinctrl_ngpios;
134 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
135 unsigned int selector,
138 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
139 struct stm32_gpio_bank *gpio_bank;
140 struct gpio_dev_priv *uc_priv;
143 if (list_empty(&priv->gpio_dev))
144 stm32_populate_gpio_dev_list(dev);
146 /* look up for the bank which owns the requested pin */
147 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
148 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
150 if (selector < (pin_count + uc_priv->gpio_count)) {
152 * we found the bank, convert pin selector to
155 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
156 selector - pin_count);
157 if (IS_ERR_VALUE(*idx))
160 return gpio_bank->gpio_dev;
162 pin_count += uc_priv->gpio_count;
168 static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
169 unsigned int selector)
171 struct gpio_dev_priv *uc_priv;
172 struct udevice *gpio_dev;
173 unsigned int gpio_idx;
175 /* look up for the bank which owns the requested pin */
176 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
178 snprintf(pin_name, PINNAME_SIZE, "Error");
180 uc_priv = dev_get_uclass_priv(gpio_dev);
182 snprintf(pin_name, PINNAME_SIZE, "%s%d",
190 static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
191 unsigned int selector,
195 struct udevice *gpio_dev;
196 struct stm32_gpio_priv *priv;
200 unsigned int gpio_idx;
203 /* look up for the bank which owns the requested pin */
204 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
209 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
210 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
211 selector, gpio_idx, mode);
212 priv = dev_get_priv(gpio_dev);
217 /* should never happen */
220 snprintf(buf, size, "%s", pinmux_mode[mode]);
223 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
224 snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
227 pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) &
229 snprintf(buf, size, "%s %s %s",
230 pinmux_mode[mode], pinmux_output[pupd],
234 otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
235 snprintf(buf, size, "%s %s %s",
236 pinmux_mode[mode], pinmux_input[otype],
246 static int stm32_pinctrl_probe(struct udevice *dev)
248 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
251 INIT_LIST_HEAD(&priv->gpio_dev);
253 /* hwspinlock property is optional, just log the error */
254 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
256 debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
262 static int stm32_gpio_config(struct gpio_desc *desc,
263 const struct stm32_gpio_ctl *ctl)
265 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
266 struct stm32_gpio_regs *regs = priv->regs;
267 struct stm32_pinctrl_priv *ctrl_priv;
271 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
272 ctl->pupd > 2 || ctl->speed > 3)
275 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
276 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
278 dev_err(desc->dev, "HWSpinlock timeout\n");
282 index = (desc->offset & 0x07) * 4;
283 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
286 index = desc->offset * 2;
287 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
289 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
290 ctl->speed << index);
291 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
293 index = desc->offset;
294 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
296 hwspinlock_unlock(&ctrl_priv->hws);
301 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
303 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
304 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
305 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
311 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
318 gpio_ctl->mode = STM32_GPIO_MODE_IN;
321 gpio_ctl->mode = STM32_GPIO_MODE_AF;
322 gpio_ctl->af = gpio_fn - 1;
325 gpio_ctl->mode = STM32_GPIO_MODE_AN;
328 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
332 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
334 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
335 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
337 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
339 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
340 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
341 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
342 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
344 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
346 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
347 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
353 static int stm32_pinctrl_config(int offset)
355 u32 pin_mux[MAX_PINS_ONE_IP];
359 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
360 * usart1) of pin controller phandle "pinctrl-0"
362 fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
363 struct stm32_gpio_dsc gpio_dsc;
364 struct stm32_gpio_ctl gpio_ctl;
367 len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
369 ARRAY_SIZE(pin_mux));
370 debug("%s: no of pinmux entries= %d\n", __func__, len);
373 for (i = 0; i < len; i++) {
374 struct gpio_desc desc;
376 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
377 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
378 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
379 rv = uclass_get_device_by_seq(UCLASS_GPIO,
384 desc.offset = gpio_dsc.pin;
385 rv = stm32_gpio_config(&desc, &gpio_ctl);
386 debug("%s: rv = %d\n\n", __func__, rv);
395 static int stm32_pinctrl_bind(struct udevice *dev)
401 dev_for_each_subnode(node, dev) {
402 debug("%s: bind %s\n", __func__, ofnode_get_name(node));
404 ofnode_get_property(node, "gpio-controller", &ret);
407 /* Get the name of each gpio node */
408 name = ofnode_get_name(node);
412 /* Bind each gpio node */
413 ret = device_bind_driver_to_node(dev, "gpio_stm32",
418 debug("%s: bind %s\n", __func__, name);
424 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
425 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
427 return stm32_pinctrl_config(dev_of_offset(config));
429 #else /* PINCTRL_FULL */
430 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
431 struct udevice *periph)
433 const void *fdt = gd->fdt_blob;
439 list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
443 debug("%s: periph->name = %s\n", __func__, periph->name);
445 size /= sizeof(*list);
446 for (i = 0; i < size; i++) {
447 phandle = fdt32_to_cpu(*list++);
449 config_node = fdt_node_offset_by_phandle(fdt, phandle);
450 if (config_node < 0) {
451 pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
455 ret = stm32_pinctrl_config(config_node);
462 #endif /* PINCTRL_FULL */
464 static struct pinctrl_ops stm32_pinctrl_ops = {
465 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
466 .set_state = stm32_pinctrl_set_state,
467 #else /* PINCTRL_FULL */
468 .set_state_simple = stm32_pinctrl_set_state_simple,
469 #endif /* PINCTRL_FULL */
470 #ifndef CONFIG_SPL_BUILD
471 .get_pin_name = stm32_pinctrl_get_pin_name,
472 .get_pins_count = stm32_pinctrl_get_pins_count,
473 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
477 static const struct udevice_id stm32_pinctrl_ids[] = {
478 { .compatible = "st,stm32f429-pinctrl" },
479 { .compatible = "st,stm32f469-pinctrl" },
480 { .compatible = "st,stm32f746-pinctrl" },
481 { .compatible = "st,stm32f769-pinctrl" },
482 { .compatible = "st,stm32h743-pinctrl" },
483 { .compatible = "st,stm32mp157-pinctrl" },
484 { .compatible = "st,stm32mp157-z-pinctrl" },
488 U_BOOT_DRIVER(pinctrl_stm32) = {
489 .name = "pinctrl_stm32",
490 .id = UCLASS_PINCTRL,
491 .of_match = stm32_pinctrl_ids,
492 .ops = &stm32_pinctrl_ops,
493 .bind = stm32_pinctrl_bind,
494 .probe = stm32_pinctrl_probe,
495 .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),