1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017-2020 STMicroelectronics - All Rights Reserved
6 #define LOG_CATEGORY UCLASS_PINCTRL
10 #include <hwspinlock.h>
15 #include <dm/device_compat.h>
17 #include <dm/pinctrl.h>
18 #include <linux/bitops.h>
19 #include <linux/err.h>
20 #include <linux/libfdt.h>
22 #include "../gpio/stm32_gpio_priv.h"
24 #define MAX_PINS_ONE_IP 70
25 #define MODE_BITS_MASK 3
31 struct stm32_pinctrl_priv {
32 struct hwspinlock hws;
34 struct list_head gpio_dev;
37 struct stm32_gpio_bank {
38 struct udevice *gpio_dev;
39 struct list_head list;
42 #ifndef CONFIG_SPL_BUILD
44 static char pin_name[PINNAME_SIZE];
45 #define PINMUX_MODE_COUNT 5
46 static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
54 static const char * const pinmux_bias[] = {
55 [STM32_GPIO_PUPD_NO] = "",
56 [STM32_GPIO_PUPD_UP] = "pull-up",
57 [STM32_GPIO_PUPD_DOWN] = "pull-down",
60 static const char * const pinmux_otype[] = {
61 [STM32_GPIO_OTYPE_PP] = "push-pull",
62 [STM32_GPIO_OTYPE_OD] = "open-drain",
65 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
67 struct stm32_gpio_priv *priv = dev_get_priv(dev);
68 struct stm32_gpio_regs *regs = priv->regs;
70 u32 alt_shift = (offset % 8) * 4;
71 u32 alt_index = offset / 8;
73 af = (readl(®s->afr[alt_index]) &
74 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
79 static int stm32_populate_gpio_dev_list(struct udevice *dev)
81 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
82 struct udevice *gpio_dev;
83 struct udevice *child;
84 struct stm32_gpio_bank *gpio_bank;
88 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
89 * a list with all gpio device reference which belongs to the
90 * current pin-controller. This list is used to find pin_name and
93 list_for_each_entry(child, &dev->child_head, sibling_node) {
94 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
99 gpio_bank = malloc(sizeof(*gpio_bank));
101 dev_err(dev, "Not enough memory\n");
105 gpio_bank->gpio_dev = gpio_dev;
106 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
112 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
114 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
115 struct gpio_dev_priv *uc_priv;
116 struct stm32_gpio_bank *gpio_bank;
119 * if get_pins_count has already been executed once on this
120 * pin-controller, no need to run it again
122 if (priv->pinctrl_ngpios)
123 return priv->pinctrl_ngpios;
125 if (list_empty(&priv->gpio_dev))
126 stm32_populate_gpio_dev_list(dev);
128 * walk through all banks to retrieve the pin-controller
131 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
132 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
134 priv->pinctrl_ngpios += uc_priv->gpio_count;
137 return priv->pinctrl_ngpios;
140 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
141 unsigned int selector,
144 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
145 struct stm32_gpio_bank *gpio_bank;
146 struct gpio_dev_priv *uc_priv;
149 if (list_empty(&priv->gpio_dev))
150 stm32_populate_gpio_dev_list(dev);
152 /* look up for the bank which owns the requested pin */
153 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
154 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
156 if (selector < (pin_count + uc_priv->gpio_count)) {
158 * we found the bank, convert pin selector to
161 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
162 selector - pin_count);
163 if (IS_ERR_VALUE(*idx))
166 return gpio_bank->gpio_dev;
168 pin_count += uc_priv->gpio_count;
174 static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
175 unsigned int selector)
177 struct gpio_dev_priv *uc_priv;
178 struct udevice *gpio_dev;
179 unsigned int gpio_idx;
181 /* look up for the bank which owns the requested pin */
182 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
184 snprintf(pin_name, PINNAME_SIZE, "Error");
186 uc_priv = dev_get_uclass_priv(gpio_dev);
188 snprintf(pin_name, PINNAME_SIZE, "%s%d",
196 static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
197 unsigned int selector,
201 struct udevice *gpio_dev;
202 struct stm32_gpio_priv *priv;
206 unsigned int gpio_idx;
209 /* look up for the bank which owns the requested pin */
210 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
215 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
216 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
217 selector, gpio_idx, mode);
218 priv = dev_get_priv(gpio_dev);
219 pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
220 otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
224 /* should never happen */
227 snprintf(buf, size, "%s", pinmux_mode[mode]);
230 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
231 snprintf(buf, size, "%s %d %s %s", pinmux_mode[mode], af_num,
232 pinmux_otype[otype], pinmux_bias[pupd]);
235 snprintf(buf, size, "%s %s %s %s",
236 pinmux_mode[mode], pinmux_otype[otype],
237 pinmux_bias[pupd], label ? label : "");
240 snprintf(buf, size, "%s %s %s", pinmux_mode[mode],
241 pinmux_bias[pupd], label ? label : "");
250 static int stm32_pinctrl_probe(struct udevice *dev)
252 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
255 INIT_LIST_HEAD(&priv->gpio_dev);
257 /* hwspinlock property is optional, just log the error */
258 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
260 dev_dbg(dev, "hwspinlock_get_by_index may have failed (%d)\n",
266 static int stm32_gpio_config(struct gpio_desc *desc,
267 const struct stm32_gpio_ctl *ctl)
269 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
270 struct stm32_gpio_regs *regs = priv->regs;
271 struct stm32_pinctrl_priv *ctrl_priv;
275 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
276 ctl->pupd > 2 || ctl->speed > 3)
279 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
280 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
282 dev_err(desc->dev, "HWSpinlock timeout\n");
286 index = (desc->offset & 0x07) * 4;
287 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
290 index = desc->offset * 2;
291 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
293 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
294 ctl->speed << index);
295 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
297 index = desc->offset;
298 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
300 hwspinlock_unlock(&ctrl_priv->hws);
305 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
307 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
308 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
309 log_debug("GPIO:port= %d, pin= %d\n", gpio_dsc->port, gpio_dsc->pin);
314 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn,
322 gpio_ctl->mode = STM32_GPIO_MODE_IN;
325 gpio_ctl->mode = STM32_GPIO_MODE_AF;
326 gpio_ctl->af = gpio_fn - 1;
329 gpio_ctl->mode = STM32_GPIO_MODE_AN;
332 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
336 gpio_ctl->speed = ofnode_read_u32_default(node, "slew-rate", 0);
338 if (ofnode_read_bool(node, "drive-open-drain"))
339 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
341 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
343 if (ofnode_read_bool(node, "bias-pull-up"))
344 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
345 else if (ofnode_read_bool(node, "bias-pull-down"))
346 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
348 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
350 log_debug("gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
351 gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
357 static int stm32_pinctrl_config(ofnode node)
359 u32 pin_mux[MAX_PINS_ONE_IP];
364 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
365 * usart1) of pin controller phandle "pinctrl-0"
367 ofnode_for_each_subnode(subnode, node) {
368 struct stm32_gpio_dsc gpio_dsc;
369 struct stm32_gpio_ctl gpio_ctl;
372 rv = ofnode_read_size(subnode, "pinmux");
375 len = rv / sizeof(pin_mux[0]);
376 log_debug("No of pinmux entries= %d\n", len);
377 if (len > MAX_PINS_ONE_IP)
379 rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len);
382 for (i = 0; i < len; i++) {
383 struct gpio_desc desc;
385 log_debug("pinmux = %x\n", *(pin_mux + i));
386 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
387 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode);
388 rv = uclass_get_device_by_seq(UCLASS_GPIO,
393 desc.offset = gpio_dsc.pin;
394 rv = stm32_gpio_config(&desc, &gpio_ctl);
395 log_debug("rv = %d\n\n", rv);
404 static int stm32_pinctrl_bind(struct udevice *dev)
410 dev_for_each_subnode(node, dev) {
411 dev_dbg(dev, "bind %s\n", ofnode_get_name(node));
413 if (!ofnode_is_enabled(node))
416 ofnode_get_property(node, "gpio-controller", &ret);
419 /* Get the name of each gpio node */
420 name = ofnode_get_name(node);
424 /* Bind each gpio node */
425 ret = device_bind_driver_to_node(dev, "gpio_stm32",
430 dev_dbg(dev, "bind %s\n", name);
436 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
437 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
439 return stm32_pinctrl_config(dev_ofnode(config));
441 #else /* PINCTRL_FULL */
442 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
443 struct udevice *periph)
450 list = ofnode_get_property(dev_ofnode(periph), "pinctrl-0", &size);
454 dev_dbg(dev, "periph->name = %s\n", periph->name);
456 size /= sizeof(*list);
457 for (i = 0; i < size; i++) {
458 phandle = fdt32_to_cpu(*list++);
460 config_node = ofnode_get_by_phandle(phandle);
461 if (!ofnode_valid(config_node)) {
463 "prop pinctrl-0 index %d invalid phandle\n", i);
467 ret = stm32_pinctrl_config(config_node);
474 #endif /* PINCTRL_FULL */
476 static struct pinctrl_ops stm32_pinctrl_ops = {
477 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
478 .set_state = stm32_pinctrl_set_state,
479 #else /* PINCTRL_FULL */
480 .set_state_simple = stm32_pinctrl_set_state_simple,
481 #endif /* PINCTRL_FULL */
482 #ifndef CONFIG_SPL_BUILD
483 .get_pin_name = stm32_pinctrl_get_pin_name,
484 .get_pins_count = stm32_pinctrl_get_pins_count,
485 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
489 static const struct udevice_id stm32_pinctrl_ids[] = {
490 { .compatible = "st,stm32f429-pinctrl" },
491 { .compatible = "st,stm32f469-pinctrl" },
492 { .compatible = "st,stm32f746-pinctrl" },
493 { .compatible = "st,stm32f769-pinctrl" },
494 { .compatible = "st,stm32h743-pinctrl" },
495 { .compatible = "st,stm32mp157-pinctrl" },
496 { .compatible = "st,stm32mp157-z-pinctrl" },
500 U_BOOT_DRIVER(pinctrl_stm32) = {
501 .name = "pinctrl_stm32",
502 .id = UCLASS_PINCTRL,
503 .of_match = stm32_pinctrl_ids,
504 .ops = &stm32_pinctrl_ops,
505 .bind = stm32_pinctrl_bind,
506 .probe = stm32_pinctrl_probe,
507 .priv_auto = sizeof(struct stm32_pinctrl_priv),