3 #include <dm/pinctrl.h>
4 #include <hwspinlock.h>
5 #include <asm/arch/gpio.h>
9 DECLARE_GLOBAL_DATA_PTR;
11 #define MAX_PINS_ONE_IP 70
12 #define MODE_BITS_MASK 3
18 struct stm32_pinctrl_priv {
19 struct hwspinlock hws;
21 struct list_head gpio_dev;
24 struct stm32_gpio_bank {
25 struct udevice *gpio_dev;
26 struct list_head list;
29 #ifndef CONFIG_SPL_BUILD
31 #define MAX_PIN_PER_BANK 16
33 static char pin_name[PINNAME_SIZE];
34 #define PINMUX_MODE_COUNT 5
35 static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
43 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
45 struct stm32_gpio_priv *priv = dev_get_priv(dev);
46 struct stm32_gpio_regs *regs = priv->regs;
48 u32 alt_shift = (offset % 8) * 4;
49 u32 alt_index = offset / 8;
51 af = (readl(®s->afr[alt_index]) &
52 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
57 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
59 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
60 struct gpio_dev_priv *uc_priv;
61 struct stm32_gpio_bank *gpio_bank;
64 * if get_pins_count has already been executed once on this
65 * pin-controller, no need to run it again
67 if (priv->pinctrl_ngpios)
68 return priv->pinctrl_ngpios;
71 * walk through all banks to retrieve the pin-controller
74 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
75 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
77 priv->pinctrl_ngpios += uc_priv->gpio_count;
80 return priv->pinctrl_ngpios;
83 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
84 unsigned int selector)
86 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
87 struct stm32_gpio_bank *gpio_bank;
88 struct gpio_dev_priv *uc_priv;
91 /* look up for the bank which owns the requested pin */
92 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
93 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
95 if (selector < (first_pin + uc_priv->gpio_count))
96 /* we found the bank */
97 return gpio_bank->gpio_dev;
99 first_pin += uc_priv->gpio_count;
105 static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
106 unsigned int selector)
108 struct gpio_dev_priv *uc_priv;
109 struct udevice *gpio_dev;
111 /* look up for the bank which owns the requested pin */
112 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector);
114 snprintf(pin_name, PINNAME_SIZE, "Error");
116 uc_priv = dev_get_uclass_priv(gpio_dev);
118 snprintf(pin_name, PINNAME_SIZE, "%s%d",
120 selector % MAX_PIN_PER_BANK);
126 static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
127 unsigned int selector,
131 struct udevice *gpio_dev;
137 /* look up for the bank which owns the requested pin */
138 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector);
143 /* translate pin-controller pin number to gpio pin number */
144 gpio_pin = selector % MAX_PIN_PER_BANK;
146 mode = gpio_get_raw_function(gpio_dev, gpio_pin, &label);
148 dev_dbg(dev, "selector = %d gpio_pin = %d mode = %d\n",
149 selector, gpio_pin, mode);
153 /* should never happen */
156 snprintf(buf, size, "%s", pinmux_mode[mode]);
159 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_pin);
160 snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
164 snprintf(buf, size, "%s %s",
165 pinmux_mode[mode], label ? label : "");
174 int stm32_pinctrl_probe(struct udevice *dev)
176 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
177 struct udevice *gpio_dev;
178 struct udevice *child;
179 struct stm32_gpio_bank *gpio_bank;
182 INIT_LIST_HEAD(&priv->gpio_dev);
185 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
186 * a list with all gpio device reference which belongs to the
187 * current pin-controller. This list is used to find pin_name and
190 list_for_each_entry(child, &dev->child_head, sibling_node) {
191 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
196 gpio_bank = malloc(sizeof(*gpio_bank));
198 dev_err(dev, "Not enough memory\n");
202 gpio_bank->gpio_dev = gpio_dev;
203 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
206 /* hwspinlock property is optional, just log the error */
207 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
209 debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
215 static int stm32_gpio_config(struct gpio_desc *desc,
216 const struct stm32_gpio_ctl *ctl)
218 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
219 struct stm32_gpio_regs *regs = priv->regs;
220 struct stm32_pinctrl_priv *ctrl_priv;
224 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
225 ctl->pupd > 2 || ctl->speed > 3)
228 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
229 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
231 dev_err(desc->dev, "HWSpinlock timeout\n");
235 index = (desc->offset & 0x07) * 4;
236 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
239 index = desc->offset * 2;
240 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
242 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
243 ctl->speed << index);
244 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
246 index = desc->offset;
247 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
249 hwspinlock_unlock(&ctrl_priv->hws);
254 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
256 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
257 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
258 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
264 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
271 gpio_ctl->mode = STM32_GPIO_MODE_IN;
274 gpio_ctl->mode = STM32_GPIO_MODE_AF;
275 gpio_ctl->af = gpio_fn - 1;
278 gpio_ctl->mode = STM32_GPIO_MODE_AN;
281 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
285 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
287 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
288 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
290 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
292 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
293 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
294 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
295 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
297 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
299 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
300 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
306 static int stm32_pinctrl_config(int offset)
308 u32 pin_mux[MAX_PINS_ONE_IP];
312 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
313 * usart1) of pin controller phandle "pinctrl-0"
315 fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
316 struct stm32_gpio_dsc gpio_dsc;
317 struct stm32_gpio_ctl gpio_ctl;
320 len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
322 ARRAY_SIZE(pin_mux));
323 debug("%s: no of pinmux entries= %d\n", __func__, len);
326 for (i = 0; i < len; i++) {
327 struct gpio_desc desc;
329 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
330 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
331 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
332 rv = uclass_get_device_by_seq(UCLASS_GPIO,
337 desc.offset = gpio_dsc.pin;
338 rv = stm32_gpio_config(&desc, &gpio_ctl);
339 debug("%s: rv = %d\n\n", __func__, rv);
348 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
349 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
351 return stm32_pinctrl_config(dev_of_offset(config));
353 #else /* PINCTRL_FULL */
354 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
355 struct udevice *periph)
357 const void *fdt = gd->fdt_blob;
363 list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
367 debug("%s: periph->name = %s\n", __func__, periph->name);
369 size /= sizeof(*list);
370 for (i = 0; i < size; i++) {
371 phandle = fdt32_to_cpu(*list++);
373 config_node = fdt_node_offset_by_phandle(fdt, phandle);
374 if (config_node < 0) {
375 pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
379 ret = stm32_pinctrl_config(config_node);
386 #endif /* PINCTRL_FULL */
388 static struct pinctrl_ops stm32_pinctrl_ops = {
389 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
390 .set_state = stm32_pinctrl_set_state,
391 #else /* PINCTRL_FULL */
392 .set_state_simple = stm32_pinctrl_set_state_simple,
393 #endif /* PINCTRL_FULL */
394 #ifndef CONFIG_SPL_BUILD
395 .get_pin_name = stm32_pinctrl_get_pin_name,
396 .get_pins_count = stm32_pinctrl_get_pins_count,
397 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
401 static const struct udevice_id stm32_pinctrl_ids[] = {
402 { .compatible = "st,stm32f429-pinctrl" },
403 { .compatible = "st,stm32f469-pinctrl" },
404 { .compatible = "st,stm32f746-pinctrl" },
405 { .compatible = "st,stm32h743-pinctrl" },
406 { .compatible = "st,stm32mp157-pinctrl" },
407 { .compatible = "st,stm32mp157-z-pinctrl" },
411 U_BOOT_DRIVER(pinctrl_stm32) = {
412 .name = "pinctrl_stm32",
413 .id = UCLASS_PINCTRL,
414 .of_match = stm32_pinctrl_ids,
415 .ops = &stm32_pinctrl_ops,
416 .bind = dm_scan_fdt_dev,
417 .probe = stm32_pinctrl_probe,
418 .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),