3 #include <dm/pinctrl.h>
4 #include <asm/arch/gpio.h>
8 DECLARE_GLOBAL_DATA_PTR;
10 #define MODE_BITS_MASK 3
16 static int stm32_gpio_config(struct gpio_desc *desc,
17 const struct stm32_gpio_ctl *ctl)
19 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
20 struct stm32_gpio_regs *regs = priv->regs;
23 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
24 ctl->pupd > 2 || ctl->speed > 3)
27 index = (desc->offset & 0x07) * 4;
28 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
31 index = desc->offset * 2;
32 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
34 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
36 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
39 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
43 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
45 gpio_dsc->port = (port_pin & 0xF000) >> 12;
46 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
47 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
53 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
60 gpio_ctl->mode = STM32_GPIO_MODE_IN;
63 gpio_ctl->mode = STM32_GPIO_MODE_AF;
64 gpio_ctl->af = gpio_fn - 1;
67 gpio_ctl->mode = STM32_GPIO_MODE_AN;
70 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
74 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
76 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
77 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
79 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
81 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
82 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
83 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
84 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
86 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
88 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
89 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
95 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
96 struct udevice *periph)
99 struct fdtdec_phandle_args args;
102 /* Get node pinctrl-0 */
103 rv = fdtdec_parse_phandle_with_args(gd->fdt_blob, periph->of_offset,
104 "pinctrl-0", 0, 0, 0, &args);
108 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
109 * usart1) of pin controller phandle "pinctrl-0"
111 fdt_for_each_subnode(args.node, gd->fdt_blob, args.node) {
112 struct stm32_gpio_dsc gpio_dsc;
113 struct stm32_gpio_ctl gpio_ctl;
116 len = fdtdec_get_int_array_count(gd->fdt_blob, args.node,
118 ARRAY_SIZE(pin_mux));
119 debug("%s: periph->name = %s, no of pinmux entries= %d\n",
120 __func__, periph->name, len);
123 for (i = 0; i < len; i++) {
124 struct gpio_desc desc;
125 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
126 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
127 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), args.node);
128 rv = uclass_get_device_by_seq(UCLASS_GPIO,
129 gpio_dsc.port, &desc.dev);
132 desc.offset = gpio_dsc.pin;
133 rv = stm32_gpio_config(&desc, &gpio_ctl);
134 debug("%s: rv = %d\n\n", __func__, rv);
143 static struct pinctrl_ops stm32_pinctrl_ops = {
144 .set_state_simple = stm32_pinctrl_set_state_simple,
147 static const struct udevice_id stm32_pinctrl_ids[] = {
148 { .compatible = "st,stm32f746-pinctrl" },
152 U_BOOT_DRIVER(pinctrl_stm32) = {
153 .name = "pinctrl_stm32",
154 .id = UCLASS_PINCTRL,
155 .of_match = stm32_pinctrl_ids,
156 .ops = &stm32_pinctrl_ops,
157 .bind = dm_scan_fdt_dev,