1 // SPDX-License-Identifier: GPL-2.0+
3 * Pinctrl driver for Microchip PIC32 SoCs
4 * Copyright (c) 2015 Microchip Technology Inc.
5 * Written by Purna Chandra Mandal <purna.mandal@microchip.com>
11 #include <asm/global_data.h>
13 #include <dm/pinctrl.h>
14 #include <linux/bitops.h>
15 #include <mach/pic32.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 /* PIC32 has 10 peripheral ports with 16 pins each.
20 * Ports are marked PORTA-PORTK or PORT0-PORT9.
31 PIC32_PORT_J = 8, /* no PORT_I */
33 PIC32_PINS_PER_PORT = 16,
36 #define PIN_CONFIG_PIC32_DIGITAL (PIN_CONFIG_END + 1)
37 #define PIN_CONFIG_PIC32_ANALOG (PIN_CONFIG_END + 2)
39 /* pin configuration descriptor */
40 struct pic32_pin_config {
41 u16 port; /* port number */
42 u16 pin; /* pin number in the port */
43 u32 config; /* one of PIN_CONFIG_* */
45 #define PIN_CONFIG(_prt, _pin, _cfg) \
46 {.port = (_prt), .pin = (_pin), .config = (_cfg), }
48 /* In PIC32 muxing is performed at pin-level through two
49 * different set of registers - one set for input functions,
50 * and other for output functions.
51 * Pin configuration is handled through port register.
53 /* Port control registers */
54 struct pic32_reg_port {
55 struct pic32_reg_atomic ansel;
56 struct pic32_reg_atomic tris;
57 struct pic32_reg_atomic port;
58 struct pic32_reg_atomic lat;
59 struct pic32_reg_atomic odc;
60 struct pic32_reg_atomic cnpu;
61 struct pic32_reg_atomic cnpd;
62 struct pic32_reg_atomic cncon;
63 struct pic32_reg_atomic unused[8];
66 /* Input function mux registers */
67 struct pic32_reg_in_mux {
114 /* output mux register offset */
115 #define PPS_OUT(__port, __pin) \
116 (((__port) * PIC32_PINS_PER_PORT + (__pin)) << 2)
119 struct pic32_pinctrl_priv {
120 struct pic32_reg_in_mux *mux_in; /* mux input function */
121 struct pic32_reg_port *pinconf; /* pin configuration*/
122 void __iomem *mux_out; /* mux output function */
138 static int pic32_pinconfig_one(struct pic32_pinctrl_priv *priv,
139 u32 port_nr, u32 pin, u32 param)
141 struct pic32_reg_port *port;
143 port = &priv->pinconf[port_nr];
145 case PIN_CONFIG_PIC32_DIGITAL:
146 writel(BIT(pin), &port->ansel.clr);
148 case PIN_CONFIG_PIC32_ANALOG:
149 writel(BIT(pin), &port->ansel.set);
151 case PIN_CONFIG_INPUT_ENABLE:
152 writel(BIT(pin), &port->tris.set);
154 case PIN_CONFIG_OUTPUT:
155 writel(BIT(pin), &port->tris.clr);
157 case PIN_CONFIG_BIAS_PULL_UP:
158 writel(BIT(pin), &port->cnpu.set);
160 case PIN_CONFIG_BIAS_PULL_DOWN:
161 writel(BIT(pin), &port->cnpd.set);
163 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
164 writel(BIT(pin), &port->odc.set);
173 static int pic32_pinconfig_set(struct pic32_pinctrl_priv *priv,
174 const struct pic32_pin_config *list, int count)
178 for (i = 0 ; i < count; i++)
179 pic32_pinconfig_one(priv, list[i].port,
180 list[i].pin, list[i].config);
185 static void pic32_eth_pin_config(struct udevice *dev)
187 struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
188 const struct pic32_pin_config configs[] = {
190 PIN_CONFIG(PIC32_PORT_D, 11, PIN_CONFIG_PIC32_DIGITAL),
191 PIN_CONFIG(PIC32_PORT_D, 11, PIN_CONFIG_OUTPUT),
193 PIN_CONFIG(PIC32_PORT_D, 6, PIN_CONFIG_PIC32_DIGITAL),
194 PIN_CONFIG(PIC32_PORT_D, 6, PIN_CONFIG_OUTPUT),
196 PIN_CONFIG(PIC32_PORT_H, 13, PIN_CONFIG_PIC32_DIGITAL),
197 PIN_CONFIG(PIC32_PORT_H, 13, PIN_CONFIG_INPUT_ENABLE),
199 PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_PIC32_DIGITAL),
200 PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_INPUT_ENABLE),
201 PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_BIAS_PULL_DOWN),
203 PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_PIC32_DIGITAL),
204 PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_INPUT_ENABLE),
205 PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_BIAS_PULL_DOWN),
207 PIN_CONFIG(PIC32_PORT_J, 11, PIN_CONFIG_PIC32_DIGITAL),
208 PIN_CONFIG(PIC32_PORT_J, 11, PIN_CONFIG_INPUT_ENABLE),
210 PIN_CONFIG(PIC32_PORT_J, 9, PIN_CONFIG_PIC32_DIGITAL),
211 PIN_CONFIG(PIC32_PORT_J, 9, PIN_CONFIG_OUTPUT),
213 PIN_CONFIG(PIC32_PORT_J, 8, PIN_CONFIG_PIC32_DIGITAL),
214 PIN_CONFIG(PIC32_PORT_J, 8, PIN_CONFIG_OUTPUT),
216 PIN_CONFIG(PIC32_PORT_J, 1, PIN_CONFIG_PIC32_DIGITAL),
217 PIN_CONFIG(PIC32_PORT_J, 1, PIN_CONFIG_INPUT_ENABLE),
219 PIN_CONFIG(PIC32_PORT_F, 3, PIN_CONFIG_PIC32_DIGITAL),
220 PIN_CONFIG(PIC32_PORT_F, 3, PIN_CONFIG_INPUT_ENABLE),
223 pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));
226 static void pic32_sdhci_pin_config(struct udevice *dev)
228 struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
229 const struct pic32_pin_config configs[] = {
231 PIN_CONFIG(PIC32_PORT_H, 2, PIN_CONFIG_PIC32_DIGITAL),
233 PIN_CONFIG(PIC32_PORT_A, 0, PIN_CONFIG_PIC32_DIGITAL),
235 PIN_CONFIG(PIC32_PORT_D, 4, PIN_CONFIG_PIC32_DIGITAL),
237 PIN_CONFIG(PIC32_PORT_A, 6, PIN_CONFIG_PIC32_DIGITAL),
239 PIN_CONFIG(PIC32_PORT_G, 13, PIN_CONFIG_PIC32_DIGITAL),
241 PIN_CONFIG(PIC32_PORT_G, 12, PIN_CONFIG_PIC32_DIGITAL),
243 PIN_CONFIG(PIC32_PORT_G, 14, PIN_CONFIG_PIC32_DIGITAL),
245 PIN_CONFIG(PIC32_PORT_A, 7, PIN_CONFIG_PIC32_DIGITAL),
248 pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));
251 static int pic32_pinctrl_request(struct udevice *dev, int func, int flags)
253 struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
256 case PERIPH_ID_UART2:
257 /* PPS for U2 RX/TX */
258 writel(0x02, priv->mux_out + PPS_OUT(PIC32_PORT_G, 9));
259 writel(0x05, &priv->mux_in->u2rx); /* B0 */
260 /* set digital mode */
261 pic32_pinconfig_one(priv, PIC32_PORT_G, 9,
262 PIN_CONFIG_PIC32_DIGITAL);
263 pic32_pinconfig_one(priv, PIC32_PORT_B, 0,
264 PIN_CONFIG_PIC32_DIGITAL);
267 pic32_eth_pin_config(dev);
269 case PERIPH_ID_SDHCI:
270 pic32_sdhci_pin_config(dev);
273 debug("%s: unknown-unhandled case\n", __func__);
280 static int pic32_pinctrl_get_periph_id(struct udevice *dev,
281 struct udevice *periph)
286 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
287 "interrupts", cell, ARRAY_SIZE(cell));
291 /* interrupt number */
294 return PERIPH_ID_UART1;
296 return PERIPH_ID_UART2;
298 return PERIPH_ID_SPI1;
300 return PERIPH_ID_SPI2;
302 return PERIPH_ID_I2C1;
304 return PERIPH_ID_I2C2;
306 return PERIPH_ID_USB;
308 return PERIPH_ID_SQI;
310 return PERIPH_ID_SDHCI;
312 return PERIPH_ID_ETH;
320 static int pic32_pinctrl_set_state_simple(struct udevice *dev,
321 struct udevice *periph)
325 debug("%s: periph %s\n", __func__, periph->name);
326 func = pic32_pinctrl_get_periph_id(dev, periph);
329 return pic32_pinctrl_request(dev, func, 0);
332 static struct pinctrl_ops pic32_pinctrl_ops = {
333 .set_state_simple = pic32_pinctrl_set_state_simple,
334 .request = pic32_pinctrl_request,
335 .get_periph_id = pic32_pinctrl_get_periph_id,
338 static int pic32_pinctrl_probe(struct udevice *dev)
340 struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
341 struct fdt_resource res;
342 void *fdt = (void *)gd->fdt_blob;
343 int node = dev_of_offset(dev);
346 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
349 printf("pinctrl: resource \"ppsin\" not found\n");
352 priv->mux_in = ioremap(res.start, fdt_resource_size(&res));
354 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
357 printf("pinctrl: resource \"ppsout\" not found\n");
360 priv->mux_out = ioremap(res.start, fdt_resource_size(&res));
362 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
365 printf("pinctrl: resource \"port\" not found\n");
368 priv->pinconf = ioremap(res.start, fdt_resource_size(&res));
373 static const struct udevice_id pic32_pinctrl_ids[] = {
374 { .compatible = "microchip,pic32mzda-pinctrl" },
378 U_BOOT_DRIVER(pinctrl_pic32) = {
379 .name = "pinctrl_pic32",
380 .id = UCLASS_PINCTRL,
381 .of_match = pic32_pinctrl_ids,
382 .ops = &pic32_pinctrl_ops,
383 .probe = pic32_pinctrl_probe,
384 .bind = dm_scan_fdt_dev,
385 .priv_auto = sizeof(struct pic32_pinctrl_priv),