drivers/pinctrl/pinctrl-xway.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  linux/drivers/pinctrl/pinmux-xway.c
   4  *  based on linux/drivers/pinctrl/pinmux-pxa910.c
   5  *
   6  *  Copyright (C) 2012 John Crispin <john@phrozen.org>
   7  *  Copyright (C) 2015 Martin Schiller <mschiller@tdt.de>
   8  */
   9
  10 #include <linux/err.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/of_address.h>
  16 #include <linux/ioport.h>
  17 #include <linux/io.h>
  18 #include <linux/device.h>
  19 #include <linux/platform_device.h>
  20
  21 #include "pinctrl-lantiq.h"
  22
  23 #include <lantiq_soc.h>
  24
  25 /* we have up to 4 banks of 16 bit each */
  26 #define PINS                    16
  27 #define PORT3                   3
  28 #define PORT(x)                 (x / PINS)
  29 #define PORT_PIN(x)             (x % PINS)
  30
  31 /* we have 2 mux bits that can be set for each pin */
  32 #define MUX_ALT0        0x1
  33 #define MUX_ALT1        0x2
  34
  35 /*
  36  * each bank has this offset apart from the 4th bank that is mixed into the
  37  * other 3 ranges
  38  */
  39 #define REG_OFF                 0x30
  40
  41 /* these are the offsets to our registers */
  42 #define GPIO_BASE(p)            (REG_OFF * PORT(p))
  43 #define GPIO_OUT(p)             GPIO_BASE(p)
  44 #define GPIO_IN(p)              (GPIO_BASE(p) + 0x04)
  45 #define GPIO_DIR(p)             (GPIO_BASE(p) + 0x08)
  46 #define GPIO_ALT0(p)            (GPIO_BASE(p) + 0x0C)
  47 #define GPIO_ALT1(p)            (GPIO_BASE(p) + 0x10)
  48 #define GPIO_OD(p)              (GPIO_BASE(p) + 0x14)
  49 #define GPIO_PUDSEL(p)          (GPIO_BASE(p) + 0x1c)
  50 #define GPIO_PUDEN(p)           (GPIO_BASE(p) + 0x20)
  51
  52 /* the 4th port needs special offsets for some registers */
  53 #define GPIO3_OD                (GPIO_BASE(0) + 0x24)
  54 #define GPIO3_PUDSEL            (GPIO_BASE(0) + 0x28)
  55 #define GPIO3_PUDEN             (GPIO_BASE(0) + 0x2C)
  56 #define GPIO3_ALT1              (GPIO_BASE(PINS) + 0x24)
  57
  58 /* macros to help us access the registers */
  59 #define gpio_getbit(m, r, p)    (!!(ltq_r32(m + r) & BIT(p)))
  60 #define gpio_setbit(m, r, p)    ltq_w32_mask(0, BIT(p), m + r)
  61 #define gpio_clearbit(m, r, p)  ltq_w32_mask(BIT(p), 0, m + r)
  62
  63 #define MFP_XWAY(a, f0, f1, f2, f3)     \
  64         {                               \
  65                 .name = #a,             \
  66                 .pin = a,               \
  67                 .func = {               \
  68                         XWAY_MUX_##f0,  \
  69                         XWAY_MUX_##f1,  \
  70                         XWAY_MUX_##f2,  \
  71                         XWAY_MUX_##f3,  \
  72                 },                      \
  73         }
  74
  75 #define GRP_MUX(a, m, p)                \
  76         { .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), }
  77
  78 #define FUNC_MUX(f, m)          \
  79         { .func = f, .mux = XWAY_MUX_##m, }
  80
  81 enum xway_mux {
  82         XWAY_MUX_GPIO = 0,
  83         XWAY_MUX_SPI,
  84         XWAY_MUX_ASC,
  85         XWAY_MUX_USIF,
  86         XWAY_MUX_PCI,
  87         XWAY_MUX_CBUS,
  88         XWAY_MUX_CGU,
  89         XWAY_MUX_EBU,
  90         XWAY_MUX_EBU2,
  91         XWAY_MUX_JTAG,
  92         XWAY_MUX_MCD,
  93         XWAY_MUX_EXIN,
  94         XWAY_MUX_TDM,
  95         XWAY_MUX_STP,
  96         XWAY_MUX_SIN,
  97         XWAY_MUX_GPT,
  98         XWAY_MUX_NMI,
  99         XWAY_MUX_MDIO,
 100         XWAY_MUX_MII,
 101         XWAY_MUX_EPHY,
 102         XWAY_MUX_DFE,
 103         XWAY_MUX_SDIO,
 104         XWAY_MUX_GPHY,
 105         XWAY_MUX_SSI,
 106         XWAY_MUX_WIFI,
 107         XWAY_MUX_NONE = 0xffff,
 108 };
 109
 110 /* ---------  ase related code --------- */
 111 #define ASE_MAX_PIN             32
 112
 113 static const struct ltq_mfp_pin ase_mfp[] = {
 114         /*       pin    f0      f1      f2      f3   */
 115         MFP_XWAY(GPIO0, GPIO,   EXIN,   MII,    TDM),
 116         MFP_XWAY(GPIO1, GPIO,   STP,    DFE,    EBU),
 117         MFP_XWAY(GPIO2, GPIO,   STP,    DFE,    EPHY),
 118         MFP_XWAY(GPIO3, GPIO,   STP,    EPHY,   EBU),
 119         MFP_XWAY(GPIO4, GPIO,   GPT,    EPHY,   MII),
 120         MFP_XWAY(GPIO5, GPIO,   MII,    ASC,    GPT),
 121         MFP_XWAY(GPIO6, GPIO,   MII,    ASC,    EXIN),
 122         MFP_XWAY(GPIO7, GPIO,   SPI,    MII,    JTAG),
 123         MFP_XWAY(GPIO8, GPIO,   SPI,    MII,    JTAG),
 124         MFP_XWAY(GPIO9, GPIO,   SPI,    MII,    JTAG),
 125         MFP_XWAY(GPIO10, GPIO,  SPI,    MII,    JTAG),
 126         MFP_XWAY(GPIO11, GPIO,  EBU,    CGU,    JTAG),
 127         MFP_XWAY(GPIO12, GPIO,  EBU,    MII,    SDIO),
 128         MFP_XWAY(GPIO13, GPIO,  EBU,    MII,    CGU),
 129         MFP_XWAY(GPIO14, GPIO,  EBU,    SPI,    CGU),
 130         MFP_XWAY(GPIO15, GPIO,  EBU,    SPI,    SDIO),
 131         MFP_XWAY(GPIO16, GPIO,  NONE,   NONE,   NONE),
 132         MFP_XWAY(GPIO17, GPIO,  NONE,   NONE,   NONE),
 133         MFP_XWAY(GPIO18, GPIO,  NONE,   NONE,   NONE),
 134         MFP_XWAY(GPIO19, GPIO,  EBU,    MII,    SDIO),
 135         MFP_XWAY(GPIO20, GPIO,  EBU,    MII,    SDIO),
 136         MFP_XWAY(GPIO21, GPIO,  EBU,    MII,    EBU2),
 137         MFP_XWAY(GPIO22, GPIO,  EBU,    MII,    CGU),
 138         MFP_XWAY(GPIO23, GPIO,  EBU,    MII,    CGU),
 139         MFP_XWAY(GPIO24, GPIO,  EBU,    EBU2,   MDIO),
 140         MFP_XWAY(GPIO25, GPIO,  EBU,    MII,    GPT),
 141         MFP_XWAY(GPIO26, GPIO,  EBU,    MII,    SDIO),
 142         MFP_XWAY(GPIO27, GPIO,  EBU,    NONE,   MDIO),
 143         MFP_XWAY(GPIO28, GPIO,  MII,    EBU,    SDIO),
 144         MFP_XWAY(GPIO29, GPIO,  EBU,    MII,    EXIN),
 145         MFP_XWAY(GPIO30, GPIO,  NONE,   NONE,   NONE),
 146         MFP_XWAY(GPIO31, GPIO,  NONE,   NONE,   NONE),
 147 };
 148
 149 static const unsigned ase_exin_pin_map[] = {GPIO6, GPIO29, GPIO0};
 150
 151 static const unsigned ase_pins_exin0[] = {GPIO6};
 152 static const unsigned ase_pins_exin1[] = {GPIO29};
 153 static const unsigned ase_pins_exin2[] = {GPIO0};
 154
 155 static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11};
 156 static const unsigned ase_pins_asc[] = {GPIO5, GPIO6};
 157 static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3};
 158 static const unsigned ase_pins_mdio[] = {GPIO24, GPIO27};
 159 static const unsigned ase_pins_ephy_led0[] = {GPIO2};
 160 static const unsigned ase_pins_ephy_led1[] = {GPIO3};
 161 static const unsigned ase_pins_ephy_led2[] = {GPIO4};
 162 static const unsigned ase_pins_dfe_led0[] = {GPIO1};
 163 static const unsigned ase_pins_dfe_led1[] = {GPIO2};
 164
 165 static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10}; /* DEPRECATED */
 166 static const unsigned ase_pins_spi_di[] = {GPIO8};
 167 static const unsigned ase_pins_spi_do[] = {GPIO9};
 168 static const unsigned ase_pins_spi_clk[] = {GPIO10};
 169 static const unsigned ase_pins_spi_cs1[] = {GPIO7};
 170 static const unsigned ase_pins_spi_cs2[] = {GPIO15};
 171 static const unsigned ase_pins_spi_cs3[] = {GPIO14};
 172
 173 static const unsigned ase_pins_gpt1[] = {GPIO5};
 174 static const unsigned ase_pins_gpt2[] = {GPIO4};
 175 static const unsigned ase_pins_gpt3[] = {GPIO25};
 176
 177 static const unsigned ase_pins_clkout0[] = {GPIO23};
 178 static const unsigned ase_pins_clkout1[] = {GPIO22};
 179 static const unsigned ase_pins_clkout2[] = {GPIO14};
 180
 181 static const struct ltq_pin_group ase_grps[] = {
 182         GRP_MUX("exin0", EXIN, ase_pins_exin0),
 183         GRP_MUX("exin1", EXIN, ase_pins_exin1),
 184         GRP_MUX("exin2", EXIN, ase_pins_exin2),
 185         GRP_MUX("jtag", JTAG, ase_pins_jtag),
 186         GRP_MUX("spi", SPI, ase_pins_spi), /* DEPRECATED */
 187         GRP_MUX("spi_di", SPI, ase_pins_spi_di),
 188         GRP_MUX("spi_do", SPI, ase_pins_spi_do),
 189         GRP_MUX("spi_clk", SPI, ase_pins_spi_clk),
 190         GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
 191         GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
 192         GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
 193         GRP_MUX("asc", ASC, ase_pins_asc),
 194         GRP_MUX("stp", STP, ase_pins_stp),
 195         GRP_MUX("gpt1", GPT, ase_pins_gpt1),
 196         GRP_MUX("gpt2", GPT, ase_pins_gpt2),
 197         GRP_MUX("gpt3", GPT, ase_pins_gpt3),
 198         GRP_MUX("clkout0", CGU, ase_pins_clkout0),
 199         GRP_MUX("clkout1", CGU, ase_pins_clkout1),
 200         GRP_MUX("clkout2", CGU, ase_pins_clkout2),
 201         GRP_MUX("mdio", MDIO, ase_pins_mdio),
 202         GRP_MUX("dfe led0", DFE, ase_pins_dfe_led0),
 203         GRP_MUX("dfe led1", DFE, ase_pins_dfe_led1),
 204         GRP_MUX("ephy led0", EPHY, ase_pins_ephy_led0),
 205         GRP_MUX("ephy led1", EPHY, ase_pins_ephy_led1),
 206         GRP_MUX("ephy led2", EPHY, ase_pins_ephy_led2),
 207 };
 208
 209 static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"};
 210 static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
 211 static const char * const ase_cgu_grps[] = {"clkout0", "clkout1",
 212                                                 "clkout2"};
 213 static const char * const ase_mdio_grps[] = {"mdio"};
 214 static const char * const ase_dfe_grps[] = {"dfe led0", "dfe led1"};
 215 static const char * const ase_ephy_grps[] = {"ephy led0", "ephy led1",
 216                                                 "ephy led2"};
 217 static const char * const ase_asc_grps[] = {"asc"};
 218 static const char * const ase_jtag_grps[] = {"jtag"};
 219 static const char * const ase_stp_grps[] = {"stp"};
 220 static const char * const ase_spi_grps[] = {"spi",  /* DEPRECATED */
 221                                                 "spi_di", "spi_do",
 222                                                 "spi_clk", "spi_cs1",
 223                                                 "spi_cs2", "spi_cs3"};
 224
 225 static const struct ltq_pmx_func ase_funcs[] = {
 226         {"spi",         ARRAY_AND_SIZE(ase_spi_grps)},
 227         {"asc",         ARRAY_AND_SIZE(ase_asc_grps)},
 228         {"cgu",         ARRAY_AND_SIZE(ase_cgu_grps)},
 229         {"jtag",        ARRAY_AND_SIZE(ase_jtag_grps)},
 230         {"exin",        ARRAY_AND_SIZE(ase_exin_grps)},
 231         {"stp",         ARRAY_AND_SIZE(ase_stp_grps)},
 232         {"gpt",         ARRAY_AND_SIZE(ase_gpt_grps)},
 233         {"mdio",        ARRAY_AND_SIZE(ase_mdio_grps)},
 234         {"ephy",        ARRAY_AND_SIZE(ase_ephy_grps)},
 235         {"dfe",         ARRAY_AND_SIZE(ase_dfe_grps)},
 236 };
 237
 238 /* ---------  danube related code --------- */
 239 #define DANUBE_MAX_PIN          32
 240
 241 static const struct ltq_mfp_pin danube_mfp[] = {
 242         /*       pin    f0      f1      f2      f3   */
 243         MFP_XWAY(GPIO0, GPIO,   EXIN,   SDIO,   TDM),
 244         MFP_XWAY(GPIO1, GPIO,   EXIN,   CBUS,   MII),
 245         MFP_XWAY(GPIO2, GPIO,   CGU,    EXIN,   MII),
 246         MFP_XWAY(GPIO3, GPIO,   CGU,    SDIO,   PCI),
 247         MFP_XWAY(GPIO4, GPIO,   STP,    DFE,    ASC),
 248         MFP_XWAY(GPIO5, GPIO,   STP,    MII,    DFE),
 249         MFP_XWAY(GPIO6, GPIO,   STP,    GPT,    ASC),
 250         MFP_XWAY(GPIO7, GPIO,   CGU,    CBUS,   MII),
 251         MFP_XWAY(GPIO8, GPIO,   CGU,    NMI,    MII),
 252         MFP_XWAY(GPIO9, GPIO,   ASC,    SPI,    MII),
 253         MFP_XWAY(GPIO10, GPIO,  ASC,    SPI,    MII),
 254         MFP_XWAY(GPIO11, GPIO,  ASC,    CBUS,   SPI),
 255         MFP_XWAY(GPIO12, GPIO,  ASC,    CBUS,   MCD),
 256         MFP_XWAY(GPIO13, GPIO,  EBU,    SPI,    MII),
 257         MFP_XWAY(GPIO14, GPIO,  CGU,    CBUS,   MII),
 258         MFP_XWAY(GPIO15, GPIO,  SPI,    SDIO,   JTAG),
 259         MFP_XWAY(GPIO16, GPIO,  SPI,    SDIO,   JTAG),
 260         MFP_XWAY(GPIO17, GPIO,  SPI,    SDIO,   JTAG),
 261         MFP_XWAY(GPIO18, GPIO,  SPI,    SDIO,   JTAG),
 262         MFP_XWAY(GPIO19, GPIO,  PCI,    SDIO,   MII),
 263         MFP_XWAY(GPIO20, GPIO,  JTAG,   SDIO,   MII),
 264         MFP_XWAY(GPIO21, GPIO,  PCI,    EBU,    GPT),
 265         MFP_XWAY(GPIO22, GPIO,  SPI,    MCD,    MII),
 266         MFP_XWAY(GPIO23, GPIO,  EBU,    PCI,    STP),
 267         MFP_XWAY(GPIO24, GPIO,  EBU,    TDM,    PCI),
 268         MFP_XWAY(GPIO25, GPIO,  TDM,    SDIO,   ASC),
 269         MFP_XWAY(GPIO26, GPIO,  EBU,    TDM,    SDIO),
 270         MFP_XWAY(GPIO27, GPIO,  TDM,    SDIO,   ASC),
 271         MFP_XWAY(GPIO28, GPIO,  GPT,    MII,    SDIO),
 272         MFP_XWAY(GPIO29, GPIO,  PCI,    CBUS,   MII),
 273         MFP_XWAY(GPIO30, GPIO,  PCI,    CBUS,   MII),
 274         MFP_XWAY(GPIO31, GPIO,  EBU,    PCI,    MII),
 275 };
 276
 277 static const unsigned danube_exin_pin_map[] = {GPIO0, GPIO1, GPIO2};
 278
 279 static const unsigned danube_pins_exin0[] = {GPIO0};
 280 static const unsigned danube_pins_exin1[] = {GPIO1};
 281 static const unsigned danube_pins_exin2[] = {GPIO2};
 282
 283 static const unsigned danube_pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO18, GPIO20};
 284 static const unsigned danube_pins_asc0[] = {GPIO11, GPIO12};
 285 static const unsigned danube_pins_asc0_cts_rts[] = {GPIO9, GPIO10};
 286 static const unsigned danube_pins_stp[] = {GPIO4, GPIO5, GPIO6};
 287 static const unsigned danube_pins_nmi[] = {GPIO8};
 288
 289 static const unsigned danube_pins_dfe_led0[] = {GPIO4};
 290 static const unsigned danube_pins_dfe_led1[] = {GPIO5};
 291
 292 static const unsigned danube_pins_ebu_a24[] = {GPIO13};
 293 static const unsigned danube_pins_ebu_clk[] = {GPIO21};
 294 static const unsigned danube_pins_ebu_cs1[] = {GPIO23};
 295 static const unsigned danube_pins_ebu_a23[] = {GPIO24};
 296 static const unsigned danube_pins_ebu_wait[] = {GPIO26};
 297 static const unsigned danube_pins_ebu_a25[] = {GPIO31};
 298
 299 static const unsigned danube_pins_nand_ale[] = {GPIO13};
 300 static const unsigned danube_pins_nand_cs1[] = {GPIO23};
 301 static const unsigned danube_pins_nand_cle[] = {GPIO24};
 302
 303 static const unsigned danube_pins_spi[] = {GPIO16, GPIO17, GPIO18}; /* DEPRECATED */
 304 static const unsigned danube_pins_spi_di[] = {GPIO16};
 305 static const unsigned danube_pins_spi_do[] = {GPIO17};
 306 static const unsigned danube_pins_spi_clk[] = {GPIO18};
 307 static const unsigned danube_pins_spi_cs1[] = {GPIO15};
 308 static const unsigned danube_pins_spi_cs2[] = {GPIO21};
 309 static const unsigned danube_pins_spi_cs3[] = {GPIO13};
 310 static const unsigned danube_pins_spi_cs4[] = {GPIO10};
 311 static const unsigned danube_pins_spi_cs5[] = {GPIO9};
 312 static const unsigned danube_pins_spi_cs6[] = {GPIO11};
 313
 314 static const unsigned danube_pins_gpt1[] = {GPIO28};
 315 static const unsigned danube_pins_gpt2[] = {GPIO21};
 316 static const unsigned danube_pins_gpt3[] = {GPIO6};
 317
 318 static const unsigned danube_pins_clkout0[] = {GPIO8};
 319 static const unsigned danube_pins_clkout1[] = {GPIO7};
 320 static const unsigned danube_pins_clkout2[] = {GPIO3};
 321 static const unsigned danube_pins_clkout3[] = {GPIO2};
 322
 323 static const unsigned danube_pins_pci_gnt1[] = {GPIO30};
 324 static const unsigned danube_pins_pci_gnt2[] = {GPIO23};
 325 static const unsigned danube_pins_pci_gnt3[] = {GPIO19};
 326 static const unsigned danube_pins_pci_req1[] = {GPIO29};
 327 static const unsigned danube_pins_pci_req2[] = {GPIO31};
 328 static const unsigned danube_pins_pci_req3[] = {GPIO3};
 329
 330 static const struct ltq_pin_group danube_grps[] = {
 331         GRP_MUX("exin0", EXIN, danube_pins_exin0),
 332         GRP_MUX("exin1", EXIN, danube_pins_exin1),
 333         GRP_MUX("exin2", EXIN, danube_pins_exin2),
 334         GRP_MUX("jtag", JTAG, danube_pins_jtag),
 335         GRP_MUX("ebu a23", EBU, danube_pins_ebu_a23),
 336         GRP_MUX("ebu a24", EBU, danube_pins_ebu_a24),
 337         GRP_MUX("ebu a25", EBU, danube_pins_ebu_a25),
 338         GRP_MUX("ebu clk", EBU, danube_pins_ebu_clk),
 339         GRP_MUX("ebu cs1", EBU, danube_pins_ebu_cs1),
 340         GRP_MUX("ebu wait", EBU, danube_pins_ebu_wait),
 341         GRP_MUX("nand ale", EBU, danube_pins_nand_ale),
 342         GRP_MUX("nand cs1", EBU, danube_pins_nand_cs1),
 343         GRP_MUX("nand cle", EBU, danube_pins_nand_cle),
 344         GRP_MUX("spi", SPI, danube_pins_spi), /* DEPRECATED */
 345         GRP_MUX("spi_di", SPI, danube_pins_spi_di),
 346         GRP_MUX("spi_do", SPI, danube_pins_spi_do),
 347         GRP_MUX("spi_clk", SPI, danube_pins_spi_clk),
 348         GRP_MUX("spi_cs1", SPI, danube_pins_spi_cs1),
 349         GRP_MUX("spi_cs2", SPI, danube_pins_spi_cs2),
 350         GRP_MUX("spi_cs3", SPI, danube_pins_spi_cs3),
 351         GRP_MUX("spi_cs4", SPI, danube_pins_spi_cs4),
 352         GRP_MUX("spi_cs5", SPI, danube_pins_spi_cs5),
 353         GRP_MUX("spi_cs6", SPI, danube_pins_spi_cs6),
 354         GRP_MUX("asc0", ASC, danube_pins_asc0),
 355         GRP_MUX("asc0 cts rts", ASC, danube_pins_asc0_cts_rts),
 356         GRP_MUX("stp", STP, danube_pins_stp),
 357         GRP_MUX("nmi", NMI, danube_pins_nmi),
 358         GRP_MUX("gpt1", GPT, danube_pins_gpt1),
 359         GRP_MUX("gpt2", GPT, danube_pins_gpt2),
 360         GRP_MUX("gpt3", GPT, danube_pins_gpt3),
 361         GRP_MUX("clkout0", CGU, danube_pins_clkout0),
 362         GRP_MUX("clkout1", CGU, danube_pins_clkout1),
 363         GRP_MUX("clkout2", CGU, danube_pins_clkout2),
 364         GRP_MUX("clkout3", CGU, danube_pins_clkout3),
 365         GRP_MUX("gnt1", PCI, danube_pins_pci_gnt1),
 366         GRP_MUX("gnt2", PCI, danube_pins_pci_gnt2),
 367         GRP_MUX("gnt3", PCI, danube_pins_pci_gnt3),
 368         GRP_MUX("req1", PCI, danube_pins_pci_req1),
 369         GRP_MUX("req2", PCI, danube_pins_pci_req2),
 370         GRP_MUX("req3", PCI, danube_pins_pci_req3),
 371         GRP_MUX("dfe led0", DFE, danube_pins_dfe_led0),
 372         GRP_MUX("dfe led1", DFE, danube_pins_dfe_led1),
 373 };
 374
 375 static const char * const danube_pci_grps[] = {"gnt1", "gnt2",
 376                                                 "gnt3", "req1",
 377                                                 "req2", "req3"};
 378 static const char * const danube_spi_grps[] = {"spi", /* DEPRECATED */
 379                                                 "spi_di", "spi_do",
 380                                                 "spi_clk", "spi_cs1",
 381                                                 "spi_cs2", "spi_cs3",
 382                                                 "spi_cs4", "spi_cs5",
 383                                                 "spi_cs6"};
 384 static const char * const danube_cgu_grps[] = {"clkout0", "clkout1",
 385                                                 "clkout2", "clkout3"};
 386 static const char * const danube_ebu_grps[] = {"ebu a23", "ebu a24",
 387                                                 "ebu a25", "ebu cs1",
 388                                                 "ebu wait", "ebu clk",
 389                                                 "nand ale", "nand cs1",
 390                                                 "nand cle"};
 391 static const char * const danube_dfe_grps[] = {"dfe led0", "dfe led1"};
 392 static const char * const danube_exin_grps[] = {"exin0", "exin1", "exin2"};
 393 static const char * const danube_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
 394 static const char * const danube_asc_grps[] = {"asc0", "asc0 cts rts"};
 395 static const char * const danube_jtag_grps[] = {"jtag"};
 396 static const char * const danube_stp_grps[] = {"stp"};
 397 static const char * const danube_nmi_grps[] = {"nmi"};
 398
 399 static const struct ltq_pmx_func danube_funcs[] = {
 400         {"spi",         ARRAY_AND_SIZE(danube_spi_grps)},
 401         {"asc",         ARRAY_AND_SIZE(danube_asc_grps)},
 402         {"cgu",         ARRAY_AND_SIZE(danube_cgu_grps)},
 403         {"jtag",        ARRAY_AND_SIZE(danube_jtag_grps)},
 404         {"exin",        ARRAY_AND_SIZE(danube_exin_grps)},
 405         {"stp",         ARRAY_AND_SIZE(danube_stp_grps)},
 406         {"gpt",         ARRAY_AND_SIZE(danube_gpt_grps)},
 407         {"nmi",         ARRAY_AND_SIZE(danube_nmi_grps)},
 408         {"pci",         ARRAY_AND_SIZE(danube_pci_grps)},
 409         {"ebu",         ARRAY_AND_SIZE(danube_ebu_grps)},
 410         {"dfe",         ARRAY_AND_SIZE(danube_dfe_grps)},
 411 };
 412
 413 /* ---------  xrx100 related code --------- */
 414 #define XRX100_MAX_PIN          56
 415
 416 static const struct ltq_mfp_pin xrx100_mfp[] = {
 417         /*       pin    f0      f1      f2      f3   */
 418         MFP_XWAY(GPIO0, GPIO,   EXIN,   SDIO,   TDM),
 419         MFP_XWAY(GPIO1, GPIO,   EXIN,   CBUS,   SIN),
 420         MFP_XWAY(GPIO2, GPIO,   CGU,    EXIN,   NONE),
 421         MFP_XWAY(GPIO3, GPIO,   CGU,    SDIO,   PCI),
 422         MFP_XWAY(GPIO4, GPIO,   STP,    DFE,    ASC),
 423         MFP_XWAY(GPIO5, GPIO,   STP,    NONE,   DFE),
 424         MFP_XWAY(GPIO6, GPIO,   STP,    GPT,    ASC),
 425         MFP_XWAY(GPIO7, GPIO,   CGU,    CBUS,   NONE),
 426         MFP_XWAY(GPIO8, GPIO,   CGU,    NMI,    NONE),
 427         MFP_XWAY(GPIO9, GPIO,   ASC,    SPI,    EXIN),
 428         MFP_XWAY(GPIO10, GPIO,  ASC,    SPI,    EXIN),
 429         MFP_XWAY(GPIO11, GPIO,  ASC,    CBUS,   SPI),
 430         MFP_XWAY(GPIO12, GPIO,  ASC,    CBUS,   MCD),
 431         MFP_XWAY(GPIO13, GPIO,  EBU,    SPI,    NONE),
 432         MFP_XWAY(GPIO14, GPIO,  CGU,    NONE,   NONE),
 433         MFP_XWAY(GPIO15, GPIO,  SPI,    SDIO,   MCD),
 434         MFP_XWAY(GPIO16, GPIO,  SPI,    SDIO,   NONE),
 435         MFP_XWAY(GPIO17, GPIO,  SPI,    SDIO,   NONE),
 436         MFP_XWAY(GPIO18, GPIO,  SPI,    SDIO,   NONE),
 437         MFP_XWAY(GPIO19, GPIO,  PCI,    SDIO,   CGU),
 438         MFP_XWAY(GPIO20, GPIO,  NONE,   SDIO,   EBU),
 439         MFP_XWAY(GPIO21, GPIO,  PCI,    EBU,    GPT),
 440         MFP_XWAY(GPIO22, GPIO,  SPI,    NONE,   EBU),
 441         MFP_XWAY(GPIO23, GPIO,  EBU,    PCI,    STP),
 442         MFP_XWAY(GPIO24, GPIO,  EBU,    TDM,    PCI),
 443         MFP_XWAY(GPIO25, GPIO,  TDM,    SDIO,   ASC),
 444         MFP_XWAY(GPIO26, GPIO,  EBU,    TDM,    SDIO),
 445         MFP_XWAY(GPIO27, GPIO,  TDM,    SDIO,   ASC),
 446         MFP_XWAY(GPIO28, GPIO,  GPT,    NONE,   SDIO),
 447         MFP_XWAY(GPIO29, GPIO,  PCI,    CBUS,   NONE),
 448         MFP_XWAY(GPIO30, GPIO,  PCI,    CBUS,   NONE),
 449         MFP_XWAY(GPIO31, GPIO,  EBU,    PCI,    NONE),
 450         MFP_XWAY(GPIO32, GPIO,  MII,    NONE,   EBU),
 451         MFP_XWAY(GPIO33, GPIO,  MII,    NONE,   EBU),
 452         MFP_XWAY(GPIO34, GPIO,  SIN,    SSI,    NONE),
 453         MFP_XWAY(GPIO35, GPIO,  SIN,    SSI,    NONE),
 454         MFP_XWAY(GPIO36, GPIO,  SIN,    SSI,    NONE),
 455         MFP_XWAY(GPIO37, GPIO,  PCI,    NONE,   NONE),
 456         MFP_XWAY(GPIO38, GPIO,  PCI,    NONE,   NONE),
 457         MFP_XWAY(GPIO39, GPIO,  NONE,   EXIN,   NONE),
 458         MFP_XWAY(GPIO40, GPIO,  MII,    TDM,    NONE),
 459         MFP_XWAY(GPIO41, GPIO,  MII,    TDM,    NONE),
 460         MFP_XWAY(GPIO42, GPIO,  MDIO,   NONE,   NONE),
 461         MFP_XWAY(GPIO43, GPIO,  MDIO,   NONE,   NONE),
 462         MFP_XWAY(GPIO44, GPIO,  MII,    SIN,    NONE),
 463         MFP_XWAY(GPIO45, GPIO,  MII,    NONE,   SIN),
 464         MFP_XWAY(GPIO46, GPIO,  MII,    NONE,   EXIN),
 465         MFP_XWAY(GPIO47, GPIO,  MII,    NONE,   SIN),
 466         MFP_XWAY(GPIO48, GPIO,  EBU,    NONE,   NONE),
 467         MFP_XWAY(GPIO49, GPIO,  EBU,    NONE,   NONE),
 468         MFP_XWAY(GPIO50, GPIO,  NONE,   NONE,   NONE),
 469         MFP_XWAY(GPIO51, GPIO,  NONE,   NONE,   NONE),
 470         MFP_XWAY(GPIO52, GPIO,  NONE,   NONE,   NONE),
 471         MFP_XWAY(GPIO53, GPIO,  NONE,   NONE,   NONE),
 472         MFP_XWAY(GPIO54, GPIO,  NONE,   NONE,   NONE),
 473         MFP_XWAY(GPIO55, GPIO,  NONE,   NONE,   NONE),
 474 };
 475
 476 static const unsigned xrx100_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};
 477
 478 static const unsigned xrx100_pins_exin0[] = {GPIO0};
 479 static const unsigned xrx100_pins_exin1[] = {GPIO1};
 480 static const unsigned xrx100_pins_exin2[] = {GPIO2};
 481 static const unsigned xrx100_pins_exin3[] = {GPIO39};
 482 static const unsigned xrx100_pins_exin4[] = {GPIO10};
 483 static const unsigned xrx100_pins_exin5[] = {GPIO9};
 484
 485 static const unsigned xrx100_pins_asc0[] = {GPIO11, GPIO12};
 486 static const unsigned xrx100_pins_asc0_cts_rts[] = {GPIO9, GPIO10};
 487 static const unsigned xrx100_pins_stp[] = {GPIO4, GPIO5, GPIO6};
 488 static const unsigned xrx100_pins_nmi[] = {GPIO8};
 489 static const unsigned xrx100_pins_mdio[] = {GPIO42, GPIO43};
 490
 491 static const unsigned xrx100_pins_dfe_led0[] = {GPIO4};
 492 static const unsigned xrx100_pins_dfe_led1[] = {GPIO5};
 493
 494 static const unsigned xrx100_pins_ebu_a24[] = {GPIO13};
 495 static const unsigned xrx100_pins_ebu_clk[] = {GPIO21};
 496 static const unsigned xrx100_pins_ebu_cs1[] = {GPIO23};
 497 static const unsigned xrx100_pins_ebu_a23[] = {GPIO24};
 498 static const unsigned xrx100_pins_ebu_wait[] = {GPIO26};
 499 static const unsigned xrx100_pins_ebu_a25[] = {GPIO31};
 500
 501 static const unsigned xrx100_pins_nand_ale[] = {GPIO13};
 502 static const unsigned xrx100_pins_nand_cs1[] = {GPIO23};
 503 static const unsigned xrx100_pins_nand_cle[] = {GPIO24};
 504 static const unsigned xrx100_pins_nand_rdy[] = {GPIO48};
 505 static const unsigned xrx100_pins_nand_rd[] = {GPIO49};
 506
 507 static const unsigned xrx100_pins_spi_di[] = {GPIO16};
 508 static const unsigned xrx100_pins_spi_do[] = {GPIO17};
 509 static const unsigned xrx100_pins_spi_clk[] = {GPIO18};
 510 static const unsigned xrx100_pins_spi_cs1[] = {GPIO15};
 511 static const unsigned xrx100_pins_spi_cs2[] = {GPIO22};
 512 static const unsigned xrx100_pins_spi_cs3[] = {GPIO13};
 513 static const unsigned xrx100_pins_spi_cs4[] = {GPIO10};
 514 static const unsigned xrx100_pins_spi_cs5[] = {GPIO9};
 515 static const unsigned xrx100_pins_spi_cs6[] = {GPIO11};
 516
 517 static const unsigned xrx100_pins_gpt1[] = {GPIO28};
 518 static const unsigned xrx100_pins_gpt2[] = {GPIO21};
 519 static const unsigned xrx100_pins_gpt3[] = {GPIO6};
 520
 521 static const unsigned xrx100_pins_clkout0[] = {GPIO8};
 522 static const unsigned xrx100_pins_clkout1[] = {GPIO7};
 523 static const unsigned xrx100_pins_clkout2[] = {GPIO3};
 524 static const unsigned xrx100_pins_clkout3[] = {GPIO2};
 525
 526 static const unsigned xrx100_pins_pci_gnt1[] = {GPIO30};
 527 static const unsigned xrx100_pins_pci_gnt2[] = {GPIO23};
 528 static const unsigned xrx100_pins_pci_gnt3[] = {GPIO19};
 529 static const unsigned xrx100_pins_pci_gnt4[] = {GPIO38};
 530 static const unsigned xrx100_pins_pci_req1[] = {GPIO29};
 531 static const unsigned xrx100_pins_pci_req2[] = {GPIO31};
 532 static const unsigned xrx100_pins_pci_req3[] = {GPIO3};
 533 static const unsigned xrx100_pins_pci_req4[] = {GPIO37};
 534
 535 static const struct ltq_pin_group xrx100_grps[] = {
 536         GRP_MUX("exin0", EXIN, xrx100_pins_exin0),
 537         GRP_MUX("exin1", EXIN, xrx100_pins_exin1),
 538         GRP_MUX("exin2", EXIN, xrx100_pins_exin2),
 539         GRP_MUX("exin3", EXIN, xrx100_pins_exin3),
 540         GRP_MUX("exin4", EXIN, xrx100_pins_exin4),
 541         GRP_MUX("exin5", EXIN, xrx100_pins_exin5),
 542         GRP_MUX("ebu a23", EBU, xrx100_pins_ebu_a23),
 543         GRP_MUX("ebu a24", EBU, xrx100_pins_ebu_a24),
 544         GRP_MUX("ebu a25", EBU, xrx100_pins_ebu_a25),
 545         GRP_MUX("ebu clk", EBU, xrx100_pins_ebu_clk),
 546         GRP_MUX("ebu cs1", EBU, xrx100_pins_ebu_cs1),
 547         GRP_MUX("ebu wait", EBU, xrx100_pins_ebu_wait),
 548         GRP_MUX("nand ale", EBU, xrx100_pins_nand_ale),
 549         GRP_MUX("nand cs1", EBU, xrx100_pins_nand_cs1),
 550         GRP_MUX("nand cle", EBU, xrx100_pins_nand_cle),
 551         GRP_MUX("nand rdy", EBU, xrx100_pins_nand_rdy),
 552         GRP_MUX("nand rd", EBU, xrx100_pins_nand_rd),
 553         GRP_MUX("spi_di", SPI, xrx100_pins_spi_di),
 554         GRP_MUX("spi_do", SPI, xrx100_pins_spi_do),
 555         GRP_MUX("spi_clk", SPI, xrx100_pins_spi_clk),
 556         GRP_MUX("spi_cs1", SPI, xrx100_pins_spi_cs1),
 557         GRP_MUX("spi_cs2", SPI, xrx100_pins_spi_cs2),
 558         GRP_MUX("spi_cs3", SPI, xrx100_pins_spi_cs3),
 559         GRP_MUX("spi_cs4", SPI, xrx100_pins_spi_cs4),
 560         GRP_MUX("spi_cs5", SPI, xrx100_pins_spi_cs5),
 561         GRP_MUX("spi_cs6", SPI, xrx100_pins_spi_cs6),
 562         GRP_MUX("asc0", ASC, xrx100_pins_asc0),
 563         GRP_MUX("asc0 cts rts", ASC, xrx100_pins_asc0_cts_rts),
 564         GRP_MUX("stp", STP, xrx100_pins_stp),
 565         GRP_MUX("nmi", NMI, xrx100_pins_nmi),
 566         GRP_MUX("gpt1", GPT, xrx100_pins_gpt1),
 567         GRP_MUX("gpt2", GPT, xrx100_pins_gpt2),
 568         GRP_MUX("gpt3", GPT, xrx100_pins_gpt3),
 569         GRP_MUX("clkout0", CGU, xrx100_pins_clkout0),
 570         GRP_MUX("clkout1", CGU, xrx100_pins_clkout1),
 571         GRP_MUX("clkout2", CGU, xrx100_pins_clkout2),
 572         GRP_MUX("clkout3", CGU, xrx100_pins_clkout3),
 573         GRP_MUX("gnt1", PCI, xrx100_pins_pci_gnt1),
 574         GRP_MUX("gnt2", PCI, xrx100_pins_pci_gnt2),
 575         GRP_MUX("gnt3", PCI, xrx100_pins_pci_gnt3),
 576         GRP_MUX("gnt4", PCI, xrx100_pins_pci_gnt4),
 577         GRP_MUX("req1", PCI, xrx100_pins_pci_req1),
 578         GRP_MUX("req2", PCI, xrx100_pins_pci_req2),
 579         GRP_MUX("req3", PCI, xrx100_pins_pci_req3),
 580         GRP_MUX("req4", PCI, xrx100_pins_pci_req4),
 581         GRP_MUX("mdio", MDIO, xrx100_pins_mdio),
 582         GRP_MUX("dfe led0", DFE, xrx100_pins_dfe_led0),
 583         GRP_MUX("dfe led1", DFE, xrx100_pins_dfe_led1),
 584 };
 585
 586 static const char * const xrx100_pci_grps[] = {"gnt1", "gnt2",
 587                                                 "gnt3", "gnt4",
 588                                                 "req1", "req2",
 589                                                 "req3", "req4"};
 590 static const char * const xrx100_spi_grps[] = {"spi_di", "spi_do",
 591                                                 "spi_clk", "spi_cs1",
 592                                                 "spi_cs2", "spi_cs3",
 593                                                 "spi_cs4", "spi_cs5",
 594                                                 "spi_cs6"};
 595 static const char * const xrx100_cgu_grps[] = {"clkout0", "clkout1",
 596                                                 "clkout2", "clkout3"};
 597 static const char * const xrx100_ebu_grps[] = {"ebu a23", "ebu a24",
 598                                                 "ebu a25", "ebu cs1",
 599                                                 "ebu wait", "ebu clk",
 600                                                 "nand ale", "nand cs1",
 601                                                 "nand cle", "nand rdy",
 602                                                 "nand rd"};
 603 static const char * const xrx100_exin_grps[] = {"exin0", "exin1", "exin2",
 604                                                 "exin3", "exin4", "exin5"};
 605 static const char * const xrx100_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
 606 static const char * const xrx100_asc_grps[] = {"asc0", "asc0 cts rts"};
 607 static const char * const xrx100_stp_grps[] = {"stp"};
 608 static const char * const xrx100_nmi_grps[] = {"nmi"};
 609 static const char * const xrx100_mdio_grps[] = {"mdio"};
 610 static const char * const xrx100_dfe_grps[] = {"dfe led0", "dfe led1"};
 611
 612 static const struct ltq_pmx_func xrx100_funcs[] = {
 613         {"spi",         ARRAY_AND_SIZE(xrx100_spi_grps)},
 614         {"asc",         ARRAY_AND_SIZE(xrx100_asc_grps)},
 615         {"cgu",         ARRAY_AND_SIZE(xrx100_cgu_grps)},
 616         {"exin",        ARRAY_AND_SIZE(xrx100_exin_grps)},
 617         {"stp",         ARRAY_AND_SIZE(xrx100_stp_grps)},
 618         {"gpt",         ARRAY_AND_SIZE(xrx100_gpt_grps)},
 619         {"nmi",         ARRAY_AND_SIZE(xrx100_nmi_grps)},
 620         {"pci",         ARRAY_AND_SIZE(xrx100_pci_grps)},
 621         {"ebu",         ARRAY_AND_SIZE(xrx100_ebu_grps)},
 622         {"mdio",        ARRAY_AND_SIZE(xrx100_mdio_grps)},
 623         {"dfe",         ARRAY_AND_SIZE(xrx100_dfe_grps)},
 624 };
 625
 626 /* ---------  xrx200 related code --------- */
 627 #define XRX200_MAX_PIN          50
 628
 629 static const struct ltq_mfp_pin xrx200_mfp[] = {
 630         /*       pin    f0      f1      f2      f3   */
 631         MFP_XWAY(GPIO0, GPIO,   EXIN,   SDIO,   TDM),
 632         MFP_XWAY(GPIO1, GPIO,   EXIN,   CBUS,   SIN),
 633         MFP_XWAY(GPIO2, GPIO,   CGU,    EXIN,   GPHY),
 634         MFP_XWAY(GPIO3, GPIO,   CGU,    SDIO,   PCI),
 635         MFP_XWAY(GPIO4, GPIO,   STP,    DFE,    USIF),
 636         MFP_XWAY(GPIO5, GPIO,   STP,    GPHY,   DFE),
 637         MFP_XWAY(GPIO6, GPIO,   STP,    GPT,    USIF),
 638         MFP_XWAY(GPIO7, GPIO,   CGU,    CBUS,   GPHY),
 639         MFP_XWAY(GPIO8, GPIO,   CGU,    NMI,    NONE),
 640         MFP_XWAY(GPIO9, GPIO,   USIF,   SPI,    EXIN),
 641         MFP_XWAY(GPIO10, GPIO,  USIF,   SPI,    EXIN),
 642         MFP_XWAY(GPIO11, GPIO,  USIF,   CBUS,   SPI),
 643         MFP_XWAY(GPIO12, GPIO,  USIF,   CBUS,   MCD),
 644         MFP_XWAY(GPIO13, GPIO,  EBU,    SPI,    NONE),
 645         MFP_XWAY(GPIO14, GPIO,  CGU,    CBUS,   USIF),
 646         MFP_XWAY(GPIO15, GPIO,  SPI,    SDIO,   MCD),
 647         MFP_XWAY(GPIO16, GPIO,  SPI,    SDIO,   NONE),
 648         MFP_XWAY(GPIO17, GPIO,  SPI,    SDIO,   NONE),
 649         MFP_XWAY(GPIO18, GPIO,  SPI,    SDIO,   NONE),
 650         MFP_XWAY(GPIO19, GPIO,  PCI,    SDIO,   CGU),
 651         MFP_XWAY(GPIO20, GPIO,  NONE,   SDIO,   EBU),
 652         MFP_XWAY(GPIO21, GPIO,  PCI,    EBU,    GPT),
 653         MFP_XWAY(GPIO22, GPIO,  SPI,    CGU,    EBU),
 654         MFP_XWAY(GPIO23, GPIO,  EBU,    PCI,    STP),
 655         MFP_XWAY(GPIO24, GPIO,  EBU,    TDM,    PCI),
 656         MFP_XWAY(GPIO25, GPIO,  TDM,    SDIO,   USIF),
 657         MFP_XWAY(GPIO26, GPIO,  EBU,    TDM,    SDIO),
 658         MFP_XWAY(GPIO27, GPIO,  TDM,    SDIO,   USIF),
 659         MFP_XWAY(GPIO28, GPIO,  GPT,    PCI,    SDIO),
 660         MFP_XWAY(GPIO29, GPIO,  PCI,    CBUS,   EXIN),
 661         MFP_XWAY(GPIO30, GPIO,  PCI,    CBUS,   NONE),
 662         MFP_XWAY(GPIO31, GPIO,  EBU,    PCI,    NONE),
 663         MFP_XWAY(GPIO32, GPIO,  MII,    NONE,   EBU),
 664         MFP_XWAY(GPIO33, GPIO,  MII,    NONE,   EBU),
 665         MFP_XWAY(GPIO34, GPIO,  SIN,    SSI,    NONE),
 666         MFP_XWAY(GPIO35, GPIO,  SIN,    SSI,    NONE),
 667         MFP_XWAY(GPIO36, GPIO,  SIN,    SSI,    EXIN),
 668         MFP_XWAY(GPIO37, GPIO,  USIF,   NONE,   PCI),
 669         MFP_XWAY(GPIO38, GPIO,  PCI,    USIF,   NONE),
 670         MFP_XWAY(GPIO39, GPIO,  USIF,   EXIN,   NONE),
 671         MFP_XWAY(GPIO40, GPIO,  MII,    TDM,    NONE),
 672         MFP_XWAY(GPIO41, GPIO,  MII,    TDM,    NONE),
 673         MFP_XWAY(GPIO42, GPIO,  MDIO,   NONE,   NONE),
 674         MFP_XWAY(GPIO43, GPIO,  MDIO,   NONE,   NONE),
 675         MFP_XWAY(GPIO44, GPIO,  MII,    SIN,    GPHY),
 676         MFP_XWAY(GPIO45, GPIO,  MII,    GPHY,   SIN),
 677         MFP_XWAY(GPIO46, GPIO,  MII,    NONE,   EXIN),
 678         MFP_XWAY(GPIO47, GPIO,  MII,    GPHY,   SIN),
 679         MFP_XWAY(GPIO48, GPIO,  EBU,    NONE,   NONE),
 680         MFP_XWAY(GPIO49, GPIO,  EBU,    NONE,   NONE),
 681 };
 682
 683 static const unsigned xrx200_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};
 684
 685 static const unsigned xrx200_pins_exin0[] = {GPIO0};
 686 static const unsigned xrx200_pins_exin1[] = {GPIO1};
 687 static const unsigned xrx200_pins_exin2[] = {GPIO2};
 688 static const unsigned xrx200_pins_exin3[] = {GPIO39};
 689 static const unsigned xrx200_pins_exin4[] = {GPIO10};
 690 static const unsigned xrx200_pins_exin5[] = {GPIO9};
 691
 692 static const unsigned xrx200_pins_usif_uart_rx[] = {GPIO11};
 693 static const unsigned xrx200_pins_usif_uart_tx[] = {GPIO12};
 694 static const unsigned xrx200_pins_usif_uart_rts[] = {GPIO9};
 695 static const unsigned xrx200_pins_usif_uart_cts[] = {GPIO10};
 696 static const unsigned xrx200_pins_usif_uart_dtr[] = {GPIO4};
 697 static const unsigned xrx200_pins_usif_uart_dsr[] = {GPIO6};
 698 static const unsigned xrx200_pins_usif_uart_dcd[] = {GPIO25};
 699 static const unsigned xrx200_pins_usif_uart_ri[] = {GPIO27};
 700
 701 static const unsigned xrx200_pins_usif_spi_di[] = {GPIO11};
 702 static const unsigned xrx200_pins_usif_spi_do[] = {GPIO12};
 703 static const unsigned xrx200_pins_usif_spi_clk[] = {GPIO38};
 704 static const unsigned xrx200_pins_usif_spi_cs0[] = {GPIO37};
 705 static const unsigned xrx200_pins_usif_spi_cs1[] = {GPIO39};
 706 static const unsigned xrx200_pins_usif_spi_cs2[] = {GPIO14};
 707
 708 static const unsigned xrx200_pins_stp[] = {GPIO4, GPIO5, GPIO6};
 709 static const unsigned xrx200_pins_nmi[] = {GPIO8};
 710 static const unsigned xrx200_pins_mdio[] = {GPIO42, GPIO43};
 711
 712 static const unsigned xrx200_pins_dfe_led0[] = {GPIO4};
 713 static const unsigned xrx200_pins_dfe_led1[] = {GPIO5};
 714
 715 static const unsigned xrx200_pins_gphy0_led0[] = {GPIO5};
 716 static const unsigned xrx200_pins_gphy0_led1[] = {GPIO7};
 717 static const unsigned xrx200_pins_gphy0_led2[] = {GPIO2};
 718 static const unsigned xrx200_pins_gphy1_led0[] = {GPIO44};
 719 static const unsigned xrx200_pins_gphy1_led1[] = {GPIO45};
 720 static const unsigned xrx200_pins_gphy1_led2[] = {GPIO47};
 721
 722 static const unsigned xrx200_pins_ebu_a24[] = {GPIO13};
 723 static const unsigned xrx200_pins_ebu_clk[] = {GPIO21};
 724 static const unsigned xrx200_pins_ebu_cs1[] = {GPIO23};
 725 static const unsigned xrx200_pins_ebu_a23[] = {GPIO24};
 726 static const unsigned xrx200_pins_ebu_wait[] = {GPIO26};
 727 static const unsigned xrx200_pins_ebu_a25[] = {GPIO31};
 728
 729 static const unsigned xrx200_pins_nand_ale[] = {GPIO13};
 730 static const unsigned xrx200_pins_nand_cs1[] = {GPIO23};
 731 static const unsigned xrx200_pins_nand_cle[] = {GPIO24};
 732 static const unsigned xrx200_pins_nand_rdy[] = {GPIO48};
 733 static const unsigned xrx200_pins_nand_rd[] = {GPIO49};
 734
 735 static const unsigned xrx200_pins_spi_di[] = {GPIO16};
 736 static const unsigned xrx200_pins_spi_do[] = {GPIO17};
 737 static const unsigned xrx200_pins_spi_clk[] = {GPIO18};
 738 static const unsigned xrx200_pins_spi_cs1[] = {GPIO15};
 739 static const unsigned xrx200_pins_spi_cs2[] = {GPIO22};
 740 static const unsigned xrx200_pins_spi_cs3[] = {GPIO13};
 741 static const unsigned xrx200_pins_spi_cs4[] = {GPIO10};
 742 static const unsigned xrx200_pins_spi_cs5[] = {GPIO9};
 743 static const unsigned xrx200_pins_spi_cs6[] = {GPIO11};
 744
 745 static const unsigned xrx200_pins_gpt1[] = {GPIO28};
 746 static const unsigned xrx200_pins_gpt2[] = {GPIO21};
 747 static const unsigned xrx200_pins_gpt3[] = {GPIO6};
 748
 749 static const unsigned xrx200_pins_clkout0[] = {GPIO8};
 750 static const unsigned xrx200_pins_clkout1[] = {GPIO7};
 751 static const unsigned xrx200_pins_clkout2[] = {GPIO3};
 752 static const unsigned xrx200_pins_clkout3[] = {GPIO2};
 753
 754 static const unsigned xrx200_pins_pci_gnt1[] = {GPIO28};
 755 static const unsigned xrx200_pins_pci_gnt2[] = {GPIO23};
 756 static const unsigned xrx200_pins_pci_gnt3[] = {GPIO19};
 757 static const unsigned xrx200_pins_pci_gnt4[] = {GPIO38};
 758 static const unsigned xrx200_pins_pci_req1[] = {GPIO29};
 759 static const unsigned xrx200_pins_pci_req2[] = {GPIO31};
 760 static const unsigned xrx200_pins_pci_req3[] = {GPIO3};
 761 static const unsigned xrx200_pins_pci_req4[] = {GPIO37};
 762
 763 static const struct ltq_pin_group xrx200_grps[] = {
 764         GRP_MUX("exin0", EXIN, xrx200_pins_exin0),
 765         GRP_MUX("exin1", EXIN, xrx200_pins_exin1),
 766         GRP_MUX("exin2", EXIN, xrx200_pins_exin2),
 767         GRP_MUX("exin3", EXIN, xrx200_pins_exin3),
 768         GRP_MUX("exin4", EXIN, xrx200_pins_exin4),
 769         GRP_MUX("exin5", EXIN, xrx200_pins_exin5),
 770         GRP_MUX("ebu a23", EBU, xrx200_pins_ebu_a23),
 771         GRP_MUX("ebu a24", EBU, xrx200_pins_ebu_a24),
 772         GRP_MUX("ebu a25", EBU, xrx200_pins_ebu_a25),
 773         GRP_MUX("ebu clk", EBU, xrx200_pins_ebu_clk),
 774         GRP_MUX("ebu cs1", EBU, xrx200_pins_ebu_cs1),
 775         GRP_MUX("ebu wait", EBU, xrx200_pins_ebu_wait),
 776         GRP_MUX("nand ale", EBU, xrx200_pins_nand_ale),
 777         GRP_MUX("nand cs1", EBU, xrx200_pins_nand_cs1),
 778         GRP_MUX("nand cle", EBU, xrx200_pins_nand_cle),
 779         GRP_MUX("nand rdy", EBU, xrx200_pins_nand_rdy),
 780         GRP_MUX("nand rd", EBU, xrx200_pins_nand_rd),
 781         GRP_MUX("spi_di", SPI, xrx200_pins_spi_di),
 782         GRP_MUX("spi_do", SPI, xrx200_pins_spi_do),
 783         GRP_MUX("spi_clk", SPI, xrx200_pins_spi_clk),
 784         GRP_MUX("spi_cs1", SPI, xrx200_pins_spi_cs1),
 785         GRP_MUX("spi_cs2", SPI, xrx200_pins_spi_cs2),
 786         GRP_MUX("spi_cs3", SPI, xrx200_pins_spi_cs3),
 787         GRP_MUX("spi_cs4", SPI, xrx200_pins_spi_cs4),
 788         GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5),
 789         GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6),
 790         GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_rx),
 791         GRP_MUX("usif uart_tx", USIF, xrx200_pins_usif_uart_tx),
 792         GRP_MUX("usif uart_rts", USIF, xrx200_pins_usif_uart_rts),
 793         GRP_MUX("usif uart_cts", USIF, xrx200_pins_usif_uart_cts),
 794         GRP_MUX("usif uart_dtr", USIF, xrx200_pins_usif_uart_dtr),
 795         GRP_MUX("usif uart_dsr", USIF, xrx200_pins_usif_uart_dsr),
 796         GRP_MUX("usif uart_dcd", USIF, xrx200_pins_usif_uart_dcd),
 797         GRP_MUX("usif uart_ri", USIF, xrx200_pins_usif_uart_ri),
 798         GRP_MUX("usif spi_di", USIF, xrx200_pins_usif_spi_di),
 799         GRP_MUX("usif spi_do", USIF, xrx200_pins_usif_spi_do),
 800         GRP_MUX("usif spi_clk", USIF, xrx200_pins_usif_spi_clk),
 801         GRP_MUX("usif spi_cs0", USIF, xrx200_pins_usif_spi_cs0),
 802         GRP_MUX("usif spi_cs1", USIF, xrx200_pins_usif_spi_cs1),
 803         GRP_MUX("usif spi_cs2", USIF, xrx200_pins_usif_spi_cs2),
 804         GRP_MUX("stp", STP, xrx200_pins_stp),
 805         GRP_MUX("nmi", NMI, xrx200_pins_nmi),
 806         GRP_MUX("gpt1", GPT, xrx200_pins_gpt1),
 807         GRP_MUX("gpt2", GPT, xrx200_pins_gpt2),
 808         GRP_MUX("gpt3", GPT, xrx200_pins_gpt3),
 809         GRP_MUX("clkout0", CGU, xrx200_pins_clkout0),
 810         GRP_MUX("clkout1", CGU, xrx200_pins_clkout1),
 811         GRP_MUX("clkout2", CGU, xrx200_pins_clkout2),
 812         GRP_MUX("clkout3", CGU, xrx200_pins_clkout3),
 813         GRP_MUX("gnt1", PCI, xrx200_pins_pci_gnt1),
 814         GRP_MUX("gnt2", PCI, xrx200_pins_pci_gnt2),
 815         GRP_MUX("gnt3", PCI, xrx200_pins_pci_gnt3),
 816         GRP_MUX("gnt4", PCI, xrx200_pins_pci_gnt4),
 817         GRP_MUX("req1", PCI, xrx200_pins_pci_req1),
 818         GRP_MUX("req2", PCI, xrx200_pins_pci_req2),
 819         GRP_MUX("req3", PCI, xrx200_pins_pci_req3),
 820         GRP_MUX("req4", PCI, xrx200_pins_pci_req4),
 821         GRP_MUX("mdio", MDIO, xrx200_pins_mdio),
 822         GRP_MUX("dfe led0", DFE, xrx200_pins_dfe_led0),
 823         GRP_MUX("dfe led1", DFE, xrx200_pins_dfe_led1),
 824         GRP_MUX("gphy0 led0", GPHY, xrx200_pins_gphy0_led0),
 825         GRP_MUX("gphy0 led1", GPHY, xrx200_pins_gphy0_led1),
 826         GRP_MUX("gphy0 led2", GPHY, xrx200_pins_gphy0_led2),
 827         GRP_MUX("gphy1 led0", GPHY, xrx200_pins_gphy1_led0),
 828         GRP_MUX("gphy1 led1", GPHY, xrx200_pins_gphy1_led1),
 829         GRP_MUX("gphy1 led2", GPHY, xrx200_pins_gphy1_led2),
 830 };
 831
 832 static const char * const xrx200_pci_grps[] = {"gnt1", "gnt2",
 833                                                 "gnt3", "gnt4",
 834                                                 "req1", "req2",
 835                                                 "req3", "req4"};
 836 static const char * const xrx200_spi_grps[] = {"spi_di", "spi_do",
 837                                                 "spi_clk", "spi_cs1",
 838                                                 "spi_cs2", "spi_cs3",
 839                                                 "spi_cs4", "spi_cs5",
 840                                                 "spi_cs6"};
 841 static const char * const xrx200_cgu_grps[] = {"clkout0", "clkout1",
 842                                                 "clkout2", "clkout3"};
 843 static const char * const xrx200_ebu_grps[] = {"ebu a23", "ebu a24",
 844                                                 "ebu a25", "ebu cs1",
 845                                                 "ebu wait", "ebu clk",
 846                                                 "nand ale", "nand cs1",
 847                                                 "nand cle", "nand rdy",
 848                                                 "nand rd"};
 849 static const char * const xrx200_exin_grps[] = {"exin0", "exin1", "exin2",
 850                                                 "exin3", "exin4", "exin5"};
 851 static const char * const xrx200_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
 852 static const char * const xrx200_usif_grps[] = {"usif uart_rx", "usif uart_tx",
 853                                                 "usif uart_rts", "usif uart_cts",
 854                                                 "usif uart_dtr", "usif uart_dsr",
 855                                                 "usif uart_dcd", "usif uart_ri",
 856                                                 "usif spi_di", "usif spi_do",
 857                                                 "usif spi_clk", "usif spi_cs0",
 858                                                 "usif spi_cs1", "usif spi_cs2"};
 859 static const char * const xrx200_stp_grps[] = {"stp"};
 860 static const char * const xrx200_nmi_grps[] = {"nmi"};
 861 static const char * const xrx200_mdio_grps[] = {"mdio"};
 862 static const char * const xrx200_dfe_grps[] = {"dfe led0", "dfe led1"};
 863 static const char * const xrx200_gphy_grps[] = {"gphy0 led0", "gphy0 led1",
 864                                                 "gphy0 led2", "gphy1 led0",
 865                                                 "gphy1 led1", "gphy1 led2"};
 866
 867 static const struct ltq_pmx_func xrx200_funcs[] = {
 868         {"spi",         ARRAY_AND_SIZE(xrx200_spi_grps)},
 869         {"usif",        ARRAY_AND_SIZE(xrx200_usif_grps)},
 870         {"cgu",         ARRAY_AND_SIZE(xrx200_cgu_grps)},
 871         {"exin",        ARRAY_AND_SIZE(xrx200_exin_grps)},
 872         {"stp",         ARRAY_AND_SIZE(xrx200_stp_grps)},
 873         {"gpt",         ARRAY_AND_SIZE(xrx200_gpt_grps)},
 874         {"nmi",         ARRAY_AND_SIZE(xrx200_nmi_grps)},
 875         {"pci",         ARRAY_AND_SIZE(xrx200_pci_grps)},
 876         {"ebu",         ARRAY_AND_SIZE(xrx200_ebu_grps)},
 877         {"mdio",        ARRAY_AND_SIZE(xrx200_mdio_grps)},
 878         {"dfe",         ARRAY_AND_SIZE(xrx200_dfe_grps)},
 879         {"gphy",        ARRAY_AND_SIZE(xrx200_gphy_grps)},
 880 };
 881
 882 /* ---------  xrx300 related code --------- */
 883 #define XRX300_MAX_PIN          64
 884
 885 static const struct ltq_mfp_pin xrx300_mfp[] = {
 886         /*       pin    f0      f1      f2      f3   */
 887         MFP_XWAY(GPIO0, GPIO,   EXIN,   EPHY,   NONE),
 888         MFP_XWAY(GPIO1, GPIO,   NONE,   EXIN,   NONE),
 889         MFP_XWAY(GPIO2, NONE,   NONE,   NONE,   NONE),
 890         MFP_XWAY(GPIO3, GPIO,   CGU,    NONE,   NONE),
 891         MFP_XWAY(GPIO4, GPIO,   STP,    DFE,    NONE),
 892         MFP_XWAY(GPIO5, GPIO,   STP,    EPHY,   DFE),
 893         MFP_XWAY(GPIO6, GPIO,   STP,    NONE,   NONE),
 894         MFP_XWAY(GPIO7, NONE,   NONE,   NONE,   NONE),
 895         MFP_XWAY(GPIO8, GPIO,   CGU,    GPHY,   EPHY),
 896         MFP_XWAY(GPIO9, GPIO,   WIFI,   NONE,   EXIN),
 897         MFP_XWAY(GPIO10, GPIO,  USIF,   SPI,    EXIN),
 898         MFP_XWAY(GPIO11, GPIO,  USIF,   WIFI,   SPI),
 899         MFP_XWAY(GPIO12, NONE,  NONE,   NONE,   NONE),
 900         MFP_XWAY(GPIO13, GPIO,  EBU,    NONE,   NONE),
 901         MFP_XWAY(GPIO14, GPIO,  CGU,    USIF,   EPHY),
 902         MFP_XWAY(GPIO15, GPIO,  SPI,    NONE,   MCD),
 903         MFP_XWAY(GPIO16, GPIO,  SPI,    EXIN,   NONE),
 904         MFP_XWAY(GPIO17, GPIO,  SPI,    NONE,   NONE),
 905         MFP_XWAY(GPIO18, GPIO,  SPI,    NONE,   NONE),
 906         MFP_XWAY(GPIO19, GPIO,  USIF,   NONE,   EPHY),
 907         MFP_XWAY(GPIO20, NONE,  NONE,   NONE,   NONE),
 908         MFP_XWAY(GPIO21, NONE,  NONE,   NONE,   NONE),
 909         MFP_XWAY(GPIO22, NONE,  NONE,   NONE,   NONE),
 910         MFP_XWAY(GPIO23, GPIO,  EBU,    NONE,   NONE),
 911         MFP_XWAY(GPIO24, GPIO,  EBU,    NONE,   NONE),
 912         MFP_XWAY(GPIO25, GPIO,  TDM,    NONE,   NONE),
 913         MFP_XWAY(GPIO26, GPIO,  TDM,    NONE,   NONE),
 914         MFP_XWAY(GPIO27, GPIO,  TDM,    NONE,   NONE),
 915         MFP_XWAY(GPIO28, NONE,  NONE,   NONE,   NONE),
 916         MFP_XWAY(GPIO29, NONE,  NONE,   NONE,   NONE),
 917         MFP_XWAY(GPIO30, NONE,  NONE,   NONE,   NONE),
 918         MFP_XWAY(GPIO31, NONE,  NONE,   NONE,   NONE),
 919         MFP_XWAY(GPIO32, NONE,  NONE,   NONE,   NONE),
 920         MFP_XWAY(GPIO33, NONE,  NONE,   NONE,   NONE),
 921         MFP_XWAY(GPIO34, GPIO,  NONE,   SSI,    NONE),
 922         MFP_XWAY(GPIO35, GPIO,  NONE,   SSI,    NONE),
 923         MFP_XWAY(GPIO36, GPIO,  NONE,   SSI,    NONE),
 924         MFP_XWAY(GPIO37, NONE,  NONE,   NONE,   NONE),
 925         MFP_XWAY(GPIO38, NONE,  NONE,   NONE,   NONE),
 926         MFP_XWAY(GPIO39, NONE,  NONE,   NONE,   NONE),
 927         MFP_XWAY(GPIO40, NONE,  NONE,   NONE,   NONE),
 928         MFP_XWAY(GPIO41, NONE,  NONE,   NONE,   NONE),
 929         MFP_XWAY(GPIO42, GPIO,  MDIO,   NONE,   NONE),
 930         MFP_XWAY(GPIO43, GPIO,  MDIO,   NONE,   NONE),
 931         MFP_XWAY(GPIO44, NONE,  NONE,   NONE,   NONE),
 932         MFP_XWAY(GPIO45, NONE,  NONE,   NONE,   NONE),
 933         MFP_XWAY(GPIO46, NONE,  NONE,   NONE,   NONE),
 934         MFP_XWAY(GPIO47, NONE,  NONE,   NONE,   NONE),
 935         MFP_XWAY(GPIO48, GPIO,  EBU,    NONE,   NONE),
 936         MFP_XWAY(GPIO49, GPIO,  EBU,    NONE,   NONE),
 937         MFP_XWAY(GPIO50, GPIO,  EBU,    NONE,   NONE),
 938         MFP_XWAY(GPIO51, GPIO,  EBU,    NONE,   NONE),
 939         MFP_XWAY(GPIO52, GPIO,  EBU,    NONE,   NONE),
 940         MFP_XWAY(GPIO53, GPIO,  EBU,    NONE,   NONE),
 941         MFP_XWAY(GPIO54, GPIO,  EBU,    NONE,   NONE),
 942         MFP_XWAY(GPIO55, GPIO,  EBU,    NONE,   NONE),
 943         MFP_XWAY(GPIO56, GPIO,  EBU,    NONE,   NONE),
 944         MFP_XWAY(GPIO57, GPIO,  EBU,    NONE,   NONE),
 945         MFP_XWAY(GPIO58, GPIO,  EBU,    TDM,    NONE),
 946         MFP_XWAY(GPIO59, GPIO,  EBU,    NONE,   NONE),
 947         MFP_XWAY(GPIO60, GPIO,  EBU,    NONE,   NONE),
 948         MFP_XWAY(GPIO61, GPIO,  EBU,    NONE,   NONE),
 949         MFP_XWAY(GPIO62, NONE,  NONE,   NONE,   NONE),
 950         MFP_XWAY(GPIO63, NONE,  NONE,   NONE,   NONE),
 951 };
 952
 953 static const unsigned xrx300_exin_pin_map[] = {GPIO0, GPIO1, GPIO16, GPIO10, GPIO9};
 954
 955 static const unsigned xrx300_pins_exin0[] = {GPIO0};
 956 static const unsigned xrx300_pins_exin1[] = {GPIO1};
 957 static const unsigned xrx300_pins_exin2[] = {GPIO16};
 958 /* EXIN3 is not available on xrX300 */
 959 static const unsigned xrx300_pins_exin4[] = {GPIO10};
 960 static const unsigned xrx300_pins_exin5[] = {GPIO9};
 961
 962 static const unsigned xrx300_pins_usif_uart_rx[] = {GPIO11};
 963 static const unsigned xrx300_pins_usif_uart_tx[] = {GPIO10};
 964
 965 static const unsigned xrx300_pins_usif_spi_di[] = {GPIO11};
 966 static const unsigned xrx300_pins_usif_spi_do[] = {GPIO10};
 967 static const unsigned xrx300_pins_usif_spi_clk[] = {GPIO19};
 968 static const unsigned xrx300_pins_usif_spi_cs0[] = {GPIO14};
 969
 970 static const unsigned xrx300_pins_stp[] = {GPIO4, GPIO5, GPIO6};
 971 static const unsigned xrx300_pins_mdio[] = {GPIO42, GPIO43};
 972
 973 static const unsigned xrx300_pins_dfe_led0[] = {GPIO4};
 974 static const unsigned xrx300_pins_dfe_led1[] = {GPIO5};
 975
 976 static const unsigned xrx300_pins_ephy0_led0[] = {GPIO5};
 977 static const unsigned xrx300_pins_ephy0_led1[] = {GPIO8};
 978 static const unsigned xrx300_pins_ephy1_led0[] = {GPIO14};
 979 static const unsigned xrx300_pins_ephy1_led1[] = {GPIO19};
 980
 981 static const unsigned xrx300_pins_nand_ale[] = {GPIO13};
 982 static const unsigned xrx300_pins_nand_cs1[] = {GPIO23};
 983 static const unsigned xrx300_pins_nand_cle[] = {GPIO24};
 984 static const unsigned xrx300_pins_nand_rdy[] = {GPIO48};
 985 static const unsigned xrx300_pins_nand_rd[] = {GPIO49};
 986 static const unsigned xrx300_pins_nand_d1[] = {GPIO50};
 987 static const unsigned xrx300_pins_nand_d0[] = {GPIO51};
 988 static const unsigned xrx300_pins_nand_d2[] = {GPIO52};
 989 static const unsigned xrx300_pins_nand_d7[] = {GPIO53};
 990 static const unsigned xrx300_pins_nand_d6[] = {GPIO54};
 991 static const unsigned xrx300_pins_nand_d5[] = {GPIO55};
 992 static const unsigned xrx300_pins_nand_d4[] = {GPIO56};
 993 static const unsigned xrx300_pins_nand_d3[] = {GPIO57};
 994 static const unsigned xrx300_pins_nand_cs0[] = {GPIO58};
 995 static const unsigned xrx300_pins_nand_wr[] = {GPIO59};
 996 static const unsigned xrx300_pins_nand_wp[] = {GPIO60};
 997 static const unsigned xrx300_pins_nand_se[] = {GPIO61};
 998
 999 static const unsigned xrx300_pins_spi_di[] = {GPIO16};
1000 static const unsigned xrx300_pins_spi_do[] = {GPIO17};
1001 static const unsigned xrx300_pins_spi_clk[] = {GPIO18};
1002 static const unsigned xrx300_pins_spi_cs1[] = {GPIO15};
1003 /* SPI_CS2 is not available on xrX300 */
1004 /* SPI_CS3 is not available on xrX300 */
1005 static const unsigned xrx300_pins_spi_cs4[] = {GPIO10};
1006 /* SPI_CS5 is not available on xrX300 */
1007 static const unsigned xrx300_pins_spi_cs6[] = {GPIO11};
1008
1009 /* CLKOUT0 is not available on xrX300 */
1010 /* CLKOUT1 is not available on xrX300 */
1011 static const unsigned xrx300_pins_clkout2[] = {GPIO3};
1012
1013 static const struct ltq_pin_group xrx300_grps[] = {
1014         GRP_MUX("exin0", EXIN, xrx300_pins_exin0),
1015         GRP_MUX("exin1", EXIN, xrx300_pins_exin1),
1016         GRP_MUX("exin2", EXIN, xrx300_pins_exin2),
1017         GRP_MUX("exin4", EXIN, xrx300_pins_exin4),
1018         GRP_MUX("exin5", EXIN, xrx300_pins_exin5),
1019         GRP_MUX("nand ale", EBU, xrx300_pins_nand_ale),
1020         GRP_MUX("nand cs1", EBU, xrx300_pins_nand_cs1),
1021         GRP_MUX("nand cle", EBU, xrx300_pins_nand_cle),
1022         GRP_MUX("nand rdy", EBU, xrx300_pins_nand_rdy),
1023         GRP_MUX("nand rd", EBU, xrx300_pins_nand_rd),
1024         GRP_MUX("nand d1", EBU, xrx300_pins_nand_d1),
1025         GRP_MUX("nand d0", EBU, xrx300_pins_nand_d0),
1026         GRP_MUX("nand d2", EBU, xrx300_pins_nand_d2),
1027         GRP_MUX("nand d7", EBU, xrx300_pins_nand_d7),
1028         GRP_MUX("nand d6", EBU, xrx300_pins_nand_d6),
1029         GRP_MUX("nand d5", EBU, xrx300_pins_nand_d5),
1030         GRP_MUX("nand d4", EBU, xrx300_pins_nand_d4),
1031         GRP_MUX("nand d3", EBU, xrx300_pins_nand_d3),
1032         GRP_MUX("nand cs0", EBU, xrx300_pins_nand_cs0),
1033         GRP_MUX("nand wr", EBU, xrx300_pins_nand_wr),
1034         GRP_MUX("nand wp", EBU, xrx300_pins_nand_wp),
1035         GRP_MUX("nand se", EBU, xrx300_pins_nand_se),
1036         GRP_MUX("spi_di", SPI, xrx300_pins_spi_di),
1037         GRP_MUX("spi_do", SPI, xrx300_pins_spi_do),
1038         GRP_MUX("spi_clk", SPI, xrx300_pins_spi_clk),
1039         GRP_MUX("spi_cs1", SPI, xrx300_pins_spi_cs1),
1040         GRP_MUX("spi_cs4", SPI, xrx300_pins_spi_cs4),
1041         GRP_MUX("spi_cs6", SPI, xrx300_pins_spi_cs6),
1042         GRP_MUX("usif uart_rx", USIF, xrx300_pins_usif_uart_rx),
1043         GRP_MUX("usif uart_tx", USIF, xrx300_pins_usif_uart_tx),
1044         GRP_MUX("usif spi_di", USIF, xrx300_pins_usif_spi_di),
1045         GRP_MUX("usif spi_do", USIF, xrx300_pins_usif_spi_do),
1046         GRP_MUX("usif spi_clk", USIF, xrx300_pins_usif_spi_clk),
1047         GRP_MUX("usif spi_cs0", USIF, xrx300_pins_usif_spi_cs0),
1048         GRP_MUX("stp", STP, xrx300_pins_stp),
1049         GRP_MUX("clkout2", CGU, xrx300_pins_clkout2),
1050         GRP_MUX("mdio", MDIO, xrx300_pins_mdio),
1051         GRP_MUX("dfe led0", DFE, xrx300_pins_dfe_led0),
1052         GRP_MUX("dfe led1", DFE, xrx300_pins_dfe_led1),
1053         GRP_MUX("ephy0 led0", GPHY, xrx300_pins_ephy0_led0),
1054         GRP_MUX("ephy0 led1", GPHY, xrx300_pins_ephy0_led1),
1055         GRP_MUX("ephy1 led0", GPHY, xrx300_pins_ephy1_led0),
1056         GRP_MUX("ephy1 led1", GPHY, xrx300_pins_ephy1_led1),
1057 };
1058
1059 static const char * const xrx300_spi_grps[] = {"spi_di", "spi_do",
1060                                                 "spi_clk", "spi_cs1",
1061                                                 "spi_cs4", "spi_cs6"};
1062 static const char * const xrx300_cgu_grps[] = {"clkout2"};
1063 static const char * const xrx300_ebu_grps[] = {"nand ale", "nand cs1",
1064                                                 "nand cle", "nand rdy",
1065                                                 "nand rd", "nand d1",
1066                                                 "nand d0", "nand d2",
1067                                                 "nand d7", "nand d6",
1068                                                 "nand d5", "nand d4",
1069                                                 "nand d3", "nand cs0",
1070                                                 "nand wr", "nand wp",
1071                                                 "nand se"};
1072 static const char * const xrx300_exin_grps[] = {"exin0", "exin1", "exin2",
1073                                                 "exin4", "exin5"};
1074 static const char * const xrx300_usif_grps[] = {"usif uart_rx", "usif uart_tx",
1075                                                 "usif spi_di", "usif spi_do",
1076                                                 "usif spi_clk", "usif spi_cs0"};
1077 static const char * const xrx300_stp_grps[] = {"stp"};
1078 static const char * const xrx300_mdio_grps[] = {"mdio"};
1079 static const char * const xrx300_dfe_grps[] = {"dfe led0", "dfe led1"};
1080 static const char * const xrx300_gphy_grps[] = {"ephy0 led0", "ephy0 led1",
1081                                                 "ephy1 led0", "ephy1 led1"};
1082
1083 static const struct ltq_pmx_func xrx300_funcs[] = {
1084         {"spi",         ARRAY_AND_SIZE(xrx300_spi_grps)},
1085         {"usif",        ARRAY_AND_SIZE(xrx300_usif_grps)},
1086         {"cgu",         ARRAY_AND_SIZE(xrx300_cgu_grps)},
1087         {"exin",        ARRAY_AND_SIZE(xrx300_exin_grps)},
1088         {"stp",         ARRAY_AND_SIZE(xrx300_stp_grps)},
1089         {"ebu",         ARRAY_AND_SIZE(xrx300_ebu_grps)},
1090         {"mdio",        ARRAY_AND_SIZE(xrx300_mdio_grps)},
1091         {"dfe",         ARRAY_AND_SIZE(xrx300_dfe_grps)},
1092         {"ephy",        ARRAY_AND_SIZE(xrx300_gphy_grps)},
1093 };
1094
1095 /* ---------  pinconf related code --------- */
1096 static int xway_pinconf_get(struct pinctrl_dev *pctldev,
1097                                 unsigned pin,
1098                                 unsigned long *config)
1099 {
1100         struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
1101         enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
1102         int port = PORT(pin);
1103         u32 reg;
1104
1105         switch (param) {
1106         case LTQ_PINCONF_PARAM_OPEN_DRAIN:
1107                 if (port == PORT3)
1108                         reg = GPIO3_OD;
1109                 else
1110                         reg = GPIO_OD(pin);
1111                 *config = LTQ_PINCONF_PACK(param,
1112                         !gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
1113                 break;
1114
1115         case LTQ_PINCONF_PARAM_PULL:
1116                 if (port == PORT3)
1117                         reg = GPIO3_PUDEN;
1118                 else
1119                         reg = GPIO_PUDEN(pin);
1120                 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) {
1121                         *config = LTQ_PINCONF_PACK(param, 0);
1122                         break;
1123                 }
1124
1125                 if (port == PORT3)
1126                         reg = GPIO3_PUDSEL;
1127                 else
1128                         reg = GPIO_PUDSEL(pin);
1129                 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)))
1130                         *config = LTQ_PINCONF_PACK(param, 2);
1131                 else
1132                         *config = LTQ_PINCONF_PACK(param, 1);
1133                 break;
1134
1135         case LTQ_PINCONF_PARAM_OUTPUT:
1136                 reg = GPIO_DIR(pin);
1137                 *config = LTQ_PINCONF_PACK(param,
1138                         gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
1139                 break;
1140         default:
1141                 dev_err(pctldev->dev, "Invalid config param %04x\n", param);
1142                 return -ENOTSUPP;
1143         }
1144         return 0;
1145 }
1146
1147 static int xway_pinconf_set(struct pinctrl_dev *pctldev,
1148                                 unsigned pin,
1149                                 unsigned long *configs,
1150                                 unsigned num_configs)
1151 {
1152         struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
1153         enum ltq_pinconf_param param;
1154         int arg;
1155         int port = PORT(pin);
1156         u32 reg;
1157         int i;
1158
1159         for (i = 0; i < num_configs; i++) {
1160                 param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
1161                 arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
1162
1163                 switch (param) {
1164                 case LTQ_PINCONF_PARAM_OPEN_DRAIN:
1165                         if (port == PORT3)
1166                                 reg = GPIO3_OD;
1167                         else
1168                                 reg = GPIO_OD(pin);
1169                         if (arg == 0)
1170                                 gpio_setbit(info->membase[0],
1171                                         reg,
1172                                         PORT_PIN(pin));
1173                         else
1174                                 gpio_clearbit(info->membase[0],
1175                                         reg,
1176                                         PORT_PIN(pin));
1177                         break;
1178
1179                 case LTQ_PINCONF_PARAM_PULL:
1180                         if (port == PORT3)
1181                                 reg = GPIO3_PUDEN;
1182                         else
1183                                 reg = GPIO_PUDEN(pin);
1184                         if (arg == 0) {
1185                                 gpio_clearbit(info->membase[0],
1186                                         reg,
1187                                         PORT_PIN(pin));
1188                                 break;
1189                         }
1190                         gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
1191
1192                         if (port == PORT3)
1193                                 reg = GPIO3_PUDSEL;
1194                         else
1195                                 reg = GPIO_PUDSEL(pin);
1196                         if (arg == 1)
1197                                 gpio_clearbit(info->membase[0],
1198                                         reg,
1199                                         PORT_PIN(pin));
1200                         else if (arg == 2)
1201                                 gpio_setbit(info->membase[0],
1202                                         reg,
1203                                         PORT_PIN(pin));
1204                         else
1205                                 dev_err(pctldev->dev,
1206                                         "Invalid pull value %d\n", arg);
1207                         break;
1208
1209                 case LTQ_PINCONF_PARAM_OUTPUT:
1210                         reg = GPIO_DIR(pin);
1211                         if (arg == 0)
1212                                 gpio_clearbit(info->membase[0],
1213                                         reg,
1214                                         PORT_PIN(pin));
1215                         else
1216                                 gpio_setbit(info->membase[0],
1217                                         reg,
1218                                         PORT_PIN(pin));
1219                         break;
1220
1221                 default:
1222                         dev_err(pctldev->dev,
1223                                 "Invalid config param %04x\n", param);
1224                         return -ENOTSUPP;
1225                 }
1226         } /* for each config */
1227
1228         return 0;
1229 }
1230
1231 int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
1232                         unsigned selector,
1233                         unsigned long *configs,
1234                         unsigned num_configs)
1235 {
1236         struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
1237         int i, ret = 0;
1238
1239         for (i = 0; i < info->grps[selector].npins && !ret; i++)
1240                 ret = xway_pinconf_set(pctldev,
1241                                 info->grps[selector].pins[i],
1242                                 configs,
1243                                 num_configs);
1244
1245         return ret;
1246 }
1247
1248 static const struct pinconf_ops xway_pinconf_ops = {
1249         .pin_config_get = xway_pinconf_get,
1250         .pin_config_set = xway_pinconf_set,
1251         .pin_config_group_set = xway_pinconf_group_set,
1252 };
1253
1254 static struct pinctrl_desc xway_pctrl_desc = {
1255         .owner          = THIS_MODULE,
1256         .confops        = &xway_pinconf_ops,
1257 };
1258
1259 static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
1260                                 int pin, int mux)
1261 {
1262         struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
1263         int port = PORT(pin);
1264         u32 alt1_reg = GPIO_ALT1(pin);
1265
1266         if (port == PORT3)
1267                 alt1_reg = GPIO3_ALT1;
1268
1269         if (mux & MUX_ALT0)
1270                 gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
1271         else
1272                 gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
1273
1274         if (mux & MUX_ALT1)
1275                 gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin));
1276         else
1277                 gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin));
1278
1279         return 0;
1280 }
1281
1282 static const struct ltq_cfg_param xway_cfg_params[] = {
1283         {"lantiq,pull",         LTQ_PINCONF_PARAM_PULL},
1284         {"lantiq,open-drain",   LTQ_PINCONF_PARAM_OPEN_DRAIN},
1285         {"lantiq,output",       LTQ_PINCONF_PARAM_OUTPUT},
1286 };
1287
1288 static struct ltq_pinmux_info xway_info = {
1289         .desc           = &xway_pctrl_desc,
1290         .apply_mux      = xway_mux_apply,
1291         .params         = xway_cfg_params,
1292         .num_params     = ARRAY_SIZE(xway_cfg_params),
1293 };
1294
1295 /* ---------  gpio_chip related code --------- */
1296 static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
1297 {
1298         struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1299
1300         if (val)
1301                 gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
1302         else
1303                 gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
1304 }
1305
1306 static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin)
1307 {
1308         struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1309
1310         return !!gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin));
1311 }
1312
1313 static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
1314 {
1315         struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1316
1317         gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
1318
1319         return 0;
1320 }
1321
1322 static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val)
1323 {
1324         struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1325
1326         if (PORT(pin) == PORT3)
1327                 gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin));
1328         else
1329                 gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin));
1330         gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
1331         xway_gpio_set(chip, pin, val);
1332
1333         return 0;
1334 }
1335
1336 /*
1337  * gpiolib gpiod_to_irq callback function.
1338  * Returns the mapped IRQ (external interrupt) number for a given GPIO pin.
1339  */
1340 static int xway_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1341 {
1342         struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1343         int i;
1344
1345         for (i = 0; i < info->num_exin; i++)
1346                 if (info->exin[i] == offset)
1347                         return ltq_eiu_get_irq(i);
1348
1349         return -1;
1350 }
1351
1352 static struct gpio_chip xway_chip = {
1353         .label = "gpio-xway",
1354         .direction_input = xway_gpio_dir_in,
1355         .direction_output = xway_gpio_dir_out,
1356         .get = xway_gpio_get,
1357         .set = xway_gpio_set,
1358         .request = gpiochip_generic_request,
1359         .free = gpiochip_generic_free,
1360         .to_irq = xway_gpio_to_irq,
1361         .base = -1,
1362 };
1363
1364
1365 /* --------- register the pinctrl layer --------- */
1366 struct pinctrl_xway_soc {
1367         int pin_count;
1368         const struct ltq_mfp_pin *mfp;
1369         const struct ltq_pin_group *grps;
1370         unsigned int num_grps;
1371         const struct ltq_pmx_func *funcs;
1372         unsigned int num_funcs;
1373         const unsigned *exin;
1374         unsigned int num_exin;
1375 };
1376
1377 /* XWAY AMAZON Family */
1378 static struct pinctrl_xway_soc ase_pinctrl = {
1379         .pin_count = ASE_MAX_PIN,
1380         .mfp = ase_mfp,
1381         .grps = ase_grps,
1382         .num_grps = ARRAY_SIZE(ase_grps),
1383         .funcs = ase_funcs,
1384         .num_funcs = ARRAY_SIZE(ase_funcs),
1385         .exin = ase_exin_pin_map,
1386         .num_exin = 3
1387 };
1388
1389 /* XWAY DANUBE Family */
1390 static struct pinctrl_xway_soc danube_pinctrl = {
1391         .pin_count = DANUBE_MAX_PIN,
1392         .mfp = danube_mfp,
1393         .grps = danube_grps,
1394         .num_grps = ARRAY_SIZE(danube_grps),
1395         .funcs = danube_funcs,
1396         .num_funcs = ARRAY_SIZE(danube_funcs),
1397         .exin = danube_exin_pin_map,
1398         .num_exin = 3
1399 };
1400
1401 /* XWAY xRX100 Family */
1402 static struct pinctrl_xway_soc xrx100_pinctrl = {
1403         .pin_count = XRX100_MAX_PIN,
1404         .mfp = xrx100_mfp,
1405         .grps = xrx100_grps,
1406         .num_grps = ARRAY_SIZE(xrx100_grps),
1407         .funcs = xrx100_funcs,
1408         .num_funcs = ARRAY_SIZE(xrx100_funcs),
1409         .exin = xrx100_exin_pin_map,
1410         .num_exin = 6
1411 };
1412
1413 /* XWAY xRX200 Family */
1414 static struct pinctrl_xway_soc xrx200_pinctrl = {
1415         .pin_count = XRX200_MAX_PIN,
1416         .mfp = xrx200_mfp,
1417         .grps = xrx200_grps,
1418         .num_grps = ARRAY_SIZE(xrx200_grps),
1419         .funcs = xrx200_funcs,
1420         .num_funcs = ARRAY_SIZE(xrx200_funcs),
1421         .exin = xrx200_exin_pin_map,
1422         .num_exin = 6
1423 };
1424
1425 /* XWAY xRX300 Family */
1426 static struct pinctrl_xway_soc xrx300_pinctrl = {
1427         .pin_count = XRX300_MAX_PIN,
1428         .mfp = xrx300_mfp,
1429         .grps = xrx300_grps,
1430         .num_grps = ARRAY_SIZE(xrx300_grps),
1431         .funcs = xrx300_funcs,
1432         .num_funcs = ARRAY_SIZE(xrx300_funcs),
1433         .exin = xrx300_exin_pin_map,
1434         .num_exin = 5
1435 };
1436
1437 static struct pinctrl_gpio_range xway_gpio_range = {
1438         .name   = "XWAY GPIO",
1439         .gc     = &xway_chip,
1440 };
1441
1442 static const struct of_device_id xway_match[] = {
1443         { .compatible = "lantiq,ase-pinctrl", .data = &ase_pinctrl},
1444         { .compatible = "lantiq,danube-pinctrl", .data = &danube_pinctrl},
1445         { .compatible = "lantiq,xrx100-pinctrl", .data = &xrx100_pinctrl},
1446         { .compatible = "lantiq,xrx200-pinctrl", .data = &xrx200_pinctrl},
1447         { .compatible = "lantiq,xrx300-pinctrl", .data = &xrx300_pinctrl},
1448         {},
1449 };
1450 MODULE_DEVICE_TABLE(of, xway_match);
1451
1452 static int pinmux_xway_probe(struct platform_device *pdev)
1453 {
1454         const struct of_device_id *match;
1455         const struct pinctrl_xway_soc *xway_soc;
1456         int ret, i;
1457
1458         /* get and remap our register range */
1459         xway_info.membase[0] = devm_platform_ioremap_resource(pdev, 0);
1460         if (IS_ERR(xway_info.membase[0]))
1461                 return PTR_ERR(xway_info.membase[0]);
1462
1463         match = of_match_device(xway_match, &pdev->dev);
1464         if (match)
1465                 xway_soc = (const struct pinctrl_xway_soc *) match->data;
1466         else
1467                 xway_soc = &danube_pinctrl;
1468
1469         /* find out how many pads we have */
1470         xway_chip.ngpio = xway_soc->pin_count;
1471
1472         /* load our pad descriptors */
1473         xway_info.pads = devm_kcalloc(&pdev->dev,
1474                         xway_chip.ngpio, sizeof(struct pinctrl_pin_desc),
1475                         GFP_KERNEL);
1476         if (!xway_info.pads)
1477                 return -ENOMEM;
1478
1479         for (i = 0; i < xway_chip.ngpio; i++) {
1480                 char *name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "io%d", i);
1481
1482                 if (!name)
1483                         return -ENOMEM;
1484
1485                 xway_info.pads[i].number = GPIO0 + i;
1486                 xway_info.pads[i].name = name;
1487         }
1488         xway_pctrl_desc.pins = xway_info.pads;
1489
1490         /* setup the data needed by pinctrl */
1491         xway_pctrl_desc.name    = dev_name(&pdev->dev);
1492         xway_pctrl_desc.npins   = xway_chip.ngpio;
1493
1494         xway_info.num_pads      = xway_chip.ngpio;
1495         xway_info.num_mfp       = xway_chip.ngpio;
1496         xway_info.mfp           = xway_soc->mfp;
1497         xway_info.grps          = xway_soc->grps;
1498         xway_info.num_grps      = xway_soc->num_grps;
1499         xway_info.funcs         = xway_soc->funcs;
1500         xway_info.num_funcs     = xway_soc->num_funcs;
1501         xway_info.exin          = xway_soc->exin;
1502         xway_info.num_exin      = xway_soc->num_exin;
1503
1504         /* register with the generic lantiq layer */
1505         ret = ltq_pinctrl_register(pdev, &xway_info);
1506         if (ret) {
1507                 dev_err(&pdev->dev, "Failed to register pinctrl driver\n");
1508                 return ret;
1509         }
1510
1511         /* register the gpio chip */
1512         xway_chip.parent = &pdev->dev;
1513         xway_chip.owner = THIS_MODULE;
1514         ret = devm_gpiochip_add_data(&pdev->dev, &xway_chip, NULL);
1515         if (ret) {
1516                 dev_err(&pdev->dev, "Failed to register gpio chip\n");
1517                 return ret;
1518         }
1519
1520         /*
1521          * For DeviceTree-supported systems, the gpio core checks the
1522          * pinctrl's device node for the "gpio-ranges" property.
1523          * If it is present, it takes care of adding the pin ranges
1524          * for the driver. In this case the driver can skip ahead.
1525          *
1526          * In order to remain compatible with older, existing DeviceTree
1527          * files which don't set the "gpio-ranges" property or systems that
1528          * utilize ACPI the driver has to call gpiochip_add_pin_range().
1529          */
1530         if (!of_property_read_bool(pdev->dev.of_node, "gpio-ranges")) {
1531                 /* finish with registering the gpio range in pinctrl */
1532                 xway_gpio_range.npins = xway_chip.ngpio;
1533                 xway_gpio_range.base = xway_chip.base;
1534                 pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range);
1535         }
1536
1537         dev_info(&pdev->dev, "Init done\n");
1538         return 0;
1539 }
1540
1541 static struct platform_driver pinmux_xway_driver = {
1542         .probe  = pinmux_xway_probe,
1543         .driver = {
1544                 .name   = "pinctrl-xway",
1545                 .of_match_table = xway_match,
1546         },
1547 };
1548
1549 static int __init pinmux_xway_init(void)
1550 {
1551         return platform_driver_register(&pinmux_xway_driver);
1552 }
1553
1554 core_initcall_sync(pinmux_xway_init);