drivers/pinctrl/pinctrl-tegra30.c

   1 /*
   2  * Pinctrl data for the NVIDIA Tegra30 pinmux
   3  *
   4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21
  22 #include "pinctrl-tegra.h"
  23
  24 /*
  25  * Most pins affected by the pinmux can also be GPIOs. Define these first.
  26  * These must match how the GPIO driver names/numbers its pins.
  27  */
  28 #define _GPIO(offset)                           (offset)
  29
  30 #define TEGRA_PIN_CLK_32K_OUT_PA0       _GPIO(0)
  31 #define TEGRA_PIN_UART3_CTS_N_PA1       _GPIO(1)
  32 #define TEGRA_PIN_DAP2_FS_PA2           _GPIO(2)
  33 #define TEGRA_PIN_DAP2_SCLK_PA3         _GPIO(3)
  34 #define TEGRA_PIN_DAP2_DIN_PA4          _GPIO(4)
  35 #define TEGRA_PIN_DAP2_DOUT_PA5         _GPIO(5)
  36 #define TEGRA_PIN_SDMMC3_CLK_PA6        _GPIO(6)
  37 #define TEGRA_PIN_SDMMC3_CMD_PA7        _GPIO(7)
  38 #define TEGRA_PIN_GMI_A17_PB0           _GPIO(8)
  39 #define TEGRA_PIN_GMI_A18_PB1           _GPIO(9)
  40 #define TEGRA_PIN_LCD_PWR0_PB2          _GPIO(10)
  41 #define TEGRA_PIN_LCD_PCLK_PB3          _GPIO(11)
  42 #define TEGRA_PIN_SDMMC3_DAT3_PB4       _GPIO(12)
  43 #define TEGRA_PIN_SDMMC3_DAT2_PB5       _GPIO(13)
  44 #define TEGRA_PIN_SDMMC3_DAT1_PB6       _GPIO(14)
  45 #define TEGRA_PIN_SDMMC3_DAT0_PB7       _GPIO(15)
  46 #define TEGRA_PIN_UART3_RTS_N_PC0       _GPIO(16)
  47 #define TEGRA_PIN_LCD_PWR1_PC1          _GPIO(17)
  48 #define TEGRA_PIN_UART2_TXD_PC2         _GPIO(18)
  49 #define TEGRA_PIN_UART2_RXD_PC3         _GPIO(19)
  50 #define TEGRA_PIN_GEN1_I2C_SCL_PC4      _GPIO(20)
  51 #define TEGRA_PIN_GEN1_I2C_SDA_PC5      _GPIO(21)
  52 #define TEGRA_PIN_LCD_PWR2_PC6          _GPIO(22)
  53 #define TEGRA_PIN_GMI_WP_N_PC7          _GPIO(23)
  54 #define TEGRA_PIN_SDMMC3_DAT5_PD0       _GPIO(24)
  55 #define TEGRA_PIN_SDMMC3_DAT4_PD1       _GPIO(25)
  56 #define TEGRA_PIN_LCD_DC1_PD2           _GPIO(26)
  57 #define TEGRA_PIN_SDMMC3_DAT6_PD3       _GPIO(27)
  58 #define TEGRA_PIN_SDMMC3_DAT7_PD4       _GPIO(28)
  59 #define TEGRA_PIN_VI_D1_PD5             _GPIO(29)
  60 #define TEGRA_PIN_VI_VSYNC_PD6          _GPIO(30)
  61 #define TEGRA_PIN_VI_HSYNC_PD7          _GPIO(31)
  62 #define TEGRA_PIN_LCD_D0_PE0            _GPIO(32)
  63 #define TEGRA_PIN_LCD_D1_PE1            _GPIO(33)
  64 #define TEGRA_PIN_LCD_D2_PE2            _GPIO(34)
  65 #define TEGRA_PIN_LCD_D3_PE3            _GPIO(35)
  66 #define TEGRA_PIN_LCD_D4_PE4            _GPIO(36)
  67 #define TEGRA_PIN_LCD_D5_PE5            _GPIO(37)
  68 #define TEGRA_PIN_LCD_D6_PE6            _GPIO(38)
  69 #define TEGRA_PIN_LCD_D7_PE7            _GPIO(39)
  70 #define TEGRA_PIN_LCD_D8_PF0            _GPIO(40)
  71 #define TEGRA_PIN_LCD_D9_PF1            _GPIO(41)
  72 #define TEGRA_PIN_LCD_D10_PF2           _GPIO(42)
  73 #define TEGRA_PIN_LCD_D11_PF3           _GPIO(43)
  74 #define TEGRA_PIN_LCD_D12_PF4           _GPIO(44)
  75 #define TEGRA_PIN_LCD_D13_PF5           _GPIO(45)
  76 #define TEGRA_PIN_LCD_D14_PF6           _GPIO(46)
  77 #define TEGRA_PIN_LCD_D15_PF7           _GPIO(47)
  78 #define TEGRA_PIN_GMI_AD0_PG0           _GPIO(48)
  79 #define TEGRA_PIN_GMI_AD1_PG1           _GPIO(49)
  80 #define TEGRA_PIN_GMI_AD2_PG2           _GPIO(50)
  81 #define TEGRA_PIN_GMI_AD3_PG3           _GPIO(51)
  82 #define TEGRA_PIN_GMI_AD4_PG4           _GPIO(52)
  83 #define TEGRA_PIN_GMI_AD5_PG5           _GPIO(53)
  84 #define TEGRA_PIN_GMI_AD6_PG6           _GPIO(54)
  85 #define TEGRA_PIN_GMI_AD7_PG7           _GPIO(55)
  86 #define TEGRA_PIN_GMI_AD8_PH0           _GPIO(56)
  87 #define TEGRA_PIN_GMI_AD9_PH1           _GPIO(57)
  88 #define TEGRA_PIN_GMI_AD10_PH2          _GPIO(58)
  89 #define TEGRA_PIN_GMI_AD11_PH3          _GPIO(59)
  90 #define TEGRA_PIN_GMI_AD12_PH4          _GPIO(60)
  91 #define TEGRA_PIN_GMI_AD13_PH5          _GPIO(61)
  92 #define TEGRA_PIN_GMI_AD14_PH6          _GPIO(62)
  93 #define TEGRA_PIN_GMI_AD15_PH7          _GPIO(63)
  94 #define TEGRA_PIN_GMI_WR_N_PI0          _GPIO(64)
  95 #define TEGRA_PIN_GMI_OE_N_PI1          _GPIO(65)
  96 #define TEGRA_PIN_GMI_DQS_PI2           _GPIO(66)
  97 #define TEGRA_PIN_GMI_CS6_N_PI3         _GPIO(67)
  98 #define TEGRA_PIN_GMI_RST_N_PI4         _GPIO(68)
  99 #define TEGRA_PIN_GMI_IORDY_PI5         _GPIO(69)
 100 #define TEGRA_PIN_GMI_CS7_N_PI6         _GPIO(70)
 101 #define TEGRA_PIN_GMI_WAIT_PI7          _GPIO(71)
 102 #define TEGRA_PIN_GMI_CS0_N_PJ0         _GPIO(72)
 103 #define TEGRA_PIN_LCD_DE_PJ1            _GPIO(73)
 104 #define TEGRA_PIN_GMI_CS1_N_PJ2         _GPIO(74)
 105 #define TEGRA_PIN_LCD_HSYNC_PJ3         _GPIO(75)
 106 #define TEGRA_PIN_LCD_VSYNC_PJ4         _GPIO(76)
 107 #define TEGRA_PIN_UART2_CTS_N_PJ5       _GPIO(77)
 108 #define TEGRA_PIN_UART2_RTS_N_PJ6       _GPIO(78)
 109 #define TEGRA_PIN_GMI_A16_PJ7           _GPIO(79)
 110 #define TEGRA_PIN_GMI_ADV_N_PK0         _GPIO(80)
 111 #define TEGRA_PIN_GMI_CLK_PK1           _GPIO(81)
 112 #define TEGRA_PIN_GMI_CS4_N_PK2         _GPIO(82)
 113 #define TEGRA_PIN_GMI_CS2_N_PK3         _GPIO(83)
 114 #define TEGRA_PIN_GMI_CS3_N_PK4         _GPIO(84)
 115 #define TEGRA_PIN_SPDIF_OUT_PK5         _GPIO(85)
 116 #define TEGRA_PIN_SPDIF_IN_PK6          _GPIO(86)
 117 #define TEGRA_PIN_GMI_A19_PK7           _GPIO(87)
 118 #define TEGRA_PIN_VI_D2_PL0             _GPIO(88)
 119 #define TEGRA_PIN_VI_D3_PL1             _GPIO(89)
 120 #define TEGRA_PIN_VI_D4_PL2             _GPIO(90)
 121 #define TEGRA_PIN_VI_D5_PL3             _GPIO(91)
 122 #define TEGRA_PIN_VI_D6_PL4             _GPIO(92)
 123 #define TEGRA_PIN_VI_D7_PL5             _GPIO(93)
 124 #define TEGRA_PIN_VI_D8_PL6             _GPIO(94)
 125 #define TEGRA_PIN_VI_D9_PL7             _GPIO(95)
 126 #define TEGRA_PIN_LCD_D16_PM0           _GPIO(96)
 127 #define TEGRA_PIN_LCD_D17_PM1           _GPIO(97)
 128 #define TEGRA_PIN_LCD_D18_PM2           _GPIO(98)
 129 #define TEGRA_PIN_LCD_D19_PM3           _GPIO(99)
 130 #define TEGRA_PIN_LCD_D20_PM4           _GPIO(100)
 131 #define TEGRA_PIN_LCD_D21_PM5           _GPIO(101)
 132 #define TEGRA_PIN_LCD_D22_PM6           _GPIO(102)
 133 #define TEGRA_PIN_LCD_D23_PM7           _GPIO(103)
 134 #define TEGRA_PIN_DAP1_FS_PN0           _GPIO(104)
 135 #define TEGRA_PIN_DAP1_DIN_PN1          _GPIO(105)
 136 #define TEGRA_PIN_DAP1_DOUT_PN2         _GPIO(106)
 137 #define TEGRA_PIN_DAP1_SCLK_PN3         _GPIO(107)
 138 #define TEGRA_PIN_LCD_CS0_N_PN4         _GPIO(108)
 139 #define TEGRA_PIN_LCD_SDOUT_PN5         _GPIO(109)
 140 #define TEGRA_PIN_LCD_DC0_PN6           _GPIO(110)
 141 #define TEGRA_PIN_HDMI_INT_PN7          _GPIO(111)
 142 #define TEGRA_PIN_ULPI_DATA7_PO0        _GPIO(112)
 143 #define TEGRA_PIN_ULPI_DATA0_PO1        _GPIO(113)
 144 #define TEGRA_PIN_ULPI_DATA1_PO2        _GPIO(114)
 145 #define TEGRA_PIN_ULPI_DATA2_PO3        _GPIO(115)
 146 #define TEGRA_PIN_ULPI_DATA3_PO4        _GPIO(116)
 147 #define TEGRA_PIN_ULPI_DATA4_PO5        _GPIO(117)
 148 #define TEGRA_PIN_ULPI_DATA5_PO6        _GPIO(118)
 149 #define TEGRA_PIN_ULPI_DATA6_PO7        _GPIO(119)
 150 #define TEGRA_PIN_DAP3_FS_PP0           _GPIO(120)
 151 #define TEGRA_PIN_DAP3_DIN_PP1          _GPIO(121)
 152 #define TEGRA_PIN_DAP3_DOUT_PP2         _GPIO(122)
 153 #define TEGRA_PIN_DAP3_SCLK_PP3         _GPIO(123)
 154 #define TEGRA_PIN_DAP4_FS_PP4           _GPIO(124)
 155 #define TEGRA_PIN_DAP4_DIN_PP5          _GPIO(125)
 156 #define TEGRA_PIN_DAP4_DOUT_PP6         _GPIO(126)
 157 #define TEGRA_PIN_DAP4_SCLK_PP7         _GPIO(127)
 158 #define TEGRA_PIN_KB_COL0_PQ0           _GPIO(128)
 159 #define TEGRA_PIN_KB_COL1_PQ1           _GPIO(129)
 160 #define TEGRA_PIN_KB_COL2_PQ2           _GPIO(130)
 161 #define TEGRA_PIN_KB_COL3_PQ3           _GPIO(131)
 162 #define TEGRA_PIN_KB_COL4_PQ4           _GPIO(132)
 163 #define TEGRA_PIN_KB_COL5_PQ5           _GPIO(133)
 164 #define TEGRA_PIN_KB_COL6_PQ6           _GPIO(134)
 165 #define TEGRA_PIN_KB_COL7_PQ7           _GPIO(135)
 166 #define TEGRA_PIN_KB_ROW0_PR0           _GPIO(136)
 167 #define TEGRA_PIN_KB_ROW1_PR1           _GPIO(137)
 168 #define TEGRA_PIN_KB_ROW2_PR2           _GPIO(138)
 169 #define TEGRA_PIN_KB_ROW3_PR3           _GPIO(139)
 170 #define TEGRA_PIN_KB_ROW4_PR4           _GPIO(140)
 171 #define TEGRA_PIN_KB_ROW5_PR5           _GPIO(141)
 172 #define TEGRA_PIN_KB_ROW6_PR6           _GPIO(142)
 173 #define TEGRA_PIN_KB_ROW7_PR7           _GPIO(143)
 174 #define TEGRA_PIN_KB_ROW8_PS0           _GPIO(144)
 175 #define TEGRA_PIN_KB_ROW9_PS1           _GPIO(145)
 176 #define TEGRA_PIN_KB_ROW10_PS2          _GPIO(146)
 177 #define TEGRA_PIN_KB_ROW11_PS3          _GPIO(147)
 178 #define TEGRA_PIN_KB_ROW12_PS4          _GPIO(148)
 179 #define TEGRA_PIN_KB_ROW13_PS5          _GPIO(149)
 180 #define TEGRA_PIN_KB_ROW14_PS6          _GPIO(150)
 181 #define TEGRA_PIN_KB_ROW15_PS7          _GPIO(151)
 182 #define TEGRA_PIN_VI_PCLK_PT0           _GPIO(152)
 183 #define TEGRA_PIN_VI_MCLK_PT1           _GPIO(153)
 184 #define TEGRA_PIN_VI_D10_PT2            _GPIO(154)
 185 #define TEGRA_PIN_VI_D11_PT3            _GPIO(155)
 186 #define TEGRA_PIN_VI_D0_PT4             _GPIO(156)
 187 #define TEGRA_PIN_GEN2_I2C_SCL_PT5      _GPIO(157)
 188 #define TEGRA_PIN_GEN2_I2C_SDA_PT6      _GPIO(158)
 189 #define TEGRA_PIN_SDMMC4_CMD_PT7        _GPIO(159)
 190 #define TEGRA_PIN_PU0                   _GPIO(160)
 191 #define TEGRA_PIN_PU1                   _GPIO(161)
 192 #define TEGRA_PIN_PU2                   _GPIO(162)
 193 #define TEGRA_PIN_PU3                   _GPIO(163)
 194 #define TEGRA_PIN_PU4                   _GPIO(164)
 195 #define TEGRA_PIN_PU5                   _GPIO(165)
 196 #define TEGRA_PIN_PU6                   _GPIO(166)
 197 #define TEGRA_PIN_JTAG_RTCK_PU7         _GPIO(167)
 198 #define TEGRA_PIN_PV0                   _GPIO(168)
 199 #define TEGRA_PIN_PV1                   _GPIO(169)
 200 #define TEGRA_PIN_PV2                   _GPIO(170)
 201 #define TEGRA_PIN_PV3                   _GPIO(171)
 202 #define TEGRA_PIN_DDC_SCL_PV4           _GPIO(172)
 203 #define TEGRA_PIN_DDC_SDA_PV5           _GPIO(173)
 204 #define TEGRA_PIN_CRT_HSYNC_PV6         _GPIO(174)
 205 #define TEGRA_PIN_CRT_VSYNC_PV7         _GPIO(175)
 206 #define TEGRA_PIN_LCD_CS1_N_PW0         _GPIO(176)
 207 #define TEGRA_PIN_LCD_M1_PW1            _GPIO(177)
 208 #define TEGRA_PIN_SPI2_CS1_N_PW2        _GPIO(178)
 209 #define TEGRA_PIN_SPI2_CS2_N_PW3        _GPIO(179)
 210 #define TEGRA_PIN_CLK1_OUT_PW4          _GPIO(180)
 211 #define TEGRA_PIN_CLK2_OUT_PW5          _GPIO(181)
 212 #define TEGRA_PIN_UART3_TXD_PW6         _GPIO(182)
 213 #define TEGRA_PIN_UART3_RXD_PW7         _GPIO(183)
 214 #define TEGRA_PIN_SPI2_MOSI_PX0         _GPIO(184)
 215 #define TEGRA_PIN_SPI2_MISO_PX1         _GPIO(185)
 216 #define TEGRA_PIN_SPI2_SCK_PX2          _GPIO(186)
 217 #define TEGRA_PIN_SPI2_CS0_N_PX3        _GPIO(187)
 218 #define TEGRA_PIN_SPI1_MOSI_PX4         _GPIO(188)
 219 #define TEGRA_PIN_SPI1_SCK_PX5          _GPIO(189)
 220 #define TEGRA_PIN_SPI1_CS0_N_PX6        _GPIO(190)
 221 #define TEGRA_PIN_SPI1_MISO_PX7         _GPIO(191)
 222 #define TEGRA_PIN_ULPI_CLK_PY0          _GPIO(192)
 223 #define TEGRA_PIN_ULPI_DIR_PY1          _GPIO(193)
 224 #define TEGRA_PIN_ULPI_NXT_PY2          _GPIO(194)
 225 #define TEGRA_PIN_ULPI_STP_PY3          _GPIO(195)
 226 #define TEGRA_PIN_SDMMC1_DAT3_PY4       _GPIO(196)
 227 #define TEGRA_PIN_SDMMC1_DAT2_PY5       _GPIO(197)
 228 #define TEGRA_PIN_SDMMC1_DAT1_PY6       _GPIO(198)
 229 #define TEGRA_PIN_SDMMC1_DAT0_PY7       _GPIO(199)
 230 #define TEGRA_PIN_SDMMC1_CLK_PZ0        _GPIO(200)
 231 #define TEGRA_PIN_SDMMC1_CMD_PZ1        _GPIO(201)
 232 #define TEGRA_PIN_LCD_SDIN_PZ2          _GPIO(202)
 233 #define TEGRA_PIN_LCD_WR_N_PZ3          _GPIO(203)
 234 #define TEGRA_PIN_LCD_SCK_PZ4           _GPIO(204)
 235 #define TEGRA_PIN_SYS_CLK_REQ_PZ5       _GPIO(205)
 236 #define TEGRA_PIN_PWR_I2C_SCL_PZ6       _GPIO(206)
 237 #define TEGRA_PIN_PWR_I2C_SDA_PZ7       _GPIO(207)
 238 #define TEGRA_PIN_SDMMC4_DAT0_PAA0      _GPIO(208)
 239 #define TEGRA_PIN_SDMMC4_DAT1_PAA1      _GPIO(209)
 240 #define TEGRA_PIN_SDMMC4_DAT2_PAA2      _GPIO(210)
 241 #define TEGRA_PIN_SDMMC4_DAT3_PAA3      _GPIO(211)
 242 #define TEGRA_PIN_SDMMC4_DAT4_PAA4      _GPIO(212)
 243 #define TEGRA_PIN_SDMMC4_DAT5_PAA5      _GPIO(213)
 244 #define TEGRA_PIN_SDMMC4_DAT6_PAA6      _GPIO(214)
 245 #define TEGRA_PIN_SDMMC4_DAT7_PAA7      _GPIO(215)
 246 #define TEGRA_PIN_PBB0                  _GPIO(216)
 247 #define TEGRA_PIN_CAM_I2C_SCL_PBB1      _GPIO(217)
 248 #define TEGRA_PIN_CAM_I2C_SDA_PBB2      _GPIO(218)
 249 #define TEGRA_PIN_PBB3                  _GPIO(219)
 250 #define TEGRA_PIN_PBB4                  _GPIO(220)
 251 #define TEGRA_PIN_PBB5                  _GPIO(221)
 252 #define TEGRA_PIN_PBB6                  _GPIO(222)
 253 #define TEGRA_PIN_PBB7                  _GPIO(223)
 254 #define TEGRA_PIN_CAM_MCLK_PCC0         _GPIO(224)
 255 #define TEGRA_PIN_PCC1                  _GPIO(225)
 256 #define TEGRA_PIN_PCC2                  _GPIO(226)
 257 #define TEGRA_PIN_SDMMC4_RST_N_PCC3     _GPIO(227)
 258 #define TEGRA_PIN_SDMMC4_CLK_PCC4       _GPIO(228)
 259 #define TEGRA_PIN_CLK2_REQ_PCC5         _GPIO(229)
 260 #define TEGRA_PIN_PEX_L2_RST_N_PCC6     _GPIO(230)
 261 #define TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7  _GPIO(231)
 262 #define TEGRA_PIN_PEX_L0_PRSNT_N_PDD0   _GPIO(232)
 263 #define TEGRA_PIN_PEX_L0_RST_N_PDD1     _GPIO(233)
 264 #define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2  _GPIO(234)
 265 #define TEGRA_PIN_PEX_WAKE_N_PDD3       _GPIO(235)
 266 #define TEGRA_PIN_PEX_L1_PRSNT_N_PDD4   _GPIO(236)
 267 #define TEGRA_PIN_PEX_L1_RST_N_PDD5     _GPIO(237)
 268 #define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6  _GPIO(238)
 269 #define TEGRA_PIN_PEX_L2_PRSNT_N_PDD7   _GPIO(239)
 270 #define TEGRA_PIN_CLK3_OUT_PEE0         _GPIO(240)
 271 #define TEGRA_PIN_CLK3_REQ_PEE1         _GPIO(241)
 272 #define TEGRA_PIN_CLK1_REQ_PEE2         _GPIO(242)
 273 #define TEGRA_PIN_HDMI_CEC_PEE3         _GPIO(243)
 274 #define TEGRA_PIN_PEE4                  _GPIO(244)
 275 #define TEGRA_PIN_PEE5                  _GPIO(245)
 276 #define TEGRA_PIN_PEE6                  _GPIO(246)
 277 #define TEGRA_PIN_PEE7                  _GPIO(247)
 278
 279 /* All non-GPIO pins follow */
 280 #define NUM_GPIOS                               (TEGRA_PIN_PEE7 + 1)
 281 #define _PIN(offset)                            (NUM_GPIOS + (offset))
 282
 283 /* Non-GPIO pins */
 284 #define TEGRA_PIN_CLK_32K_IN            _PIN(0)
 285 #define TEGRA_PIN_CORE_PWR_REQ          _PIN(1)
 286 #define TEGRA_PIN_CPU_PWR_REQ           _PIN(2)
 287 #define TEGRA_PIN_JTAG_TCK              _PIN(3)
 288 #define TEGRA_PIN_JTAG_TDI              _PIN(4)
 289 #define TEGRA_PIN_JTAG_TDO              _PIN(5)
 290 #define TEGRA_PIN_JTAG_TMS              _PIN(6)
 291 #define TEGRA_PIN_JTAG_TRST_N           _PIN(7)
 292 #define TEGRA_PIN_OWR                   _PIN(8)
 293 #define TEGRA_PIN_PWR_INT_N             _PIN(9)
 294 #define TEGRA_PIN_SYS_RESET_N           _PIN(10)
 295 #define TEGRA_PIN_TEST_MODE_EN          _PIN(11)
 296
 297 static const struct pinctrl_pin_desc tegra30_pins[] = {
 298         PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
 299         PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
 300         PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
 301         PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
 302         PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
 303         PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
 304         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
 305         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
 306         PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
 307         PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
 308         PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
 309         PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
 310         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
 311         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
 312         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
 313         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
 314         PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
 315         PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
 316         PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
 317         PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
 318         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
 319         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
 320         PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
 321         PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
 322         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT5_PD0, "SDMMC3_DAT5 PD0"),
 323         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, "SDMMC3_DAT4 PD1"),
 324         PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, "LCD_DC1 PD2"),
 325         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, "SDMMC3_DAT6 PD3"),
 326         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, "SDMMC3_DAT7 PD4"),
 327         PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
 328         PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
 329         PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
 330         PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
 331         PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
 332         PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
 333         PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
 334         PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
 335         PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
 336         PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
 337         PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
 338         PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
 339         PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
 340         PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
 341         PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
 342         PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
 343         PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
 344         PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
 345         PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
 346         PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
 347         PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
 348         PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
 349         PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
 350         PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
 351         PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
 352         PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
 353         PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
 354         PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
 355         PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
 356         PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
 357         PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
 358         PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
 359         PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
 360         PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
 361         PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
 362         PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
 363         PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
 364         PINCTRL_PIN(TEGRA_PIN_GMI_DQS_PI2, "GMI_DQS PI2"),
 365         PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
 366         PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
 367         PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
 368         PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
 369         PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
 370         PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
 371         PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
 372         PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
 373         PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
 374         PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
 375         PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
 376         PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
 377         PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
 378         PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
 379         PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
 380         PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
 381         PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
 382         PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
 383         PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
 384         PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
 385         PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
 386         PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
 387         PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
 388         PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
 389         PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
 390         PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
 391         PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
 392         PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
 393         PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
 394         PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
 395         PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
 396         PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
 397         PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
 398         PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
 399         PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
 400         PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
 401         PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
 402         PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
 403         PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
 404         PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
 405         PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
 406         PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
 407         PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
 408         PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
 409         PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
 410         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
 411         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
 412         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
 413         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
 414         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
 415         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
 416         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
 417         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
 418         PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
 419         PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
 420         PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
 421         PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
 422         PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
 423         PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
 424         PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
 425         PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
 426         PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
 427         PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
 428         PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
 429         PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
 430         PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
 431         PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
 432         PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
 433         PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
 434         PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
 435         PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
 436         PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
 437         PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
 438         PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
 439         PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
 440         PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
 441         PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
 442         PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
 443         PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
 444         PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
 445         PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
 446         PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
 447         PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
 448         PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
 449         PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
 450         PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
 451         PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
 452         PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VI_D10 PT2"),
 453         PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
 454         PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
 455         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
 456         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
 457         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
 458         PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
 459         PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
 460         PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
 461         PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
 462         PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
 463         PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
 464         PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
 465         PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
 466         PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
 467         PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
 468         PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
 469         PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
 470         PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
 471         PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
 472         PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC_PV6, "CRT_HSYNC PV6"),
 473         PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC_PV7, "CRT_VSYNC PV7"),
 474         PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
 475         PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
 476         PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
 477         PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
 478         PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
 479         PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
 480         PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
 481         PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
 482         PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
 483         PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
 484         PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
 485         PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
 486         PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
 487         PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
 488         PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
 489         PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
 490         PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
 491         PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
 492         PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
 493         PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
 494         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
 495         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
 496         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
 497         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
 498         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
 499         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
 500         PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
 501         PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
 502         PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
 503         PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
 504         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
 505         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
 506         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
 507         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
 508         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
 509         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
 510         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
 511         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
 512         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
 513         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
 514         PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
 515         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
 516         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
 517         PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
 518         PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
 519         PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
 520         PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
 521         PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
 522         PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
 523         PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
 524         PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
 525         PINCTRL_PIN(TEGRA_PIN_SDMMC4_RST_N_PCC3, "SDMMC4_RST_N PCC3"),
 526         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
 527         PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
 528         PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PCC6, "PEX_L2_RST_N PCC6"),
 529         PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7, "PEX_L2_CLKREQ_N PCC7"),
 530         PINCTRL_PIN(TEGRA_PIN_PEX_L0_PRSNT_N_PDD0, "PEX_L0_PRSNT_N PDD0"),
 531         PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
 532         PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
 533         PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
 534         PINCTRL_PIN(TEGRA_PIN_PEX_L1_PRSNT_N_PDD4, "PEX_L1_PRSNT_N PDD4"),
 535         PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
 536         PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
 537         PINCTRL_PIN(TEGRA_PIN_PEX_L2_PRSNT_N_PDD7, "PEX_L2_PRSNT_N PDD7"),
 538         PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
 539         PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
 540         PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
 541         PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
 542         PINCTRL_PIN(TEGRA_PIN_PEE4, "PEE4"),
 543         PINCTRL_PIN(TEGRA_PIN_PEE5, "PEE5"),
 544         PINCTRL_PIN(TEGRA_PIN_PEE6, "PEE6"),
 545         PINCTRL_PIN(TEGRA_PIN_PEE7, "PEE7"),
 546         PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
 547         PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
 548         PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
 549         PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
 550         PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
 551         PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
 552         PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
 553         PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
 554         PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
 555         PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
 556         PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),
 557         PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
 558 };
 559
 560 static const unsigned clk_32k_out_pa0_pins[] = {
 561         TEGRA_PIN_CLK_32K_OUT_PA0,
 562 };
 563
 564 static const unsigned uart3_cts_n_pa1_pins[] = {
 565         TEGRA_PIN_UART3_CTS_N_PA1,
 566 };
 567
 568 static const unsigned dap2_fs_pa2_pins[] = {
 569         TEGRA_PIN_DAP2_FS_PA2,
 570 };
 571
 572 static const unsigned dap2_sclk_pa3_pins[] = {
 573         TEGRA_PIN_DAP2_SCLK_PA3,
 574 };
 575
 576 static const unsigned dap2_din_pa4_pins[] = {
 577         TEGRA_PIN_DAP2_DIN_PA4,
 578 };
 579
 580 static const unsigned dap2_dout_pa5_pins[] = {
 581         TEGRA_PIN_DAP2_DOUT_PA5,
 582 };
 583
 584 static const unsigned sdmmc3_clk_pa6_pins[] = {
 585         TEGRA_PIN_SDMMC3_CLK_PA6,
 586 };
 587
 588 static const unsigned sdmmc3_cmd_pa7_pins[] = {
 589         TEGRA_PIN_SDMMC3_CMD_PA7,
 590 };
 591
 592 static const unsigned gmi_a17_pb0_pins[] = {
 593         TEGRA_PIN_GMI_A17_PB0,
 594 };
 595
 596 static const unsigned gmi_a18_pb1_pins[] = {
 597         TEGRA_PIN_GMI_A18_PB1,
 598 };
 599
 600 static const unsigned lcd_pwr0_pb2_pins[] = {
 601         TEGRA_PIN_LCD_PWR0_PB2,
 602 };
 603
 604 static const unsigned lcd_pclk_pb3_pins[] = {
 605         TEGRA_PIN_LCD_PCLK_PB3,
 606 };
 607
 608 static const unsigned sdmmc3_dat3_pb4_pins[] = {
 609         TEGRA_PIN_SDMMC3_DAT3_PB4,
 610 };
 611
 612 static const unsigned sdmmc3_dat2_pb5_pins[] = {
 613         TEGRA_PIN_SDMMC3_DAT2_PB5,
 614 };
 615
 616 static const unsigned sdmmc3_dat1_pb6_pins[] = {
 617         TEGRA_PIN_SDMMC3_DAT1_PB6,
 618 };
 619
 620 static const unsigned sdmmc3_dat0_pb7_pins[] = {
 621         TEGRA_PIN_SDMMC3_DAT0_PB7,
 622 };
 623
 624 static const unsigned uart3_rts_n_pc0_pins[] = {
 625         TEGRA_PIN_UART3_RTS_N_PC0,
 626 };
 627
 628 static const unsigned lcd_pwr1_pc1_pins[] = {
 629         TEGRA_PIN_LCD_PWR1_PC1,
 630 };
 631
 632 static const unsigned uart2_txd_pc2_pins[] = {
 633         TEGRA_PIN_UART2_TXD_PC2,
 634 };
 635
 636 static const unsigned uart2_rxd_pc3_pins[] = {
 637         TEGRA_PIN_UART2_RXD_PC3,
 638 };
 639
 640 static const unsigned gen1_i2c_scl_pc4_pins[] = {
 641         TEGRA_PIN_GEN1_I2C_SCL_PC4,
 642 };
 643
 644 static const unsigned gen1_i2c_sda_pc5_pins[] = {
 645         TEGRA_PIN_GEN1_I2C_SDA_PC5,
 646 };
 647
 648 static const unsigned lcd_pwr2_pc6_pins[] = {
 649         TEGRA_PIN_LCD_PWR2_PC6,
 650 };
 651
 652 static const unsigned gmi_wp_n_pc7_pins[] = {
 653         TEGRA_PIN_GMI_WP_N_PC7,
 654 };
 655
 656 static const unsigned sdmmc3_dat5_pd0_pins[] = {
 657         TEGRA_PIN_SDMMC3_DAT5_PD0,
 658 };
 659
 660 static const unsigned sdmmc3_dat4_pd1_pins[] = {
 661         TEGRA_PIN_SDMMC3_DAT4_PD1,
 662 };
 663
 664 static const unsigned lcd_dc1_pd2_pins[] = {
 665         TEGRA_PIN_LCD_DC1_PD2,
 666 };
 667
 668 static const unsigned sdmmc3_dat6_pd3_pins[] = {
 669         TEGRA_PIN_SDMMC3_DAT6_PD3,
 670 };
 671
 672 static const unsigned sdmmc3_dat7_pd4_pins[] = {
 673         TEGRA_PIN_SDMMC3_DAT7_PD4,
 674 };
 675
 676 static const unsigned vi_d1_pd5_pins[] = {
 677         TEGRA_PIN_VI_D1_PD5,
 678 };
 679
 680 static const unsigned vi_vsync_pd6_pins[] = {
 681         TEGRA_PIN_VI_VSYNC_PD6,
 682 };
 683
 684 static const unsigned vi_hsync_pd7_pins[] = {
 685         TEGRA_PIN_VI_HSYNC_PD7,
 686 };
 687
 688 static const unsigned lcd_d0_pe0_pins[] = {
 689         TEGRA_PIN_LCD_D0_PE0,
 690 };
 691
 692 static const unsigned lcd_d1_pe1_pins[] = {
 693         TEGRA_PIN_LCD_D1_PE1,
 694 };
 695
 696 static const unsigned lcd_d2_pe2_pins[] = {
 697         TEGRA_PIN_LCD_D2_PE2,
 698 };
 699
 700 static const unsigned lcd_d3_pe3_pins[] = {
 701         TEGRA_PIN_LCD_D3_PE3,
 702 };
 703
 704 static const unsigned lcd_d4_pe4_pins[] = {
 705         TEGRA_PIN_LCD_D4_PE4,
 706 };
 707
 708 static const unsigned lcd_d5_pe5_pins[] = {
 709         TEGRA_PIN_LCD_D5_PE5,
 710 };
 711
 712 static const unsigned lcd_d6_pe6_pins[] = {
 713         TEGRA_PIN_LCD_D6_PE6,
 714 };
 715
 716 static const unsigned lcd_d7_pe7_pins[] = {
 717         TEGRA_PIN_LCD_D7_PE7,
 718 };
 719
 720 static const unsigned lcd_d8_pf0_pins[] = {
 721         TEGRA_PIN_LCD_D8_PF0,
 722 };
 723
 724 static const unsigned lcd_d9_pf1_pins[] = {
 725         TEGRA_PIN_LCD_D9_PF1,
 726 };
 727
 728 static const unsigned lcd_d10_pf2_pins[] = {
 729         TEGRA_PIN_LCD_D10_PF2,
 730 };
 731
 732 static const unsigned lcd_d11_pf3_pins[] = {
 733         TEGRA_PIN_LCD_D11_PF3,
 734 };
 735
 736 static const unsigned lcd_d12_pf4_pins[] = {
 737         TEGRA_PIN_LCD_D12_PF4,
 738 };
 739
 740 static const unsigned lcd_d13_pf5_pins[] = {
 741         TEGRA_PIN_LCD_D13_PF5,
 742 };
 743
 744 static const unsigned lcd_d14_pf6_pins[] = {
 745         TEGRA_PIN_LCD_D14_PF6,
 746 };
 747
 748 static const unsigned lcd_d15_pf7_pins[] = {
 749         TEGRA_PIN_LCD_D15_PF7,
 750 };
 751
 752 static const unsigned gmi_ad0_pg0_pins[] = {
 753         TEGRA_PIN_GMI_AD0_PG0,
 754 };
 755
 756 static const unsigned gmi_ad1_pg1_pins[] = {
 757         TEGRA_PIN_GMI_AD1_PG1,
 758 };
 759
 760 static const unsigned gmi_ad2_pg2_pins[] = {
 761         TEGRA_PIN_GMI_AD2_PG2,
 762 };
 763
 764 static const unsigned gmi_ad3_pg3_pins[] = {
 765         TEGRA_PIN_GMI_AD3_PG3,
 766 };
 767
 768 static const unsigned gmi_ad4_pg4_pins[] = {
 769         TEGRA_PIN_GMI_AD4_PG4,
 770 };
 771
 772 static const unsigned gmi_ad5_pg5_pins[] = {
 773         TEGRA_PIN_GMI_AD5_PG5,
 774 };
 775
 776 static const unsigned gmi_ad6_pg6_pins[] = {
 777         TEGRA_PIN_GMI_AD6_PG6,
 778 };
 779
 780 static const unsigned gmi_ad7_pg7_pins[] = {
 781         TEGRA_PIN_GMI_AD7_PG7,
 782 };
 783
 784 static const unsigned gmi_ad8_ph0_pins[] = {
 785         TEGRA_PIN_GMI_AD8_PH0,
 786 };
 787
 788 static const unsigned gmi_ad9_ph1_pins[] = {
 789         TEGRA_PIN_GMI_AD9_PH1,
 790 };
 791
 792 static const unsigned gmi_ad10_ph2_pins[] = {
 793         TEGRA_PIN_GMI_AD10_PH2,
 794 };
 795
 796 static const unsigned gmi_ad11_ph3_pins[] = {
 797         TEGRA_PIN_GMI_AD11_PH3,
 798 };
 799
 800 static const unsigned gmi_ad12_ph4_pins[] = {
 801         TEGRA_PIN_GMI_AD12_PH4,
 802 };
 803
 804 static const unsigned gmi_ad13_ph5_pins[] = {
 805         TEGRA_PIN_GMI_AD13_PH5,
 806 };
 807
 808 static const unsigned gmi_ad14_ph6_pins[] = {
 809         TEGRA_PIN_GMI_AD14_PH6,
 810 };
 811
 812 static const unsigned gmi_ad15_ph7_pins[] = {
 813         TEGRA_PIN_GMI_AD15_PH7,
 814 };
 815
 816 static const unsigned gmi_wr_n_pi0_pins[] = {
 817         TEGRA_PIN_GMI_WR_N_PI0,
 818 };
 819
 820 static const unsigned gmi_oe_n_pi1_pins[] = {
 821         TEGRA_PIN_GMI_OE_N_PI1,
 822 };
 823
 824 static const unsigned gmi_dqs_pi2_pins[] = {
 825         TEGRA_PIN_GMI_DQS_PI2,
 826 };
 827
 828 static const unsigned gmi_cs6_n_pi3_pins[] = {
 829         TEGRA_PIN_GMI_CS6_N_PI3,
 830 };
 831
 832 static const unsigned gmi_rst_n_pi4_pins[] = {
 833         TEGRA_PIN_GMI_RST_N_PI4,
 834 };
 835
 836 static const unsigned gmi_iordy_pi5_pins[] = {
 837         TEGRA_PIN_GMI_IORDY_PI5,
 838 };
 839
 840 static const unsigned gmi_cs7_n_pi6_pins[] = {
 841         TEGRA_PIN_GMI_CS7_N_PI6,
 842 };
 843
 844 static const unsigned gmi_wait_pi7_pins[] = {
 845         TEGRA_PIN_GMI_WAIT_PI7,
 846 };
 847
 848 static const unsigned gmi_cs0_n_pj0_pins[] = {
 849         TEGRA_PIN_GMI_CS0_N_PJ0,
 850 };
 851
 852 static const unsigned lcd_de_pj1_pins[] = {
 853         TEGRA_PIN_LCD_DE_PJ1,
 854 };
 855
 856 static const unsigned gmi_cs1_n_pj2_pins[] = {
 857         TEGRA_PIN_GMI_CS1_N_PJ2,
 858 };
 859
 860 static const unsigned lcd_hsync_pj3_pins[] = {
 861         TEGRA_PIN_LCD_HSYNC_PJ3,
 862 };
 863
 864 static const unsigned lcd_vsync_pj4_pins[] = {
 865         TEGRA_PIN_LCD_VSYNC_PJ4,
 866 };
 867
 868 static const unsigned uart2_cts_n_pj5_pins[] = {
 869         TEGRA_PIN_UART2_CTS_N_PJ5,
 870 };
 871
 872 static const unsigned uart2_rts_n_pj6_pins[] = {
 873         TEGRA_PIN_UART2_RTS_N_PJ6,
 874 };
 875
 876 static const unsigned gmi_a16_pj7_pins[] = {
 877         TEGRA_PIN_GMI_A16_PJ7,
 878 };
 879
 880 static const unsigned gmi_adv_n_pk0_pins[] = {
 881         TEGRA_PIN_GMI_ADV_N_PK0,
 882 };
 883
 884 static const unsigned gmi_clk_pk1_pins[] = {
 885         TEGRA_PIN_GMI_CLK_PK1,
 886 };
 887
 888 static const unsigned gmi_cs4_n_pk2_pins[] = {
 889         TEGRA_PIN_GMI_CS4_N_PK2,
 890 };
 891
 892 static const unsigned gmi_cs2_n_pk3_pins[] = {
 893         TEGRA_PIN_GMI_CS2_N_PK3,
 894 };
 895
 896 static const unsigned gmi_cs3_n_pk4_pins[] = {
 897         TEGRA_PIN_GMI_CS3_N_PK4,
 898 };
 899
 900 static const unsigned spdif_out_pk5_pins[] = {
 901         TEGRA_PIN_SPDIF_OUT_PK5,
 902 };
 903
 904 static const unsigned spdif_in_pk6_pins[] = {
 905         TEGRA_PIN_SPDIF_IN_PK6,
 906 };
 907
 908 static const unsigned gmi_a19_pk7_pins[] = {
 909         TEGRA_PIN_GMI_A19_PK7,
 910 };
 911
 912 static const unsigned vi_d2_pl0_pins[] = {
 913         TEGRA_PIN_VI_D2_PL0,
 914 };
 915
 916 static const unsigned vi_d3_pl1_pins[] = {
 917         TEGRA_PIN_VI_D3_PL1,
 918 };
 919
 920 static const unsigned vi_d4_pl2_pins[] = {
 921         TEGRA_PIN_VI_D4_PL2,
 922 };
 923
 924 static const unsigned vi_d5_pl3_pins[] = {
 925         TEGRA_PIN_VI_D5_PL3,
 926 };
 927
 928 static const unsigned vi_d6_pl4_pins[] = {
 929         TEGRA_PIN_VI_D6_PL4,
 930 };
 931
 932 static const unsigned vi_d7_pl5_pins[] = {
 933         TEGRA_PIN_VI_D7_PL5,
 934 };
 935
 936 static const unsigned vi_d8_pl6_pins[] = {
 937         TEGRA_PIN_VI_D8_PL6,
 938 };
 939
 940 static const unsigned vi_d9_pl7_pins[] = {
 941         TEGRA_PIN_VI_D9_PL7,
 942 };
 943
 944 static const unsigned lcd_d16_pm0_pins[] = {
 945         TEGRA_PIN_LCD_D16_PM0,
 946 };
 947
 948 static const unsigned lcd_d17_pm1_pins[] = {
 949         TEGRA_PIN_LCD_D17_PM1,
 950 };
 951
 952 static const unsigned lcd_d18_pm2_pins[] = {
 953         TEGRA_PIN_LCD_D18_PM2,
 954 };
 955
 956 static const unsigned lcd_d19_pm3_pins[] = {
 957         TEGRA_PIN_LCD_D19_PM3,
 958 };
 959
 960 static const unsigned lcd_d20_pm4_pins[] = {
 961         TEGRA_PIN_LCD_D20_PM4,
 962 };
 963
 964 static const unsigned lcd_d21_pm5_pins[] = {
 965         TEGRA_PIN_LCD_D21_PM5,
 966 };
 967
 968 static const unsigned lcd_d22_pm6_pins[] = {
 969         TEGRA_PIN_LCD_D22_PM6,
 970 };
 971
 972 static const unsigned lcd_d23_pm7_pins[] = {
 973         TEGRA_PIN_LCD_D23_PM7,
 974 };
 975
 976 static const unsigned dap1_fs_pn0_pins[] = {
 977         TEGRA_PIN_DAP1_FS_PN0,
 978 };
 979
 980 static const unsigned dap1_din_pn1_pins[] = {
 981         TEGRA_PIN_DAP1_DIN_PN1,
 982 };
 983
 984 static const unsigned dap1_dout_pn2_pins[] = {
 985         TEGRA_PIN_DAP1_DOUT_PN2,
 986 };
 987
 988 static const unsigned dap1_sclk_pn3_pins[] = {
 989         TEGRA_PIN_DAP1_SCLK_PN3,
 990 };
 991
 992 static const unsigned lcd_cs0_n_pn4_pins[] = {
 993         TEGRA_PIN_LCD_CS0_N_PN4,
 994 };
 995
 996 static const unsigned lcd_sdout_pn5_pins[] = {
 997         TEGRA_PIN_LCD_SDOUT_PN5,
 998 };
 999
1000 static const unsigned lcd_dc0_pn6_pins[] = {
1001         TEGRA_PIN_LCD_DC0_PN6,
1002 };
1003
1004 static const unsigned hdmi_int_pn7_pins[] = {
1005         TEGRA_PIN_HDMI_INT_PN7,
1006 };
1007
1008 static const unsigned ulpi_data7_po0_pins[] = {
1009         TEGRA_PIN_ULPI_DATA7_PO0,
1010 };
1011
1012 static const unsigned ulpi_data0_po1_pins[] = {
1013         TEGRA_PIN_ULPI_DATA0_PO1,
1014 };
1015
1016 static const unsigned ulpi_data1_po2_pins[] = {
1017         TEGRA_PIN_ULPI_DATA1_PO2,
1018 };
1019
1020 static const unsigned ulpi_data2_po3_pins[] = {
1021         TEGRA_PIN_ULPI_DATA2_PO3,
1022 };
1023
1024 static const unsigned ulpi_data3_po4_pins[] = {
1025         TEGRA_PIN_ULPI_DATA3_PO4,
1026 };
1027
1028 static const unsigned ulpi_data4_po5_pins[] = {
1029         TEGRA_PIN_ULPI_DATA4_PO5,
1030 };
1031
1032 static const unsigned ulpi_data5_po6_pins[] = {
1033         TEGRA_PIN_ULPI_DATA5_PO6,
1034 };
1035
1036 static const unsigned ulpi_data6_po7_pins[] = {
1037         TEGRA_PIN_ULPI_DATA6_PO7,
1038 };
1039
1040 static const unsigned dap3_fs_pp0_pins[] = {
1041         TEGRA_PIN_DAP3_FS_PP0,
1042 };
1043
1044 static const unsigned dap3_din_pp1_pins[] = {
1045         TEGRA_PIN_DAP3_DIN_PP1,
1046 };
1047
1048 static const unsigned dap3_dout_pp2_pins[] = {
1049         TEGRA_PIN_DAP3_DOUT_PP2,
1050 };
1051
1052 static const unsigned dap3_sclk_pp3_pins[] = {
1053         TEGRA_PIN_DAP3_SCLK_PP3,
1054 };
1055
1056 static const unsigned dap4_fs_pp4_pins[] = {
1057         TEGRA_PIN_DAP4_FS_PP4,
1058 };
1059
1060 static const unsigned dap4_din_pp5_pins[] = {
1061         TEGRA_PIN_DAP4_DIN_PP5,
1062 };
1063
1064 static const unsigned dap4_dout_pp6_pins[] = {
1065         TEGRA_PIN_DAP4_DOUT_PP6,
1066 };
1067
1068 static const unsigned dap4_sclk_pp7_pins[] = {
1069         TEGRA_PIN_DAP4_SCLK_PP7,
1070 };
1071
1072 static const unsigned kb_col0_pq0_pins[] = {
1073         TEGRA_PIN_KB_COL0_PQ0,
1074 };
1075
1076 static const unsigned kb_col1_pq1_pins[] = {
1077         TEGRA_PIN_KB_COL1_PQ1,
1078 };
1079
1080 static const unsigned kb_col2_pq2_pins[] = {
1081         TEGRA_PIN_KB_COL2_PQ2,
1082 };
1083
1084 static const unsigned kb_col3_pq3_pins[] = {
1085         TEGRA_PIN_KB_COL3_PQ3,
1086 };
1087
1088 static const unsigned kb_col4_pq4_pins[] = {
1089         TEGRA_PIN_KB_COL4_PQ4,
1090 };
1091
1092 static const unsigned kb_col5_pq5_pins[] = {
1093         TEGRA_PIN_KB_COL5_PQ5,
1094 };
1095
1096 static const unsigned kb_col6_pq6_pins[] = {
1097         TEGRA_PIN_KB_COL6_PQ6,
1098 };
1099
1100 static const unsigned kb_col7_pq7_pins[] = {
1101         TEGRA_PIN_KB_COL7_PQ7,
1102 };
1103
1104 static const unsigned kb_row0_pr0_pins[] = {
1105         TEGRA_PIN_KB_ROW0_PR0,
1106 };
1107
1108 static const unsigned kb_row1_pr1_pins[] = {
1109         TEGRA_PIN_KB_ROW1_PR1,
1110 };
1111
1112 static const unsigned kb_row2_pr2_pins[] = {
1113         TEGRA_PIN_KB_ROW2_PR2,
1114 };
1115
1116 static const unsigned kb_row3_pr3_pins[] = {
1117         TEGRA_PIN_KB_ROW3_PR3,
1118 };
1119
1120 static const unsigned kb_row4_pr4_pins[] = {
1121         TEGRA_PIN_KB_ROW4_PR4,
1122 };
1123
1124 static const unsigned kb_row5_pr5_pins[] = {
1125         TEGRA_PIN_KB_ROW5_PR5,
1126 };
1127
1128 static const unsigned kb_row6_pr6_pins[] = {
1129         TEGRA_PIN_KB_ROW6_PR6,
1130 };
1131
1132 static const unsigned kb_row7_pr7_pins[] = {
1133         TEGRA_PIN_KB_ROW7_PR7,
1134 };
1135
1136 static const unsigned kb_row8_ps0_pins[] = {
1137         TEGRA_PIN_KB_ROW8_PS0,
1138 };
1139
1140 static const unsigned kb_row9_ps1_pins[] = {
1141         TEGRA_PIN_KB_ROW9_PS1,
1142 };
1143
1144 static const unsigned kb_row10_ps2_pins[] = {
1145         TEGRA_PIN_KB_ROW10_PS2,
1146 };
1147
1148 static const unsigned kb_row11_ps3_pins[] = {
1149         TEGRA_PIN_KB_ROW11_PS3,
1150 };
1151
1152 static const unsigned kb_row12_ps4_pins[] = {
1153         TEGRA_PIN_KB_ROW12_PS4,
1154 };
1155
1156 static const unsigned kb_row13_ps5_pins[] = {
1157         TEGRA_PIN_KB_ROW13_PS5,
1158 };
1159
1160 static const unsigned kb_row14_ps6_pins[] = {
1161         TEGRA_PIN_KB_ROW14_PS6,
1162 };
1163
1164 static const unsigned kb_row15_ps7_pins[] = {
1165         TEGRA_PIN_KB_ROW15_PS7,
1166 };
1167
1168 static const unsigned vi_pclk_pt0_pins[] = {
1169         TEGRA_PIN_VI_PCLK_PT0,
1170 };
1171
1172 static const unsigned vi_mclk_pt1_pins[] = {
1173         TEGRA_PIN_VI_MCLK_PT1,
1174 };
1175
1176 static const unsigned vi_d10_pt2_pins[] = {
1177         TEGRA_PIN_VI_D10_PT2,
1178 };
1179
1180 static const unsigned vi_d11_pt3_pins[] = {
1181         TEGRA_PIN_VI_D11_PT3,
1182 };
1183
1184 static const unsigned vi_d0_pt4_pins[] = {
1185         TEGRA_PIN_VI_D0_PT4,
1186 };
1187
1188 static const unsigned gen2_i2c_scl_pt5_pins[] = {
1189         TEGRA_PIN_GEN2_I2C_SCL_PT5,
1190 };
1191
1192 static const unsigned gen2_i2c_sda_pt6_pins[] = {
1193         TEGRA_PIN_GEN2_I2C_SDA_PT6,
1194 };
1195
1196 static const unsigned sdmmc4_cmd_pt7_pins[] = {
1197         TEGRA_PIN_SDMMC4_CMD_PT7,
1198 };
1199
1200 static const unsigned pu0_pins[] = {
1201         TEGRA_PIN_PU0,
1202 };
1203
1204 static const unsigned pu1_pins[] = {
1205         TEGRA_PIN_PU1,
1206 };
1207
1208 static const unsigned pu2_pins[] = {
1209         TEGRA_PIN_PU2,
1210 };
1211
1212 static const unsigned pu3_pins[] = {
1213         TEGRA_PIN_PU3,
1214 };
1215
1216 static const unsigned pu4_pins[] = {
1217         TEGRA_PIN_PU4,
1218 };
1219
1220 static const unsigned pu5_pins[] = {
1221         TEGRA_PIN_PU5,
1222 };
1223
1224 static const unsigned pu6_pins[] = {
1225         TEGRA_PIN_PU6,
1226 };
1227
1228 static const unsigned jtag_rtck_pu7_pins[] = {
1229         TEGRA_PIN_JTAG_RTCK_PU7,
1230 };
1231
1232 static const unsigned pv0_pins[] = {
1233         TEGRA_PIN_PV0,
1234 };
1235
1236 static const unsigned pv1_pins[] = {
1237         TEGRA_PIN_PV1,
1238 };
1239
1240 static const unsigned pv2_pins[] = {
1241         TEGRA_PIN_PV2,
1242 };
1243
1244 static const unsigned pv3_pins[] = {
1245         TEGRA_PIN_PV3,
1246 };
1247
1248 static const unsigned ddc_scl_pv4_pins[] = {
1249         TEGRA_PIN_DDC_SCL_PV4,
1250 };
1251
1252 static const unsigned ddc_sda_pv5_pins[] = {
1253         TEGRA_PIN_DDC_SDA_PV5,
1254 };
1255
1256 static const unsigned crt_hsync_pv6_pins[] = {
1257         TEGRA_PIN_CRT_HSYNC_PV6,
1258 };
1259
1260 static const unsigned crt_vsync_pv7_pins[] = {
1261         TEGRA_PIN_CRT_VSYNC_PV7,
1262 };
1263
1264 static const unsigned lcd_cs1_n_pw0_pins[] = {
1265         TEGRA_PIN_LCD_CS1_N_PW0,
1266 };
1267
1268 static const unsigned lcd_m1_pw1_pins[] = {
1269         TEGRA_PIN_LCD_M1_PW1,
1270 };
1271
1272 static const unsigned spi2_cs1_n_pw2_pins[] = {
1273         TEGRA_PIN_SPI2_CS1_N_PW2,
1274 };
1275
1276 static const unsigned spi2_cs2_n_pw3_pins[] = {
1277         TEGRA_PIN_SPI2_CS2_N_PW3,
1278 };
1279
1280 static const unsigned clk1_out_pw4_pins[] = {
1281         TEGRA_PIN_CLK1_OUT_PW4,
1282 };
1283
1284 static const unsigned clk2_out_pw5_pins[] = {
1285         TEGRA_PIN_CLK2_OUT_PW5,
1286 };
1287
1288 static const unsigned uart3_txd_pw6_pins[] = {
1289         TEGRA_PIN_UART3_TXD_PW6,
1290 };
1291
1292 static const unsigned uart3_rxd_pw7_pins[] = {
1293         TEGRA_PIN_UART3_RXD_PW7,
1294 };
1295
1296 static const unsigned spi2_mosi_px0_pins[] = {
1297         TEGRA_PIN_SPI2_MOSI_PX0,
1298 };
1299
1300 static const unsigned spi2_miso_px1_pins[] = {
1301         TEGRA_PIN_SPI2_MISO_PX1,
1302 };
1303
1304 static const unsigned spi2_sck_px2_pins[] = {
1305         TEGRA_PIN_SPI2_SCK_PX2,
1306 };
1307
1308 static const unsigned spi2_cs0_n_px3_pins[] = {
1309         TEGRA_PIN_SPI2_CS0_N_PX3,
1310 };
1311
1312 static const unsigned spi1_mosi_px4_pins[] = {
1313         TEGRA_PIN_SPI1_MOSI_PX4,
1314 };
1315
1316 static const unsigned spi1_sck_px5_pins[] = {
1317         TEGRA_PIN_SPI1_SCK_PX5,
1318 };
1319
1320 static const unsigned spi1_cs0_n_px6_pins[] = {
1321         TEGRA_PIN_SPI1_CS0_N_PX6,
1322 };
1323
1324 static const unsigned spi1_miso_px7_pins[] = {
1325         TEGRA_PIN_SPI1_MISO_PX7,
1326 };
1327
1328 static const unsigned ulpi_clk_py0_pins[] = {
1329         TEGRA_PIN_ULPI_CLK_PY0,
1330 };
1331
1332 static const unsigned ulpi_dir_py1_pins[] = {
1333         TEGRA_PIN_ULPI_DIR_PY1,
1334 };
1335
1336 static const unsigned ulpi_nxt_py2_pins[] = {
1337         TEGRA_PIN_ULPI_NXT_PY2,
1338 };
1339
1340 static const unsigned ulpi_stp_py3_pins[] = {
1341         TEGRA_PIN_ULPI_STP_PY3,
1342 };
1343
1344 static const unsigned sdmmc1_dat3_py4_pins[] = {
1345         TEGRA_PIN_SDMMC1_DAT3_PY4,
1346 };
1347
1348 static const unsigned sdmmc1_dat2_py5_pins[] = {
1349         TEGRA_PIN_SDMMC1_DAT2_PY5,
1350 };
1351
1352 static const unsigned sdmmc1_dat1_py6_pins[] = {
1353         TEGRA_PIN_SDMMC1_DAT1_PY6,
1354 };
1355
1356 static const unsigned sdmmc1_dat0_py7_pins[] = {
1357         TEGRA_PIN_SDMMC1_DAT0_PY7,
1358 };
1359
1360 static const unsigned sdmmc1_clk_pz0_pins[] = {
1361         TEGRA_PIN_SDMMC1_CLK_PZ0,
1362 };
1363
1364 static const unsigned sdmmc1_cmd_pz1_pins[] = {
1365         TEGRA_PIN_SDMMC1_CMD_PZ1,
1366 };
1367
1368 static const unsigned lcd_sdin_pz2_pins[] = {
1369         TEGRA_PIN_LCD_SDIN_PZ2,
1370 };
1371
1372 static const unsigned lcd_wr_n_pz3_pins[] = {
1373         TEGRA_PIN_LCD_WR_N_PZ3,
1374 };
1375
1376 static const unsigned lcd_sck_pz4_pins[] = {
1377         TEGRA_PIN_LCD_SCK_PZ4,
1378 };
1379
1380 static const unsigned sys_clk_req_pz5_pins[] = {
1381         TEGRA_PIN_SYS_CLK_REQ_PZ5,
1382 };
1383
1384 static const unsigned pwr_i2c_scl_pz6_pins[] = {
1385         TEGRA_PIN_PWR_I2C_SCL_PZ6,
1386 };
1387
1388 static const unsigned pwr_i2c_sda_pz7_pins[] = {
1389         TEGRA_PIN_PWR_I2C_SDA_PZ7,
1390 };
1391
1392 static const unsigned sdmmc4_dat0_paa0_pins[] = {
1393         TEGRA_PIN_SDMMC4_DAT0_PAA0,
1394 };
1395
1396 static const unsigned sdmmc4_dat1_paa1_pins[] = {
1397         TEGRA_PIN_SDMMC4_DAT1_PAA1,
1398 };
1399
1400 static const unsigned sdmmc4_dat2_paa2_pins[] = {
1401         TEGRA_PIN_SDMMC4_DAT2_PAA2,
1402 };
1403
1404 static const unsigned sdmmc4_dat3_paa3_pins[] = {
1405         TEGRA_PIN_SDMMC4_DAT3_PAA3,
1406 };
1407
1408 static const unsigned sdmmc4_dat4_paa4_pins[] = {
1409         TEGRA_PIN_SDMMC4_DAT4_PAA4,
1410 };
1411
1412 static const unsigned sdmmc4_dat5_paa5_pins[] = {
1413         TEGRA_PIN_SDMMC4_DAT5_PAA5,
1414 };
1415
1416 static const unsigned sdmmc4_dat6_paa6_pins[] = {
1417         TEGRA_PIN_SDMMC4_DAT6_PAA6,
1418 };
1419
1420 static const unsigned sdmmc4_dat7_paa7_pins[] = {
1421         TEGRA_PIN_SDMMC4_DAT7_PAA7,
1422 };
1423
1424 static const unsigned pbb0_pins[] = {
1425         TEGRA_PIN_PBB0,
1426 };
1427
1428 static const unsigned cam_i2c_scl_pbb1_pins[] = {
1429         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1430 };
1431
1432 static const unsigned cam_i2c_sda_pbb2_pins[] = {
1433         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1434 };
1435
1436 static const unsigned pbb3_pins[] = {
1437         TEGRA_PIN_PBB3,
1438 };
1439
1440 static const unsigned pbb4_pins[] = {
1441         TEGRA_PIN_PBB4,
1442 };
1443
1444 static const unsigned pbb5_pins[] = {
1445         TEGRA_PIN_PBB5,
1446 };
1447
1448 static const unsigned pbb6_pins[] = {
1449         TEGRA_PIN_PBB6,
1450 };
1451
1452 static const unsigned pbb7_pins[] = {
1453         TEGRA_PIN_PBB7,
1454 };
1455
1456 static const unsigned cam_mclk_pcc0_pins[] = {
1457         TEGRA_PIN_CAM_MCLK_PCC0,
1458 };
1459
1460 static const unsigned pcc1_pins[] = {
1461         TEGRA_PIN_PCC1,
1462 };
1463
1464 static const unsigned pcc2_pins[] = {
1465         TEGRA_PIN_PCC2,
1466 };
1467
1468 static const unsigned sdmmc4_rst_n_pcc3_pins[] = {
1469         TEGRA_PIN_SDMMC4_RST_N_PCC3,
1470 };
1471
1472 static const unsigned sdmmc4_clk_pcc4_pins[] = {
1473         TEGRA_PIN_SDMMC4_CLK_PCC4,
1474 };
1475
1476 static const unsigned clk2_req_pcc5_pins[] = {
1477         TEGRA_PIN_CLK2_REQ_PCC5,
1478 };
1479
1480 static const unsigned pex_l2_rst_n_pcc6_pins[] = {
1481         TEGRA_PIN_PEX_L2_RST_N_PCC6,
1482 };
1483
1484 static const unsigned pex_l2_clkreq_n_pcc7_pins[] = {
1485         TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7,
1486 };
1487
1488 static const unsigned pex_l0_prsnt_n_pdd0_pins[] = {
1489         TEGRA_PIN_PEX_L0_PRSNT_N_PDD0,
1490 };
1491
1492 static const unsigned pex_l0_rst_n_pdd1_pins[] = {
1493         TEGRA_PIN_PEX_L0_RST_N_PDD1,
1494 };
1495
1496 static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
1497         TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1498 };
1499
1500 static const unsigned pex_wake_n_pdd3_pins[] = {
1501         TEGRA_PIN_PEX_WAKE_N_PDD3,
1502 };
1503
1504 static const unsigned pex_l1_prsnt_n_pdd4_pins[] = {
1505         TEGRA_PIN_PEX_L1_PRSNT_N_PDD4,
1506 };
1507
1508 static const unsigned pex_l1_rst_n_pdd5_pins[] = {
1509         TEGRA_PIN_PEX_L1_RST_N_PDD5,
1510 };
1511
1512 static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
1513         TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1514 };
1515
1516 static const unsigned pex_l2_prsnt_n_pdd7_pins[] = {
1517         TEGRA_PIN_PEX_L2_PRSNT_N_PDD7,
1518 };
1519
1520 static const unsigned clk3_out_pee0_pins[] = {
1521         TEGRA_PIN_CLK3_OUT_PEE0,
1522 };
1523
1524 static const unsigned clk3_req_pee1_pins[] = {
1525         TEGRA_PIN_CLK3_REQ_PEE1,
1526 };
1527
1528 static const unsigned clk1_req_pee2_pins[] = {
1529         TEGRA_PIN_CLK1_REQ_PEE2,
1530 };
1531
1532 static const unsigned hdmi_cec_pee3_pins[] = {
1533         TEGRA_PIN_HDMI_CEC_PEE3,
1534 };
1535
1536 static const unsigned clk_32k_in_pins[] = {
1537         TEGRA_PIN_CLK_32K_IN,
1538 };
1539
1540 static const unsigned core_pwr_req_pins[] = {
1541         TEGRA_PIN_CORE_PWR_REQ,
1542 };
1543
1544 static const unsigned cpu_pwr_req_pins[] = {
1545         TEGRA_PIN_CPU_PWR_REQ,
1546 };
1547
1548 static const unsigned owr_pins[] = {
1549         TEGRA_PIN_OWR,
1550 };
1551
1552 static const unsigned pwr_int_n_pins[] = {
1553         TEGRA_PIN_PWR_INT_N,
1554 };
1555
1556 static const unsigned drive_ao1_pins[] = {
1557         TEGRA_PIN_KB_ROW0_PR0,
1558         TEGRA_PIN_KB_ROW1_PR1,
1559         TEGRA_PIN_KB_ROW2_PR2,
1560         TEGRA_PIN_KB_ROW3_PR3,
1561         TEGRA_PIN_KB_ROW4_PR4,
1562         TEGRA_PIN_KB_ROW5_PR5,
1563         TEGRA_PIN_KB_ROW6_PR6,
1564         TEGRA_PIN_KB_ROW7_PR7,
1565         TEGRA_PIN_PWR_I2C_SCL_PZ6,
1566         TEGRA_PIN_PWR_I2C_SDA_PZ7,
1567         TEGRA_PIN_SYS_RESET_N,
1568 };
1569
1570 static const unsigned drive_ao2_pins[] = {
1571         TEGRA_PIN_CLK_32K_OUT_PA0,
1572         TEGRA_PIN_KB_COL0_PQ0,
1573         TEGRA_PIN_KB_COL1_PQ1,
1574         TEGRA_PIN_KB_COL2_PQ2,
1575         TEGRA_PIN_KB_COL3_PQ3,
1576         TEGRA_PIN_KB_COL4_PQ4,
1577         TEGRA_PIN_KB_COL5_PQ5,
1578         TEGRA_PIN_KB_COL6_PQ6,
1579         TEGRA_PIN_KB_COL7_PQ7,
1580         TEGRA_PIN_KB_ROW8_PS0,
1581         TEGRA_PIN_KB_ROW9_PS1,
1582         TEGRA_PIN_KB_ROW10_PS2,
1583         TEGRA_PIN_KB_ROW11_PS3,
1584         TEGRA_PIN_KB_ROW12_PS4,
1585         TEGRA_PIN_KB_ROW13_PS5,
1586         TEGRA_PIN_KB_ROW14_PS6,
1587         TEGRA_PIN_KB_ROW15_PS7,
1588         TEGRA_PIN_SYS_CLK_REQ_PZ5,
1589         TEGRA_PIN_CLK_32K_IN,
1590         TEGRA_PIN_CORE_PWR_REQ,
1591         TEGRA_PIN_CPU_PWR_REQ,
1592         TEGRA_PIN_PWR_INT_N,
1593 };
1594
1595 static const unsigned drive_at1_pins[] = {
1596         TEGRA_PIN_GMI_AD8_PH0,
1597         TEGRA_PIN_GMI_AD9_PH1,
1598         TEGRA_PIN_GMI_AD10_PH2,
1599         TEGRA_PIN_GMI_AD11_PH3,
1600         TEGRA_PIN_GMI_AD12_PH4,
1601         TEGRA_PIN_GMI_AD13_PH5,
1602         TEGRA_PIN_GMI_AD14_PH6,
1603         TEGRA_PIN_GMI_AD15_PH7,
1604         TEGRA_PIN_GMI_IORDY_PI5,
1605         TEGRA_PIN_GMI_CS7_N_PI6,
1606 };
1607
1608 static const unsigned drive_at2_pins[] = {
1609         TEGRA_PIN_GMI_AD0_PG0,
1610         TEGRA_PIN_GMI_AD1_PG1,
1611         TEGRA_PIN_GMI_AD2_PG2,
1612         TEGRA_PIN_GMI_AD3_PG3,
1613         TEGRA_PIN_GMI_AD4_PG4,
1614         TEGRA_PIN_GMI_AD5_PG5,
1615         TEGRA_PIN_GMI_AD6_PG6,
1616         TEGRA_PIN_GMI_AD7_PG7,
1617         TEGRA_PIN_GMI_WR_N_PI0,
1618         TEGRA_PIN_GMI_OE_N_PI1,
1619         TEGRA_PIN_GMI_DQS_PI2,
1620         TEGRA_PIN_GMI_CS6_N_PI3,
1621         TEGRA_PIN_GMI_RST_N_PI4,
1622         TEGRA_PIN_GMI_WAIT_PI7,
1623         TEGRA_PIN_GMI_ADV_N_PK0,
1624         TEGRA_PIN_GMI_CLK_PK1,
1625         TEGRA_PIN_GMI_CS4_N_PK2,
1626         TEGRA_PIN_GMI_CS2_N_PK3,
1627         TEGRA_PIN_GMI_CS3_N_PK4,
1628 };
1629
1630 static const unsigned drive_at3_pins[] = {
1631         TEGRA_PIN_GMI_WP_N_PC7,
1632         TEGRA_PIN_GMI_CS0_N_PJ0,
1633 };
1634
1635 static const unsigned drive_at4_pins[] = {
1636         TEGRA_PIN_GMI_A17_PB0,
1637         TEGRA_PIN_GMI_A18_PB1,
1638         TEGRA_PIN_GMI_CS1_N_PJ2,
1639         TEGRA_PIN_GMI_A16_PJ7,
1640         TEGRA_PIN_GMI_A19_PK7,
1641 };
1642
1643 static const unsigned drive_at5_pins[] = {
1644         TEGRA_PIN_GEN2_I2C_SCL_PT5,
1645         TEGRA_PIN_GEN2_I2C_SDA_PT6,
1646 };
1647
1648 static const unsigned drive_cdev1_pins[] = {
1649         TEGRA_PIN_CLK1_OUT_PW4,
1650         TEGRA_PIN_CLK1_REQ_PEE2,
1651 };
1652
1653 static const unsigned drive_cdev2_pins[] = {
1654         TEGRA_PIN_CLK2_OUT_PW5,
1655         TEGRA_PIN_CLK2_REQ_PCC5,
1656 };
1657
1658 static const unsigned drive_cec_pins[] = {
1659         TEGRA_PIN_HDMI_CEC_PEE3,
1660 };
1661
1662 static const unsigned drive_crt_pins[] = {
1663         TEGRA_PIN_CRT_HSYNC_PV6,
1664         TEGRA_PIN_CRT_VSYNC_PV7,
1665 };
1666
1667 static const unsigned drive_csus_pins[] = {
1668         TEGRA_PIN_VI_MCLK_PT1,
1669 };
1670
1671 static const unsigned drive_dap1_pins[] = {
1672         TEGRA_PIN_SPDIF_OUT_PK5,
1673         TEGRA_PIN_SPDIF_IN_PK6,
1674         TEGRA_PIN_DAP1_FS_PN0,
1675         TEGRA_PIN_DAP1_DIN_PN1,
1676         TEGRA_PIN_DAP1_DOUT_PN2,
1677         TEGRA_PIN_DAP1_SCLK_PN3,
1678 };
1679
1680 static const unsigned drive_dap2_pins[] = {
1681         TEGRA_PIN_DAP2_FS_PA2,
1682         TEGRA_PIN_DAP2_SCLK_PA3,
1683         TEGRA_PIN_DAP2_DIN_PA4,
1684         TEGRA_PIN_DAP2_DOUT_PA5,
1685 };
1686
1687 static const unsigned drive_dap3_pins[] = {
1688         TEGRA_PIN_DAP3_FS_PP0,
1689         TEGRA_PIN_DAP3_DIN_PP1,
1690         TEGRA_PIN_DAP3_DOUT_PP2,
1691         TEGRA_PIN_DAP3_SCLK_PP3,
1692 };
1693
1694 static const unsigned drive_dap4_pins[] = {
1695         TEGRA_PIN_DAP4_FS_PP4,
1696         TEGRA_PIN_DAP4_DIN_PP5,
1697         TEGRA_PIN_DAP4_DOUT_PP6,
1698         TEGRA_PIN_DAP4_SCLK_PP7,
1699 };
1700
1701 static const unsigned drive_dbg_pins[] = {
1702         TEGRA_PIN_GEN1_I2C_SCL_PC4,
1703         TEGRA_PIN_GEN1_I2C_SDA_PC5,
1704         TEGRA_PIN_PU0,
1705         TEGRA_PIN_PU1,
1706         TEGRA_PIN_PU2,
1707         TEGRA_PIN_PU3,
1708         TEGRA_PIN_PU4,
1709         TEGRA_PIN_PU5,
1710         TEGRA_PIN_PU6,
1711         TEGRA_PIN_JTAG_RTCK_PU7,
1712         TEGRA_PIN_JTAG_TCK,
1713         TEGRA_PIN_JTAG_TDI,
1714         TEGRA_PIN_JTAG_TDO,
1715         TEGRA_PIN_JTAG_TMS,
1716         TEGRA_PIN_JTAG_TRST_N,
1717         TEGRA_PIN_TEST_MODE_EN,
1718 };
1719
1720 static const unsigned drive_ddc_pins[] = {
1721         TEGRA_PIN_DDC_SCL_PV4,
1722         TEGRA_PIN_DDC_SDA_PV5,
1723 };
1724
1725 static const unsigned drive_dev3_pins[] = {
1726         TEGRA_PIN_CLK3_OUT_PEE0,
1727         TEGRA_PIN_CLK3_REQ_PEE1,
1728 };
1729
1730 static const unsigned drive_gma_pins[] = {
1731         TEGRA_PIN_SDMMC4_DAT0_PAA0,
1732         TEGRA_PIN_SDMMC4_DAT1_PAA1,
1733         TEGRA_PIN_SDMMC4_DAT2_PAA2,
1734         TEGRA_PIN_SDMMC4_DAT3_PAA3,
1735         TEGRA_PIN_SDMMC4_RST_N_PCC3,
1736 };
1737
1738 static const unsigned drive_gmb_pins[] = {
1739         TEGRA_PIN_SDMMC4_DAT4_PAA4,
1740         TEGRA_PIN_SDMMC4_DAT5_PAA5,
1741         TEGRA_PIN_SDMMC4_DAT6_PAA6,
1742         TEGRA_PIN_SDMMC4_DAT7_PAA7,
1743 };
1744
1745 static const unsigned drive_gmc_pins[] = {
1746         TEGRA_PIN_SDMMC4_CLK_PCC4,
1747 };
1748
1749 static const unsigned drive_gmd_pins[] = {
1750         TEGRA_PIN_SDMMC4_CMD_PT7,
1751 };
1752
1753 static const unsigned drive_gme_pins[] = {
1754         TEGRA_PIN_PBB0,
1755         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1756         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1757         TEGRA_PIN_PBB3,
1758         TEGRA_PIN_PCC2,
1759 };
1760
1761 static const unsigned drive_gmf_pins[] = {
1762         TEGRA_PIN_PBB4,
1763         TEGRA_PIN_PBB5,
1764         TEGRA_PIN_PBB6,
1765         TEGRA_PIN_PBB7,
1766 };
1767
1768 static const unsigned drive_gmg_pins[] = {
1769         TEGRA_PIN_CAM_MCLK_PCC0,
1770 };
1771
1772 static const unsigned drive_gmh_pins[] = {
1773         TEGRA_PIN_PCC1,
1774 };
1775
1776 static const unsigned drive_gpv_pins[] = {
1777         TEGRA_PIN_PEX_L2_RST_N_PCC6,
1778         TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7,
1779         TEGRA_PIN_PEX_L0_PRSNT_N_PDD0,
1780         TEGRA_PIN_PEX_L0_RST_N_PDD1,
1781         TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1782         TEGRA_PIN_PEX_WAKE_N_PDD3,
1783         TEGRA_PIN_PEX_L1_PRSNT_N_PDD4,
1784         TEGRA_PIN_PEX_L1_RST_N_PDD5,
1785         TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1786         TEGRA_PIN_PEX_L2_PRSNT_N_PDD7,
1787 };
1788
1789 static const unsigned drive_lcd1_pins[] = {
1790         TEGRA_PIN_LCD_PWR1_PC1,
1791         TEGRA_PIN_LCD_PWR2_PC6,
1792         TEGRA_PIN_LCD_CS0_N_PN4,
1793         TEGRA_PIN_LCD_SDOUT_PN5,
1794         TEGRA_PIN_LCD_DC0_PN6,
1795         TEGRA_PIN_LCD_SDIN_PZ2,
1796         TEGRA_PIN_LCD_WR_N_PZ3,
1797         TEGRA_PIN_LCD_SCK_PZ4,
1798 };
1799
1800 static const unsigned drive_lcd2_pins[] = {
1801         TEGRA_PIN_LCD_PWR0_PB2,
1802         TEGRA_PIN_LCD_PCLK_PB3,
1803         TEGRA_PIN_LCD_DC1_PD2,
1804         TEGRA_PIN_LCD_D0_PE0,
1805         TEGRA_PIN_LCD_D1_PE1,
1806         TEGRA_PIN_LCD_D2_PE2,
1807         TEGRA_PIN_LCD_D3_PE3,
1808         TEGRA_PIN_LCD_D4_PE4,
1809         TEGRA_PIN_LCD_D5_PE5,
1810         TEGRA_PIN_LCD_D6_PE6,
1811         TEGRA_PIN_LCD_D7_PE7,
1812         TEGRA_PIN_LCD_D8_PF0,
1813         TEGRA_PIN_LCD_D9_PF1,
1814         TEGRA_PIN_LCD_D10_PF2,
1815         TEGRA_PIN_LCD_D11_PF3,
1816         TEGRA_PIN_LCD_D12_PF4,
1817         TEGRA_PIN_LCD_D13_PF5,
1818         TEGRA_PIN_LCD_D14_PF6,
1819         TEGRA_PIN_LCD_D15_PF7,
1820         TEGRA_PIN_LCD_DE_PJ1,
1821         TEGRA_PIN_LCD_HSYNC_PJ3,
1822         TEGRA_PIN_LCD_VSYNC_PJ4,
1823         TEGRA_PIN_LCD_D16_PM0,
1824         TEGRA_PIN_LCD_D17_PM1,
1825         TEGRA_PIN_LCD_D18_PM2,
1826         TEGRA_PIN_LCD_D19_PM3,
1827         TEGRA_PIN_LCD_D20_PM4,
1828         TEGRA_PIN_LCD_D21_PM5,
1829         TEGRA_PIN_LCD_D22_PM6,
1830         TEGRA_PIN_LCD_D23_PM7,
1831         TEGRA_PIN_HDMI_INT_PN7,
1832         TEGRA_PIN_LCD_CS1_N_PW0,
1833         TEGRA_PIN_LCD_M1_PW1,
1834 };
1835
1836 static const unsigned drive_owr_pins[] = {
1837         TEGRA_PIN_OWR,
1838 };
1839
1840 static const unsigned drive_sdio1_pins[] = {
1841         TEGRA_PIN_SDMMC1_DAT3_PY4,
1842         TEGRA_PIN_SDMMC1_DAT2_PY5,
1843         TEGRA_PIN_SDMMC1_DAT1_PY6,
1844         TEGRA_PIN_SDMMC1_DAT0_PY7,
1845         TEGRA_PIN_SDMMC1_CLK_PZ0,
1846         TEGRA_PIN_SDMMC1_CMD_PZ1,
1847 };
1848
1849 static const unsigned drive_sdio2_pins[] = {
1850         TEGRA_PIN_SDMMC3_DAT5_PD0,
1851         TEGRA_PIN_SDMMC3_DAT4_PD1,
1852         TEGRA_PIN_SDMMC3_DAT6_PD3,
1853         TEGRA_PIN_SDMMC3_DAT7_PD4,
1854 };
1855
1856 static const unsigned drive_sdio3_pins[] = {
1857         TEGRA_PIN_SDMMC3_CLK_PA6,
1858         TEGRA_PIN_SDMMC3_CMD_PA7,
1859         TEGRA_PIN_SDMMC3_DAT3_PB4,
1860         TEGRA_PIN_SDMMC3_DAT2_PB5,
1861         TEGRA_PIN_SDMMC3_DAT1_PB6,
1862         TEGRA_PIN_SDMMC3_DAT0_PB7,
1863 };
1864
1865 static const unsigned drive_spi_pins[] = {
1866         TEGRA_PIN_SPI2_CS1_N_PW2,
1867         TEGRA_PIN_SPI2_CS2_N_PW3,
1868         TEGRA_PIN_SPI2_MOSI_PX0,
1869         TEGRA_PIN_SPI2_MISO_PX1,
1870         TEGRA_PIN_SPI2_SCK_PX2,
1871         TEGRA_PIN_SPI2_CS0_N_PX3,
1872         TEGRA_PIN_SPI1_MOSI_PX4,
1873         TEGRA_PIN_SPI1_SCK_PX5,
1874         TEGRA_PIN_SPI1_CS0_N_PX6,
1875         TEGRA_PIN_SPI1_MISO_PX7,
1876 };
1877
1878 static const unsigned drive_uaa_pins[] = {
1879         TEGRA_PIN_ULPI_DATA0_PO1,
1880         TEGRA_PIN_ULPI_DATA1_PO2,
1881         TEGRA_PIN_ULPI_DATA2_PO3,
1882         TEGRA_PIN_ULPI_DATA3_PO4,
1883 };
1884
1885 static const unsigned drive_uab_pins[] = {
1886         TEGRA_PIN_ULPI_DATA7_PO0,
1887         TEGRA_PIN_ULPI_DATA4_PO5,
1888         TEGRA_PIN_ULPI_DATA5_PO6,
1889         TEGRA_PIN_ULPI_DATA6_PO7,
1890         TEGRA_PIN_PV0,
1891         TEGRA_PIN_PV1,
1892         TEGRA_PIN_PV2,
1893         TEGRA_PIN_PV3,
1894 };
1895
1896 static const unsigned drive_uart2_pins[] = {
1897         TEGRA_PIN_UART2_TXD_PC2,
1898         TEGRA_PIN_UART2_RXD_PC3,
1899         TEGRA_PIN_UART2_CTS_N_PJ5,
1900         TEGRA_PIN_UART2_RTS_N_PJ6,
1901 };
1902
1903 static const unsigned drive_uart3_pins[] = {
1904         TEGRA_PIN_UART3_CTS_N_PA1,
1905         TEGRA_PIN_UART3_RTS_N_PC0,
1906         TEGRA_PIN_UART3_TXD_PW6,
1907         TEGRA_PIN_UART3_RXD_PW7,
1908 };
1909
1910 static const unsigned drive_uda_pins[] = {
1911         TEGRA_PIN_ULPI_CLK_PY0,
1912         TEGRA_PIN_ULPI_DIR_PY1,
1913         TEGRA_PIN_ULPI_NXT_PY2,
1914         TEGRA_PIN_ULPI_STP_PY3,
1915 };
1916
1917 static const unsigned drive_vi1_pins[] = {
1918         TEGRA_PIN_VI_D1_PD5,
1919         TEGRA_PIN_VI_VSYNC_PD6,
1920         TEGRA_PIN_VI_HSYNC_PD7,
1921         TEGRA_PIN_VI_D2_PL0,
1922         TEGRA_PIN_VI_D3_PL1,
1923         TEGRA_PIN_VI_D4_PL2,
1924         TEGRA_PIN_VI_D5_PL3,
1925         TEGRA_PIN_VI_D6_PL4,
1926         TEGRA_PIN_VI_D7_PL5,
1927         TEGRA_PIN_VI_D8_PL6,
1928         TEGRA_PIN_VI_D9_PL7,
1929         TEGRA_PIN_VI_PCLK_PT0,
1930         TEGRA_PIN_VI_D10_PT2,
1931         TEGRA_PIN_VI_D11_PT3,
1932         TEGRA_PIN_VI_D0_PT4,
1933 };
1934
1935 enum tegra_mux {
1936         TEGRA_MUX_BLINK,
1937         TEGRA_MUX_CEC,
1938         TEGRA_MUX_CLK_12M_OUT,
1939         TEGRA_MUX_CLK_32K_IN,
1940         TEGRA_MUX_CORE_PWR_REQ,
1941         TEGRA_MUX_CPU_PWR_REQ,
1942         TEGRA_MUX_CRT,
1943         TEGRA_MUX_DAP,
1944         TEGRA_MUX_DDR,
1945         TEGRA_MUX_DEV3,
1946         TEGRA_MUX_DISPLAYA,
1947         TEGRA_MUX_DISPLAYB,
1948         TEGRA_MUX_DTV,
1949         TEGRA_MUX_EXTPERIPH1,
1950         TEGRA_MUX_EXTPERIPH2,
1951         TEGRA_MUX_EXTPERIPH3,
1952         TEGRA_MUX_GMI,
1953         TEGRA_MUX_GMI_ALT,
1954         TEGRA_MUX_HDA,
1955         TEGRA_MUX_HDCP,
1956         TEGRA_MUX_HDMI,
1957         TEGRA_MUX_HSI,
1958         TEGRA_MUX_I2C1,
1959         TEGRA_MUX_I2C2,
1960         TEGRA_MUX_I2C3,
1961         TEGRA_MUX_I2C4,
1962         TEGRA_MUX_I2CPWR,
1963         TEGRA_MUX_I2S0,
1964         TEGRA_MUX_I2S1,
1965         TEGRA_MUX_I2S2,
1966         TEGRA_MUX_I2S3,
1967         TEGRA_MUX_I2S4,
1968         TEGRA_MUX_INVALID,
1969         TEGRA_MUX_KBC,
1970         TEGRA_MUX_MIO,
1971         TEGRA_MUX_NAND,
1972         TEGRA_MUX_NAND_ALT,
1973         TEGRA_MUX_OWR,
1974         TEGRA_MUX_PCIE,
1975         TEGRA_MUX_PWM0,
1976         TEGRA_MUX_PWM1,
1977         TEGRA_MUX_PWM2,
1978         TEGRA_MUX_PWM3,
1979         TEGRA_MUX_PWR_INT_N,
1980         TEGRA_MUX_RSVD1,
1981         TEGRA_MUX_RSVD2,
1982         TEGRA_MUX_RSVD3,
1983         TEGRA_MUX_RSVD4,
1984         TEGRA_MUX_RTCK,
1985         TEGRA_MUX_SATA,
1986         TEGRA_MUX_SDMMC1,
1987         TEGRA_MUX_SDMMC2,
1988         TEGRA_MUX_SDMMC3,
1989         TEGRA_MUX_SDMMC4,
1990         TEGRA_MUX_SPDIF,
1991         TEGRA_MUX_SPI1,
1992         TEGRA_MUX_SPI2,
1993         TEGRA_MUX_SPI2_ALT,
1994         TEGRA_MUX_SPI3,
1995         TEGRA_MUX_SPI4,
1996         TEGRA_MUX_SPI5,
1997         TEGRA_MUX_SPI6,
1998         TEGRA_MUX_SYSCLK,
1999         TEGRA_MUX_TEST,
2000         TEGRA_MUX_TRACE,
2001         TEGRA_MUX_UARTA,
2002         TEGRA_MUX_UARTB,
2003         TEGRA_MUX_UARTC,
2004         TEGRA_MUX_UARTD,
2005         TEGRA_MUX_UARTE,
2006         TEGRA_MUX_ULPI,
2007         TEGRA_MUX_VGP1,
2008         TEGRA_MUX_VGP2,
2009         TEGRA_MUX_VGP3,
2010         TEGRA_MUX_VGP4,
2011         TEGRA_MUX_VGP5,
2012         TEGRA_MUX_VGP6,
2013         TEGRA_MUX_VI,
2014         TEGRA_MUX_VI_ALT1,
2015         TEGRA_MUX_VI_ALT2,
2016         TEGRA_MUX_VI_ALT3,
2017 };
2018 static const char * const blink_groups[] = {
2019         "clk_32k_out_pa0",
2020 };
2021
2022 static const char * const cec_groups[] = {
2023         "hdmi_cec_pee3",
2024         "owr",
2025 };
2026
2027 static const char * const clk_12m_out_groups[] = {
2028         "pv3",
2029 };
2030
2031 static const char * const clk_32k_in_groups[] = {
2032         "clk_32k_in",
2033 };
2034
2035 static const char * const core_pwr_req_groups[] = {
2036         "core_pwr_req",
2037 };
2038
2039 static const char * const cpu_pwr_req_groups[] = {
2040         "cpu_pwr_req",
2041 };
2042
2043 static const char * const crt_groups[] = {
2044         "crt_hsync_pv6",
2045         "crt_vsync_pv7",
2046 };
2047
2048 static const char * const dap_groups[] = {
2049         "clk1_req_pee2",
2050         "clk2_req_pcc5",
2051 };
2052
2053 static const char * const ddr_groups[] = {
2054         "vi_d0_pt4",
2055         "vi_d1_pd5",
2056         "vi_d10_pt2",
2057         "vi_d11_pt3",
2058         "vi_d2_pl0",
2059         "vi_d3_pl1",
2060         "vi_d4_pl2",
2061         "vi_d5_pl3",
2062         "vi_d6_pl4",
2063         "vi_d7_pl5",
2064         "vi_d8_pl6",
2065         "vi_d9_pl7",
2066         "vi_hsync_pd7",
2067         "vi_vsync_pd6",
2068 };
2069
2070 static const char * const dev3_groups[] = {
2071         "clk3_req_pee1",
2072 };
2073
2074 static const char * const displaya_groups[] = {
2075         "dap3_din_pp1",
2076         "dap3_dout_pp2",
2077         "dap3_fs_pp0",
2078         "dap3_sclk_pp3",
2079         "pbb3",
2080         "pbb4",
2081         "pbb5",
2082         "pbb6",
2083         "lcd_cs0_n_pn4",
2084         "lcd_cs1_n_pw0",
2085         "lcd_d0_pe0",
2086         "lcd_d1_pe1",
2087         "lcd_d10_pf2",
2088         "lcd_d11_pf3",
2089         "lcd_d12_pf4",
2090         "lcd_d13_pf5",
2091         "lcd_d14_pf6",
2092         "lcd_d15_pf7",
2093         "lcd_d16_pm0",
2094         "lcd_d17_pm1",
2095         "lcd_d18_pm2",
2096         "lcd_d19_pm3",
2097         "lcd_d2_pe2",
2098         "lcd_d20_pm4",
2099         "lcd_d21_pm5",
2100         "lcd_d22_pm6",
2101         "lcd_d23_pm7",
2102         "lcd_d3_pe3",
2103         "lcd_d4_pe4",
2104         "lcd_d5_pe5",
2105         "lcd_d6_pe6",
2106         "lcd_d7_pe7",
2107         "lcd_d8_pf0",
2108         "lcd_d9_pf1",
2109         "lcd_dc0_pn6",
2110         "lcd_dc1_pd2",
2111         "lcd_de_pj1",
2112         "lcd_hsync_pj3",
2113         "lcd_m1_pw1",
2114         "lcd_pclk_pb3",
2115         "lcd_pwr0_pb2",
2116         "lcd_pwr1_pc1",
2117         "lcd_pwr2_pc6",
2118         "lcd_sck_pz4",
2119         "lcd_sdin_pz2",
2120         "lcd_sdout_pn5",
2121         "lcd_vsync_pj4",
2122         "lcd_wr_n_pz3",
2123 };
2124
2125 static const char * const displayb_groups[] = {
2126         "dap3_din_pp1",
2127         "dap3_dout_pp2",
2128         "dap3_fs_pp0",
2129         "dap3_sclk_pp3",
2130         "pbb3",
2131         "pbb4",
2132         "pbb5",
2133         "pbb6",
2134         "lcd_cs0_n_pn4",
2135         "lcd_cs1_n_pw0",
2136         "lcd_d0_pe0",
2137         "lcd_d1_pe1",
2138         "lcd_d10_pf2",
2139         "lcd_d11_pf3",
2140         "lcd_d12_pf4",
2141         "lcd_d13_pf5",
2142         "lcd_d14_pf6",
2143         "lcd_d15_pf7",
2144         "lcd_d16_pm0",
2145         "lcd_d17_pm1",
2146         "lcd_d18_pm2",
2147         "lcd_d19_pm3",
2148         "lcd_d2_pe2",
2149         "lcd_d20_pm4",
2150         "lcd_d21_pm5",
2151         "lcd_d22_pm6",
2152         "lcd_d23_pm7",
2153         "lcd_d3_pe3",
2154         "lcd_d4_pe4",
2155         "lcd_d5_pe5",
2156         "lcd_d6_pe6",
2157         "lcd_d7_pe7",
2158         "lcd_d8_pf0",
2159         "lcd_d9_pf1",
2160         "lcd_dc0_pn6",
2161         "lcd_dc1_pd2",
2162         "lcd_de_pj1",
2163         "lcd_hsync_pj3",
2164         "lcd_m1_pw1",
2165         "lcd_pclk_pb3",
2166         "lcd_pwr0_pb2",
2167         "lcd_pwr1_pc1",
2168         "lcd_pwr2_pc6",
2169         "lcd_sck_pz4",
2170         "lcd_sdin_pz2",
2171         "lcd_sdout_pn5",
2172         "lcd_vsync_pj4",
2173         "lcd_wr_n_pz3",
2174 };
2175
2176 static const char * const dtv_groups[] = {
2177         "gmi_a17_pb0",
2178         "gmi_a18_pb1",
2179         "gmi_cs0_n_pj0",
2180         "gmi_cs1_n_pj2",
2181 };
2182
2183 static const char * const extperiph1_groups[] = {
2184         "clk1_out_pw4",
2185 };
2186
2187 static const char * const extperiph2_groups[] = {
2188         "clk2_out_pw5",
2189 };
2190
2191 static const char * const extperiph3_groups[] = {
2192         "clk3_out_pee0",
2193 };
2194
2195 static const char * const gmi_groups[] = {
2196         "dap1_din_pn1",
2197         "dap1_dout_pn2",
2198         "dap1_fs_pn0",
2199         "dap1_sclk_pn3",
2200         "dap2_din_pa4",
2201         "dap2_dout_pa5",
2202         "dap2_fs_pa2",
2203         "dap2_sclk_pa3",
2204         "dap4_din_pp5",
2205         "dap4_dout_pp6",
2206         "dap4_fs_pp4",
2207         "dap4_sclk_pp7",
2208         "gen2_i2c_scl_pt5",
2209         "gen2_i2c_sda_pt6",
2210         "gmi_a16_pj7",
2211         "gmi_a17_pb0",
2212         "gmi_a18_pb1",
2213         "gmi_a19_pk7",
2214         "gmi_ad0_pg0",
2215         "gmi_ad1_pg1",
2216         "gmi_ad10_ph2",
2217         "gmi_ad11_ph3",
2218         "gmi_ad12_ph4",
2219         "gmi_ad13_ph5",
2220         "gmi_ad14_ph6",
2221         "gmi_ad15_ph7",
2222         "gmi_ad2_pg2",
2223         "gmi_ad3_pg3",
2224         "gmi_ad4_pg4",
2225         "gmi_ad5_pg5",
2226         "gmi_ad6_pg6",
2227         "gmi_ad7_pg7",
2228         "gmi_ad8_ph0",
2229         "gmi_ad9_ph1",
2230         "gmi_adv_n_pk0",
2231         "gmi_clk_pk1",
2232         "gmi_cs0_n_pj0",
2233         "gmi_cs1_n_pj2",
2234         "gmi_cs2_n_pk3",
2235         "gmi_cs3_n_pk4",
2236         "gmi_cs4_n_pk2",
2237         "gmi_cs6_n_pi3",
2238         "gmi_cs7_n_pi6",
2239         "gmi_dqs_pi2",
2240         "gmi_iordy_pi5",
2241         "gmi_oe_n_pi1",
2242         "gmi_rst_n_pi4",
2243         "gmi_wait_pi7",
2244         "gmi_wp_n_pc7",
2245         "gmi_wr_n_pi0",
2246         "pu0",
2247         "pu1",
2248         "pu2",
2249         "pu3",
2250         "pu4",
2251         "pu5",
2252         "pu6",
2253         "sdmmc4_clk_pcc4",
2254         "sdmmc4_cmd_pt7",
2255         "sdmmc4_dat0_paa0",
2256         "sdmmc4_dat1_paa1",
2257         "sdmmc4_dat2_paa2",
2258         "sdmmc4_dat3_paa3",
2259         "sdmmc4_dat4_paa4",
2260         "sdmmc4_dat5_paa5",
2261         "sdmmc4_dat6_paa6",
2262         "sdmmc4_dat7_paa7",
2263         "spi1_cs0_n_px6",
2264         "spi1_mosi_px4",
2265         "spi1_sck_px5",
2266         "spi2_cs0_n_px3",
2267         "spi2_miso_px1",
2268         "spi2_mosi_px0",
2269         "spi2_sck_px2",
2270         "uart2_cts_n_pj5",
2271         "uart2_rts_n_pj6",
2272         "uart3_cts_n_pa1",
2273         "uart3_rts_n_pc0",
2274         "uart3_rxd_pw7",
2275         "uart3_txd_pw6",
2276 };
2277
2278 static const char * const gmi_alt_groups[] = {
2279         "gmi_a16_pj7",
2280         "gmi_cs3_n_pk4",
2281         "gmi_cs7_n_pi6",
2282         "gmi_wp_n_pc7",
2283 };
2284
2285 static const char * const hda_groups[] = {
2286         "clk1_req_pee2",
2287         "dap1_din_pn1",
2288         "dap1_dout_pn2",
2289         "dap1_fs_pn0",
2290         "dap1_sclk_pn3",
2291         "dap2_din_pa4",
2292         "dap2_dout_pa5",
2293         "dap2_fs_pa2",
2294         "dap2_sclk_pa3",
2295         "pex_l0_clkreq_n_pdd2",
2296         "pex_l0_prsnt_n_pdd0",
2297         "pex_l0_rst_n_pdd1",
2298         "pex_l1_clkreq_n_pdd6",
2299         "pex_l1_prsnt_n_pdd4",
2300         "pex_l1_rst_n_pdd5",
2301         "pex_l2_clkreq_n_pcc7",
2302         "pex_l2_prsnt_n_pdd7",
2303         "pex_l2_rst_n_pcc6",
2304         "pex_wake_n_pdd3",
2305         "spdif_in_pk6",
2306 };
2307
2308 static const char * const hdcp_groups[] = {
2309         "gen2_i2c_scl_pt5",
2310         "gen2_i2c_sda_pt6",
2311         "lcd_pwr0_pb2",
2312         "lcd_pwr2_pc6",
2313         "lcd_sck_pz4",
2314         "lcd_sdout_pn5",
2315         "lcd_wr_n_pz3",
2316 };
2317
2318 static const char * const hdmi_groups[] = {
2319         "hdmi_int_pn7",
2320 };
2321
2322 static const char * const hsi_groups[] = {
2323         "ulpi_data0_po1",
2324         "ulpi_data1_po2",
2325         "ulpi_data2_po3",
2326         "ulpi_data3_po4",
2327         "ulpi_data4_po5",
2328         "ulpi_data5_po6",
2329         "ulpi_data6_po7",
2330         "ulpi_data7_po0",
2331 };
2332
2333 static const char * const i2c1_groups[] = {
2334         "gen1_i2c_scl_pc4",
2335         "gen1_i2c_sda_pc5",
2336         "spdif_in_pk6",
2337         "spdif_out_pk5",
2338         "spi2_cs1_n_pw2",
2339         "spi2_cs2_n_pw3",
2340 };
2341
2342 static const char * const i2c2_groups[] = {
2343         "gen2_i2c_scl_pt5",
2344         "gen2_i2c_sda_pt6",
2345 };
2346
2347 static const char * const i2c3_groups[] = {
2348         "cam_i2c_scl_pbb1",
2349         "cam_i2c_sda_pbb2",
2350         "sdmmc4_cmd_pt7",
2351         "sdmmc4_dat4_paa4",
2352 };
2353
2354 static const char * const i2c4_groups[] = {
2355         "ddc_scl_pv4",
2356         "ddc_sda_pv5",
2357 };
2358
2359 static const char * const i2cpwr_groups[] = {
2360         "pwr_i2c_scl_pz6",
2361         "pwr_i2c_sda_pz7",
2362 };
2363
2364 static const char * const i2s0_groups[] = {
2365         "dap1_din_pn1",
2366         "dap1_dout_pn2",
2367         "dap1_fs_pn0",
2368         "dap1_sclk_pn3",
2369 };
2370
2371 static const char * const i2s1_groups[] = {
2372         "dap2_din_pa4",
2373         "dap2_dout_pa5",
2374         "dap2_fs_pa2",
2375         "dap2_sclk_pa3",
2376 };
2377
2378 static const char * const i2s2_groups[] = {
2379         "dap3_din_pp1",
2380         "dap3_dout_pp2",
2381         "dap3_fs_pp0",
2382         "dap3_sclk_pp3",
2383 };
2384
2385 static const char * const i2s3_groups[] = {
2386         "dap4_din_pp5",
2387         "dap4_dout_pp6",
2388         "dap4_fs_pp4",
2389         "dap4_sclk_pp7",
2390 };
2391
2392 static const char * const i2s4_groups[] = {
2393         "pbb0",
2394         "pbb7",
2395         "pcc1",
2396         "pcc2",
2397         "sdmmc4_dat4_paa4",
2398         "sdmmc4_dat5_paa5",
2399         "sdmmc4_dat6_paa6",
2400         "sdmmc4_dat7_paa7",
2401 };
2402
2403 static const char * const invalid_groups[] = {
2404         "kb_row3_pr3",
2405         "sdmmc4_clk_pcc4",
2406 };
2407
2408 static const char * const kbc_groups[] = {
2409         "kb_col0_pq0",
2410         "kb_col1_pq1",
2411         "kb_col2_pq2",
2412         "kb_col3_pq3",
2413         "kb_col4_pq4",
2414         "kb_col5_pq5",
2415         "kb_col6_pq6",
2416         "kb_col7_pq7",
2417         "kb_row0_pr0",
2418         "kb_row1_pr1",
2419         "kb_row10_ps2",
2420         "kb_row11_ps3",
2421         "kb_row12_ps4",
2422         "kb_row13_ps5",
2423         "kb_row14_ps6",
2424         "kb_row15_ps7",
2425         "kb_row2_pr2",
2426         "kb_row3_pr3",
2427         "kb_row4_pr4",
2428         "kb_row5_pr5",
2429         "kb_row6_pr6",
2430         "kb_row7_pr7",
2431         "kb_row8_ps0",
2432         "kb_row9_ps1",
2433 };
2434
2435 static const char * const mio_groups[] = {
2436         "kb_col6_pq6",
2437         "kb_col7_pq7",
2438         "kb_row10_ps2",
2439         "kb_row11_ps3",
2440         "kb_row12_ps4",
2441         "kb_row13_ps5",
2442         "kb_row14_ps6",
2443         "kb_row15_ps7",
2444         "kb_row6_pr6",
2445         "kb_row7_pr7",
2446         "kb_row8_ps0",
2447         "kb_row9_ps1",
2448 };
2449
2450 static const char * const nand_groups[] = {
2451         "gmi_ad0_pg0",
2452         "gmi_ad1_pg1",
2453         "gmi_ad10_ph2",
2454         "gmi_ad11_ph3",
2455         "gmi_ad12_ph4",
2456         "gmi_ad13_ph5",
2457         "gmi_ad14_ph6",
2458         "gmi_ad15_ph7",
2459         "gmi_ad2_pg2",
2460         "gmi_ad3_pg3",
2461         "gmi_ad4_pg4",
2462         "gmi_ad5_pg5",
2463         "gmi_ad6_pg6",
2464         "gmi_ad7_pg7",
2465         "gmi_ad8_ph0",
2466         "gmi_ad9_ph1",
2467         "gmi_adv_n_pk0",
2468         "gmi_clk_pk1",
2469         "gmi_cs0_n_pj0",
2470         "gmi_cs1_n_pj2",
2471         "gmi_cs2_n_pk3",
2472         "gmi_cs3_n_pk4",
2473         "gmi_cs4_n_pk2",
2474         "gmi_cs6_n_pi3",
2475         "gmi_cs7_n_pi6",
2476         "gmi_dqs_pi2",
2477         "gmi_iordy_pi5",
2478         "gmi_oe_n_pi1",
2479         "gmi_rst_n_pi4",
2480         "gmi_wait_pi7",
2481         "gmi_wp_n_pc7",
2482         "gmi_wr_n_pi0",
2483         "kb_col0_pq0",
2484         "kb_col1_pq1",
2485         "kb_col2_pq2",
2486         "kb_col3_pq3",
2487         "kb_col4_pq4",
2488         "kb_col5_pq5",
2489         "kb_col6_pq6",
2490         "kb_col7_pq7",
2491         "kb_row0_pr0",
2492         "kb_row1_pr1",
2493         "kb_row10_ps2",
2494         "kb_row11_ps3",
2495         "kb_row12_ps4",
2496         "kb_row13_ps5",
2497         "kb_row14_ps6",
2498         "kb_row15_ps7",
2499         "kb_row2_pr2",
2500         "kb_row3_pr3",
2501         "kb_row4_pr4",
2502         "kb_row5_pr5",
2503         "kb_row6_pr6",
2504         "kb_row7_pr7",
2505         "kb_row8_ps0",
2506         "kb_row9_ps1",
2507         "sdmmc4_clk_pcc4",
2508         "sdmmc4_cmd_pt7",
2509 };
2510
2511 static const char * const nand_alt_groups[] = {
2512         "gmi_cs6_n_pi3",
2513         "gmi_cs7_n_pi6",
2514         "gmi_rst_n_pi4",
2515 };
2516
2517 static const char * const owr_groups[] = {
2518         "pu0",
2519         "pv2",
2520         "kb_row5_pr5",
2521         "owr",
2522 };
2523
2524 static const char * const pcie_groups[] = {
2525         "pex_l0_clkreq_n_pdd2",
2526         "pex_l0_prsnt_n_pdd0",
2527         "pex_l0_rst_n_pdd1",
2528         "pex_l1_clkreq_n_pdd6",
2529         "pex_l1_prsnt_n_pdd4",
2530         "pex_l1_rst_n_pdd5",
2531         "pex_l2_clkreq_n_pcc7",
2532         "pex_l2_prsnt_n_pdd7",
2533         "pex_l2_rst_n_pcc6",
2534         "pex_wake_n_pdd3",
2535 };
2536
2537 static const char * const pwm0_groups[] = {
2538         "gmi_ad8_ph0",
2539         "pu3",
2540         "sdmmc3_dat3_pb4",
2541         "sdmmc3_dat5_pd0",
2542         "uart3_rts_n_pc0",
2543 };
2544
2545 static const char * const pwm1_groups[] = {
2546         "gmi_ad9_ph1",
2547         "pu4",
2548         "sdmmc3_dat2_pb5",
2549         "sdmmc3_dat4_pd1",
2550 };
2551
2552 static const char * const pwm2_groups[] = {
2553         "gmi_ad10_ph2",
2554         "pu5",
2555         "sdmmc3_clk_pa6",
2556 };
2557
2558 static const char * const pwm3_groups[] = {
2559         "gmi_ad11_ph3",
2560         "pu6",
2561         "sdmmc3_cmd_pa7",
2562 };
2563
2564 static const char * const pwr_int_n_groups[] = {
2565         "pwr_int_n",
2566 };
2567
2568 static const char * const rsvd1_groups[] = {
2569         "gmi_ad0_pg0",
2570         "gmi_ad1_pg1",
2571         "gmi_ad12_ph4",
2572         "gmi_ad13_ph5",
2573         "gmi_ad14_ph6",
2574         "gmi_ad15_ph7",
2575         "gmi_ad2_pg2",
2576         "gmi_ad3_pg3",
2577         "gmi_ad4_pg4",
2578         "gmi_ad5_pg5",
2579         "gmi_ad6_pg6",
2580         "gmi_ad7_pg7",
2581         "gmi_adv_n_pk0",
2582         "gmi_clk_pk1",
2583         "gmi_cs0_n_pj0",
2584         "gmi_cs1_n_pj2",
2585         "gmi_cs2_n_pk3",
2586         "gmi_cs3_n_pk4",
2587         "gmi_cs4_n_pk2",
2588         "gmi_dqs_pi2",
2589         "gmi_iordy_pi5",
2590         "gmi_oe_n_pi1",
2591         "gmi_wait_pi7",
2592         "gmi_wp_n_pc7",
2593         "gmi_wr_n_pi0",
2594         "pu1",
2595         "pu2",
2596         "pv0",
2597         "pv1",
2598         "sdmmc3_dat0_pb7",
2599         "sdmmc3_dat1_pb6",
2600         "sdmmc3_dat2_pb5",
2601         "sdmmc3_dat3_pb4",
2602         "vi_pclk_pt0",
2603 };
2604
2605 static const char * const rsvd2_groups[] = {
2606         "clk1_out_pw4",
2607         "clk2_out_pw5",
2608         "clk2_req_pcc5",
2609         "clk3_out_pee0",
2610         "clk3_req_pee1",
2611         "clk_32k_in",
2612         "clk_32k_out_pa0",
2613         "core_pwr_req",
2614         "cpu_pwr_req",
2615         "crt_hsync_pv6",
2616         "crt_vsync_pv7",
2617         "dap3_din_pp1",
2618         "dap3_dout_pp2",
2619         "dap3_fs_pp0",
2620         "dap3_sclk_pp3",
2621         "dap4_din_pp5",
2622         "dap4_dout_pp6",
2623         "dap4_fs_pp4",
2624         "dap4_sclk_pp7",
2625         "ddc_scl_pv4",
2626         "ddc_sda_pv5",
2627         "gen1_i2c_scl_pc4",
2628         "gen1_i2c_sda_pc5",
2629         "pbb0",
2630         "pbb7",
2631         "pcc1",
2632         "pcc2",
2633         "pv0",
2634         "pv1",
2635         "pv2",
2636         "pv3",
2637         "hdmi_cec_pee3",
2638         "hdmi_int_pn7",
2639         "jtag_rtck_pu7",
2640         "pwr_i2c_scl_pz6",
2641         "pwr_i2c_sda_pz7",
2642         "pwr_int_n",
2643         "sdmmc1_clk_pz0",
2644         "sdmmc1_cmd_pz1",
2645         "sdmmc1_dat0_py7",
2646         "sdmmc1_dat1_py6",
2647         "sdmmc1_dat2_py5",
2648         "sdmmc1_dat3_py4",
2649         "sdmmc3_dat0_pb7",
2650         "sdmmc3_dat1_pb6",
2651         "sdmmc4_rst_n_pcc3",
2652         "spdif_out_pk5",
2653         "sys_clk_req_pz5",
2654         "uart3_cts_n_pa1",
2655         "uart3_rxd_pw7",
2656         "uart3_txd_pw6",
2657         "ulpi_clk_py0",
2658         "ulpi_dir_py1",
2659         "ulpi_nxt_py2",
2660         "ulpi_stp_py3",
2661         "vi_d0_pt4",
2662         "vi_d10_pt2",
2663         "vi_d11_pt3",
2664         "vi_hsync_pd7",
2665         "vi_vsync_pd6",
2666 };
2667
2668 static const char * const rsvd3_groups[] = {
2669         "cam_i2c_scl_pbb1",
2670         "cam_i2c_sda_pbb2",
2671         "clk1_out_pw4",
2672         "clk1_req_pee2",
2673         "clk2_out_pw5",
2674         "clk2_req_pcc5",
2675         "clk3_out_pee0",
2676         "clk3_req_pee1",
2677         "clk_32k_in",
2678         "clk_32k_out_pa0",
2679         "core_pwr_req",
2680         "cpu_pwr_req",
2681         "crt_hsync_pv6",
2682         "crt_vsync_pv7",
2683         "dap2_din_pa4",
2684         "dap2_dout_pa5",
2685         "dap2_fs_pa2",
2686         "dap2_sclk_pa3",
2687         "ddc_scl_pv4",
2688         "ddc_sda_pv5",
2689         "gen1_i2c_scl_pc4",
2690         "gen1_i2c_sda_pc5",
2691         "pbb0",
2692         "pbb7",
2693         "pcc1",
2694         "pcc2",
2695         "pv0",
2696         "pv1",
2697         "pv2",
2698         "pv3",
2699         "hdmi_cec_pee3",
2700         "hdmi_int_pn7",
2701         "jtag_rtck_pu7",
2702         "kb_row0_pr0",
2703         "kb_row1_pr1",
2704         "kb_row2_pr2",
2705         "kb_row3_pr3",
2706         "lcd_d0_pe0",
2707         "lcd_d1_pe1",
2708         "lcd_d10_pf2",
2709         "lcd_d11_pf3",
2710         "lcd_d12_pf4",
2711         "lcd_d13_pf5",
2712         "lcd_d14_pf6",
2713         "lcd_d15_pf7",
2714         "lcd_d16_pm0",
2715         "lcd_d17_pm1",
2716         "lcd_d18_pm2",
2717         "lcd_d19_pm3",
2718         "lcd_d2_pe2",
2719         "lcd_d20_pm4",
2720         "lcd_d21_pm5",
2721         "lcd_d22_pm6",
2722         "lcd_d23_pm7",
2723         "lcd_d3_pe3",
2724         "lcd_d4_pe4",
2725         "lcd_d5_pe5",
2726         "lcd_d6_pe6",
2727         "lcd_d7_pe7",
2728         "lcd_d8_pf0",
2729         "lcd_d9_pf1",
2730         "lcd_dc0_pn6",
2731         "lcd_dc1_pd2",
2732         "lcd_de_pj1",
2733         "lcd_hsync_pj3",
2734         "lcd_m1_pw1",
2735         "lcd_pclk_pb3",
2736         "lcd_pwr1_pc1",
2737         "lcd_vsync_pj4",
2738         "owr",
2739         "pex_l0_clkreq_n_pdd2",
2740         "pex_l0_prsnt_n_pdd0",
2741         "pex_l0_rst_n_pdd1",
2742         "pex_l1_clkreq_n_pdd6",
2743         "pex_l1_prsnt_n_pdd4",
2744         "pex_l1_rst_n_pdd5",
2745         "pex_l2_clkreq_n_pcc7",
2746         "pex_l2_prsnt_n_pdd7",
2747         "pex_l2_rst_n_pcc6",
2748         "pex_wake_n_pdd3",
2749         "pwr_i2c_scl_pz6",
2750         "pwr_i2c_sda_pz7",
2751         "pwr_int_n",
2752         "sdmmc1_clk_pz0",
2753         "sdmmc1_cmd_pz1",
2754         "sdmmc4_rst_n_pcc3",
2755         "sys_clk_req_pz5",
2756 };
2757
2758 static const char * const rsvd4_groups[] = {
2759         "clk1_out_pw4",
2760         "clk1_req_pee2",
2761         "clk2_out_pw5",
2762         "clk2_req_pcc5",
2763         "clk3_out_pee0",
2764         "clk3_req_pee1",
2765         "clk_32k_in",
2766         "clk_32k_out_pa0",
2767         "core_pwr_req",
2768         "cpu_pwr_req",
2769         "crt_hsync_pv6",
2770         "crt_vsync_pv7",
2771         "dap4_din_pp5",
2772         "dap4_dout_pp6",
2773         "dap4_fs_pp4",
2774         "dap4_sclk_pp7",
2775         "ddc_scl_pv4",
2776         "ddc_sda_pv5",
2777         "gen1_i2c_scl_pc4",
2778         "gen1_i2c_sda_pc5",
2779         "gen2_i2c_scl_pt5",
2780         "gen2_i2c_sda_pt6",
2781         "gmi_a19_pk7",
2782         "gmi_ad0_pg0",
2783         "gmi_ad1_pg1",
2784         "gmi_ad10_ph2",
2785         "gmi_ad11_ph3",
2786         "gmi_ad12_ph4",
2787         "gmi_ad13_ph5",
2788         "gmi_ad14_ph6",
2789         "gmi_ad15_ph7",
2790         "gmi_ad2_pg2",
2791         "gmi_ad3_pg3",
2792         "gmi_ad4_pg4",
2793         "gmi_ad5_pg5",
2794         "gmi_ad6_pg6",
2795         "gmi_ad7_pg7",
2796         "gmi_ad8_ph0",
2797         "gmi_ad9_ph1",
2798         "gmi_adv_n_pk0",
2799         "gmi_clk_pk1",
2800         "gmi_cs2_n_pk3",
2801         "gmi_cs4_n_pk2",
2802         "gmi_dqs_pi2",
2803         "gmi_iordy_pi5",
2804         "gmi_oe_n_pi1",
2805         "gmi_rst_n_pi4",
2806         "gmi_wait_pi7",
2807         "gmi_wr_n_pi0",
2808         "pcc2",
2809         "pu0",
2810         "pu1",
2811         "pu2",
2812         "pu3",
2813         "pu4",
2814         "pu5",
2815         "pu6",
2816         "pv0",
2817         "pv1",
2818         "pv2",
2819         "pv3",
2820         "hdmi_cec_pee3",
2821         "hdmi_int_pn7",
2822         "jtag_rtck_pu7",
2823         "kb_col2_pq2",
2824         "kb_col3_pq3",
2825         "kb_col4_pq4",
2826         "kb_col5_pq5",
2827         "kb_row0_pr0",
2828         "kb_row1_pr1",
2829         "kb_row2_pr2",
2830         "kb_row4_pr4",
2831         "lcd_cs0_n_pn4",
2832         "lcd_cs1_n_pw0",
2833         "lcd_d0_pe0",
2834         "lcd_d1_pe1",
2835         "lcd_d10_pf2",
2836         "lcd_d11_pf3",
2837         "lcd_d12_pf4",
2838         "lcd_d13_pf5",
2839         "lcd_d14_pf6",
2840         "lcd_d15_pf7",
2841         "lcd_d16_pm0",
2842         "lcd_d17_pm1",
2843         "lcd_d18_pm2",
2844         "lcd_d19_pm3",
2845         "lcd_d2_pe2",
2846         "lcd_d20_pm4",
2847         "lcd_d21_pm5",
2848         "lcd_d22_pm6",
2849         "lcd_d23_pm7",
2850         "lcd_d3_pe3",
2851         "lcd_d4_pe4",
2852         "lcd_d5_pe5",
2853         "lcd_d6_pe6",
2854         "lcd_d7_pe7",
2855         "lcd_d8_pf0",
2856         "lcd_d9_pf1",
2857         "lcd_dc0_pn6",
2858         "lcd_dc1_pd2",
2859         "lcd_de_pj1",
2860         "lcd_hsync_pj3",
2861         "lcd_m1_pw1",
2862         "lcd_pclk_pb3",
2863         "lcd_pwr1_pc1",
2864         "lcd_sdin_pz2",
2865         "lcd_vsync_pj4",
2866         "owr",
2867         "pex_l0_clkreq_n_pdd2",
2868         "pex_l0_prsnt_n_pdd0",
2869         "pex_l0_rst_n_pdd1",
2870         "pex_l1_clkreq_n_pdd6",
2871         "pex_l1_prsnt_n_pdd4",
2872         "pex_l1_rst_n_pdd5",
2873         "pex_l2_clkreq_n_pcc7",
2874         "pex_l2_prsnt_n_pdd7",
2875         "pex_l2_rst_n_pcc6",
2876         "pex_wake_n_pdd3",
2877         "pwr_i2c_scl_pz6",
2878         "pwr_i2c_sda_pz7",
2879         "pwr_int_n",
2880         "spi1_miso_px7",
2881         "sys_clk_req_pz5",
2882         "uart3_cts_n_pa1",
2883         "uart3_rts_n_pc0",
2884         "uart3_rxd_pw7",
2885         "uart3_txd_pw6",
2886         "vi_d0_pt4",
2887         "vi_d1_pd5",
2888         "vi_d10_pt2",
2889         "vi_d11_pt3",
2890         "vi_d2_pl0",
2891         "vi_d3_pl1",
2892         "vi_d4_pl2",
2893         "vi_d5_pl3",
2894         "vi_d6_pl4",
2895         "vi_d7_pl5",
2896         "vi_d8_pl6",
2897         "vi_d9_pl7",
2898         "vi_hsync_pd7",
2899         "vi_pclk_pt0",
2900         "vi_vsync_pd6",
2901 };
2902
2903 static const char * const rtck_groups[] = {
2904         "jtag_rtck_pu7",
2905 };
2906
2907 static const char * const sata_groups[] = {
2908         "gmi_cs6_n_pi3",
2909 };
2910
2911 static const char * const sdmmc1_groups[] = {
2912         "sdmmc1_clk_pz0",
2913         "sdmmc1_cmd_pz1",
2914         "sdmmc1_dat0_py7",
2915         "sdmmc1_dat1_py6",
2916         "sdmmc1_dat2_py5",
2917         "sdmmc1_dat3_py4",
2918 };
2919
2920 static const char * const sdmmc2_groups[] = {
2921         "dap1_din_pn1",
2922         "dap1_dout_pn2",
2923         "dap1_fs_pn0",
2924         "dap1_sclk_pn3",
2925         "kb_row10_ps2",
2926         "kb_row11_ps3",
2927         "kb_row12_ps4",
2928         "kb_row13_ps5",
2929         "kb_row14_ps6",
2930         "kb_row15_ps7",
2931         "kb_row6_pr6",
2932         "kb_row7_pr7",
2933         "kb_row8_ps0",
2934         "kb_row9_ps1",
2935         "spdif_in_pk6",
2936         "spdif_out_pk5",
2937         "vi_d1_pd5",
2938         "vi_d2_pl0",
2939         "vi_d3_pl1",
2940         "vi_d4_pl2",
2941         "vi_d5_pl3",
2942         "vi_d6_pl4",
2943         "vi_d7_pl5",
2944         "vi_d8_pl6",
2945         "vi_d9_pl7",
2946         "vi_pclk_pt0",
2947 };
2948
2949 static const char * const sdmmc3_groups[] = {
2950         "sdmmc3_clk_pa6",
2951         "sdmmc3_cmd_pa7",
2952         "sdmmc3_dat0_pb7",
2953         "sdmmc3_dat1_pb6",
2954         "sdmmc3_dat2_pb5",
2955         "sdmmc3_dat3_pb4",
2956         "sdmmc3_dat4_pd1",
2957         "sdmmc3_dat5_pd0",
2958         "sdmmc3_dat6_pd3",
2959         "sdmmc3_dat7_pd4",
2960 };
2961
2962 static const char * const sdmmc4_groups[] = {
2963         "cam_i2c_scl_pbb1",
2964         "cam_i2c_sda_pbb2",
2965         "cam_mclk_pcc0",
2966         "pbb0",
2967         "pbb3",
2968         "pbb4",
2969         "pbb5",
2970         "pbb6",
2971         "pbb7",
2972         "pcc1",
2973         "sdmmc4_clk_pcc4",
2974         "sdmmc4_cmd_pt7",
2975         "sdmmc4_dat0_paa0",
2976         "sdmmc4_dat1_paa1",
2977         "sdmmc4_dat2_paa2",
2978         "sdmmc4_dat3_paa3",
2979         "sdmmc4_dat4_paa4",
2980         "sdmmc4_dat5_paa5",
2981         "sdmmc4_dat6_paa6",
2982         "sdmmc4_dat7_paa7",
2983         "sdmmc4_rst_n_pcc3",
2984 };
2985
2986 static const char * const spdif_groups[] = {
2987         "sdmmc3_dat6_pd3",
2988         "sdmmc3_dat7_pd4",
2989         "spdif_in_pk6",
2990         "spdif_out_pk5",
2991         "uart2_rxd_pc3",
2992         "uart2_txd_pc2",
2993 };
2994
2995 static const char * const spi1_groups[] = {
2996         "spi1_cs0_n_px6",
2997         "spi1_miso_px7",
2998         "spi1_mosi_px4",
2999         "spi1_sck_px5",
3000         "ulpi_clk_py0",
3001         "ulpi_dir_py1",
3002         "ulpi_nxt_py2",
3003         "ulpi_stp_py3",
3004 };
3005
3006 static const char * const spi2_groups[] = {
3007         "sdmmc3_cmd_pa7",
3008         "sdmmc3_dat4_pd1",
3009         "sdmmc3_dat5_pd0",
3010         "sdmmc3_dat6_pd3",
3011         "sdmmc3_dat7_pd4",
3012         "spi1_cs0_n_px6",
3013         "spi1_mosi_px4",
3014         "spi1_sck_px5",
3015         "spi2_cs0_n_px3",
3016         "spi2_cs1_n_pw2",
3017         "spi2_cs2_n_pw3",
3018         "spi2_miso_px1",
3019         "spi2_mosi_px0",
3020         "spi2_sck_px2",
3021         "ulpi_data4_po5",
3022         "ulpi_data5_po6",
3023         "ulpi_data6_po7",
3024         "ulpi_data7_po0",
3025 };
3026
3027 static const char * const spi2_alt_groups[] = {
3028         "spi1_cs0_n_px6",
3029         "spi1_miso_px7",
3030         "spi1_mosi_px4",
3031         "spi1_sck_px5",
3032         "spi2_cs1_n_pw2",
3033         "spi2_cs2_n_pw3",
3034 };
3035
3036 static const char * const spi3_groups[] = {
3037         "sdmmc3_clk_pa6",
3038         "sdmmc3_dat0_pb7",
3039         "sdmmc3_dat1_pb6",
3040         "sdmmc3_dat2_pb5",
3041         "sdmmc3_dat3_pb4",
3042         "sdmmc4_dat0_paa0",
3043         "sdmmc4_dat1_paa1",
3044         "sdmmc4_dat2_paa2",
3045         "sdmmc4_dat3_paa3",
3046         "spi1_miso_px7",
3047         "spi2_cs0_n_px3",
3048         "spi2_cs1_n_pw2",
3049         "spi2_cs2_n_pw3",
3050         "spi2_miso_px1",
3051         "spi2_mosi_px0",
3052         "spi2_sck_px2",
3053         "ulpi_data0_po1",
3054         "ulpi_data1_po2",
3055         "ulpi_data2_po3",
3056         "ulpi_data3_po4",
3057 };
3058
3059 static const char * const spi4_groups[] = {
3060         "gmi_a16_pj7",
3061         "gmi_a17_pb0",
3062         "gmi_a18_pb1",
3063         "gmi_a19_pk7",
3064         "sdmmc3_dat4_pd1",
3065         "sdmmc3_dat5_pd0",
3066         "sdmmc3_dat6_pd3",
3067         "sdmmc3_dat7_pd4",
3068         "uart2_cts_n_pj5",
3069         "uart2_rts_n_pj6",
3070         "uart2_rxd_pc3",
3071         "uart2_txd_pc2",
3072 };
3073
3074 static const char * const spi5_groups[] = {
3075         "lcd_cs0_n_pn4",
3076         "lcd_cs1_n_pw0",
3077         "lcd_pwr0_pb2",
3078         "lcd_pwr2_pc6",
3079         "lcd_sck_pz4",
3080         "lcd_sdin_pz2",
3081         "lcd_sdout_pn5",
3082         "lcd_wr_n_pz3",
3083 };
3084
3085 static const char * const spi6_groups[] = {
3086         "spi2_cs0_n_px3",
3087         "spi2_miso_px1",
3088         "spi2_mosi_px0",
3089         "spi2_sck_px2",
3090 };
3091
3092 static const char * const sysclk_groups[] = {
3093         "sys_clk_req_pz5",
3094 };
3095
3096 static const char * const test_groups[] = {
3097         "kb_col0_pq0",
3098         "kb_col1_pq1",
3099 };
3100
3101 static const char * const trace_groups[] = {
3102         "kb_col0_pq0",
3103         "kb_col1_pq1",
3104         "kb_col2_pq2",
3105         "kb_col3_pq3",
3106         "kb_col4_pq4",
3107         "kb_col5_pq5",
3108         "kb_col6_pq6",
3109         "kb_col7_pq7",
3110         "kb_row4_pr4",
3111         "kb_row5_pr5",
3112 };
3113
3114 static const char * const uarta_groups[] = {
3115         "pu0",
3116         "pu1",
3117         "pu2",
3118         "pu3",
3119         "pu4",
3120         "pu5",
3121         "pu6",
3122         "sdmmc1_clk_pz0",
3123         "sdmmc1_cmd_pz1",
3124         "sdmmc1_dat0_py7",
3125         "sdmmc1_dat1_py6",
3126         "sdmmc1_dat2_py5",
3127         "sdmmc1_dat3_py4",
3128         "sdmmc3_clk_pa6",
3129         "sdmmc3_cmd_pa7",
3130         "uart2_cts_n_pj5",
3131         "uart2_rts_n_pj6",
3132         "uart2_rxd_pc3",
3133         "uart2_txd_pc2",
3134         "ulpi_data0_po1",
3135         "ulpi_data1_po2",
3136         "ulpi_data2_po3",
3137         "ulpi_data3_po4",
3138         "ulpi_data4_po5",
3139         "ulpi_data5_po6",
3140         "ulpi_data6_po7",
3141         "ulpi_data7_po0",
3142 };
3143
3144 static const char * const uartb_groups[] = {
3145         "uart2_cts_n_pj5",
3146         "uart2_rts_n_pj6",
3147         "uart2_rxd_pc3",
3148         "uart2_txd_pc2",
3149 };
3150
3151 static const char * const uartc_groups[] = {
3152         "uart3_cts_n_pa1",
3153         "uart3_rts_n_pc0",
3154         "uart3_rxd_pw7",
3155         "uart3_txd_pw6",
3156 };
3157
3158 static const char * const uartd_groups[] = {
3159         "gmi_a16_pj7",
3160         "gmi_a17_pb0",
3161         "gmi_a18_pb1",
3162         "gmi_a19_pk7",
3163         "ulpi_clk_py0",
3164         "ulpi_dir_py1",
3165         "ulpi_nxt_py2",
3166         "ulpi_stp_py3",
3167 };
3168
3169 static const char * const uarte_groups[] = {
3170         "sdmmc1_dat0_py7",
3171         "sdmmc1_dat1_py6",
3172         "sdmmc1_dat2_py5",
3173         "sdmmc1_dat3_py4",
3174         "sdmmc4_dat0_paa0",
3175         "sdmmc4_dat1_paa1",
3176         "sdmmc4_dat2_paa2",
3177         "sdmmc4_dat3_paa3",
3178 };
3179
3180 static const char * const ulpi_groups[] = {
3181         "ulpi_clk_py0",
3182         "ulpi_data0_po1",
3183         "ulpi_data1_po2",
3184         "ulpi_data2_po3",
3185         "ulpi_data3_po4",
3186         "ulpi_data4_po5",
3187         "ulpi_data5_po6",
3188         "ulpi_data6_po7",
3189         "ulpi_data7_po0",
3190         "ulpi_dir_py1",
3191         "ulpi_nxt_py2",
3192         "ulpi_stp_py3",
3193 };
3194
3195 static const char * const vgp1_groups[] = {
3196         "cam_i2c_scl_pbb1",
3197 };
3198
3199 static const char * const vgp2_groups[] = {
3200         "cam_i2c_sda_pbb2",
3201 };
3202
3203 static const char * const vgp3_groups[] = {
3204         "pbb3",
3205         "sdmmc4_dat5_paa5",
3206 };
3207
3208 static const char * const vgp4_groups[] = {
3209         "pbb4",
3210         "sdmmc4_dat6_paa6",
3211 };
3212
3213 static const char * const vgp5_groups[] = {
3214         "pbb5",
3215         "sdmmc4_dat7_paa7",
3216 };
3217
3218 static const char * const vgp6_groups[] = {
3219         "pbb6",
3220         "sdmmc4_rst_n_pcc3",
3221 };
3222
3223 static const char * const vi_groups[] = {
3224         "cam_mclk_pcc0",
3225         "vi_d0_pt4",
3226         "vi_d1_pd5",
3227         "vi_d10_pt2",
3228         "vi_d11_pt3",
3229         "vi_d2_pl0",
3230         "vi_d3_pl1",
3231         "vi_d4_pl2",
3232         "vi_d5_pl3",
3233         "vi_d6_pl4",
3234         "vi_d7_pl5",
3235         "vi_d8_pl6",
3236         "vi_d9_pl7",
3237         "vi_hsync_pd7",
3238         "vi_mclk_pt1",
3239         "vi_pclk_pt0",
3240         "vi_vsync_pd6",
3241 };
3242
3243 static const char * const vi_alt1_groups[] = {
3244         "cam_mclk_pcc0",
3245         "vi_mclk_pt1",
3246 };
3247
3248 static const char * const vi_alt2_groups[] = {
3249         "vi_mclk_pt1",
3250 };
3251
3252 static const char * const vi_alt3_groups[] = {
3253         "cam_mclk_pcc0",
3254         "vi_mclk_pt1",
3255 };
3256
3257 #define FUNCTION(fname)                                 \
3258         {                                               \
3259                 .name = #fname,                         \
3260                 .groups = fname##_groups,               \
3261                 .ngroups = ARRAY_SIZE(fname##_groups),  \
3262         }
3263
3264 static const struct tegra_function tegra30_functions[] = {
3265         FUNCTION(blink),
3266         FUNCTION(cec),
3267         FUNCTION(clk_12m_out),
3268         FUNCTION(clk_32k_in),
3269         FUNCTION(core_pwr_req),
3270         FUNCTION(cpu_pwr_req),
3271         FUNCTION(crt),
3272         FUNCTION(dap),
3273         FUNCTION(ddr),
3274         FUNCTION(dev3),
3275         FUNCTION(displaya),
3276         FUNCTION(displayb),
3277         FUNCTION(dtv),
3278         FUNCTION(extperiph1),
3279         FUNCTION(extperiph2),
3280         FUNCTION(extperiph3),
3281         FUNCTION(gmi),
3282         FUNCTION(gmi_alt),
3283         FUNCTION(hda),
3284         FUNCTION(hdcp),
3285         FUNCTION(hdmi),
3286         FUNCTION(hsi),
3287         FUNCTION(i2c1),
3288         FUNCTION(i2c2),
3289         FUNCTION(i2c3),
3290         FUNCTION(i2c4),
3291         FUNCTION(i2cpwr),
3292         FUNCTION(i2s0),
3293         FUNCTION(i2s1),
3294         FUNCTION(i2s2),
3295         FUNCTION(i2s3),
3296         FUNCTION(i2s4),
3297         FUNCTION(invalid),
3298         FUNCTION(kbc),
3299         FUNCTION(mio),
3300         FUNCTION(nand),
3301         FUNCTION(nand_alt),
3302         FUNCTION(owr),
3303         FUNCTION(pcie),
3304         FUNCTION(pwm0),
3305         FUNCTION(pwm1),
3306         FUNCTION(pwm2),
3307         FUNCTION(pwm3),
3308         FUNCTION(pwr_int_n),
3309         FUNCTION(rsvd1),
3310         FUNCTION(rsvd2),
3311         FUNCTION(rsvd3),
3312         FUNCTION(rsvd4),
3313         FUNCTION(rtck),
3314         FUNCTION(sata),
3315         FUNCTION(sdmmc1),
3316         FUNCTION(sdmmc2),
3317         FUNCTION(sdmmc3),
3318         FUNCTION(sdmmc4),
3319         FUNCTION(spdif),
3320         FUNCTION(spi1),
3321         FUNCTION(spi2),
3322         FUNCTION(spi2_alt),
3323         FUNCTION(spi3),
3324         FUNCTION(spi4),
3325         FUNCTION(spi5),
3326         FUNCTION(spi6),
3327         FUNCTION(sysclk),
3328         FUNCTION(test),
3329         FUNCTION(trace),
3330         FUNCTION(uarta),
3331         FUNCTION(uartb),
3332         FUNCTION(uartc),
3333         FUNCTION(uartd),
3334         FUNCTION(uarte),
3335         FUNCTION(ulpi),
3336         FUNCTION(vgp1),
3337         FUNCTION(vgp2),
3338         FUNCTION(vgp3),
3339         FUNCTION(vgp4),
3340         FUNCTION(vgp5),
3341         FUNCTION(vgp6),
3342         FUNCTION(vi),
3343         FUNCTION(vi_alt1),
3344         FUNCTION(vi_alt2),
3345         FUNCTION(vi_alt3),
3346 };
3347
3348 #define DRV_PINGROUP_REG_A      0x868   /* bank 0 */
3349 #define PINGROUP_REG_A          0x3000  /* bank 1 */
3350
3351 #define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
3352 #define PINGROUP_REG_N(r) -1
3353
3354 #define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior)   \
3355         {                                                       \
3356                 .name = #pg_name,                               \
3357                 .pins = pg_name##_pins,                         \
3358                 .npins = ARRAY_SIZE(pg_name##_pins),            \
3359                 .funcs = {                                      \
3360                         TEGRA_MUX_ ## f0,                       \
3361                         TEGRA_MUX_ ## f1,                       \
3362                         TEGRA_MUX_ ## f2,                       \
3363                         TEGRA_MUX_ ## f3,                       \
3364                 },                                              \
3365                 .func_safe = TEGRA_MUX_ ## f_safe,              \
3366                 .mux_reg = PINGROUP_REG_Y(r),                   \
3367                 .mux_bank = 1,                                  \
3368                 .mux_bit = 0,                                   \
3369                 .pupd_reg = PINGROUP_REG_Y(r),                  \
3370                 .pupd_bank = 1,                                 \
3371                 .pupd_bit = 2,                                  \
3372                 .tri_reg = PINGROUP_REG_Y(r),                   \
3373                 .tri_bank = 1,                                  \
3374                 .tri_bit = 4,                                   \
3375                 .einput_reg = PINGROUP_REG_Y(r),                \
3376                 .einput_bank = 1,                               \
3377                 .einput_bit = 5,                                \
3378                 .odrain_reg = PINGROUP_REG_##od(r),             \
3379                 .odrain_bank = 1,                               \
3380                 .odrain_bit = 6,                                \
3381                 .lock_reg = PINGROUP_REG_Y(r),                  \
3382                 .lock_bank = 1,                                 \
3383                 .lock_bit = 7,                                  \
3384                 .ioreset_reg = PINGROUP_REG_##ior(r),           \
3385                 .ioreset_bank = 1,                              \
3386                 .ioreset_bit = 8,                               \
3387                 .rcv_sel_reg = -1,                              \
3388                 .drv_reg = -1,                                  \
3389                 .drvtype_reg = -1,                              \
3390         }
3391
3392 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b,      \
3393                      drvdn_b, drvdn_w, drvup_b, drvup_w,        \
3394                      slwr_b, slwr_w, slwf_b, slwf_w)            \
3395         {                                                       \
3396                 .name = "drive_" #pg_name,                      \
3397                 .pins = drive_##pg_name##_pins,                 \
3398                 .npins = ARRAY_SIZE(drive_##pg_name##_pins),    \
3399                 .mux_reg = -1,                                  \
3400                 .pupd_reg = -1,                                 \
3401                 .tri_reg = -1,                                  \
3402                 .einput_reg = -1,                               \
3403                 .odrain_reg = -1,                               \
3404                 .lock_reg = -1,                                 \
3405                 .ioreset_reg = -1,                              \
3406                 .rcv_sel_reg = -1,                              \
3407                 .drv_reg = ((r) - DRV_PINGROUP_REG_A),          \
3408                 .drv_bank = 0,                                  \
3409                 .hsm_bit = hsm_b,                               \
3410                 .schmitt_bit = schmitt_b,                       \
3411                 .lpmd_bit = lpmd_b,                             \
3412                 .drvdn_bit = drvdn_b,                           \
3413                 .drvdn_width = drvdn_w,                         \
3414                 .drvup_bit = drvup_b,                           \
3415                 .drvup_width = drvup_w,                         \
3416                 .slwr_bit = slwr_b,                             \
3417                 .slwr_width = slwr_w,                           \
3418                 .slwf_bit = slwf_b,                             \
3419                 .slwf_width = slwf_w,                           \
3420                 .drvtype_reg = -1,                              \
3421         }
3422
3423 static const struct tegra_pingroup tegra30_groups[] = {
3424         /*       pg_name,              f0,           f1,           f2,           f3,           safe,         r,      od, ior */
3425         /* FIXME: Fill in correct data in safe column */
3426         PINGROUP(clk_32k_out_pa0,      BLINK,        RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x331c, N, N),
3427         PINGROUP(uart3_cts_n_pa1,      UARTC,        RSVD2,        GMI,          RSVD4,        RSVD4,        0x317c, N, N),
3428         PINGROUP(dap2_fs_pa2,          I2S1,         HDA,          RSVD3,        GMI,          RSVD3,        0x3358, N, N),
3429         PINGROUP(dap2_sclk_pa3,        I2S1,         HDA,          RSVD3,        GMI,          RSVD3,        0x3364, N, N),
3430         PINGROUP(dap2_din_pa4,         I2S1,         HDA,          RSVD3,        GMI,          RSVD3,        0x335c, N, N),
3431         PINGROUP(dap2_dout_pa5,        I2S1,         HDA,          RSVD3,        GMI,          RSVD3,        0x3360, N, N),
3432         PINGROUP(sdmmc3_clk_pa6,       UARTA,        PWM2,         SDMMC3,       SPI3,         SPI3,         0x3390, N, N),
3433         PINGROUP(sdmmc3_cmd_pa7,       UARTA,        PWM3,         SDMMC3,       SPI2,         SPI2,         0x3394, N, N),
3434         PINGROUP(gmi_a17_pb0,          UARTD,        SPI4,         GMI,          DTV,          DTV,          0x3234, N, N),
3435         PINGROUP(gmi_a18_pb1,          UARTD,        SPI4,         GMI,          DTV,          DTV,          0x3238, N, N),
3436         PINGROUP(lcd_pwr0_pb2,         DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         HDCP,         0x3090, N, N),
3437         PINGROUP(lcd_pclk_pb3,         DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x3094, N, N),
3438         PINGROUP(sdmmc3_dat3_pb4,      RSVD1,        PWM0,         SDMMC3,       SPI3,         RSVD1,        0x33a4, N, N),
3439         PINGROUP(sdmmc3_dat2_pb5,      RSVD1,        PWM1,         SDMMC3,       SPI3,         RSVD1,        0x33a0, N, N),
3440         PINGROUP(sdmmc3_dat1_pb6,      RSVD1,        RSVD2,        SDMMC3,       SPI3,         RSVD2,        0x339c, N, N),
3441         PINGROUP(sdmmc3_dat0_pb7,      RSVD1,        RSVD2,        SDMMC3,       SPI3,         RSVD2,        0x3398, N, N),
3442         PINGROUP(uart3_rts_n_pc0,      UARTC,        PWM0,         GMI,          RSVD4,        RSVD4,        0x3180, N, N),
3443         PINGROUP(lcd_pwr1_pc1,         DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x3070, N, N),
3444         PINGROUP(uart2_txd_pc2,        UARTB,        SPDIF,        UARTA,        SPI4,         SPI4,         0x3168, N, N),
3445         PINGROUP(uart2_rxd_pc3,        UARTB,        SPDIF,        UARTA,        SPI4,         SPI4,         0x3164, N, N),
3446         PINGROUP(gen1_i2c_scl_pc4,     I2C1,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x31a4, Y, N),
3447         PINGROUP(gen1_i2c_sda_pc5,     I2C1,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x31a0, Y, N),
3448         PINGROUP(lcd_pwr2_pc6,         DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         HDCP,         0x3074, N, N),
3449         PINGROUP(gmi_wp_n_pc7,         RSVD1,        NAND,         GMI,          GMI_ALT,      RSVD1,        0x31c0, N, N),
3450         PINGROUP(sdmmc3_dat5_pd0,      PWM0,         SPI4,         SDMMC3,       SPI2,         SPI2,         0x33ac, N, N),
3451         PINGROUP(sdmmc3_dat4_pd1,      PWM1,         SPI4,         SDMMC3,       SPI2,         SPI2,         0x33a8, N, N),
3452         PINGROUP(lcd_dc1_pd2,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x310c, N, N),
3453         PINGROUP(sdmmc3_dat6_pd3,      SPDIF,        SPI4,         SDMMC3,       SPI2,         SPI2,         0x33b0, N, N),
3454         PINGROUP(sdmmc3_dat7_pd4,      SPDIF,        SPI4,         SDMMC3,       SPI2,         SPI2,         0x33b4, N, N),
3455         PINGROUP(vi_d1_pd5,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x3128, N, Y),
3456         PINGROUP(vi_vsync_pd6,         DDR,          RSVD2,        VI,           RSVD4,        RSVD4,        0x315c, N, Y),
3457         PINGROUP(vi_hsync_pd7,         DDR,          RSVD2,        VI,           RSVD4,        RSVD4,        0x3160, N, Y),
3458         PINGROUP(lcd_d0_pe0,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30a4, N, N),
3459         PINGROUP(lcd_d1_pe1,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30a8, N, N),
3460         PINGROUP(lcd_d2_pe2,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30ac, N, N),
3461         PINGROUP(lcd_d3_pe3,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30b0, N, N),
3462         PINGROUP(lcd_d4_pe4,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30b4, N, N),
3463         PINGROUP(lcd_d5_pe5,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30b8, N, N),
3464         PINGROUP(lcd_d6_pe6,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30bc, N, N),
3465         PINGROUP(lcd_d7_pe7,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30c0, N, N),
3466         PINGROUP(lcd_d8_pf0,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30c4, N, N),
3467         PINGROUP(lcd_d9_pf1,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30c8, N, N),
3468         PINGROUP(lcd_d10_pf2,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30cc, N, N),
3469         PINGROUP(lcd_d11_pf3,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30d0, N, N),
3470         PINGROUP(lcd_d12_pf4,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30d4, N, N),
3471         PINGROUP(lcd_d13_pf5,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30d8, N, N),
3472         PINGROUP(lcd_d14_pf6,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30dc, N, N),
3473         PINGROUP(lcd_d15_pf7,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30e0, N, N),
3474         PINGROUP(gmi_ad0_pg0,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31f0, N, N),
3475         PINGROUP(gmi_ad1_pg1,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31f4, N, N),
3476         PINGROUP(gmi_ad2_pg2,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31f8, N, N),
3477         PINGROUP(gmi_ad3_pg3,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31fc, N, N),
3478         PINGROUP(gmi_ad4_pg4,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3200, N, N),
3479         PINGROUP(gmi_ad5_pg5,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3204, N, N),
3480         PINGROUP(gmi_ad6_pg6,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3208, N, N),
3481         PINGROUP(gmi_ad7_pg7,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x320c, N, N),
3482         PINGROUP(gmi_ad8_ph0,          PWM0,         NAND,         GMI,          RSVD4,        RSVD4,        0x3210, N, N),
3483         PINGROUP(gmi_ad9_ph1,          PWM1,         NAND,         GMI,          RSVD4,        RSVD4,        0x3214, N, N),
3484         PINGROUP(gmi_ad10_ph2,         PWM2,         NAND,         GMI,          RSVD4,        RSVD4,        0x3218, N, N),
3485         PINGROUP(gmi_ad11_ph3,         PWM3,         NAND,         GMI,          RSVD4,        RSVD4,        0x321c, N, N),
3486         PINGROUP(gmi_ad12_ph4,         RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3220, N, N),
3487         PINGROUP(gmi_ad13_ph5,         RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3224, N, N),
3488         PINGROUP(gmi_ad14_ph6,         RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3228, N, N),
3489         PINGROUP(gmi_ad15_ph7,         RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x322c, N, N),
3490         PINGROUP(gmi_wr_n_pi0,         RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3240, N, N),
3491         PINGROUP(gmi_oe_n_pi1,         RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3244, N, N),
3492         PINGROUP(gmi_dqs_pi2,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x3248, N, N),
3493         PINGROUP(gmi_cs6_n_pi3,        NAND,         NAND_ALT,     GMI,          SATA,         SATA,         0x31e8, N, N),
3494         PINGROUP(gmi_rst_n_pi4,        NAND,         NAND_ALT,     GMI,          RSVD4,        RSVD4,        0x324c, N, N),
3495         PINGROUP(gmi_iordy_pi5,        RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31c4, N, N),
3496         PINGROUP(gmi_cs7_n_pi6,        NAND,         NAND_ALT,     GMI,          GMI_ALT,      GMI_ALT,      0x31ec, N, N),
3497         PINGROUP(gmi_wait_pi7,         RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31c8, N, N),
3498         PINGROUP(gmi_cs0_n_pj0,        RSVD1,        NAND,         GMI,          DTV,          RSVD1,        0x31d4, N, N),
3499         PINGROUP(lcd_de_pj1,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x3098, N, N),
3500         PINGROUP(gmi_cs1_n_pj2,        RSVD1,        NAND,         GMI,          DTV,          RSVD1,        0x31d8, N, N),
3501         PINGROUP(lcd_hsync_pj3,        DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x309c, N, N),
3502         PINGROUP(lcd_vsync_pj4,        DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30a0, N, N),
3503         PINGROUP(uart2_cts_n_pj5,      UARTA,        UARTB,        GMI,          SPI4,         SPI4,         0x3170, N, N),
3504         PINGROUP(uart2_rts_n_pj6,      UARTA,        UARTB,        GMI,          SPI4,         SPI4,         0x316c, N, N),
3505         PINGROUP(gmi_a16_pj7,          UARTD,        SPI4,         GMI,          GMI_ALT,      GMI_ALT,      0x3230, N, N),
3506         PINGROUP(gmi_adv_n_pk0,        RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31cc, N, N),
3507         PINGROUP(gmi_clk_pk1,          RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31d0, N, N),
3508         PINGROUP(gmi_cs4_n_pk2,        RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31e4, N, N),
3509         PINGROUP(gmi_cs2_n_pk3,        RSVD1,        NAND,         GMI,          RSVD4,        RSVD4,        0x31dc, N, N),
3510         PINGROUP(gmi_cs3_n_pk4,        RSVD1,        NAND,         GMI,          GMI_ALT,      RSVD1,        0x31e0, N, N),
3511         PINGROUP(spdif_out_pk5,        SPDIF,        RSVD2,        I2C1,         SDMMC2,       RSVD2,        0x3354, N, N),
3512         PINGROUP(spdif_in_pk6,         SPDIF,        HDA,          I2C1,         SDMMC2,       SDMMC2,       0x3350, N, N),
3513         PINGROUP(gmi_a19_pk7,          UARTD,        SPI4,         GMI,          RSVD4,        RSVD4,        0x323c, N, N),
3514         PINGROUP(vi_d2_pl0,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x312c, N, Y),
3515         PINGROUP(vi_d3_pl1,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x3130, N, Y),
3516         PINGROUP(vi_d4_pl2,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x3134, N, Y),
3517         PINGROUP(vi_d5_pl3,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x3138, N, Y),
3518         PINGROUP(vi_d6_pl4,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x313c, N, Y),
3519         PINGROUP(vi_d7_pl5,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x3140, N, Y),
3520         PINGROUP(vi_d8_pl6,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x3144, N, Y),
3521         PINGROUP(vi_d9_pl7,            DDR,          SDMMC2,       VI,           RSVD4,        RSVD4,        0x3148, N, Y),
3522         PINGROUP(lcd_d16_pm0,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30e4, N, N),
3523         PINGROUP(lcd_d17_pm1,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30e8, N, N),
3524         PINGROUP(lcd_d18_pm2,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30ec, N, N),
3525         PINGROUP(lcd_d19_pm3,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30f0, N, N),
3526         PINGROUP(lcd_d20_pm4,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30f4, N, N),
3527         PINGROUP(lcd_d21_pm5,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30f8, N, N),
3528         PINGROUP(lcd_d22_pm6,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x30fc, N, N),
3529         PINGROUP(lcd_d23_pm7,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x3100, N, N),
3530         PINGROUP(dap1_fs_pn0,          I2S0,         HDA,          GMI,          SDMMC2,       SDMMC2,       0x3338, N, N),
3531         PINGROUP(dap1_din_pn1,         I2S0,         HDA,          GMI,          SDMMC2,       SDMMC2,       0x333c, N, N),
3532         PINGROUP(dap1_dout_pn2,        I2S0,         HDA,          GMI,          SDMMC2,       SDMMC2,       0x3340, N, N),
3533         PINGROUP(dap1_sclk_pn3,        I2S0,         HDA,          GMI,          SDMMC2,       SDMMC2,       0x3344, N, N),
3534         PINGROUP(lcd_cs0_n_pn4,        DISPLAYA,     DISPLAYB,     SPI5,         RSVD4,        RSVD4,        0x3084, N, N),
3535         PINGROUP(lcd_sdout_pn5,        DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         HDCP,         0x307c, N, N),
3536         PINGROUP(lcd_dc0_pn6,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x3088, N, N),
3537         PINGROUP(hdmi_int_pn7,         HDMI,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3110, N, N),
3538         PINGROUP(ulpi_data7_po0,       SPI2,         HSI,          UARTA,        ULPI,         ULPI,         0x301c, N, N),
3539         PINGROUP(ulpi_data0_po1,       SPI3,         HSI,          UARTA,        ULPI,         ULPI,         0x3000, N, N),
3540         PINGROUP(ulpi_data1_po2,       SPI3,         HSI,          UARTA,        ULPI,         ULPI,         0x3004, N, N),
3541         PINGROUP(ulpi_data2_po3,       SPI3,         HSI,          UARTA,        ULPI,         ULPI,         0x3008, N, N),
3542         PINGROUP(ulpi_data3_po4,       SPI3,         HSI,          UARTA,        ULPI,         ULPI,         0x300c, N, N),
3543         PINGROUP(ulpi_data4_po5,       SPI2,         HSI,          UARTA,        ULPI,         ULPI,         0x3010, N, N),
3544         PINGROUP(ulpi_data5_po6,       SPI2,         HSI,          UARTA,        ULPI,         ULPI,         0x3014, N, N),
3545         PINGROUP(ulpi_data6_po7,       SPI2,         HSI,          UARTA,        ULPI,         ULPI,         0x3018, N, N),
3546         PINGROUP(dap3_fs_pp0,          I2S2,         RSVD2,        DISPLAYA,     DISPLAYB,     RSVD2,        0x3030, N, N),
3547         PINGROUP(dap3_din_pp1,         I2S2,         RSVD2,        DISPLAYA,     DISPLAYB,     RSVD2,        0x3034, N, N),
3548         PINGROUP(dap3_dout_pp2,        I2S2,         RSVD2,        DISPLAYA,     DISPLAYB,     RSVD2,        0x3038, N, N),
3549         PINGROUP(dap3_sclk_pp3,        I2S2,         RSVD2,        DISPLAYA,     DISPLAYB,     RSVD2,        0x303c, N, N),
3550         PINGROUP(dap4_fs_pp4,          I2S3,         RSVD2,        GMI,          RSVD4,        RSVD4,        0x31a8, N, N),
3551         PINGROUP(dap4_din_pp5,         I2S3,         RSVD2,        GMI,          RSVD4,        RSVD4,        0x31ac, N, N),
3552         PINGROUP(dap4_dout_pp6,        I2S3,         RSVD2,        GMI,          RSVD4,        RSVD4,        0x31b0, N, N),
3553         PINGROUP(dap4_sclk_pp7,        I2S3,         RSVD2,        GMI,          RSVD4,        RSVD4,        0x31b4, N, N),
3554         PINGROUP(kb_col0_pq0,          KBC,          NAND,         TRACE,        TEST,         TEST,         0x32fc, N, N),
3555         PINGROUP(kb_col1_pq1,          KBC,          NAND,         TRACE,        TEST,         TEST,         0x3300, N, N),
3556         PINGROUP(kb_col2_pq2,          KBC,          NAND,         TRACE,        RSVD4,        RSVD4,        0x3304, N, N),
3557         PINGROUP(kb_col3_pq3,          KBC,          NAND,         TRACE,        RSVD4,        RSVD4,        0x3308, N, N),
3558         PINGROUP(kb_col4_pq4,          KBC,          NAND,         TRACE,        RSVD4,        RSVD4,        0x330c, N, N),
3559         PINGROUP(kb_col5_pq5,          KBC,          NAND,         TRACE,        RSVD4,        RSVD4,        0x3310, N, N),
3560         PINGROUP(kb_col6_pq6,          KBC,          NAND,         TRACE,        MIO,          MIO,          0x3314, N, N),
3561         PINGROUP(kb_col7_pq7,          KBC,          NAND,         TRACE,        MIO,          MIO,          0x3318, N, N),
3562         PINGROUP(kb_row0_pr0,          KBC,          NAND,         RSVD3,        RSVD4,        RSVD4,        0x32bc, N, N),
3563         PINGROUP(kb_row1_pr1,          KBC,          NAND,         RSVD3,        RSVD4,        RSVD4,        0x32c0, N, N),
3564         PINGROUP(kb_row2_pr2,          KBC,          NAND,         RSVD3,        RSVD4,        RSVD4,        0x32c4, N, N),
3565         PINGROUP(kb_row3_pr3,          KBC,          NAND,         RSVD3,        INVALID,      RSVD3,        0x32c8, N, N),
3566         PINGROUP(kb_row4_pr4,          KBC,          NAND,         TRACE,        RSVD4,        RSVD4,        0x32cc, N, N),
3567         PINGROUP(kb_row5_pr5,          KBC,          NAND,         TRACE,        OWR,          OWR,          0x32d0, N, N),
3568         PINGROUP(kb_row6_pr6,          KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32d4, N, N),
3569         PINGROUP(kb_row7_pr7,          KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32d8, N, N),
3570         PINGROUP(kb_row8_ps0,          KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32dc, N, N),
3571         PINGROUP(kb_row9_ps1,          KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32e0, N, N),
3572         PINGROUP(kb_row10_ps2,         KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32e4, N, N),
3573         PINGROUP(kb_row11_ps3,         KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32e8, N, N),
3574         PINGROUP(kb_row12_ps4,         KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32ec, N, N),
3575         PINGROUP(kb_row13_ps5,         KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32f0, N, N),
3576         PINGROUP(kb_row14_ps6,         KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32f4, N, N),
3577         PINGROUP(kb_row15_ps7,         KBC,          NAND,         SDMMC2,       MIO,          MIO,          0x32f8, N, N),
3578         PINGROUP(vi_pclk_pt0,          RSVD1,        SDMMC2,       VI,           RSVD4,        RSVD4,        0x3154, N, Y),
3579         PINGROUP(vi_mclk_pt1,          VI,           VI_ALT1,      VI_ALT2,      VI_ALT3,      VI_ALT3,      0x3158, N, Y),
3580         PINGROUP(vi_d10_pt2,           DDR,          RSVD2,        VI,           RSVD4,        RSVD4,        0x314c, N, Y),
3581         PINGROUP(vi_d11_pt3,           DDR,          RSVD2,        VI,           RSVD4,        RSVD4,        0x3150, N, Y),
3582         PINGROUP(vi_d0_pt4,            DDR,          RSVD2,        VI,           RSVD4,        RSVD4,        0x3124, N, Y),
3583         PINGROUP(gen2_i2c_scl_pt5,     I2C2,         HDCP,         GMI,          RSVD4,        RSVD4,        0x3250, Y, N),
3584         PINGROUP(gen2_i2c_sda_pt6,     I2C2,         HDCP,         GMI,          RSVD4,        RSVD4,        0x3254, Y, N),
3585         PINGROUP(sdmmc4_cmd_pt7,       I2C3,         NAND,         GMI,          SDMMC4,       SDMMC4,       0x325c, N, Y),
3586         PINGROUP(pu0,                  OWR,          UARTA,        GMI,          RSVD4,        RSVD4,        0x3184, N, N),
3587         PINGROUP(pu1,                  RSVD1,        UARTA,        GMI,          RSVD4,        RSVD4,        0x3188, N, N),
3588         PINGROUP(pu2,                  RSVD1,        UARTA,        GMI,          RSVD4,        RSVD4,        0x318c, N, N),
3589         PINGROUP(pu3,                  PWM0,         UARTA,        GMI,          RSVD4,        RSVD4,        0x3190, N, N),
3590         PINGROUP(pu4,                  PWM1,         UARTA,        GMI,          RSVD4,        RSVD4,        0x3194, N, N),
3591         PINGROUP(pu5,                  PWM2,         UARTA,        GMI,          RSVD4,        RSVD4,        0x3198, N, N),
3592         PINGROUP(pu6,                  PWM3,         UARTA,        GMI,          RSVD4,        RSVD4,        0x319c, N, N),
3593         PINGROUP(jtag_rtck_pu7,        RTCK,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x32b0, N, N),
3594         PINGROUP(pv0,                  RSVD1,        RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3040, N, N),
3595         PINGROUP(pv1,                  RSVD1,        RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3044, N, N),
3596         PINGROUP(pv2,                  OWR,          RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3060, N, N),
3597         PINGROUP(pv3,                  CLK_12M_OUT,  RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3064, N, N),
3598         PINGROUP(ddc_scl_pv4,          I2C4,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3114, N, N),
3599         PINGROUP(ddc_sda_pv5,          I2C4,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3118, N, N),
3600         PINGROUP(crt_hsync_pv6,        CRT,          RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x311c, N, N),
3601         PINGROUP(crt_vsync_pv7,        CRT,          RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3120, N, N),
3602         PINGROUP(lcd_cs1_n_pw0,        DISPLAYA,     DISPLAYB,     SPI5,         RSVD4,        RSVD4,        0x3104, N, N),
3603         PINGROUP(lcd_m1_pw1,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        RSVD4,        0x3108, N, N),
3604         PINGROUP(spi2_cs1_n_pw2,       SPI3,         SPI2,         SPI2_ALT,     I2C1,         I2C1,         0x3388, N, N),
3605         PINGROUP(spi2_cs2_n_pw3,       SPI3,         SPI2,         SPI2_ALT,     I2C1,         I2C1,         0x338c, N, N),
3606         PINGROUP(clk1_out_pw4,         EXTPERIPH1,   RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x334c, N, N),
3607         PINGROUP(clk2_out_pw5,         EXTPERIPH2,   RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3068, N, N),
3608         PINGROUP(uart3_txd_pw6,        UARTC,        RSVD2,        GMI,          RSVD4,        RSVD4,        0x3174, N, N),
3609         PINGROUP(uart3_rxd_pw7,        UARTC,        RSVD2,        GMI,          RSVD4,        RSVD4,        0x3178, N, N),
3610         PINGROUP(spi2_mosi_px0,        SPI6,         SPI2,         SPI3,         GMI,          GMI,          0x3368, N, N),
3611         PINGROUP(spi2_miso_px1,        SPI6,         SPI2,         SPI3,         GMI,          GMI,          0x336c, N, N),
3612         PINGROUP(spi2_sck_px2,         SPI6,         SPI2,         SPI3,         GMI,          GMI,          0x3374, N, N),
3613         PINGROUP(spi2_cs0_n_px3,       SPI6,         SPI2,         SPI3,         GMI,          GMI,          0x3370, N, N),
3614         PINGROUP(spi1_mosi_px4,        SPI2,         SPI1,         SPI2_ALT,     GMI,          GMI,          0x3378, N, N),
3615         PINGROUP(spi1_sck_px5,         SPI2,         SPI1,         SPI2_ALT,     GMI,          GMI,          0x337c, N, N),
3616         PINGROUP(spi1_cs0_n_px6,       SPI2,         SPI1,         SPI2_ALT,     GMI,          GMI,          0x3380, N, N),
3617         PINGROUP(spi1_miso_px7,        SPI3,         SPI1,         SPI2_ALT,     RSVD4,        RSVD4,        0x3384, N, N),
3618         PINGROUP(ulpi_clk_py0,         SPI1,         RSVD2,        UARTD,        ULPI,         RSVD2,        0x3020, N, N),
3619         PINGROUP(ulpi_dir_py1,         SPI1,         RSVD2,        UARTD,        ULPI,         RSVD2,        0x3024, N, N),
3620         PINGROUP(ulpi_nxt_py2,         SPI1,         RSVD2,        UARTD,        ULPI,         RSVD2,        0x3028, N, N),
3621         PINGROUP(ulpi_stp_py3,         SPI1,         RSVD2,        UARTD,        ULPI,         RSVD2,        0x302c, N, N),
3622         PINGROUP(sdmmc1_dat3_py4,      SDMMC1,       RSVD2,        UARTE,        UARTA,        RSVD2,        0x3050, N, N),
3623         PINGROUP(sdmmc1_dat2_py5,      SDMMC1,       RSVD2,        UARTE,        UARTA,        RSVD2,        0x3054, N, N),
3624         PINGROUP(sdmmc1_dat1_py6,      SDMMC1,       RSVD2,        UARTE,        UARTA,        RSVD2,        0x3058, N, N),
3625         PINGROUP(sdmmc1_dat0_py7,      SDMMC1,       RSVD2,        UARTE,        UARTA,        RSVD2,        0x305c, N, N),
3626         PINGROUP(sdmmc1_clk_pz0,       SDMMC1,       RSVD2,        RSVD3,        UARTA,        RSVD3,        0x3048, N, N),
3627         PINGROUP(sdmmc1_cmd_pz1,       SDMMC1,       RSVD2,        RSVD3,        UARTA,        RSVD3,        0x304c, N, N),
3628         PINGROUP(lcd_sdin_pz2,         DISPLAYA,     DISPLAYB,     SPI5,         RSVD4,        RSVD4,        0x3078, N, N),
3629         PINGROUP(lcd_wr_n_pz3,         DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         HDCP,         0x3080, N, N),
3630         PINGROUP(lcd_sck_pz4,          DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         HDCP,         0x308c, N, N),
3631         PINGROUP(sys_clk_req_pz5,      SYSCLK,       RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3320, N, N),
3632         PINGROUP(pwr_i2c_scl_pz6,      I2CPWR,       RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x32b4, Y, N),
3633         PINGROUP(pwr_i2c_sda_pz7,      I2CPWR,       RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x32b8, Y, N),
3634         PINGROUP(sdmmc4_dat0_paa0,     UARTE,        SPI3,         GMI,          SDMMC4,       SDMMC4,       0x3260, N, Y),
3635         PINGROUP(sdmmc4_dat1_paa1,     UARTE,        SPI3,         GMI,          SDMMC4,       SDMMC4,       0x3264, N, Y),
3636         PINGROUP(sdmmc4_dat2_paa2,     UARTE,        SPI3,         GMI,          SDMMC4,       SDMMC4,       0x3268, N, Y),
3637         PINGROUP(sdmmc4_dat3_paa3,     UARTE,        SPI3,         GMI,          SDMMC4,       SDMMC4,       0x326c, N, Y),
3638         PINGROUP(sdmmc4_dat4_paa4,     I2C3,         I2S4,         GMI,          SDMMC4,       SDMMC4,       0x3270, N, Y),
3639         PINGROUP(sdmmc4_dat5_paa5,     VGP3,         I2S4,         GMI,          SDMMC4,       SDMMC4,       0x3274, N, Y),
3640         PINGROUP(sdmmc4_dat6_paa6,     VGP4,         I2S4,         GMI,          SDMMC4,       SDMMC4,       0x3278, N, Y),
3641         PINGROUP(sdmmc4_dat7_paa7,     VGP5,         I2S4,         GMI,          SDMMC4,       SDMMC4,       0x327c, N, Y),
3642         PINGROUP(pbb0,                 I2S4,         RSVD2,        RSVD3,        SDMMC4,       RSVD3,        0x328c, N, N),
3643         PINGROUP(cam_i2c_scl_pbb1,     VGP1,         I2C3,         RSVD3,        SDMMC4,       RSVD3,        0x3290, Y, N),
3644         PINGROUP(cam_i2c_sda_pbb2,     VGP2,         I2C3,         RSVD3,        SDMMC4,       RSVD3,        0x3294, Y, N),
3645         PINGROUP(pbb3,                 VGP3,         DISPLAYA,     DISPLAYB,     SDMMC4,       SDMMC4,       0x3298, N, N),
3646         PINGROUP(pbb4,                 VGP4,         DISPLAYA,     DISPLAYB,     SDMMC4,       SDMMC4,       0x329c, N, N),
3647         PINGROUP(pbb5,                 VGP5,         DISPLAYA,     DISPLAYB,     SDMMC4,       SDMMC4,       0x32a0, N, N),
3648         PINGROUP(pbb6,                 VGP6,         DISPLAYA,     DISPLAYB,     SDMMC4,       SDMMC4,       0x32a4, N, N),
3649         PINGROUP(pbb7,                 I2S4,         RSVD2,        RSVD3,        SDMMC4,       RSVD3,        0x32a8, N, N),
3650         PINGROUP(cam_mclk_pcc0,        VI,           VI_ALT1,      VI_ALT3,      SDMMC4,       SDMMC4,       0x3284, N, N),
3651         PINGROUP(pcc1,                 I2S4,         RSVD2,        RSVD3,        SDMMC4,       RSVD3,        0x3288, N, N),
3652         PINGROUP(pcc2,                 I2S4,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x32ac, N, N),
3653         PINGROUP(sdmmc4_rst_n_pcc3,    VGP6,         RSVD2,        RSVD3,        SDMMC4,       RSVD3,        0x3280, N, Y),
3654         PINGROUP(sdmmc4_clk_pcc4,      INVALID,      NAND,         GMI,          SDMMC4,       SDMMC4,       0x3258, N, Y),
3655         PINGROUP(clk2_req_pcc5,        DAP,          RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x306c, N, N),
3656         PINGROUP(pex_l2_rst_n_pcc6,    PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33d8, N, N),
3657         PINGROUP(pex_l2_clkreq_n_pcc7, PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33dc, N, N),
3658         PINGROUP(pex_l0_prsnt_n_pdd0,  PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33b8, N, N),
3659         PINGROUP(pex_l0_rst_n_pdd1,    PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33bc, N, N),
3660         PINGROUP(pex_l0_clkreq_n_pdd2, PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33c0, N, N),
3661         PINGROUP(pex_wake_n_pdd3,      PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33c4, N, N),
3662         PINGROUP(pex_l1_prsnt_n_pdd4,  PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33c8, N, N),
3663         PINGROUP(pex_l1_rst_n_pdd5,    PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33cc, N, N),
3664         PINGROUP(pex_l1_clkreq_n_pdd6, PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33d0, N, N),
3665         PINGROUP(pex_l2_prsnt_n_pdd7,  PCIE,         HDA,          RSVD3,        RSVD4,        RSVD4,        0x33d4, N, N),
3666         PINGROUP(clk3_out_pee0,        EXTPERIPH3,   RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x31b8, N, N),
3667         PINGROUP(clk3_req_pee1,        DEV3,         RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x31bc, N, N),
3668         PINGROUP(clk1_req_pee2,        DAP,          HDA,          RSVD3,        RSVD4,        RSVD4,        0x3348, N, N),
3669         PINGROUP(hdmi_cec_pee3,        CEC,          RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x33e0, Y, N),
3670         PINGROUP(clk_32k_in,           CLK_32K_IN,   RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3330, N, N),
3671         PINGROUP(core_pwr_req,         CORE_PWR_REQ, RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3324, N, N),
3672         PINGROUP(cpu_pwr_req,          CPU_PWR_REQ,  RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x3328, N, N),
3673         PINGROUP(owr,                  OWR,          CEC,          RSVD3,        RSVD4,        RSVD4,        0x3334, N, N),
3674         PINGROUP(pwr_int_n,            PWR_INT_N,    RSVD2,        RSVD3,        RSVD4,        RSVD4,        0x332c, N, N),
3675         /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
3676         DRV_PINGROUP(ao1,   0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3677         DRV_PINGROUP(ao2,   0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3678         DRV_PINGROUP(at1,   0x870,  2,  3,  4,  14,  5,  19,  5,  24,  2,  28,  2),
3679         DRV_PINGROUP(at2,   0x874,  2,  3,  4,  14,  5,  19,  5,  24,  2,  28,  2),
3680         DRV_PINGROUP(at3,   0x878,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
3681         DRV_PINGROUP(at4,   0x87c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
3682         DRV_PINGROUP(at5,   0x880,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
3683         DRV_PINGROUP(cdev1, 0x884,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3684         DRV_PINGROUP(cdev2, 0x888,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3685         DRV_PINGROUP(cec,   0x938,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3686         DRV_PINGROUP(crt,   0x8f8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3687         DRV_PINGROUP(csus,  0x88c, -1, -1, -1,  12,  5,  19,  5,  24,  4,  28,  4),
3688         DRV_PINGROUP(dap1,  0x890,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3689         DRV_PINGROUP(dap2,  0x894,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3690         DRV_PINGROUP(dap3,  0x898,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3691         DRV_PINGROUP(dap4,  0x89c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3692         DRV_PINGROUP(dbg,   0x8a0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3693         DRV_PINGROUP(ddc,   0x8fc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3694         DRV_PINGROUP(dev3,  0x92c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3695         DRV_PINGROUP(gma,   0x900, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
3696         DRV_PINGROUP(gmb,   0x904, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
3697         DRV_PINGROUP(gmc,   0x908, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
3698         DRV_PINGROUP(gmd,   0x90c, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
3699         DRV_PINGROUP(gme,   0x910,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
3700         DRV_PINGROUP(gmf,   0x914,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
3701         DRV_PINGROUP(gmg,   0x918,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
3702         DRV_PINGROUP(gmh,   0x91c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
3703         DRV_PINGROUP(gpv,   0x928,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3704         DRV_PINGROUP(lcd1,  0x8a4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3705         DRV_PINGROUP(lcd2,  0x8a8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3706         DRV_PINGROUP(owr,   0x920,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3707         DRV_PINGROUP(sdio1, 0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2),
3708         DRV_PINGROUP(sdio2, 0x8ac,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2),
3709         DRV_PINGROUP(sdio3, 0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2),
3710         DRV_PINGROUP(spi,   0x8b4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3711         DRV_PINGROUP(uaa,   0x8b8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3712         DRV_PINGROUP(uab,   0x8bc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3713         DRV_PINGROUP(uart2, 0x8c0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3714         DRV_PINGROUP(uart3, 0x8c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3715         DRV_PINGROUP(uda,   0x924,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
3716         DRV_PINGROUP(vi1,   0x8c8, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
3717 };
3718
3719 static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
3720         .ngpios = NUM_GPIOS,
3721         .pins = tegra30_pins,
3722         .npins = ARRAY_SIZE(tegra30_pins),
3723         .functions = tegra30_functions,
3724         .nfunctions = ARRAY_SIZE(tegra30_functions),
3725         .groups = tegra30_groups,
3726         .ngroups = ARRAY_SIZE(tegra30_groups),
3727 };
3728
3729 static int tegra30_pinctrl_probe(struct platform_device *pdev)
3730 {
3731         return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
3732 }
3733
3734 static struct of_device_id tegra30_pinctrl_of_match[] = {
3735         { .compatible = "nvidia,tegra30-pinmux", },
3736         { },
3737 };
3738
3739 static struct platform_driver tegra30_pinctrl_driver = {
3740         .driver = {
3741                 .name = "tegra30-pinctrl",
3742                 .owner = THIS_MODULE,
3743                 .of_match_table = tegra30_pinctrl_of_match,
3744         },
3745         .probe = tegra30_pinctrl_probe,
3746         .remove = tegra_pinctrl_remove,
3747 };
3748
3749 static int __init tegra30_pinctrl_init(void)
3750 {
3751         return platform_driver_register(&tegra30_pinctrl_driver);
3752 }
3753 arch_initcall(tegra30_pinctrl_init);
3754
3755 static void __exit tegra30_pinctrl_exit(void)
3756 {
3757         platform_driver_unregister(&tegra30_pinctrl_driver);
3758 }
3759 module_exit(tegra30_pinctrl_exit);
3760
3761 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
3762 MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver");
3763 MODULE_LICENSE("GPL v2");
3764 MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);