2 * Driver for the NVIDIA Tegra pinmux
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
7 * Copyright (C) 2010 Google, Inc.
8 * Copyright (C) 2010 NVIDIA Corporation
9 * Copyright (C) 2009-2011 ST-Ericsson AB
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms and conditions of the GNU General Public License,
13 * version 2, as published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 #include <linux/err.h>
22 #include <linux/init.h>
24 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 #include <linux/slab.h>
33 #include <mach/pinconf-tegra.h>
36 #include "pinctrl-tegra.h"
40 struct pinctrl_dev *pctl;
42 const struct tegra_pinctrl_soc_data *soc;
48 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
50 return readl(pmx->regs[bank] + reg);
53 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
55 writel(val, pmx->regs[bank] + reg);
58 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
60 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
62 return pmx->soc->ngroups;
65 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
68 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
70 return pmx->soc->groups[group].name;
73 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
75 const unsigned **pins,
78 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
80 *pins = pmx->soc->groups[group].pins;
81 *num_pins = pmx->soc->groups[group].npins;
86 #ifdef CONFIG_DEBUG_FS
87 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
91 seq_printf(s, " %s", dev_name(pctldev->dev));
95 static int reserve_map(struct device *dev, struct pinctrl_map **map,
96 unsigned *reserved_maps, unsigned *num_maps,
99 unsigned old_num = *reserved_maps;
100 unsigned new_num = *num_maps + reserve;
101 struct pinctrl_map *new_map;
103 if (old_num >= new_num)
106 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
108 dev_err(dev, "krealloc(map) failed\n");
112 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
115 *reserved_maps = new_num;
120 static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
121 unsigned *num_maps, const char *group,
122 const char *function)
124 if (WARN_ON(*num_maps == *reserved_maps))
127 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
128 (*map)[*num_maps].data.mux.group = group;
129 (*map)[*num_maps].data.mux.function = function;
135 static int add_map_configs(struct device *dev, struct pinctrl_map **map,
136 unsigned *reserved_maps, unsigned *num_maps,
137 const char *group, unsigned long *configs,
138 unsigned num_configs)
140 unsigned long *dup_configs;
142 if (WARN_ON(*num_maps == *reserved_maps))
145 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
148 dev_err(dev, "kmemdup(configs) failed\n");
152 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
153 (*map)[*num_maps].data.configs.group_or_pin = group;
154 (*map)[*num_maps].data.configs.configs = dup_configs;
155 (*map)[*num_maps].data.configs.num_configs = num_configs;
161 static int add_config(struct device *dev, unsigned long **configs,
162 unsigned *num_configs, unsigned long config)
164 unsigned old_num = *num_configs;
165 unsigned new_num = old_num + 1;
166 unsigned long *new_configs;
168 new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
171 dev_err(dev, "krealloc(configs) failed\n");
175 new_configs[old_num] = config;
177 *configs = new_configs;
178 *num_configs = new_num;
183 void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
184 struct pinctrl_map *map, unsigned num_maps)
188 for (i = 0; i < num_maps; i++)
189 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
190 kfree(map[i].data.configs.configs);
195 static const struct cfg_param {
196 const char *property;
197 enum tegra_pinconf_param param;
199 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
200 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
201 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
202 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
203 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
204 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
205 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
206 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
207 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
208 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
209 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
210 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
211 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
214 int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
215 struct device_node *np,
216 struct pinctrl_map **map,
217 unsigned *reserved_maps,
221 const char *function;
223 unsigned long config;
224 unsigned long *configs = NULL;
225 unsigned num_configs = 0;
227 struct property *prop;
230 ret = of_property_read_string(np, "nvidia,function", &function);
232 /* EINVAL=missing, which is fine since it's optional */
235 "could not parse property nvidia,function\n");
239 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
240 ret = of_property_read_u32(np, cfg_params[i].property, &val);
242 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
243 ret = add_config(dev, &configs, &num_configs, config);
246 /* EINVAL=missing, which is fine since it's optional */
247 } else if (ret != -EINVAL) {
248 dev_err(dev, "could not parse property %s\n",
249 cfg_params[i].property);
254 if (function != NULL)
258 ret = of_property_count_strings(np, "nvidia,pins");
260 dev_err(dev, "could not parse property nvidia,pins\n");
265 ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
269 of_property_for_each_string(np, "nvidia,pins", prop, group) {
271 ret = add_map_mux(map, reserved_maps, num_maps,
278 ret = add_map_configs(dev, map, reserved_maps,
279 num_maps, group, configs,
293 int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
294 struct device_node *np_config,
295 struct pinctrl_map **map, unsigned *num_maps)
297 unsigned reserved_maps;
298 struct device_node *np;
305 for_each_child_of_node(np_config, np) {
306 ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
307 &reserved_maps, num_maps);
309 tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
317 static struct pinctrl_ops tegra_pinctrl_ops = {
318 .get_groups_count = tegra_pinctrl_get_groups_count,
319 .get_group_name = tegra_pinctrl_get_group_name,
320 .get_group_pins = tegra_pinctrl_get_group_pins,
321 #ifdef CONFIG_DEBUG_FS
322 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
324 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
325 .dt_free_map = tegra_pinctrl_dt_free_map,
328 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
330 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
332 return pmx->soc->nfunctions;
335 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
338 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
340 return pmx->soc->functions[function].name;
343 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
345 const char * const **groups,
346 unsigned * const num_groups)
348 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
350 *groups = pmx->soc->functions[function].groups;
351 *num_groups = pmx->soc->functions[function].ngroups;
356 static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
359 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
360 const struct tegra_pingroup *g;
364 g = &pmx->soc->groups[group];
366 if (WARN_ON(g->mux_reg < 0))
369 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
370 if (g->funcs[i] == function)
373 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
376 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
377 val &= ~(0x3 << g->mux_bit);
378 val |= i << g->mux_bit;
379 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
384 static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
385 unsigned function, unsigned group)
387 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
388 const struct tegra_pingroup *g;
391 g = &pmx->soc->groups[group];
393 if (WARN_ON(g->mux_reg < 0))
396 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
397 val &= ~(0x3 << g->mux_bit);
398 val |= g->func_safe << g->mux_bit;
399 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
402 static struct pinmux_ops tegra_pinmux_ops = {
403 .get_functions_count = tegra_pinctrl_get_funcs_count,
404 .get_function_name = tegra_pinctrl_get_func_name,
405 .get_function_groups = tegra_pinctrl_get_func_groups,
406 .enable = tegra_pinctrl_enable,
407 .disable = tegra_pinctrl_disable,
410 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
411 const struct tegra_pingroup *g,
412 enum tegra_pinconf_param param,
414 s8 *bank, s16 *reg, s8 *bit, s8 *width)
417 case TEGRA_PINCONF_PARAM_PULL:
418 *bank = g->pupd_bank;
423 case TEGRA_PINCONF_PARAM_TRISTATE:
429 case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
430 *bank = g->einput_bank;
431 *reg = g->einput_reg;
432 *bit = g->einput_bit;
435 case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
436 *bank = g->odrain_bank;
437 *reg = g->odrain_reg;
438 *bit = g->odrain_bit;
441 case TEGRA_PINCONF_PARAM_LOCK:
442 *bank = g->lock_bank;
447 case TEGRA_PINCONF_PARAM_IORESET:
448 *bank = g->ioreset_bank;
449 *reg = g->ioreset_reg;
450 *bit = g->ioreset_bit;
453 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
459 case TEGRA_PINCONF_PARAM_SCHMITT:
462 *bit = g->schmitt_bit;
465 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
471 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
475 *width = g->drvdn_width;
477 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
481 *width = g->drvup_width;
483 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
487 *width = g->slwf_width;
489 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
493 *width = g->slwr_width;
496 dev_err(pmx->dev, "Invalid config param %04x\n", param);
503 "Config param %04x not supported on group %s\n",
511 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
512 unsigned pin, unsigned long *config)
514 dev_err(pctldev->dev, "pin_config_get op not supported\n");
518 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
519 unsigned pin, unsigned long config)
521 dev_err(pctldev->dev, "pin_config_set op not supported\n");
525 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
526 unsigned group, unsigned long *config)
528 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
529 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
531 const struct tegra_pingroup *g;
537 g = &pmx->soc->groups[group];
539 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
544 val = pmx_readl(pmx, bank, reg);
545 mask = (1 << width) - 1;
546 arg = (val >> bit) & mask;
548 *config = TEGRA_PINCONF_PACK(param, arg);
553 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
554 unsigned group, unsigned long config)
556 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
557 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
558 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
559 const struct tegra_pingroup *g;
565 g = &pmx->soc->groups[group];
567 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
572 val = pmx_readl(pmx, bank, reg);
574 /* LOCK can't be cleared */
575 if (param == TEGRA_PINCONF_PARAM_LOCK) {
576 if ((val & BIT(bit)) && !arg) {
577 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
582 /* Special-case Boolean values; allow any non-zero as true */
586 /* Range-check user-supplied value */
587 mask = (1 << width) - 1;
589 dev_err(pctldev->dev,
590 "config %lx: %x too big for %d bit register\n",
595 /* Update register */
596 val &= ~(mask << bit);
598 pmx_writel(pmx, val, bank, reg);
603 #ifdef CONFIG_DEBUG_FS
604 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
605 struct seq_file *s, unsigned offset)
609 static const char *strip_prefix(const char *s)
611 const char *comma = strchr(s, ',');
618 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
619 struct seq_file *s, unsigned group)
621 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
622 const struct tegra_pingroup *g;
628 g = &pmx->soc->groups[group];
630 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
631 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
632 &bank, ®, &bit, &width);
636 val = pmx_readl(pmx, bank, reg);
638 val &= (1 << width) - 1;
640 seq_printf(s, "\n\t%s=%u",
641 strip_prefix(cfg_params[i].property), val);
645 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
647 unsigned long config)
649 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
650 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
651 const char *pname = "unknown";
654 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
655 if (cfg_params[i].param == param) {
656 pname = cfg_params[i].property;
661 seq_printf(s, "%s=%d", strip_prefix(pname), arg);
665 struct pinconf_ops tegra_pinconf_ops = {
666 .pin_config_get = tegra_pinconf_get,
667 .pin_config_set = tegra_pinconf_set,
668 .pin_config_group_get = tegra_pinconf_group_get,
669 .pin_config_group_set = tegra_pinconf_group_set,
670 #ifdef CONFIG_DEBUG_FS
671 .pin_config_dbg_show = tegra_pinconf_dbg_show,
672 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
673 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
677 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
678 .name = "Tegra GPIOs",
683 static struct pinctrl_desc tegra_pinctrl_desc = {
684 .pctlops = &tegra_pinctrl_ops,
685 .pmxops = &tegra_pinmux_ops,
686 .confops = &tegra_pinconf_ops,
687 .owner = THIS_MODULE,
690 int __devinit tegra_pinctrl_probe(struct platform_device *pdev,
691 const struct tegra_pinctrl_soc_data *soc_data)
693 struct tegra_pmx *pmx;
694 struct resource *res;
697 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
699 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
702 pmx->dev = &pdev->dev;
705 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
706 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
707 tegra_pinctrl_desc.pins = pmx->soc->pins;
708 tegra_pinctrl_desc.npins = pmx->soc->npins;
711 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
717 pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
720 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
724 for (i = 0; i < pmx->nbanks; i++) {
725 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
727 dev_err(&pdev->dev, "Missing MEM resource\n");
731 if (!devm_request_mem_region(&pdev->dev, res->start,
733 dev_name(&pdev->dev))) {
735 "Couldn't request MEM resource %d\n", i);
739 pmx->regs[i] = devm_ioremap(&pdev->dev, res->start,
742 dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
747 pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
749 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
753 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
755 platform_set_drvdata(pdev, pmx);
757 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
761 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
763 int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
765 struct tegra_pmx *pmx = platform_get_drvdata(pdev);
767 pinctrl_unregister(pmx->pctl);
771 EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);