2 * pinmux driver for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/init.h>
10 #include <linux/module.h>
11 #include <linux/irq.h>
12 #include <linux/platform_device.h>
14 #include <linux/slab.h>
15 #include <linux/err.h>
16 #include <linux/irqdomain.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/consumer.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/of_platform.h>
24 #include <linux/bitops.h>
25 #include <linux/gpio.h>
26 #include <linux/of_gpio.h>
28 #define DRIVER_NAME "pinmux-sirf"
30 #define SIRFSOC_NUM_PADS 622
31 #define SIRFSOC_RSC_PIN_MUX 0x4
33 #define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
34 #define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4)
35 #define SIRFSOC_GPIO_DSP_EN0 (0x80)
36 #define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
37 #define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C)
39 #define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1
40 #define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2
41 #define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4
42 #define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8
43 #define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10
44 #define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20
45 #define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40
46 #define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80
47 #define SIRFSOC_GPIO_CTL_PULL_MASK 0x100
48 #define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200
49 #define SIRFSOC_GPIO_CTL_DSP_INT 0x400
51 #define SIRFSOC_GPIO_NO_OF_BANKS 5
52 #define SIRFSOC_GPIO_BANK_SIZE 32
53 #define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index))
55 struct sirfsoc_gpio_bank {
56 struct of_mm_gpio_chip chip;
57 struct irq_domain *domain;
63 static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
64 static DEFINE_SPINLOCK(sgpio_lock);
67 * pad list for the pinmux subsystem
68 * refer to CS-131858-DC-6A.xls
70 static const struct pinctrl_pin_desc sirfsoc_pads[] = {
71 PINCTRL_PIN(4, "pwm0"),
72 PINCTRL_PIN(5, "pwm1"),
73 PINCTRL_PIN(6, "pwm2"),
74 PINCTRL_PIN(7, "pwm3"),
75 PINCTRL_PIN(8, "warm_rst_b"),
76 PINCTRL_PIN(9, "odo_0"),
77 PINCTRL_PIN(10, "odo_1"),
78 PINCTRL_PIN(11, "dr_dir"),
79 PINCTRL_PIN(13, "scl_1"),
80 PINCTRL_PIN(15, "sda_1"),
81 PINCTRL_PIN(16, "x_ldd[16]"),
82 PINCTRL_PIN(17, "x_ldd[17]"),
83 PINCTRL_PIN(18, "x_ldd[18]"),
84 PINCTRL_PIN(19, "x_ldd[19]"),
85 PINCTRL_PIN(20, "x_ldd[20]"),
86 PINCTRL_PIN(21, "x_ldd[21]"),
87 PINCTRL_PIN(22, "x_ldd[22]"),
88 PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
89 PINCTRL_PIN(24, "gps_sgn"),
90 PINCTRL_PIN(25, "gps_mag"),
91 PINCTRL_PIN(26, "gps_clk"),
92 PINCTRL_PIN(27, "sd_cd_b_1"),
93 PINCTRL_PIN(28, "sd_vcc_on_1"),
94 PINCTRL_PIN(29, "sd_wp_b_1"),
95 PINCTRL_PIN(30, "sd_clk_3"),
96 PINCTRL_PIN(31, "sd_cmd_3"),
98 PINCTRL_PIN(32, "x_sd_dat_3[0]"),
99 PINCTRL_PIN(33, "x_sd_dat_3[1]"),
100 PINCTRL_PIN(34, "x_sd_dat_3[2]"),
101 PINCTRL_PIN(35, "x_sd_dat_3[3]"),
102 PINCTRL_PIN(36, "x_sd_clk_4"),
103 PINCTRL_PIN(37, "x_sd_cmd_4"),
104 PINCTRL_PIN(38, "x_sd_dat_4[0]"),
105 PINCTRL_PIN(39, "x_sd_dat_4[1]"),
106 PINCTRL_PIN(40, "x_sd_dat_4[2]"),
107 PINCTRL_PIN(41, "x_sd_dat_4[3]"),
108 PINCTRL_PIN(42, "x_cko_1"),
109 PINCTRL_PIN(43, "x_ac97_bit_clk"),
110 PINCTRL_PIN(44, "x_ac97_dout"),
111 PINCTRL_PIN(45, "x_ac97_din"),
112 PINCTRL_PIN(46, "x_ac97_sync"),
113 PINCTRL_PIN(47, "x_txd_1"),
114 PINCTRL_PIN(48, "x_txd_2"),
115 PINCTRL_PIN(49, "x_rxd_1"),
116 PINCTRL_PIN(50, "x_rxd_2"),
117 PINCTRL_PIN(51, "x_usclk_0"),
118 PINCTRL_PIN(52, "x_utxd_0"),
119 PINCTRL_PIN(53, "x_urxd_0"),
120 PINCTRL_PIN(54, "x_utfs_0"),
121 PINCTRL_PIN(55, "x_urfs_0"),
122 PINCTRL_PIN(56, "x_usclk_1"),
123 PINCTRL_PIN(57, "x_utxd_1"),
124 PINCTRL_PIN(58, "x_urxd_1"),
125 PINCTRL_PIN(59, "x_utfs_1"),
126 PINCTRL_PIN(60, "x_urfs_1"),
127 PINCTRL_PIN(61, "x_usclk_2"),
128 PINCTRL_PIN(62, "x_utxd_2"),
129 PINCTRL_PIN(63, "x_urxd_2"),
131 PINCTRL_PIN(64, "x_utfs_2"),
132 PINCTRL_PIN(65, "x_urfs_2"),
133 PINCTRL_PIN(66, "x_df_we_b"),
134 PINCTRL_PIN(67, "x_df_re_b"),
135 PINCTRL_PIN(68, "x_txd_0"),
136 PINCTRL_PIN(69, "x_rxd_0"),
137 PINCTRL_PIN(78, "x_cko_0"),
138 PINCTRL_PIN(79, "x_vip_pxd[7]"),
139 PINCTRL_PIN(80, "x_vip_pxd[6]"),
140 PINCTRL_PIN(81, "x_vip_pxd[5]"),
141 PINCTRL_PIN(82, "x_vip_pxd[4]"),
142 PINCTRL_PIN(83, "x_vip_pxd[3]"),
143 PINCTRL_PIN(84, "x_vip_pxd[2]"),
144 PINCTRL_PIN(85, "x_vip_pxd[1]"),
145 PINCTRL_PIN(86, "x_vip_pxd[0]"),
146 PINCTRL_PIN(87, "x_vip_vsync"),
147 PINCTRL_PIN(88, "x_vip_hsync"),
148 PINCTRL_PIN(89, "x_vip_pxclk"),
149 PINCTRL_PIN(90, "x_sda_0"),
150 PINCTRL_PIN(91, "x_scl_0"),
151 PINCTRL_PIN(92, "x_df_ry_by"),
152 PINCTRL_PIN(93, "x_df_cs_b[1]"),
153 PINCTRL_PIN(94, "x_df_cs_b[0]"),
154 PINCTRL_PIN(95, "x_l_pclk"),
156 PINCTRL_PIN(96, "x_l_lck"),
157 PINCTRL_PIN(97, "x_l_fck"),
158 PINCTRL_PIN(98, "x_l_de"),
159 PINCTRL_PIN(99, "x_ldd[0]"),
160 PINCTRL_PIN(100, "x_ldd[1]"),
161 PINCTRL_PIN(101, "x_ldd[2]"),
162 PINCTRL_PIN(102, "x_ldd[3]"),
163 PINCTRL_PIN(103, "x_ldd[4]"),
164 PINCTRL_PIN(104, "x_ldd[5]"),
165 PINCTRL_PIN(105, "x_ldd[6]"),
166 PINCTRL_PIN(106, "x_ldd[7]"),
167 PINCTRL_PIN(107, "x_ldd[8]"),
168 PINCTRL_PIN(108, "x_ldd[9]"),
169 PINCTRL_PIN(109, "x_ldd[10]"),
170 PINCTRL_PIN(110, "x_ldd[11]"),
171 PINCTRL_PIN(111, "x_ldd[12]"),
172 PINCTRL_PIN(112, "x_ldd[13]"),
173 PINCTRL_PIN(113, "x_ldd[14]"),
174 PINCTRL_PIN(114, "x_ldd[15]"),
178 * @dev: a pointer back to containing device
179 * @virtbase: the offset to the controller in virtual memory
183 struct pinctrl_dev *pmx;
184 void __iomem *gpio_virtbase;
185 void __iomem *rsc_virtbase;
188 /* SIRFSOC_GPIO_PAD_EN set */
189 struct sirfsoc_muxmask {
194 struct sirfsoc_padmux {
195 unsigned long muxmask_counts;
196 const struct sirfsoc_muxmask *muxmask;
197 /* RSC_PIN_MUX set */
198 unsigned long funcmask;
199 unsigned long funcval;
203 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
204 * @name: the name of this specific pin group
205 * @pins: an array of discrete physical pins used in this group, taken
206 * from the driver-local pin enumeration space
207 * @num_pins: the number of pins in this group array, i.e. the number of
208 * elements in .pins so we can iterate over that array
210 struct sirfsoc_pin_group {
212 const unsigned int *pins;
213 const unsigned num_pins;
216 static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
219 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
220 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
228 static const struct sirfsoc_padmux lcd_16bits_padmux = {
229 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
230 .muxmask = lcd_16bits_sirfsoc_muxmask,
235 static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
236 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
238 static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
241 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
242 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
249 .mask = BIT(16) | BIT(17),
253 static const struct sirfsoc_padmux lcd_18bits_padmux = {
254 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
255 .muxmask = lcd_18bits_muxmask,
260 static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
261 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
263 static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
266 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
267 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
274 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
278 static const struct sirfsoc_padmux lcd_24bits_padmux = {
279 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
280 .muxmask = lcd_24bits_muxmask,
285 static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
286 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
288 static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
291 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
292 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
303 static const struct sirfsoc_padmux lcdrom_padmux = {
304 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
305 .muxmask = lcdrom_muxmask,
310 static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
311 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
313 static const struct sirfsoc_muxmask uart0_muxmask[] = {
316 .mask = BIT(4) | BIT(5),
319 .mask = BIT(23) | BIT(28),
323 static const struct sirfsoc_padmux uart0_padmux = {
324 .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
325 .muxmask = uart0_muxmask,
330 static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
332 static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
335 .mask = BIT(4) | BIT(5),
339 static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
340 .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
341 .muxmask = uart0_nostreamctrl_muxmask,
344 static const unsigned uart0_nostreamctrl_pins[] = { 68, 39 };
346 static const struct sirfsoc_muxmask uart1_muxmask[] = {
349 .mask = BIT(15) | BIT(17),
353 static const struct sirfsoc_padmux uart1_padmux = {
354 .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
355 .muxmask = uart1_muxmask,
358 static const unsigned uart1_pins[] = { 47, 49 };
360 static const struct sirfsoc_muxmask uart2_muxmask[] = {
363 .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
367 static const struct sirfsoc_padmux uart2_padmux = {
368 .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
369 .muxmask = uart2_muxmask,
374 static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
376 static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
379 .mask = BIT(16) | BIT(18),
383 static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
384 .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
385 .muxmask = uart2_nostreamctrl_muxmask,
388 static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
390 static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
393 .mask = BIT(30) | BIT(31),
396 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
400 static const struct sirfsoc_padmux sdmmc3_padmux = {
401 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
402 .muxmask = sdmmc3_muxmask,
407 static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
409 static const struct sirfsoc_muxmask spi0_muxmask[] = {
412 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
416 static const struct sirfsoc_padmux spi0_padmux = {
417 .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
418 .muxmask = spi0_muxmask,
423 static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
425 static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
428 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
432 static const struct sirfsoc_padmux sdmmc4_padmux = {
433 .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
434 .muxmask = sdmmc4_muxmask,
437 static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
439 static const struct sirfsoc_muxmask cko1_muxmask[] = {
446 static const struct sirfsoc_padmux cko1_padmux = {
447 .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
448 .muxmask = cko1_muxmask,
453 static const unsigned cko1_pins[] = { 42 };
455 static const struct sirfsoc_muxmask i2s_muxmask[] = {
459 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19)
464 static const struct sirfsoc_padmux i2s_padmux = {
465 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
466 .muxmask = i2s_muxmask,
467 .funcmask = BIT(3) | BIT(9),
471 static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 };
473 static const struct sirfsoc_muxmask ac97_muxmask[] = {
476 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
480 static const struct sirfsoc_padmux ac97_padmux = {
481 .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
482 .muxmask = ac97_muxmask,
487 static const unsigned ac97_pins[] = { 33, 34, 35, 36 };
489 static const struct sirfsoc_muxmask spi1_muxmask[] = {
492 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
496 static const struct sirfsoc_padmux spi1_padmux = {
497 .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
498 .muxmask = spi1_muxmask,
503 static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
505 static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
508 .mask = BIT(27) | BIT(28) | BIT(29),
512 static const struct sirfsoc_padmux sdmmc1_padmux = {
513 .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
514 .muxmask = sdmmc1_muxmask,
517 static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
519 static const struct sirfsoc_muxmask gps_muxmask[] = {
522 .mask = BIT(24) | BIT(25) | BIT(26),
526 static const struct sirfsoc_padmux gps_padmux = {
527 .muxmask_counts = ARRAY_SIZE(gps_muxmask),
528 .muxmask = gps_muxmask,
529 .funcmask = BIT(12) | BIT(13) | BIT(14),
533 static const unsigned gps_pins[] = { 24, 25, 26 };
535 static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
538 .mask = BIT(24) | BIT(25) | BIT(26),
544 .mask = BIT(0) | BIT(1),
548 static const struct sirfsoc_padmux sdmmc5_padmux = {
549 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
550 .muxmask = sdmmc5_muxmask,
551 .funcmask = BIT(13) | BIT(14),
552 .funcval = BIT(13) | BIT(14),
555 static const unsigned sdmmc5_pins[] = { 24, 25, 26, 61, 64, 65 };
557 static const struct sirfsoc_muxmask usp0_muxmask[] = {
560 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
564 static const struct sirfsoc_padmux usp0_padmux = {
565 .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
566 .muxmask = usp0_muxmask,
567 .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
571 static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
573 static const struct sirfsoc_muxmask usp1_muxmask[] = {
576 .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
580 static const struct sirfsoc_padmux usp1_padmux = {
581 .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
582 .muxmask = usp1_muxmask,
583 .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
587 static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
589 static const struct sirfsoc_muxmask usp2_muxmask[] = {
592 .mask = BIT(29) | BIT(30) | BIT(31),
595 .mask = BIT(0) | BIT(1),
599 static const struct sirfsoc_padmux usp2_padmux = {
600 .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
601 .muxmask = usp2_muxmask,
602 .funcmask = BIT(13) | BIT(14),
606 static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
608 static const struct sirfsoc_muxmask nand_muxmask[] = {
611 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
615 static const struct sirfsoc_padmux nand_padmux = {
616 .muxmask_counts = ARRAY_SIZE(nand_muxmask),
617 .muxmask = nand_muxmask,
622 static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
624 static const struct sirfsoc_padmux sdmmc0_padmux = {
630 static const unsigned sdmmc0_pins[] = { };
632 static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
635 .mask = BIT(2) | BIT(3),
639 static const struct sirfsoc_padmux sdmmc2_padmux = {
640 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
641 .muxmask = sdmmc2_muxmask,
646 static const unsigned sdmmc2_pins[] = { 66, 67 };
648 static const struct sirfsoc_muxmask cko0_muxmask[] = {
655 static const struct sirfsoc_padmux cko0_padmux = {
656 .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
657 .muxmask = cko0_muxmask,
660 static const unsigned cko0_pins[] = { 78 };
662 static const struct sirfsoc_muxmask vip_muxmask[] = {
665 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
666 | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
671 static const struct sirfsoc_padmux vip_padmux = {
672 .muxmask_counts = ARRAY_SIZE(vip_muxmask),
673 .muxmask = vip_muxmask,
678 static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
680 static const struct sirfsoc_muxmask i2c0_muxmask[] = {
683 .mask = BIT(26) | BIT(27),
687 static const struct sirfsoc_padmux i2c0_padmux = {
688 .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
689 .muxmask = i2c0_muxmask,
692 static const unsigned i2c0_pins[] = { 90, 91 };
694 static const struct sirfsoc_muxmask i2c1_muxmask[] = {
697 .mask = BIT(13) | BIT(15),
701 static const struct sirfsoc_padmux i2c1_padmux = {
702 .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
703 .muxmask = i2c1_muxmask,
706 static const unsigned i2c1_pins[] = { 13, 15 };
708 static const struct sirfsoc_muxmask viprom_muxmask[] = {
711 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
712 | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
720 static const struct sirfsoc_padmux viprom_padmux = {
721 .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
722 .muxmask = viprom_muxmask,
727 static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
729 static const struct sirfsoc_muxmask pwm0_muxmask[] = {
736 static const struct sirfsoc_padmux pwm0_padmux = {
737 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
738 .muxmask = pwm0_muxmask,
743 static const unsigned pwm0_pins[] = { 4 };
745 static const struct sirfsoc_muxmask pwm1_muxmask[] = {
752 static const struct sirfsoc_padmux pwm1_padmux = {
753 .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
754 .muxmask = pwm1_muxmask,
757 static const unsigned pwm1_pins[] = { 5 };
759 static const struct sirfsoc_muxmask pwm2_muxmask[] = {
766 static const struct sirfsoc_padmux pwm2_padmux = {
767 .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
768 .muxmask = pwm2_muxmask,
771 static const unsigned pwm2_pins[] = { 6 };
773 static const struct sirfsoc_muxmask pwm3_muxmask[] = {
780 static const struct sirfsoc_padmux pwm3_padmux = {
781 .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
782 .muxmask = pwm3_muxmask,
785 static const unsigned pwm3_pins[] = { 7 };
787 static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
794 static const struct sirfsoc_padmux warm_rst_padmux = {
795 .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
796 .muxmask = warm_rst_muxmask,
799 static const unsigned warm_rst_pins[] = { 8 };
801 static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
807 static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
808 .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
809 .muxmask = usb0_utmi_drvbus_muxmask,
811 .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
814 static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
816 static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
823 static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
824 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
825 .muxmask = usb1_utmi_drvbus_muxmask,
827 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
830 static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
832 static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
835 .mask = BIT(9) | BIT(10) | BIT(11),
839 static const struct sirfsoc_padmux pulse_count_padmux = {
840 .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
841 .muxmask = pulse_count_muxmask,
844 static const unsigned pulse_count_pins[] = { 9, 10, 11 };
846 #define SIRFSOC_PIN_GROUP(n, p) \
850 .num_pins = ARRAY_SIZE(p), \
853 static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
854 SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
855 SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
856 SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
857 SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
858 SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
859 SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
860 SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
861 SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
862 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
863 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
864 SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
865 SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
866 SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
867 SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
868 SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
869 SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
870 SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
871 SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
872 SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
873 SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
874 SIRFSOC_PIN_GROUP("cko0_rstgrp", cko0_pins),
875 SIRFSOC_PIN_GROUP("cko1_rstgrp", cko1_pins),
876 SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
877 SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
878 SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
879 SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
880 SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
881 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
882 SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
883 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
884 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
885 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
886 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
887 SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
888 SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
889 SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
890 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
893 static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
895 return ARRAY_SIZE(sirfsoc_pin_groups);
898 static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
901 return sirfsoc_pin_groups[selector].name;
904 static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
905 const unsigned **pins,
908 *pins = sirfsoc_pin_groups[selector].pins;
909 *num_pins = sirfsoc_pin_groups[selector].num_pins;
913 static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
916 seq_printf(s, " " DRIVER_NAME);
919 static struct pinctrl_ops sirfsoc_pctrl_ops = {
920 .get_groups_count = sirfsoc_get_groups_count,
921 .get_group_name = sirfsoc_get_group_name,
922 .get_group_pins = sirfsoc_get_group_pins,
923 .pin_dbg_show = sirfsoc_pin_dbg_show,
926 struct sirfsoc_pmx_func {
928 const char * const *groups;
929 const unsigned num_groups;
930 const struct sirfsoc_padmux *padmux;
933 static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
934 static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
935 static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
936 static const char * const lcdromgrp[] = { "lcdromgrp" };
937 static const char * const uart0grp[] = { "uart0grp" };
938 static const char * const uart1grp[] = { "uart1grp" };
939 static const char * const uart2grp[] = { "uart2grp" };
940 static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
941 static const char * const usp0grp[] = { "usp0grp" };
942 static const char * const usp1grp[] = { "usp1grp" };
943 static const char * const usp2grp[] = { "usp2grp" };
944 static const char * const i2c0grp[] = { "i2c0grp" };
945 static const char * const i2c1grp[] = { "i2c1grp" };
946 static const char * const pwm0grp[] = { "pwm0grp" };
947 static const char * const pwm1grp[] = { "pwm1grp" };
948 static const char * const pwm2grp[] = { "pwm2grp" };
949 static const char * const pwm3grp[] = { "pwm3grp" };
950 static const char * const vipgrp[] = { "vipgrp" };
951 static const char * const vipromgrp[] = { "vipromgrp" };
952 static const char * const warm_rstgrp[] = { "warm_rstgrp" };
953 static const char * const cko0grp[] = { "cko0grp" };
954 static const char * const cko1grp[] = { "cko1grp" };
955 static const char * const sdmmc0grp[] = { "sdmmc0grp" };
956 static const char * const sdmmc1grp[] = { "sdmmc1grp" };
957 static const char * const sdmmc2grp[] = { "sdmmc2grp" };
958 static const char * const sdmmc3grp[] = { "sdmmc3grp" };
959 static const char * const sdmmc4grp[] = { "sdmmc4grp" };
960 static const char * const sdmmc5grp[] = { "sdmmc5grp" };
961 static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
962 static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
963 static const char * const pulse_countgrp[] = { "pulse_countgrp" };
964 static const char * const i2sgrp[] = { "i2sgrp" };
965 static const char * const ac97grp[] = { "ac97grp" };
966 static const char * const nandgrp[] = { "nandgrp" };
967 static const char * const spi0grp[] = { "spi0grp" };
968 static const char * const spi1grp[] = { "spi1grp" };
969 static const char * const gpsgrp[] = { "gpsgrp" };
971 #define SIRFSOC_PMX_FUNCTION(n, g, m) \
975 .num_groups = ARRAY_SIZE(g), \
979 static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
980 SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
981 SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
982 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
983 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
984 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
985 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
986 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
987 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
988 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
989 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
990 SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
991 SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
992 SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
993 SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
994 SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
995 SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
996 SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
997 SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
998 SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
999 SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
1000 SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
1001 SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
1002 SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
1003 SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
1004 SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1005 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1006 SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
1007 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1008 SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
1009 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1010 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1011 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1012 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1013 SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1014 SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
1015 SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
1016 SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1019 static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
1023 const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
1024 const struct sirfsoc_muxmask *mask = mux->muxmask;
1026 for (i = 0; i < mux->muxmask_counts; i++) {
1028 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
1030 muxval = muxval & ~mask[i].mask;
1032 muxval = muxval | mask[i].mask;
1033 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
1036 if (mux->funcmask && enable) {
1039 readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
1041 (func_en_val & ~mux->funcmask) | (mux->
1043 writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
1047 static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
1050 struct sirfsoc_pmx *spmx;
1052 spmx = pinctrl_dev_get_drvdata(pmxdev);
1053 sirfsoc_pinmux_endisable(spmx, selector, true);
1058 static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
1061 struct sirfsoc_pmx *spmx;
1063 spmx = pinctrl_dev_get_drvdata(pmxdev);
1064 sirfsoc_pinmux_endisable(spmx, selector, false);
1067 static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
1069 return ARRAY_SIZE(sirfsoc_pmx_functions);
1072 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
1075 return sirfsoc_pmx_functions[selector].name;
1078 static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
1079 const char * const **groups,
1080 unsigned * const num_groups)
1082 *groups = sirfsoc_pmx_functions[selector].groups;
1083 *num_groups = sirfsoc_pmx_functions[selector].num_groups;
1087 static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
1088 struct pinctrl_gpio_range *range, unsigned offset)
1090 struct sirfsoc_pmx *spmx;
1092 int group = range->id;
1096 spmx = pinctrl_dev_get_drvdata(pmxdev);
1098 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
1099 muxval = muxval | (1 << (offset - range->pin_base));
1100 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
1105 static struct pinmux_ops sirfsoc_pinmux_ops = {
1106 .enable = sirfsoc_pinmux_enable,
1107 .disable = sirfsoc_pinmux_disable,
1108 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
1109 .get_function_name = sirfsoc_pinmux_get_func_name,
1110 .get_function_groups = sirfsoc_pinmux_get_groups,
1111 .gpio_request_enable = sirfsoc_pinmux_request_gpio,
1114 static struct pinctrl_desc sirfsoc_pinmux_desc = {
1115 .name = DRIVER_NAME,
1116 .pins = sirfsoc_pads,
1117 .npins = ARRAY_SIZE(sirfsoc_pads),
1118 .pctlops = &sirfsoc_pctrl_ops,
1119 .pmxops = &sirfsoc_pinmux_ops,
1120 .owner = THIS_MODULE,
1124 * Todo: bind irq_chip to every pinctrl_gpio_range
1126 static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
1128 .name = "sirfsoc-gpio*",
1134 .name = "sirfsoc-gpio*",
1140 .name = "sirfsoc-gpio*",
1146 .name = "sirfsoc-gpio*",
1154 static void __iomem *sirfsoc_rsc_of_iomap(void)
1156 const struct of_device_id rsc_ids[] = {
1157 { .compatible = "sirf,prima2-rsc" },
1160 struct device_node *np;
1162 np = of_find_matching_node(NULL, rsc_ids);
1164 panic("unable to find compatible rsc node in dtb\n");
1166 return of_iomap(np, 0);
1169 static int __devinit sirfsoc_pinmux_probe(struct platform_device *pdev)
1172 struct sirfsoc_pmx *spmx;
1173 struct device_node *np = pdev->dev.of_node;
1176 /* Create state holders etc for this driver */
1177 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
1181 spmx->dev = &pdev->dev;
1183 platform_set_drvdata(pdev, spmx);
1185 spmx->gpio_virtbase = of_iomap(np, 0);
1186 if (!spmx->gpio_virtbase) {
1188 dev_err(&pdev->dev, "can't map gpio registers\n");
1189 goto out_no_gpio_remap;
1192 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
1193 if (!spmx->rsc_virtbase) {
1195 dev_err(&pdev->dev, "can't map rsc registers\n");
1196 goto out_no_rsc_remap;
1199 /* Now register the pin controller and all pins it handles */
1200 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
1202 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
1207 for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++)
1208 pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
1210 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
1215 iounmap(spmx->rsc_virtbase);
1217 iounmap(spmx->gpio_virtbase);
1219 platform_set_drvdata(pdev, NULL);
1220 devm_kfree(&pdev->dev, spmx);
1224 static const struct of_device_id pinmux_ids[] __devinitconst = {
1225 { .compatible = "sirf,prima2-gpio-pinmux" },
1229 static struct platform_driver sirfsoc_pinmux_driver = {
1231 .name = DRIVER_NAME,
1232 .owner = THIS_MODULE,
1233 .of_match_table = pinmux_ids,
1235 .probe = sirfsoc_pinmux_probe,
1238 static int __init sirfsoc_pinmux_init(void)
1240 return platform_driver_register(&sirfsoc_pinmux_driver);
1242 arch_initcall(sirfsoc_pinmux_init);
1244 static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1246 struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
1247 struct sirfsoc_gpio_bank, chip);
1249 return irq_find_mapping(bank->domain, offset);
1252 static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
1254 return gpio % SIRFSOC_GPIO_BANK_SIZE;
1257 static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
1259 return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
1262 void sirfsoc_gpio_set_pull(unsigned gpio, unsigned mode)
1264 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio);
1265 int idx = sirfsoc_gpio_to_offset(gpio);
1267 unsigned long flags;
1269 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1271 spin_lock_irqsave(&sgpio_lock, flags);
1273 val = readl(bank->chip.regs + offset);
1276 case SIRFSOC_GPIO_PULL_NONE:
1277 val &= ~SIRFSOC_GPIO_CTL_PULL_MASK;
1279 case SIRFSOC_GPIO_PULL_UP:
1280 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1281 val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
1283 case SIRFSOC_GPIO_PULL_DOWN:
1284 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1285 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
1291 writel(val, bank->chip.regs + offset);
1293 spin_unlock_irqrestore(&sgpio_lock, flags);
1295 EXPORT_SYMBOL(sirfsoc_gpio_set_pull);
1297 static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
1299 return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
1302 static void sirfsoc_gpio_irq_ack(struct irq_data *d)
1304 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1305 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1307 unsigned long flags;
1309 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1311 spin_lock_irqsave(&sgpio_lock, flags);
1313 val = readl(bank->chip.regs + offset);
1315 writel(val, bank->chip.regs + offset);
1317 spin_unlock_irqrestore(&sgpio_lock, flags);
1320 static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
1323 unsigned long flags;
1325 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1327 spin_lock_irqsave(&sgpio_lock, flags);
1329 val = readl(bank->chip.regs + offset);
1330 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1331 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1332 writel(val, bank->chip.regs + offset);
1334 spin_unlock_irqrestore(&sgpio_lock, flags);
1337 static void sirfsoc_gpio_irq_mask(struct irq_data *d)
1339 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1341 __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
1344 static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
1346 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1347 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1349 unsigned long flags;
1351 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1353 spin_lock_irqsave(&sgpio_lock, flags);
1355 val = readl(bank->chip.regs + offset);
1356 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1357 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1358 writel(val, bank->chip.regs + offset);
1360 spin_unlock_irqrestore(&sgpio_lock, flags);
1363 static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
1365 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1366 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1368 unsigned long flags;
1370 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1372 spin_lock_irqsave(&sgpio_lock, flags);
1374 val = readl(bank->chip.regs + offset);
1375 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1380 case IRQ_TYPE_EDGE_RISING:
1381 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1382 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1384 case IRQ_TYPE_EDGE_FALLING:
1385 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1386 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1388 case IRQ_TYPE_EDGE_BOTH:
1389 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
1390 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1392 case IRQ_TYPE_LEVEL_LOW:
1393 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1394 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1396 case IRQ_TYPE_LEVEL_HIGH:
1397 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1398 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1402 writel(val, bank->chip.regs + offset);
1404 spin_unlock_irqrestore(&sgpio_lock, flags);
1409 static struct irq_chip sirfsoc_irq_chip = {
1410 .name = "sirf-gpio-irq",
1411 .irq_ack = sirfsoc_gpio_irq_ack,
1412 .irq_mask = sirfsoc_gpio_irq_mask,
1413 .irq_unmask = sirfsoc_gpio_irq_unmask,
1414 .irq_set_type = sirfsoc_gpio_irq_type,
1417 static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
1419 struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
1422 unsigned int first_irq;
1424 status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
1427 "%s: gpio id %d status %#x no interrupt is flaged\n",
1428 __func__, bank->id, status);
1429 handle_bad_irq(irq, desc);
1433 first_irq = bank->domain->revmap_data.legacy.first_irq;
1436 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
1439 * Here we must check whether the corresponding GPIO's interrupt
1440 * has been enabled, otherwise just skip it
1442 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
1443 pr_debug("%s: gpio id %d idx %d happens\n",
1444 __func__, bank->id, idx);
1445 generic_handle_irq(first_irq + idx);
1449 status = status >> 1;
1453 static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
1456 unsigned long flags;
1458 spin_lock_irqsave(&bank->lock, flags);
1460 val = readl(bank->chip.regs + ctrl_offset);
1461 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1462 writel(val, bank->chip.regs + ctrl_offset);
1464 spin_unlock_irqrestore(&bank->lock, flags);
1467 static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
1469 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1470 unsigned long flags;
1472 if (pinctrl_request_gpio(chip->base + offset))
1475 spin_lock_irqsave(&bank->lock, flags);
1479 * set direction as input and mask irq
1481 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1482 __sirfsoc_gpio_irq_mask(bank, offset);
1484 spin_unlock_irqrestore(&bank->lock, flags);
1489 static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
1491 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1492 unsigned long flags;
1494 spin_lock_irqsave(&bank->lock, flags);
1496 __sirfsoc_gpio_irq_mask(bank, offset);
1497 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1499 spin_unlock_irqrestore(&bank->lock, flags);
1501 pinctrl_free_gpio(chip->base + offset);
1504 static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1506 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1507 int idx = sirfsoc_gpio_to_offset(gpio);
1508 unsigned long flags;
1511 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1513 spin_lock_irqsave(&bank->lock, flags);
1515 sirfsoc_gpio_set_input(bank, offset);
1517 spin_unlock_irqrestore(&bank->lock, flags);
1522 static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
1526 unsigned long flags;
1528 spin_lock_irqsave(&bank->lock, flags);
1530 out_ctrl = readl(bank->chip.regs + offset);
1532 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1534 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1536 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1537 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1538 writel(out_ctrl, bank->chip.regs + offset);
1540 spin_unlock_irqrestore(&bank->lock, flags);
1543 static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1545 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1546 int idx = sirfsoc_gpio_to_offset(gpio);
1548 unsigned long flags;
1550 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1552 spin_lock_irqsave(&sgpio_lock, flags);
1554 sirfsoc_gpio_set_output(bank, offset, value);
1556 spin_unlock_irqrestore(&sgpio_lock, flags);
1561 static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
1563 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1565 unsigned long flags;
1567 spin_lock_irqsave(&bank->lock, flags);
1569 val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1571 spin_unlock_irqrestore(&bank->lock, flags);
1573 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
1576 static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
1579 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1581 unsigned long flags;
1583 spin_lock_irqsave(&bank->lock, flags);
1585 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1587 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1589 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1590 writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1592 spin_unlock_irqrestore(&bank->lock, flags);
1595 int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1596 irq_hw_number_t hwirq)
1598 struct sirfsoc_gpio_bank *bank = d->host_data;
1603 irq_set_chip(irq, &sirfsoc_irq_chip);
1604 irq_set_handler(irq, handle_level_irq);
1605 irq_set_chip_data(irq, bank);
1606 set_irq_flags(irq, IRQF_VALID);
1611 const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
1612 .map = sirfsoc_gpio_irq_map,
1613 .xlate = irq_domain_xlate_twocell,
1616 static int __devinit sirfsoc_gpio_probe(struct device_node *np)
1619 struct sirfsoc_gpio_bank *bank;
1621 struct platform_device *pdev;
1623 pdev = of_find_device_by_node(np);
1627 regs = of_iomap(np, 0);
1631 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1632 bank = &sgpio_bank[i];
1633 spin_lock_init(&bank->lock);
1634 bank->chip.gc.request = sirfsoc_gpio_request;
1635 bank->chip.gc.free = sirfsoc_gpio_free;
1636 bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
1637 bank->chip.gc.get = sirfsoc_gpio_get_value;
1638 bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
1639 bank->chip.gc.set = sirfsoc_gpio_set_value;
1640 bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
1641 bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
1642 bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
1643 bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
1644 bank->chip.gc.of_node = np;
1645 bank->chip.regs = regs;
1647 bank->parent_irq = platform_get_irq(pdev, i);
1648 if (bank->parent_irq < 0) {
1649 err = bank->parent_irq;
1653 err = gpiochip_add(&bank->chip.gc);
1655 pr_err("%s: error in probe function with status %d\n",
1656 np->full_name, err);
1660 bank->domain = irq_domain_add_legacy(np, SIRFSOC_GPIO_BANK_SIZE,
1661 SIRFSOC_GPIO_IRQ_START + i * SIRFSOC_GPIO_BANK_SIZE, 0,
1662 &sirfsoc_gpio_irq_simple_ops, bank);
1664 if (!bank->domain) {
1665 pr_err("%s: Failed to create irqdomain\n", np->full_name);
1670 irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
1671 irq_set_handler_data(bank->parent_irq, bank);
1679 static int __init sirfsoc_gpio_init(void)
1682 struct device_node *np;
1684 np = of_find_matching_node(NULL, pinmux_ids);
1689 return sirfsoc_gpio_probe(np);
1691 subsys_initcall(sirfsoc_gpio_init);
1693 MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
1694 "Yuping Luo <yuping.luo@csr.com>, "
1695 "Barry Song <baohua.song@csr.com>");
1696 MODULE_DESCRIPTION("SIRFSOC pin control driver");
1697 MODULE_LICENSE("GPL");