1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
4 * Copyright (C) 2021 Dario Binacchi <dariobin@libero.it>
9 #include <dm/device_compat.h>
10 #include <dm/devres.h>
11 #include <dm/pinctrl.h>
12 #include <linux/libfdt.h>
13 #include <linux/list.h>
18 * struct single_pdata - platform data
19 * @base: first configuration register
20 * @offset: index of last configuration register
21 * @mask: configuration-value mask bits
22 * @width: configuration register bit width
23 * @bits_per_mux: true if one register controls more than one pin
34 * struct single_func - pinctrl function
36 * @name: pinctrl function name
37 * @npins: number of entries in pins array
41 struct list_head node;
48 * struct single_priv - private data
49 * @bits_per_pin: number of bits per pin
50 * @npins: number of selectable pins
51 * @pin_name: temporary buffer to store the pin name
54 #if (IS_ENABLED(CONFIG_SANDBOX))
57 unsigned int bits_per_pin;
59 char pin_name[PINNAME_SIZE];
60 struct list_head functions;
64 * struct single_fdt_pin_cfg - pin configuration
66 * This structure is used for the pin configuration parameters in case
67 * the register controls only one pin.
69 * @reg: configuration register offset
70 * @val: configuration register value
72 struct single_fdt_pin_cfg {
78 * struct single_fdt_bits_cfg - pin configuration
80 * This structure is used for the pin configuration parameters in case
81 * the register controls more than one pin.
83 * @reg: configuration register offset
84 * @val: configuration register value
85 * @mask: configuration register mask
87 struct single_fdt_bits_cfg {
93 #if (!IS_ENABLED(CONFIG_SANDBOX))
95 static unsigned int single_read(struct udevice *dev, fdt_addr_t reg)
97 struct single_pdata *pdata = dev_get_plat(dev);
99 switch (pdata->width) {
104 default: /* 32 bits */
111 static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
113 struct single_pdata *pdata = dev_get_plat(dev);
115 switch (pdata->width) {
122 default: /* 32 bits */
127 #else /* CONFIG_SANDBOX */
129 static unsigned int single_read(struct udevice *dev, fdt_addr_t reg)
131 struct single_priv *priv = dev_get_priv(dev);
133 return priv->sandbox_regs[reg];
136 static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
138 struct single_priv *priv = dev_get_priv(dev);
140 priv->sandbox_regs[reg] = val;
143 #endif /* CONFIG_SANDBOX */
146 * single_get_pin_by_offset() - get a pin based on the register offset
147 * @dev: single driver instance
148 * @offset: register offset from the base
150 static int single_get_pin_by_offset(struct udevice *dev, unsigned int offset)
152 struct single_pdata *pdata = dev_get_plat(dev);
153 struct single_priv *priv = dev_get_priv(dev);
155 if (offset > pdata->offset) {
156 dev_err(dev, "mux offset out of range: 0x%x (0x%x)\n",
157 offset, pdata->offset);
161 if (pdata->bits_per_mux)
162 return (offset * BITS_PER_BYTE) / priv->bits_per_pin;
164 return offset / (pdata->width / BITS_PER_BYTE);
167 static int single_get_offset_by_pin(struct udevice *dev, unsigned int pin)
169 struct single_pdata *pdata = dev_get_plat(dev);
170 struct single_priv *priv = dev_get_priv(dev);
171 unsigned int mux_bytes;
173 if (pin >= priv->npins)
176 mux_bytes = pdata->width / BITS_PER_BYTE;
177 if (pdata->bits_per_mux) {
180 byte_num = (priv->bits_per_pin * pin) / BITS_PER_BYTE;
181 return (byte_num / mux_bytes) * mux_bytes;
184 return pin * mux_bytes;
187 static const char *single_get_pin_function(struct udevice *dev,
190 struct single_priv *priv = dev_get_priv(dev);
191 struct single_func *func;
194 list_for_each_entry(func, &priv->functions, node) {
195 for (i = 0; i < func->npins; i++) {
196 if (pin == func->pins[i])
199 if (pin < func->pins[i])
207 static int single_get_pin_muxing(struct udevice *dev, unsigned int pin,
210 struct single_pdata *pdata = dev_get_plat(dev);
211 struct single_priv *priv = dev_get_priv(dev);
215 int offset, pin_shift = 0;
217 offset = single_get_offset_by_pin(dev, pin);
221 reg = pdata->base + offset;
222 val = single_read(dev, reg);
224 if (pdata->bits_per_mux)
225 pin_shift = pin % (pdata->width / priv->bits_per_pin) *
228 val &= (pdata->mask << pin_shift);
229 fname = single_get_pin_function(dev, pin);
230 snprintf(buf, size, "%pa 0x%08x %s", ®, val,
231 fname ? fname : "UNCLAIMED");
235 static struct single_func *single_allocate_function(struct udevice *dev,
236 unsigned int group_pins)
238 struct single_func *func;
240 func = devm_kmalloc(dev, sizeof(*func), GFP_KERNEL);
242 return ERR_PTR(-ENOMEM);
244 func->pins = devm_kmalloc(dev, sizeof(unsigned int) * group_pins,
247 return ERR_PTR(-ENOMEM);
252 static int single_pin_compare(const void *s1, const void *s2)
254 int pin1 = *(const unsigned int *)s1;
255 int pin2 = *(const unsigned int *)s2;
261 * single_configure_pins() - Configure pins based on FDT data
263 * @dev: Pointer to single pin configuration device which is the parent of
264 * the pins node holding the pin configuration data.
265 * @pins: Pointer to the first element of an array of register/value pairs
266 * of type 'struct single_fdt_pin_cfg'. Each such pair describes the
267 * the pin to be configured and the value to be used for configuration.
268 * This pointer points to a 'pinctrl-single,pins' property in the
270 * @size: Size of the 'pins' array in bytes.
271 * The number of register/value pairs in the 'pins' array therefore
272 * equals to 'size / sizeof(struct single_fdt_pin_cfg)'.
273 * @fname: Function name.
275 static int single_configure_pins(struct udevice *dev,
276 const struct single_fdt_pin_cfg *pins,
277 int size, const char *fname)
279 struct single_pdata *pdata = dev_get_plat(dev);
280 struct single_priv *priv = dev_get_priv(dev);
281 int n, pin, count = size / sizeof(struct single_fdt_pin_cfg);
282 struct single_func *func;
286 /* If function mask is null, needn't enable it. */
290 func = single_allocate_function(dev, count);
292 return PTR_ERR(func);
296 for (n = 0; n < count; n++, pins++) {
297 offset = fdt32_to_cpu(pins->reg);
298 if (offset > pdata->offset) {
299 dev_err(dev, " invalid register offset 0x%x\n",
304 reg = pdata->base + offset;
305 val = fdt32_to_cpu(pins->val) & pdata->mask;
306 pin = single_get_pin_by_offset(dev, offset);
308 dev_err(dev, " failed to get pin by offset %x\n",
313 single_write(dev, (single_read(dev, reg) & ~pdata->mask) | val,
315 dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val);
316 func->pins[func->npins] = pin;
320 qsort(func->pins, func->npins, sizeof(func->pins[0]),
322 list_add(&func->node, &priv->functions);
326 static int single_configure_bits(struct udevice *dev,
327 const struct single_fdt_bits_cfg *pins,
328 int size, const char *fname)
330 struct single_pdata *pdata = dev_get_plat(dev);
331 struct single_priv *priv = dev_get_priv(dev);
332 int n, pin, count = size / sizeof(struct single_fdt_bits_cfg);
333 int npins_in_reg, pin_num_from_lsb;
334 struct single_func *func;
336 u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask;
338 /* If function mask is null, needn't enable it. */
342 npins_in_reg = pdata->width / priv->bits_per_pin;
343 func = single_allocate_function(dev, count * npins_in_reg);
345 return PTR_ERR(func);
349 for (n = 0; n < count; n++, pins++) {
350 offset = fdt32_to_cpu(pins->reg);
351 if (offset > pdata->offset) {
352 dev_dbg(dev, " invalid register offset 0x%x\n",
357 reg = pdata->base + offset;
359 pin = single_get_pin_by_offset(dev, offset);
361 dev_err(dev, " failed to get pin by offset 0x%pa\n",
366 mask = fdt32_to_cpu(pins->mask);
367 val = fdt32_to_cpu(pins->val) & mask;
368 single_write(dev, (single_read(dev, reg) & ~mask) | val, reg);
369 dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val);
372 bit_pos = __ffs(mask);
373 pin_num_from_lsb = bit_pos / priv->bits_per_pin;
374 mask_pos = pdata->mask << bit_pos;
375 val_pos = val & mask_pos;
376 submask = mask & mask_pos;
378 if ((mask & mask_pos) == 0) {
379 dev_err(dev, "Invalid mask at 0x%x\n", offset);
385 if (submask != mask_pos) {
387 "Invalid submask 0x%x at 0x%x\n",
392 func->pins[func->npins] = pin + pin_num_from_lsb;
397 qsort(func->pins, func->npins, sizeof(func->pins[0]),
399 list_add(&func->node, &priv->functions);
402 static int single_set_state(struct udevice *dev,
403 struct udevice *config)
405 const struct single_fdt_pin_cfg *prop;
406 const struct single_fdt_bits_cfg *prop_bits;
409 prop = dev_read_prop(config, "pinctrl-single,pins", &len);
412 dev_dbg(dev, "configuring pins for %s\n", config->name);
413 if (len % sizeof(struct single_fdt_pin_cfg)) {
414 dev_dbg(dev, " invalid pin configuration in fdt\n");
415 return -FDT_ERR_BADSTRUCTURE;
417 single_configure_pins(dev, prop, len, config->name);
421 /* pinctrl-single,pins not found so check for pinctrl-single,bits */
422 prop_bits = dev_read_prop(config, "pinctrl-single,bits", &len);
424 dev_dbg(dev, "configuring pins for %s\n", config->name);
425 if (len % sizeof(struct single_fdt_bits_cfg)) {
426 dev_dbg(dev, " invalid bits configuration in fdt\n");
427 return -FDT_ERR_BADSTRUCTURE;
429 single_configure_bits(dev, prop_bits, len, config->name);
433 /* Neither 'pinctrl-single,pins' nor 'pinctrl-single,bits' were found */
437 static const char *single_get_pin_name(struct udevice *dev,
438 unsigned int selector)
440 struct single_priv *priv = dev_get_priv(dev);
442 if (selector >= priv->npins)
443 snprintf(priv->pin_name, PINNAME_SIZE, "Error");
445 snprintf(priv->pin_name, PINNAME_SIZE, "PIN%u", selector);
447 return priv->pin_name;
450 static int single_get_pins_count(struct udevice *dev)
452 struct single_priv *priv = dev_get_priv(dev);
457 static int single_probe(struct udevice *dev)
459 struct single_pdata *pdata = dev_get_plat(dev);
460 struct single_priv *priv = dev_get_priv(dev);
463 INIT_LIST_HEAD(&priv->functions);
465 size = pdata->offset + pdata->width / BITS_PER_BYTE;
466 #if (CONFIG_IS_ENABLED(SANDBOX))
468 devm_kzalloc(dev, size * sizeof(*priv->sandbox_regs),
470 if (!priv->sandbox_regs)
474 priv->npins = size / (pdata->width / BITS_PER_BYTE);
475 if (pdata->bits_per_mux) {
477 dev_err(dev, "function mask needs to be non-zero\n");
481 priv->bits_per_pin = fls(pdata->mask);
482 priv->npins *= (pdata->width / priv->bits_per_pin);
485 dev_dbg(dev, "%d pins\n", priv->npins);
489 static int single_of_to_plat(struct udevice *dev)
493 struct single_pdata *pdata = dev_get_plat(dev);
496 ret = dev_read_u32(dev, "pinctrl-single,register-width", &pdata->width);
498 dev_err(dev, "missing register width\n");
502 switch (pdata->width) {
508 dev_err(dev, "wrong register width\n");
512 addr = dev_read_addr_size(dev, "reg", &size);
513 if (addr == FDT_ADDR_T_NONE) {
514 dev_err(dev, "failed to get base register size\n");
518 pdata->offset = size - pdata->width / BITS_PER_BYTE;
520 addr = dev_read_addr(dev);
521 if (addr == FDT_ADDR_T_NONE) {
522 dev_dbg(dev, "no valid base register address\n");
527 ret = dev_read_u32(dev, "pinctrl-single,function-mask", &pdata->mask);
530 dev_warn(dev, "missing function register mask\n");
533 pdata->bits_per_mux = dev_read_bool(dev, "pinctrl-single,bit-per-mux");
538 const struct pinctrl_ops single_pinctrl_ops = {
539 .get_pins_count = single_get_pins_count,
540 .get_pin_name = single_get_pin_name,
541 .set_state = single_set_state,
542 .get_pin_muxing = single_get_pin_muxing,
545 static const struct udevice_id single_pinctrl_match[] = {
546 { .compatible = "pinctrl-single" },
550 U_BOOT_DRIVER(single_pinctrl) = {
551 .name = "single-pinctrl",
552 .id = UCLASS_PINCTRL,
553 .of_match = single_pinctrl_match,
554 .ops = &single_pinctrl_ops,
555 .plat_auto = sizeof(struct single_pdata),
556 .priv_auto = sizeof(struct single_priv),
557 .of_to_plat = single_of_to_plat,
558 .probe = single_probe,