1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
4 * Copyright (C) 2021 Dario Binacchi <dariobin@libero.it>
9 #include <dm/device_compat.h>
10 #include <dm/devres.h>
11 #include <dm/of_access.h>
12 #include <dm/pinctrl.h>
13 #include <linux/libfdt.h>
14 #include <linux/list.h>
19 * struct single_pdata - platform data
20 * @base: first configuration register
21 * @offset: index of last configuration register
22 * @mask: configuration-value mask bits
23 * @width: configuration register bit width
24 * @bits_per_mux: true if one register controls more than one pin
36 * struct single_func - pinctrl function
38 * @name: pinctrl function name
39 * @npins: number of entries in pins array
43 struct list_head node;
50 * struct single_gpiofunc_range - pin ranges with same mux value of gpio fun
51 * @offset: offset base of pins
52 * @npins: number pins with the same mux value of gpio function
53 * @gpiofunc: mux value of gpio function
56 struct single_gpiofunc_range {
60 struct list_head node;
64 * struct single_priv - private data
65 * @bits_per_pin: number of bits per pin
66 * @npins: number of selectable pins
67 * @pin_name: temporary buffer to store the pin name
68 * @functions: list pin functions
69 * @gpiofuncs: list gpio functions
72 #if (IS_ENABLED(CONFIG_SANDBOX))
75 unsigned int bits_per_pin;
77 char pin_name[PINNAME_SIZE];
78 struct list_head functions;
79 struct list_head gpiofuncs;
83 * struct single_fdt_bits_cfg - pin configuration
85 * This structure is used for the pin configuration parameters in case
86 * the register controls more than one pin.
88 * @reg: configuration register offset
89 * @val: configuration register value
90 * @mask: configuration register mask
92 struct single_fdt_bits_cfg {
98 #if (!IS_ENABLED(CONFIG_SANDBOX))
100 static unsigned int single_read(struct udevice *dev, fdt_addr_t reg)
102 struct single_pdata *pdata = dev_get_plat(dev);
104 switch (pdata->width) {
109 default: /* 32 bits */
116 static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
118 struct single_pdata *pdata = dev_get_plat(dev);
120 switch (pdata->width) {
127 default: /* 32 bits */
132 #else /* CONFIG_SANDBOX */
134 static unsigned int single_read(struct udevice *dev, fdt_addr_t reg)
136 struct single_priv *priv = dev_get_priv(dev);
138 return priv->sandbox_regs[reg];
141 static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
143 struct single_priv *priv = dev_get_priv(dev);
145 priv->sandbox_regs[reg] = val;
148 #endif /* CONFIG_SANDBOX */
151 * single_get_pin_by_offset() - get a pin based on the register offset
152 * @dev: single driver instance
153 * @offset: register offset from the base
155 static int single_get_pin_by_offset(struct udevice *dev, unsigned int offset)
157 struct single_pdata *pdata = dev_get_plat(dev);
158 struct single_priv *priv = dev_get_priv(dev);
160 if (offset > pdata->offset) {
161 dev_err(dev, "mux offset out of range: 0x%x (0x%x)\n",
162 offset, pdata->offset);
166 if (pdata->bits_per_mux)
167 return (offset * BITS_PER_BYTE) / priv->bits_per_pin;
169 return offset / (pdata->width / BITS_PER_BYTE);
172 static int single_get_offset_by_pin(struct udevice *dev, unsigned int pin)
174 struct single_pdata *pdata = dev_get_plat(dev);
175 struct single_priv *priv = dev_get_priv(dev);
176 unsigned int mux_bytes;
178 if (pin >= priv->npins)
181 mux_bytes = pdata->width / BITS_PER_BYTE;
182 if (pdata->bits_per_mux) {
185 byte_num = (priv->bits_per_pin * pin) / BITS_PER_BYTE;
186 return (byte_num / mux_bytes) * mux_bytes;
189 return pin * mux_bytes;
192 static const char *single_get_pin_function(struct udevice *dev,
195 struct single_priv *priv = dev_get_priv(dev);
196 struct single_func *func;
199 list_for_each_entry(func, &priv->functions, node) {
200 for (i = 0; i < func->npins; i++) {
201 if (pin == func->pins[i])
204 if (pin < func->pins[i])
212 static int single_get_pin_muxing(struct udevice *dev, unsigned int pin,
215 struct single_pdata *pdata = dev_get_plat(dev);
216 struct single_priv *priv = dev_get_priv(dev);
220 int offset, pin_shift = 0;
222 offset = single_get_offset_by_pin(dev, pin);
226 reg = pdata->base + offset;
227 val = single_read(dev, reg);
229 if (pdata->bits_per_mux)
230 pin_shift = pin % (pdata->width / priv->bits_per_pin) *
233 val &= (pdata->mask << pin_shift);
234 fname = single_get_pin_function(dev, pin);
235 snprintf(buf, size, "%pa 0x%08x %s", ®, val,
236 fname ? fname : "UNCLAIMED");
240 static int single_request(struct udevice *dev, int pin, int flags)
242 struct single_priv *priv = dev_get_priv(dev);
243 struct single_pdata *pdata = dev_get_plat(dev);
244 struct single_gpiofunc_range *frange = NULL;
245 struct list_head *pos, *tmp;
250 /* If function mask is null, needn't enable it. */
254 list_for_each_safe(pos, tmp, &priv->gpiofuncs) {
255 frange = list_entry(pos, struct single_gpiofunc_range, node);
256 if ((pin >= frange->offset + frange->npins) ||
257 pin < frange->offset)
260 mux_bytes = pdata->width / BITS_PER_BYTE;
261 reg = pdata->base + pin * mux_bytes;
263 data = single_read(dev, reg);
264 data &= ~pdata->mask;
265 data |= frange->gpiofunc;
266 single_write(dev, data, reg);
273 static struct single_func *single_allocate_function(struct udevice *dev,
274 unsigned int group_pins)
276 struct single_func *func;
278 func = devm_kmalloc(dev, sizeof(*func), GFP_KERNEL);
280 return ERR_PTR(-ENOMEM);
282 func->pins = devm_kmalloc(dev, sizeof(unsigned int) * group_pins,
285 return ERR_PTR(-ENOMEM);
290 static int single_pin_compare(const void *s1, const void *s2)
292 int pin1 = *(const unsigned int *)s1;
293 int pin2 = *(const unsigned int *)s2;
299 * single_configure_pins() - Configure pins based on FDT data
301 * @dev: Pointer to single pin configuration device which is the parent of
302 * the pins node holding the pin configuration data.
303 * @pins: Pointer to the first element of an array of register/value pairs
304 * of type 'u32'. Each such pair describes the pin to be configured
305 * and the value to be used for configuration.
306 * The value can either be a simple value if #pinctrl-cells = 1
307 * or a configuration value and a pin mux mode value if it is 2
308 * This pointer points to a 'pinctrl-single,pins' property in the
310 * @size: Size of the 'pins' array in bytes.
311 * The number of cells in the array therefore equals to
312 * 'size / sizeof(u32)'.
313 * @fname: Function name.
315 static int single_configure_pins(struct udevice *dev,
317 int size, const char *fname)
319 struct single_pdata *pdata = dev_get_plat(dev);
320 struct single_priv *priv = dev_get_priv(dev);
321 int stride = pdata->args_count + 1;
322 int n, pin, count = size / sizeof(u32);
323 struct single_func *func;
325 u32 offset, val, mux;
327 /* If function mask is null, needn't enable it. */
331 func = single_allocate_function(dev, count);
333 return PTR_ERR(func);
337 for (n = 0; n < count; n += stride) {
338 offset = fdt32_to_cpu(pins[n]);
339 if (offset > pdata->offset) {
340 dev_err(dev, " invalid register offset 0x%x\n",
345 /* if the pinctrl-cells is 2 then the second cell contains the mux */
347 mux = fdt32_to_cpu(pins[n + 2]);
351 reg = pdata->base + offset;
352 val = (fdt32_to_cpu(pins[n + 1]) | mux) & pdata->mask;
353 pin = single_get_pin_by_offset(dev, offset);
355 dev_err(dev, " failed to get pin by offset %x\n",
360 single_write(dev, (single_read(dev, reg) & ~pdata->mask) | val,
362 dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val);
363 func->pins[func->npins] = pin;
367 qsort(func->pins, func->npins, sizeof(func->pins[0]),
369 list_add(&func->node, &priv->functions);
373 static int single_configure_bits(struct udevice *dev,
374 const struct single_fdt_bits_cfg *pins,
375 int size, const char *fname)
377 struct single_pdata *pdata = dev_get_plat(dev);
378 struct single_priv *priv = dev_get_priv(dev);
379 int n, pin, count = size / sizeof(struct single_fdt_bits_cfg);
380 int npins_in_reg, pin_num_from_lsb;
381 struct single_func *func;
383 u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask;
385 /* If function mask is null, needn't enable it. */
389 npins_in_reg = pdata->width / priv->bits_per_pin;
390 func = single_allocate_function(dev, count * npins_in_reg);
392 return PTR_ERR(func);
396 for (n = 0; n < count; n++, pins++) {
397 offset = fdt32_to_cpu(pins->reg);
398 if (offset > pdata->offset) {
399 dev_dbg(dev, " invalid register offset 0x%x\n",
404 reg = pdata->base + offset;
406 pin = single_get_pin_by_offset(dev, offset);
408 dev_err(dev, " failed to get pin by offset 0x%pa\n",
413 mask = fdt32_to_cpu(pins->mask);
414 val = fdt32_to_cpu(pins->val) & mask;
415 single_write(dev, (single_read(dev, reg) & ~mask) | val, reg);
416 dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val);
419 bit_pos = __ffs(mask);
420 pin_num_from_lsb = bit_pos / priv->bits_per_pin;
421 mask_pos = pdata->mask << bit_pos;
422 val_pos = val & mask_pos;
423 submask = mask & mask_pos;
425 if ((mask & mask_pos) == 0) {
426 dev_err(dev, "Invalid mask at 0x%x\n", offset);
432 if (submask != mask_pos) {
434 "Invalid submask 0x%x at 0x%x\n",
439 func->pins[func->npins] = pin + pin_num_from_lsb;
444 qsort(func->pins, func->npins, sizeof(func->pins[0]),
446 list_add(&func->node, &priv->functions);
449 static int single_set_state(struct udevice *dev,
450 struct udevice *config)
453 const struct single_fdt_bits_cfg *prop_bits;
456 prop = dev_read_prop(config, "pinctrl-single,pins", &len);
459 dev_dbg(dev, "configuring pins for %s\n", config->name);
460 if (len % sizeof(u32)) {
461 dev_dbg(dev, " invalid pin configuration in fdt\n");
462 return -FDT_ERR_BADSTRUCTURE;
464 single_configure_pins(dev, prop, len, config->name);
468 /* pinctrl-single,pins not found so check for pinctrl-single,bits */
469 prop_bits = dev_read_prop(config, "pinctrl-single,bits", &len);
471 dev_dbg(dev, "configuring pins for %s\n", config->name);
472 if (len % sizeof(struct single_fdt_bits_cfg)) {
473 dev_dbg(dev, " invalid bits configuration in fdt\n");
474 return -FDT_ERR_BADSTRUCTURE;
476 single_configure_bits(dev, prop_bits, len, config->name);
480 /* Neither 'pinctrl-single,pins' nor 'pinctrl-single,bits' were found */
484 static const char *single_get_pin_name(struct udevice *dev,
485 unsigned int selector)
487 struct single_priv *priv = dev_get_priv(dev);
489 if (selector >= priv->npins)
490 snprintf(priv->pin_name, PINNAME_SIZE, "Error");
492 snprintf(priv->pin_name, PINNAME_SIZE, "PIN%u", selector);
494 return priv->pin_name;
497 static int single_get_pins_count(struct udevice *dev)
499 struct single_priv *priv = dev_get_priv(dev);
504 static int single_add_gpio_func(struct udevice *dev)
506 struct single_priv *priv = dev_get_priv(dev);
507 const char *propname = "pinctrl-single,gpio-range";
508 const char *cellname = "#pinctrl-single,gpio-range-cells";
509 struct single_gpiofunc_range *range;
510 struct ofnode_phandle_args gpiospec;
514 ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), propname,
515 cellname, 0, i, &gpiospec);
516 /* Do not treat it as error. Only treat it as end condition. */
521 range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL);
526 range->offset = gpiospec.args[0];
527 range->npins = gpiospec.args[1];
528 range->gpiofunc = gpiospec.args[2];
529 list_add_tail(&range->node, &priv->gpiofuncs);
534 static int single_probe(struct udevice *dev)
536 struct single_pdata *pdata = dev_get_plat(dev);
537 struct single_priv *priv = dev_get_priv(dev);
540 INIT_LIST_HEAD(&priv->functions);
541 INIT_LIST_HEAD(&priv->gpiofuncs);
543 size = pdata->offset + pdata->width / BITS_PER_BYTE;
544 #if (IS_ENABLED(CONFIG_SANDBOX))
546 devm_kzalloc(dev, size * sizeof(*priv->sandbox_regs),
548 if (!priv->sandbox_regs)
552 /* looks like a possible divide by 0, but data->width avoids this */
553 priv->npins = size / (pdata->width / BITS_PER_BYTE);
554 if (pdata->bits_per_mux) {
556 dev_err(dev, "function mask needs to be non-zero\n");
560 priv->bits_per_pin = fls(pdata->mask);
561 priv->npins *= (pdata->width / priv->bits_per_pin);
564 if (single_add_gpio_func(dev))
565 dev_dbg(dev, "gpio functions are not added\n");
567 dev_dbg(dev, "%d pins\n", priv->npins);
571 static int single_of_to_plat(struct udevice *dev)
575 struct single_pdata *pdata = dev_get_plat(dev);
578 ret = dev_read_u32(dev, "pinctrl-single,register-width", &pdata->width);
580 dev_err(dev, "missing register width\n");
584 switch (pdata->width) {
590 dev_err(dev, "wrong register width\n");
594 addr = dev_read_addr_size_index(dev, 0, &size);
595 if (addr == FDT_ADDR_T_NONE) {
596 dev_err(dev, "failed to get base register address\n");
600 pdata->offset = size - pdata->width / BITS_PER_BYTE;
603 ret = dev_read_u32(dev, "pinctrl-single,function-mask", &pdata->mask);
606 dev_warn(dev, "missing function register mask\n");
609 pdata->bits_per_mux = dev_read_bool(dev, "pinctrl-single,bit-per-mux");
611 /* If no pinctrl-cells is present, default to old style of 2 cells with
612 * bits per mux and 1 cell otherwise.
614 ret = dev_read_u32(dev, "#pinctrl-cells", &pdata->args_count);
616 pdata->args_count = pdata->bits_per_mux ? 2 : 1;
621 const struct pinctrl_ops single_pinctrl_ops = {
622 .get_pins_count = single_get_pins_count,
623 .get_pin_name = single_get_pin_name,
624 .set_state = single_set_state,
625 .get_pin_muxing = single_get_pin_muxing,
626 .request = single_request,
629 static const struct udevice_id single_pinctrl_match[] = {
630 { .compatible = "pinctrl-single" },
634 U_BOOT_DRIVER(single_pinctrl) = {
635 .name = "single-pinctrl",
636 .id = UCLASS_PINCTRL,
637 .of_match = single_pinctrl_match,
638 .ops = &single_pinctrl_ops,
639 .plat_auto = sizeof(struct single_pdata),
640 .priv_auto = sizeof(struct single_priv),
641 .of_to_plat = single_of_to_plat,
642 .probe = single_probe,