1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Raspberry Pi RP1 GPIO unit (pinctrl + GPIO)
5 * Copyright (C) 2023 Raspberry Pi Ltd.
7 * This driver is inspired by:
8 * pinctrl-bcm2835.c, please see original file for copyright information
11 #include <linux/bitmap.h>
12 #include <linux/bitops.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/pinctrl/machine.h>
27 #include <linux/pinctrl/pinconf.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_device.h>
32 #include <linux/seq_file.h>
33 #include <linux/spinlock.h>
34 #include <linux/types.h>
37 #include "pinctrl-utils.h"
39 #define MODULE_NAME "pinctrl-rp1"
40 #define RP1_NUM_GPIOS 54
41 #define RP1_NUM_BANKS 3
43 #define RP1_RW_OFFSET 0x0000
44 #define RP1_XOR_OFFSET 0x1000
45 #define RP1_SET_OFFSET 0x2000
46 #define RP1_CLR_OFFSET 0x3000
48 #define RP1_GPIO_STATUS 0x0000
49 #define RP1_GPIO_CTRL 0x0004
51 #define RP1_GPIO_PCIE_INTE 0x011c
52 #define RP1_GPIO_PCIE_INTS 0x0124
54 #define RP1_GPIO_EVENTS_SHIFT_RAW 20
55 #define RP1_GPIO_STATUS_FALLING BIT(20)
56 #define RP1_GPIO_STATUS_RISING BIT(21)
57 #define RP1_GPIO_STATUS_LOW BIT(22)
58 #define RP1_GPIO_STATUS_HIGH BIT(23)
60 #define RP1_GPIO_EVENTS_SHIFT_FILTERED 24
61 #define RP1_GPIO_STATUS_F_FALLING BIT(24)
62 #define RP1_GPIO_STATUS_F_RISING BIT(25)
63 #define RP1_GPIO_STATUS_F_LOW BIT(26)
64 #define RP1_GPIO_STATUS_F_HIGH BIT(27)
66 #define RP1_GPIO_CTRL_FUNCSEL_LSB 0
67 #define RP1_GPIO_CTRL_FUNCSEL_MASK 0x0000001f
68 #define RP1_GPIO_CTRL_OUTOVER_LSB 12
69 #define RP1_GPIO_CTRL_OUTOVER_MASK 0x00003000
70 #define RP1_GPIO_CTRL_OEOVER_LSB 14
71 #define RP1_GPIO_CTRL_OEOVER_MASK 0x0000c000
72 #define RP1_GPIO_CTRL_INOVER_LSB 16
73 #define RP1_GPIO_CTRL_INOVER_MASK 0x00030000
74 #define RP1_GPIO_CTRL_IRQEN_FALLING BIT(20)
75 #define RP1_GPIO_CTRL_IRQEN_RISING BIT(21)
76 #define RP1_GPIO_CTRL_IRQEN_LOW BIT(22)
77 #define RP1_GPIO_CTRL_IRQEN_HIGH BIT(23)
78 #define RP1_GPIO_CTRL_IRQEN_F_FALLING BIT(24)
79 #define RP1_GPIO_CTRL_IRQEN_F_RISING BIT(25)
80 #define RP1_GPIO_CTRL_IRQEN_F_LOW BIT(26)
81 #define RP1_GPIO_CTRL_IRQEN_F_HIGH BIT(27)
82 #define RP1_GPIO_CTRL_IRQRESET BIT(28)
83 #define RP1_GPIO_CTRL_IRQOVER_LSB 30
84 #define RP1_GPIO_CTRL_IRQOVER_MASK 0xc0000000
86 #define RP1_INT_EDGE_FALLING BIT(0)
87 #define RP1_INT_EDGE_RISING BIT(1)
88 #define RP1_INT_LEVEL_LOW BIT(2)
89 #define RP1_INT_LEVEL_HIGH BIT(3)
90 #define RP1_INT_MASK 0xf
92 #define RP1_INT_EDGE_BOTH (RP1_INT_EDGE_FALLING | \
95 #define RP1_PUD_DOWN 1
98 #define RP1_FSEL_COUNT 9
100 #define RP1_FSEL_ALT0 0x00
101 #define RP1_FSEL_GPIO 0x05
102 #define RP1_FSEL_NONE 0x09
103 #define RP1_FSEL_NONE_HW 0x1f
105 #define RP1_DIR_OUTPUT 0
106 #define RP1_DIR_INPUT 1
108 #define RP1_OUTOVER_PERI 0
109 #define RP1_OUTOVER_INVPERI 1
110 #define RP1_OUTOVER_LOW 2
111 #define RP1_OUTOVER_HIGH 3
113 #define RP1_OEOVER_PERI 0
114 #define RP1_OEOVER_INVPERI 1
115 #define RP1_OEOVER_DISABLE 2
116 #define RP1_OEOVER_ENABLE 3
118 #define RP1_INOVER_PERI 0
119 #define RP1_INOVER_INVPERI 1
120 #define RP1_INOVER_LOW 2
121 #define RP1_INOVER_HIGH 3
123 #define RP1_RIO_OUT 0x00
124 #define RP1_RIO_OE 0x04
125 #define RP1_RIO_IN 0x08
127 #define RP1_PAD_SLEWFAST_MASK 0x00000001
128 #define RP1_PAD_SLEWFAST_LSB 0
129 #define RP1_PAD_SCHMITT_MASK 0x00000002
130 #define RP1_PAD_SCHMITT_LSB 1
131 #define RP1_PAD_PULL_MASK 0x0000000c
132 #define RP1_PAD_PULL_LSB 2
133 #define RP1_PAD_DRIVE_MASK 0x00000030
134 #define RP1_PAD_DRIVE_LSB 4
135 #define RP1_PAD_IN_ENABLE_MASK 0x00000040
136 #define RP1_PAD_IN_ENABLE_LSB 6
137 #define RP1_PAD_OUT_DISABLE_MASK 0x00000080
138 #define RP1_PAD_OUT_DISABLE_LSB 7
140 #define RP1_PAD_DRIVE_2MA 0x00000000
141 #define RP1_PAD_DRIVE_4MA 0x00000010
142 #define RP1_PAD_DRIVE_8MA 0x00000020
143 #define RP1_PAD_DRIVE_12MA 0x00000030
145 #define FLD_GET(r, f) (((r) & (f ## _MASK)) >> (f ## _LSB))
146 #define FLD_SET(r, f, v) r = (((r) & ~(f ## _MASK)) | ((v) << (f ## _LSB)))
150 #define RP1_MAX_FSEL 8
151 #define PIN(i, f0, f1, f2, f3, f4, f5, f6, f7, f8) \
166 #define LEGACY_MAP(n, f0, f1, f2, f3, f4, f5) \
178 struct rp1_iobank_desc {
188 struct rp1_pin_info {
267 func_invalid = func__,
270 struct rp1_pin_funcs {
271 u8 funcs[RP1_FSEL_COUNT];
276 void __iomem *gpio_base;
277 void __iomem *rio_base;
278 void __iomem *pads_base;
279 int irq[RP1_NUM_BANKS];
280 struct rp1_pin_info pins[RP1_NUM_GPIOS];
282 struct pinctrl_dev *pctl_dev;
283 struct gpio_chip gpio_chip;
284 struct pinctrl_gpio_range gpio_range;
286 raw_spinlock_t irq_lock[RP1_NUM_BANKS];
289 const struct rp1_iobank_desc rp1_iobanks[RP1_NUM_BANKS] = {
290 /* gpio inte ints rio pads */
291 { 0, 28, 0x0000, 0x011c, 0x0124, 0x0000, 0x0004 },
292 { 28, 6, 0x4000, 0x411c, 0x4124, 0x4000, 0x4004 },
293 { 34, 20, 0x8000, 0x811c, 0x8124, 0x8000, 0x8004 },
296 /* pins are just named GPIO0..GPIO53 */
297 #define RP1_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
298 static struct pinctrl_pin_desc rp1_gpio_pins[] = {
355 /* one pin per group */
356 static const char * const rp1_gpio_groups[] = {
413 static const char * const rp1_func_names[] = {
479 static const struct rp1_pin_funcs rp1_gpio_pin_funcs[] = {
480 PIN(0, spi0, dpi, uart1, i2c0, _, gpio, proc_rio, pio, spi2),
481 PIN(1, spi0, dpi, uart1, i2c0, _, gpio, proc_rio, pio, spi2),
482 PIN(2, spi0, dpi, uart1, i2c1, ir, gpio, proc_rio, pio, spi2),
483 PIN(3, spi0, dpi, uart1, i2c1, ir, gpio, proc_rio, pio, spi2),
484 PIN(4, gpclk0, dpi, uart2, i2c2, ri0, gpio, proc_rio, pio, spi3),
485 PIN(5, gpclk1, dpi, uart2, i2c2, dtr0, gpio, proc_rio, pio, spi3),
486 PIN(6, gpclk2, dpi, uart2, i2c3, dcd0, gpio, proc_rio, pio, spi3),
487 PIN(7, spi0, dpi, uart2, i2c3, dsr0, gpio, proc_rio, pio, spi3),
488 PIN(8, spi0, dpi, uart3, i2c0, _, gpio, proc_rio, pio, spi4),
489 PIN(9, spi0, dpi, uart3, i2c0, _, gpio, proc_rio, pio, spi4),
490 PIN(10, spi0, dpi, uart3, i2c1, _, gpio, proc_rio, pio, spi4),
491 PIN(11, spi0, dpi, uart3, i2c1, _, gpio, proc_rio, pio, spi4),
492 PIN(12, pwm0, dpi, uart4, i2c2, aaud, gpio, proc_rio, pio, spi5),
493 PIN(13, pwm0, dpi, uart4, i2c2, aaud, gpio, proc_rio, pio, spi5),
494 PIN(14, pwm0, dpi, uart4, i2c3, uart0, gpio, proc_rio, pio, spi5),
495 PIN(15, pwm0, dpi, uart4, i2c3, uart0, gpio, proc_rio, pio, spi5),
496 PIN(16, spi1, dpi, dsi0_te_ext, _, uart0, gpio, proc_rio, pio, _),
497 PIN(17, spi1, dpi, dsi1_te_ext, _, uart0, gpio, proc_rio, pio, _),
498 PIN(18, spi1, dpi, i2s0, pwm0, i2s1, gpio, proc_rio, pio, gpclk1),
499 PIN(19, spi1, dpi, i2s0, pwm0, i2s1, gpio, proc_rio, pio, _),
500 PIN(20, spi1, dpi, i2s0, gpclk0, i2s1, gpio, proc_rio, pio, _),
501 PIN(21, spi1, dpi, i2s0, gpclk1, i2s1, gpio, proc_rio, pio, _),
502 PIN(22, sd0, dpi, i2s0, i2c3, i2s1, gpio, proc_rio, pio, _),
503 PIN(23, sd0, dpi, i2s0, i2c3, i2s1, gpio, proc_rio, pio, _),
504 PIN(24, sd0, dpi, i2s0, _, i2s1, gpio, proc_rio, pio, spi2),
505 PIN(25, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi3),
506 PIN(26, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi5),
507 PIN(27, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi1),
508 PIN(28, sd1, i2c4, i2s2, spi6, vbus0, gpio, proc_rio, _, _),
509 PIN(29, sd1, i2c4, i2s2, spi6, vbus0, gpio, proc_rio, _, _),
510 PIN(30, sd1, i2c5, i2s2, spi6, uart5, gpio, proc_rio, _, _),
511 PIN(31, sd1, i2c5, i2s2, spi6, uart5, gpio, proc_rio, _, _),
512 PIN(32, sd1, gpclk3, i2s2, spi6, uart5, gpio, proc_rio, _, _),
513 PIN(33, sd1, gpclk4, i2s2, spi6, uart5, gpio, proc_rio, _, _),
514 PIN(34, pwm1, gpclk3, vbus0, i2c4, mic, gpio, proc_rio, _, _),
515 PIN(35, spi8, pwm1, vbus0, i2c4, mic, gpio, proc_rio, _, _),
516 PIN(36, spi8, uart5, pcie_clkreq_n, i2c5, mic, gpio, proc_rio, _, _),
517 PIN(37, spi8, uart5, mic, i2c5, pcie_clkreq_n, gpio, proc_rio, _, _),
518 PIN(38, spi8, uart5, mic, i2c6, aaud, gpio, proc_rio, dsi0_te_ext, _),
519 PIN(39, spi8, uart5, mic, i2c6, aaud, gpio, proc_rio, dsi1_te_ext, _),
520 PIN(40, pwm1, uart5, i2c4, spi6, aaud, gpio, proc_rio, _, _),
521 PIN(41, pwm1, uart5, i2c4, spi6, aaud, gpio, proc_rio, _, _),
522 PIN(42, gpclk5, uart5, vbus1, spi6, i2s2, gpio, proc_rio, _, _),
523 PIN(43, gpclk4, uart5, vbus1, spi6, i2s2, gpio, proc_rio, _, _),
524 PIN(44, gpclk5, i2c5, pwm1, spi6, i2s2, gpio, proc_rio, _, _),
525 PIN(45, pwm1, i2c5, spi7, spi6, i2s2, gpio, proc_rio, _, _),
526 PIN(46, gpclk3, i2c4, spi7, mic, i2s2, gpio, proc_rio, dsi0_te_ext, _),
527 PIN(47, gpclk5, i2c4, spi7, mic, i2s2, gpio, proc_rio, dsi1_te_ext, _),
528 PIN(48, pwm1, pcie_clkreq_n, spi7, mic, uart5, gpio, proc_rio, _, _),
529 PIN(49, spi8, spi7, i2c5, aaud, uart5, gpio, proc_rio, _, _),
530 PIN(50, spi8, spi7, i2c5, aaud, vbus2, gpio, proc_rio, _, _),
531 PIN(51, spi8, spi7, i2c6, aaud, vbus2, gpio, proc_rio, _, _),
532 PIN(52, spi8, _, i2c6, aaud, vbus3, gpio, proc_rio, _, _),
533 PIN(53, spi8, spi7, _, pcie_clkreq_n, vbus3, gpio, proc_rio, _, _),
536 static const u8 legacy_fsel_map[][8] = {
537 LEGACY_MAP(0, i2c0, _, dpi, spi2, uart1, _),
538 LEGACY_MAP(1, i2c0, _, dpi, spi2, uart1, _),
539 LEGACY_MAP(2, i2c1, _, dpi, spi2, uart1, _),
540 LEGACY_MAP(3, i2c1, _, dpi, spi2, uart1, _),
541 LEGACY_MAP(4, gpclk0, _, dpi, spi3, uart2, i2c2),
542 LEGACY_MAP(5, gpclk1, _, dpi, spi3, uart2, i2c2),
543 LEGACY_MAP(6, gpclk2, _, dpi, spi3, uart2, i2c3),
544 LEGACY_MAP(7, spi0, _, dpi, spi3, uart2, i2c3),
545 LEGACY_MAP(8, spi0, _, dpi, _, uart3, i2c0),
546 LEGACY_MAP(9, spi0, _, dpi, _, uart3, i2c0),
547 LEGACY_MAP(10, spi0, _, dpi, _, uart3, i2c1),
548 LEGACY_MAP(11, spi0, _, dpi, _, uart3, i2c1),
549 LEGACY_MAP(12, pwm0, _, dpi, spi5, uart4, i2c2),
550 LEGACY_MAP(13, pwm0, _, dpi, spi5, uart4, i2c2),
551 LEGACY_MAP(14, uart0, _, dpi, spi5, uart4, _),
552 LEGACY_MAP(15, uart0, _, dpi, spi5, uart4, _),
553 LEGACY_MAP(16, _, _, dpi, uart0, spi1, _),
554 LEGACY_MAP(17, _, _, dpi, uart0, spi1, _),
555 LEGACY_MAP(18, i2s0, _, dpi, _, spi1, pwm0),
556 LEGACY_MAP(19, i2s0, _, dpi, _, spi1, pwm0),
557 LEGACY_MAP(20, i2s0, _, dpi, _, spi1, gpclk0),
558 LEGACY_MAP(21, i2s0, _, dpi, _, spi1, gpclk1),
559 LEGACY_MAP(22, sd0, _, dpi, _, _, i2c3),
560 LEGACY_MAP(23, sd0, _, dpi, _, _, i2c3),
561 LEGACY_MAP(24, sd0, _, dpi, _, _, spi2),
562 LEGACY_MAP(25, sd0, _, dpi, _, _, spi3),
563 LEGACY_MAP(26, sd0, _, dpi, _, _, spi5),
564 LEGACY_MAP(27, sd0, _, dpi, _, _, _),
567 static const char * const irq_type_names[] = {
568 [IRQ_TYPE_NONE] = "none",
569 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
570 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
571 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
572 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
573 [IRQ_TYPE_LEVEL_LOW] = "level-low",
576 static int rp1_pinconf_set(struct pinctrl_dev *pctldev,
577 unsigned int offset, unsigned long *configs,
578 unsigned int num_configs);
580 static struct rp1_pin_info *rp1_get_pin(struct gpio_chip *chip,
583 struct rp1_pinctrl *pc = gpiochip_get_data(chip);
585 if (pc && offset < RP1_NUM_GPIOS)
586 return &pc->pins[offset];
590 static struct rp1_pin_info *rp1_get_pin_pctl(struct pinctrl_dev *pctldev,
593 struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
595 if (pc && offset < RP1_NUM_GPIOS)
596 return &pc->pins[offset];
600 static void rp1_pad_update(struct rp1_pin_info *pin, u32 clr, u32 set)
602 u32 padctrl = readl(pin->pad);
607 writel(padctrl, pin->pad);
610 static void rp1_input_enable(struct rp1_pin_info *pin, int value)
612 rp1_pad_update(pin, RP1_PAD_IN_ENABLE_MASK,
613 value ? RP1_PAD_IN_ENABLE_MASK : 0);
616 static void rp1_output_enable(struct rp1_pin_info *pin, int value)
618 rp1_pad_update(pin, RP1_PAD_OUT_DISABLE_MASK,
619 value ? 0 : RP1_PAD_OUT_DISABLE_MASK);
622 static u32 rp1_get_fsel(struct rp1_pin_info *pin)
624 u32 ctrl = readl(pin->gpio + RP1_GPIO_CTRL);
625 u32 oeover = FLD_GET(ctrl, RP1_GPIO_CTRL_OEOVER);
626 u32 fsel = FLD_GET(ctrl, RP1_GPIO_CTRL_FUNCSEL);
628 if (oeover != RP1_OEOVER_PERI || fsel >= RP1_FSEL_COUNT)
629 fsel = RP1_FSEL_NONE;
634 static void rp1_set_fsel(struct rp1_pin_info *pin, u32 fsel)
636 u32 ctrl = readl(pin->gpio + RP1_GPIO_CTRL);
638 if (fsel >= RP1_FSEL_COUNT)
639 fsel = RP1_FSEL_NONE_HW;
641 rp1_input_enable(pin, 1);
642 rp1_output_enable(pin, 1);
644 if (fsel == RP1_FSEL_NONE) {
645 FLD_SET(ctrl, RP1_GPIO_CTRL_OEOVER, RP1_OEOVER_DISABLE);
647 FLD_SET(ctrl, RP1_GPIO_CTRL_OUTOVER, RP1_OUTOVER_PERI);
648 FLD_SET(ctrl, RP1_GPIO_CTRL_OEOVER, RP1_OEOVER_PERI);
650 FLD_SET(ctrl, RP1_GPIO_CTRL_FUNCSEL, fsel);
651 writel(ctrl, pin->gpio + RP1_GPIO_CTRL);
654 static int rp1_get_dir(struct rp1_pin_info *pin)
656 return !(readl(pin->rio + RP1_RIO_OE) & (1 << pin->offset)) ?
657 RP1_DIR_INPUT : RP1_DIR_OUTPUT;
660 static void rp1_set_dir(struct rp1_pin_info *pin, bool is_input)
662 int offset = is_input ? RP1_CLR_OFFSET : RP1_SET_OFFSET;
664 writel(1 << pin->offset, pin->rio + RP1_RIO_OE + offset);
667 static int rp1_get_value(struct rp1_pin_info *pin)
669 return !!(readl(pin->rio + RP1_RIO_IN) & (1 << pin->offset));
672 static void rp1_set_value(struct rp1_pin_info *pin, int value)
674 /* Assume the pin is already an output */
675 writel(1 << pin->offset,
676 pin->rio + RP1_RIO_OUT + (value ? RP1_SET_OFFSET : RP1_CLR_OFFSET));
679 static int rp1_gpio_get(struct gpio_chip *chip, unsigned offset)
681 struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
686 ret = rp1_get_value(pin);
690 static void rp1_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
692 struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
695 rp1_set_value(pin, value);
698 static int rp1_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
700 struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
705 fsel = rp1_get_fsel(pin);
706 if (fsel != RP1_FSEL_GPIO)
708 return (rp1_get_dir(pin) == RP1_DIR_OUTPUT) ?
709 GPIO_LINE_DIRECTION_OUT :
710 GPIO_LINE_DIRECTION_IN;
713 static int rp1_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
715 struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
719 rp1_set_dir(pin, RP1_DIR_INPUT);
720 rp1_set_fsel(pin, RP1_FSEL_GPIO);
724 static int rp1_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
727 struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
731 rp1_set_value(pin, value);
732 rp1_set_dir(pin, RP1_DIR_OUTPUT);
733 rp1_set_fsel(pin, RP1_FSEL_GPIO);
737 static int rp1_gpio_set_config(struct gpio_chip *gc, unsigned offset,
738 unsigned long config)
740 struct rp1_pinctrl *pc = gpiochip_get_data(gc);
741 unsigned long configs[] = { config };
743 return rp1_pinconf_set(pc->pctl_dev, offset, configs,
744 ARRAY_SIZE(configs));
747 static const struct gpio_chip rp1_gpio_chip = {
748 .label = MODULE_NAME,
749 .owner = THIS_MODULE,
750 .request = gpiochip_generic_request,
751 .free = gpiochip_generic_free,
752 .direction_input = rp1_gpio_direction_input,
753 .direction_output = rp1_gpio_direction_output,
754 .get_direction = rp1_gpio_get_direction,
758 .set_config = rp1_gpio_set_config,
759 .ngpio = RP1_NUM_GPIOS,
763 static void rp1_gpio_irq_handler(struct irq_desc *desc)
765 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
766 struct rp1_pinctrl *pc = gpiochip_get_data(chip);
767 struct irq_chip *host_chip = irq_desc_get_chip(desc);
768 const struct rp1_iobank_desc *bank;
769 int irq = irq_desc_get_irq(desc);
773 if (pc->irq[0] == irq)
774 bank = &rp1_iobanks[0];
775 else if (pc->irq[1] == irq)
776 bank = &rp1_iobanks[1];
778 bank = &rp1_iobanks[2];
780 chained_irq_enter(host_chip, desc);
782 ints = readl(pc->gpio_base + bank->ints_offset);
783 for_each_set_bit(b, &ints, 32) {
784 struct rp1_pin_info *pin = rp1_get_pin(chip, b);
786 writel(RP1_GPIO_CTRL_IRQRESET,
787 pin->gpio + RP1_SET_OFFSET + RP1_GPIO_CTRL);
788 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
789 bank->gpio_offset + b));
792 chained_irq_exit(host_chip, desc);
795 static void rp1_gpio_irq_config(struct rp1_pin_info *pin, bool enable)
797 writel(1 << pin->offset,
798 pin->inte + (enable ? RP1_SET_OFFSET : RP1_CLR_OFFSET));
800 /* Clear any latched events */
801 writel(RP1_GPIO_CTRL_IRQRESET,
802 pin->gpio + RP1_SET_OFFSET + RP1_GPIO_CTRL);
805 static void rp1_gpio_irq_enable(struct irq_data *data)
807 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
808 unsigned gpio = irqd_to_hwirq(data);
809 struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
811 rp1_gpio_irq_config(pin, true);
814 static void rp1_gpio_irq_disable(struct irq_data *data)
816 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
817 unsigned gpio = irqd_to_hwirq(data);
818 struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
820 rp1_gpio_irq_config(pin, false);
823 static int rp1_irq_set_type(struct rp1_pin_info *pin, unsigned int type)
831 case IRQ_TYPE_EDGE_RISING:
832 irq_flags = RP1_INT_EDGE_RISING;
834 case IRQ_TYPE_EDGE_FALLING:
835 irq_flags = RP1_INT_EDGE_FALLING;
837 case IRQ_TYPE_EDGE_BOTH:
838 irq_flags = RP1_INT_EDGE_RISING | RP1_INT_EDGE_FALLING;
840 case IRQ_TYPE_LEVEL_HIGH:
841 irq_flags = RP1_INT_LEVEL_HIGH;
843 case IRQ_TYPE_LEVEL_LOW:
844 irq_flags = RP1_INT_LEVEL_LOW;
852 writel(RP1_INT_MASK << RP1_GPIO_EVENTS_SHIFT_RAW,
853 pin->gpio + RP1_CLR_OFFSET + RP1_GPIO_CTRL);
854 /* Set those that are needed */
855 writel(irq_flags << RP1_GPIO_EVENTS_SHIFT_RAW,
856 pin->gpio + RP1_SET_OFFSET + RP1_GPIO_CTRL);
857 pin->irq_type = type;
862 static int rp1_gpio_irq_set_type(struct irq_data *data, unsigned int type)
864 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
865 struct rp1_pinctrl *pc = gpiochip_get_data(chip);
866 unsigned gpio = irqd_to_hwirq(data);
867 struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
868 int bank = pin->bank;
872 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
874 ret = rp1_irq_set_type(pin, type);
876 if (type & IRQ_TYPE_EDGE_BOTH)
877 irq_set_handler_locked(data, handle_edge_irq);
879 irq_set_handler_locked(data, handle_level_irq);
882 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
887 static void rp1_gpio_irq_ack(struct irq_data *data)
889 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
890 unsigned gpio = irqd_to_hwirq(data);
891 struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
893 /* Clear any latched events */
894 writel(RP1_GPIO_CTRL_IRQRESET, pin->gpio + RP1_SET_OFFSET + RP1_GPIO_CTRL);
897 static struct irq_chip rp1_gpio_irq_chip = {
899 .irq_enable = rp1_gpio_irq_enable,
900 .irq_disable = rp1_gpio_irq_disable,
901 .irq_set_type = rp1_gpio_irq_set_type,
902 .irq_ack = rp1_gpio_irq_ack,
903 .irq_mask = rp1_gpio_irq_disable,
904 .irq_unmask = rp1_gpio_irq_enable,
905 .flags = IRQCHIP_IMMUTABLE,
908 static int rp1_pctl_get_groups_count(struct pinctrl_dev *pctldev)
910 return ARRAY_SIZE(rp1_gpio_groups);
913 static const char *rp1_pctl_get_group_name(struct pinctrl_dev *pctldev,
916 return rp1_gpio_groups[selector];
919 static enum funcs rp1_get_fsel_func(unsigned pin, unsigned fsel)
921 if (pin < RP1_NUM_GPIOS) {
922 if (fsel < RP1_FSEL_COUNT)
923 return rp1_gpio_pin_funcs[pin].funcs[fsel];
924 else if (fsel == RP1_FSEL_NONE)
930 static int rp1_pctl_get_group_pins(struct pinctrl_dev *pctldev,
932 const unsigned **pins,
935 *pins = &rp1_gpio_pins[selector].number;
941 static void rp1_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
945 struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
946 struct gpio_chip *chip = &pc->gpio_chip;
947 struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
948 u32 fsel = rp1_get_fsel(pin);
949 enum funcs func = rp1_get_fsel_func(offset, fsel);
950 int value = rp1_get_value(pin);
951 int irq = irq_find_mapping(chip->irq.domain, offset);
953 seq_printf(s, "function %s (%s) in %s; irq %d (%s)",
954 rp1_func_names[fsel], rp1_func_names[func],
956 irq, irq_type_names[pin->irq_type]);
959 static void rp1_pctl_dt_free_map(struct pinctrl_dev *pctldev,
960 struct pinctrl_map *maps, unsigned num_maps)
964 for (i = 0; i < num_maps; i++)
965 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
966 kfree(maps[i].data.configs.configs);
971 static int rp1_pctl_legacy_map_func(struct rp1_pinctrl *pc,
972 struct device_node *np, u32 pin, u32 fnum,
973 struct pinctrl_map *maps,
974 unsigned int *num_maps)
976 struct pinctrl_map *map = &maps[*num_maps];
979 if (fnum >= ARRAY_SIZE(legacy_fsel_map[0])) {
980 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
984 func = legacy_fsel_map[pin][fnum];
985 if (func == func_invalid) {
986 dev_err(pc->dev, "%pOF: brcm,function %d not supported on pin %d\n",
990 map->type = PIN_MAP_TYPE_MUX_GROUP;
991 map->data.mux.group = rp1_gpio_groups[pin];
992 map->data.mux.function = rp1_func_names[func];
998 static int rp1_pctl_legacy_map_pull(struct rp1_pinctrl *pc,
999 struct device_node *np, u32 pin, u32 pull,
1000 struct pinctrl_map *maps,
1001 unsigned int *num_maps)
1003 struct pinctrl_map *map = &maps[*num_maps];
1004 enum pin_config_param param;
1005 unsigned long *configs;
1009 param = PIN_CONFIG_BIAS_DISABLE;
1012 param = PIN_CONFIG_BIAS_PULL_DOWN;
1015 param = PIN_CONFIG_BIAS_PULL_UP;
1018 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
1022 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
1026 configs[0] = pinconf_to_config_packed(param, 0);
1027 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
1028 map->data.configs.group_or_pin = rp1_gpio_pins[pin].name;
1029 map->data.configs.configs = configs;
1030 map->data.configs.num_configs = 1;
1036 static int rp1_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
1037 struct device_node *np,
1038 struct pinctrl_map **map,
1039 unsigned int *num_maps)
1041 struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1042 struct property *pins, *funcs, *pulls;
1043 int num_pins, num_funcs, num_pulls, maps_per_pin;
1044 struct pinctrl_map *maps;
1045 unsigned long *configs = NULL;
1046 const char *function = NULL;
1047 unsigned int reserved_maps;
1048 int num_configs = 0;
1050 u32 pin, func, pull;
1052 /* Check for legacy pin declaration */
1053 pins = of_find_property(np, "brcm,pins", NULL);
1055 if (!pins) /* Assume generic bindings in this node */
1056 return pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
1058 funcs = of_find_property(np, "brcm,function", NULL);
1060 of_property_read_string(np, "function", &function);
1062 pulls = of_find_property(np, "brcm,pull", NULL);
1064 pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);
1066 if (!function && !funcs && !num_configs && !pulls) {
1068 "%pOF: no function, brcm,function, brcm,pull, etc.\n",
1073 num_pins = pins->length / 4;
1074 num_funcs = funcs ? (funcs->length / 4) : 0;
1075 num_pulls = pulls ? (pulls->length / 4) : 0;
1077 if (num_funcs > 1 && num_funcs != num_pins) {
1079 "%pOF: brcm,function must have 1 or %d entries\n",
1084 if (num_pulls > 1 && num_pulls != num_pins) {
1086 "%pOF: brcm,pull must have 1 or %d entries\n",
1092 if (function || num_funcs)
1094 if (num_configs || num_pulls)
1096 reserved_maps = num_pins * maps_per_pin;
1097 maps = kcalloc(reserved_maps, sizeof(*maps), GFP_KERNEL);
1103 for (i = 0; i < num_pins; i++) {
1104 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
1107 if (pin >= ARRAY_SIZE(legacy_fsel_map)) {
1108 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
1115 err = of_property_read_u32_index(np, "brcm,function",
1116 (num_funcs > 1) ? i : 0,
1120 err = rp1_pctl_legacy_map_func(pc, np, pin, func,
1122 } else if (function) {
1123 err = pinctrl_utils_add_map_mux(pctldev, &maps,
1124 &reserved_maps, num_maps,
1125 rp1_gpio_groups[pin],
1133 err = of_property_read_u32_index(np, "brcm,pull",
1134 (num_pulls > 1) ? i : 0,
1138 err = rp1_pctl_legacy_map_pull(pc, np, pin, pull,
1140 } else if (num_configs) {
1141 err = pinctrl_utils_add_map_configs(pctldev, &maps,
1142 &reserved_maps, num_maps,
1143 rp1_gpio_groups[pin],
1144 configs, num_configs,
1145 PIN_MAP_TYPE_CONFIGS_PIN);
1157 rp1_pctl_dt_free_map(pctldev, maps, reserved_maps);
1161 static const struct pinctrl_ops rp1_pctl_ops = {
1162 .get_groups_count = rp1_pctl_get_groups_count,
1163 .get_group_name = rp1_pctl_get_group_name,
1164 .get_group_pins = rp1_pctl_get_group_pins,
1165 .pin_dbg_show = rp1_pctl_pin_dbg_show,
1166 .dt_node_to_map = rp1_pctl_dt_node_to_map,
1167 .dt_free_map = rp1_pctl_dt_free_map,
1170 static int rp1_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
1172 struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1173 u32 fsel = rp1_get_fsel(pin);
1175 /* Return non-GPIOs to GPIO_IN */
1176 if (fsel != RP1_FSEL_GPIO) {
1177 rp1_set_dir(pin, RP1_DIR_INPUT);
1178 rp1_set_fsel(pin, RP1_FSEL_GPIO);
1184 static int rp1_pmx_get_functions_count(struct pinctrl_dev *pctldev)
1189 static const char *rp1_pmx_get_function_name(struct pinctrl_dev *pctldev,
1192 return (selector < func_count) ? rp1_func_names[selector] : NULL;
1195 static int rp1_pmx_get_function_groups(struct pinctrl_dev *pctldev,
1197 const char * const **groups,
1198 unsigned * const num_groups)
1200 /* every pin can do every function */
1201 *groups = rp1_gpio_groups;
1202 *num_groups = ARRAY_SIZE(rp1_gpio_groups);
1207 static int rp1_pmx_set(struct pinctrl_dev *pctldev, unsigned func_selector,
1208 unsigned group_selector)
1210 struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, group_selector);
1211 const u8 *pin_funcs;
1214 /* func_selector is an enum funcs, so needs translation */
1216 if (func_selector >= RP1_FSEL_COUNT) {
1217 /* Convert to an fsel number */
1218 pin_funcs = rp1_gpio_pin_funcs[pin->num].funcs;
1219 for (fsel = 0; fsel < RP1_FSEL_COUNT; fsel++) {
1220 if (pin_funcs[fsel] == func_selector)
1224 fsel = (int)func_selector;
1227 if (fsel >= RP1_FSEL_COUNT && fsel != RP1_FSEL_NONE)
1230 rp1_set_fsel(pin, fsel);
1235 static void rp1_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
1236 struct pinctrl_gpio_range *range,
1239 (void)rp1_pmx_free(pctldev, offset);
1242 static int rp1_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1243 struct pinctrl_gpio_range *range,
1247 struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1249 rp1_set_dir(pin, input);
1250 rp1_set_fsel(pin, RP1_FSEL_GPIO);
1255 static const struct pinmux_ops rp1_pmx_ops = {
1256 .free = rp1_pmx_free,
1257 .get_functions_count = rp1_pmx_get_functions_count,
1258 .get_function_name = rp1_pmx_get_function_name,
1259 .get_function_groups = rp1_pmx_get_function_groups,
1260 .set_mux = rp1_pmx_set,
1261 .gpio_disable_free = rp1_pmx_gpio_disable_free,
1262 .gpio_set_direction = rp1_pmx_gpio_set_direction,
1265 static void rp1_pull_config_set(struct rp1_pin_info *pin, unsigned int arg)
1267 u32 padctrl = readl(pin->pad);
1269 FLD_SET(padctrl, RP1_PAD_PULL, arg & 0x3);
1271 writel(padctrl, pin->pad);
1274 /* Generic pinconf methods */
1276 static int rp1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int offset,
1277 unsigned long *configs, unsigned int num_configs)
1279 struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1286 for (i = 0; i < num_configs; i++) {
1287 param = pinconf_to_config_param(configs[i]);
1288 arg = pinconf_to_config_argument(configs[i]);
1291 case PIN_CONFIG_BIAS_DISABLE:
1292 rp1_pull_config_set(pin, RP1_PUD_OFF);
1295 case PIN_CONFIG_BIAS_PULL_DOWN:
1296 rp1_pull_config_set(pin, RP1_PUD_DOWN);
1299 case PIN_CONFIG_BIAS_PULL_UP:
1300 rp1_pull_config_set(pin, RP1_PUD_UP);
1303 case PIN_CONFIG_INPUT_ENABLE:
1304 rp1_input_enable(pin, arg);
1307 case PIN_CONFIG_OUTPUT_ENABLE:
1308 rp1_output_enable(pin, arg);
1311 case PIN_CONFIG_OUTPUT:
1312 rp1_set_value(pin, arg);
1313 rp1_set_dir(pin, RP1_DIR_OUTPUT);
1314 rp1_set_fsel(pin, RP1_FSEL_GPIO);
1317 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1318 rp1_pad_update(pin, RP1_PAD_SCHMITT_MASK,
1319 arg ? RP1_PAD_SCHMITT_MASK : 0);
1322 case PIN_CONFIG_SLEW_RATE:
1323 rp1_pad_update(pin, RP1_PAD_SLEWFAST_MASK,
1324 arg ? RP1_PAD_SLEWFAST_MASK : 0);
1327 case PIN_CONFIG_DRIVE_STRENGTH:
1330 arg = RP1_PAD_DRIVE_2MA;
1333 arg = RP1_PAD_DRIVE_4MA;
1336 arg = RP1_PAD_DRIVE_8MA;
1339 arg = RP1_PAD_DRIVE_12MA;
1344 rp1_pad_update(pin, RP1_PAD_DRIVE_MASK, arg);
1350 } /* switch param type */
1351 } /* for each config */
1356 static int rp1_pinconf_get(struct pinctrl_dev *pctldev, unsigned offset,
1357 unsigned long *config)
1359 struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1360 enum pin_config_param param = pinconf_to_config_param(*config);
1367 padctrl = readl(pin->pad);
1370 case PIN_CONFIG_INPUT_ENABLE:
1371 arg = !!(padctrl & RP1_PAD_IN_ENABLE_MASK);
1373 case PIN_CONFIG_OUTPUT_ENABLE:
1374 arg = !(padctrl & RP1_PAD_OUT_DISABLE_MASK);
1376 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1377 arg = !!(padctrl & RP1_PAD_SCHMITT_MASK);
1379 case PIN_CONFIG_SLEW_RATE:
1380 arg = !!(padctrl & RP1_PAD_SLEWFAST_MASK);
1382 case PIN_CONFIG_DRIVE_STRENGTH:
1383 switch (padctrl & RP1_PAD_DRIVE_MASK) {
1384 case RP1_PAD_DRIVE_2MA:
1387 case RP1_PAD_DRIVE_4MA:
1390 case RP1_PAD_DRIVE_8MA:
1393 case RP1_PAD_DRIVE_12MA:
1398 case PIN_CONFIG_BIAS_DISABLE:
1399 arg = ((padctrl & RP1_PAD_PULL_MASK) == (RP1_PUD_OFF << RP1_PAD_PULL_LSB));
1401 case PIN_CONFIG_BIAS_PULL_DOWN:
1402 arg = ((padctrl & RP1_PAD_PULL_MASK) == (RP1_PUD_DOWN << RP1_PAD_PULL_LSB));
1405 case PIN_CONFIG_BIAS_PULL_UP:
1406 arg = ((padctrl & RP1_PAD_PULL_MASK) == (RP1_PUD_UP << RP1_PAD_PULL_LSB));
1412 *config = pinconf_to_config_packed(param, arg);
1417 static const struct pinconf_ops rp1_pinconf_ops = {
1419 .pin_config_get = rp1_pinconf_get,
1420 .pin_config_set = rp1_pinconf_set,
1423 static struct pinctrl_desc rp1_pinctrl_desc = {
1424 .name = MODULE_NAME,
1425 .pins = rp1_gpio_pins,
1426 .npins = ARRAY_SIZE(rp1_gpio_pins),
1427 .pctlops = &rp1_pctl_ops,
1428 .pmxops = &rp1_pmx_ops,
1429 .confops = &rp1_pinconf_ops,
1430 .owner = THIS_MODULE,
1433 static struct pinctrl_gpio_range rp1_pinctrl_gpio_range = {
1434 .name = MODULE_NAME,
1435 .npins = RP1_NUM_GPIOS,
1438 static const struct of_device_id rp1_pinctrl_match[] = {
1440 .compatible = "raspberrypi,rp1-gpio",
1441 .data = &rp1_pinconf_ops,
1446 static inline void __iomem *devm_auto_iomap(struct platform_device *pdev,
1449 struct device *dev = &pdev->dev;
1450 struct device_node *np = dev->of_node;
1453 return devm_of_iomap(dev, np, (int)index, NULL);
1455 return devm_platform_ioremap_resource(pdev, index);
1458 static int rp1_pinctrl_probe(struct platform_device *pdev)
1460 struct device *dev = &pdev->dev;
1461 struct device_node *np = dev->of_node;
1462 struct rp1_pinctrl *pc;
1463 struct gpio_irq_chip *girq;
1466 BUILD_BUG_ON(ARRAY_SIZE(rp1_gpio_pins) != RP1_NUM_GPIOS);
1467 BUILD_BUG_ON(ARRAY_SIZE(rp1_gpio_groups) != RP1_NUM_GPIOS);
1469 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1473 platform_set_drvdata(pdev, pc);
1476 pc->gpio_base = devm_auto_iomap(pdev, 0);
1477 if (IS_ERR(pc->gpio_base)) {
1478 dev_err(dev, "could not get GPIO IO memory\n");
1479 return PTR_ERR(pc->gpio_base);
1482 pc->rio_base = devm_auto_iomap(pdev, 1);
1483 if (IS_ERR(pc->rio_base)) {
1484 dev_err(dev, "could not get RIO IO memory\n");
1485 return PTR_ERR(pc->rio_base);
1488 pc->pads_base = devm_auto_iomap(pdev, 2);
1489 if (IS_ERR(pc->pads_base)) {
1490 dev_err(dev, "could not get PADS IO memory\n");
1491 return PTR_ERR(pc->pads_base);
1494 pc->gpio_chip = rp1_gpio_chip;
1495 pc->gpio_chip.parent = dev;
1497 for (i = 0; i < RP1_NUM_BANKS; i++) {
1498 const struct rp1_iobank_desc *bank = &rp1_iobanks[i];
1501 for (j = 0; j < bank->num_gpios; j++) {
1502 struct rp1_pin_info *pin =
1503 &pc->pins[bank->min_gpio + j];
1505 pin->num = bank->min_gpio + j;
1509 pin->gpio = pc->gpio_base + bank->gpio_offset +
1510 j * sizeof(u32) * 2;
1511 pin->inte = pc->gpio_base + bank->inte_offset;
1512 pin->ints = pc->gpio_base + bank->ints_offset;
1513 pin->rio = pc->rio_base + bank->rio_offset;
1514 pin->pad = pc->pads_base + bank->pads_offset +
1518 raw_spin_lock_init(&pc->irq_lock[i]);
1521 pc->pctl_dev = devm_pinctrl_register(dev, &rp1_pinctrl_desc, pc);
1522 if (IS_ERR(pc->pctl_dev))
1523 return PTR_ERR(pc->pctl_dev);
1525 girq = &pc->gpio_chip.irq;
1526 girq->chip = &rp1_gpio_irq_chip;
1527 girq->parent_handler = rp1_gpio_irq_handler;
1528 girq->num_parents = RP1_NUM_BANKS;
1529 girq->parents = pc->irq;
1532 * Use the same handler for all groups: this is necessary
1533 * since we use one gpiochip to cover all lines - the
1534 * irq handler then needs to figure out which group and
1535 * bank that was firing the IRQ and look up the per-group
1538 for (i = 0; i < RP1_NUM_BANKS; i++) {
1539 pc->irq[i] = irq_of_parse_and_map(np, i);
1541 girq->num_parents = i;
1546 girq->default_type = IRQ_TYPE_NONE;
1547 girq->handler = handle_level_irq;
1549 err = devm_gpiochip_add_data(dev, &pc->gpio_chip, pc);
1551 dev_err(dev, "could not add GPIO chip\n");
1555 pc->gpio_range = rp1_pinctrl_gpio_range;
1556 pc->gpio_range.base = pc->gpio_chip.base;
1557 pc->gpio_range.gc = &pc->gpio_chip;
1558 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1563 static struct platform_driver rp1_pinctrl_driver = {
1564 .probe = rp1_pinctrl_probe,
1566 .name = MODULE_NAME,
1567 .of_match_table = rp1_pinctrl_match,
1568 .suppress_bind_attrs = true,
1571 builtin_platform_driver(rp1_pinctrl_driver);