1 // SPDX-License-Identifier: GPL-2.0-only
3 * Pinctrl driver for Rockchip SoCs
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
22 #include <linux/bitops.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/of_address.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/irqchip/chained_irq.h>
33 #include <linux/clk.h>
34 #include <linux/regmap.h>
35 #include <linux/mfd/syscon.h>
36 #include <linux/string_helpers.h>
38 #include <dt-bindings/pinctrl/rockchip.h>
42 #include "pinctrl-rockchip.h"
45 * Generate a bitmask for setting a value (v) with a write mask bit in hiword
46 * register 31:16 area.
48 #define WRITE_MASK_VAL(h, l, v) \
49 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
52 * Encode variants of iomux registers into a type variable
54 #define IOMUX_GPIO_ONLY BIT(0)
55 #define IOMUX_WIDTH_4BIT BIT(1)
56 #define IOMUX_SOURCE_PMU BIT(2)
57 #define IOMUX_UNROUTED BIT(3)
58 #define IOMUX_WIDTH_3BIT BIT(4)
59 #define IOMUX_WIDTH_2BIT BIT(5)
61 #define PIN_BANK(id, pins, label) \
74 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
80 { .type = iom0, .offset = -1 }, \
81 { .type = iom1, .offset = -1 }, \
82 { .type = iom2, .offset = -1 }, \
83 { .type = iom3, .offset = -1 }, \
87 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
99 { .drv_type = type0, .offset = -1 }, \
100 { .drv_type = type1, .offset = -1 }, \
101 { .drv_type = type2, .offset = -1 }, \
102 { .drv_type = type3, .offset = -1 }, \
106 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
107 drv2, drv3, pull0, pull1, \
120 { .drv_type = drv0, .offset = -1 }, \
121 { .drv_type = drv1, .offset = -1 }, \
122 { .drv_type = drv2, .offset = -1 }, \
123 { .drv_type = drv3, .offset = -1 }, \
125 .pull_type[0] = pull0, \
126 .pull_type[1] = pull1, \
127 .pull_type[2] = pull2, \
128 .pull_type[3] = pull3, \
131 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
132 iom2, iom3, drv0, drv1, drv2, \
133 drv3, offset0, offset1, \
140 { .type = iom0, .offset = -1 }, \
141 { .type = iom1, .offset = -1 }, \
142 { .type = iom2, .offset = -1 }, \
143 { .type = iom3, .offset = -1 }, \
146 { .drv_type = drv0, .offset = offset0 }, \
147 { .drv_type = drv1, .offset = offset1 }, \
148 { .drv_type = drv2, .offset = offset2 }, \
149 { .drv_type = drv3, .offset = offset3 }, \
153 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
154 label, iom0, iom1, iom2, \
155 iom3, drv0, drv1, drv2, \
156 drv3, offset0, offset1, \
157 offset2, offset3, pull0, \
158 pull1, pull2, pull3) \
164 { .type = iom0, .offset = -1 }, \
165 { .type = iom1, .offset = -1 }, \
166 { .type = iom2, .offset = -1 }, \
167 { .type = iom3, .offset = -1 }, \
170 { .drv_type = drv0, .offset = offset0 }, \
171 { .drv_type = drv1, .offset = offset1 }, \
172 { .drv_type = drv2, .offset = offset2 }, \
173 { .drv_type = drv3, .offset = offset3 }, \
175 .pull_type[0] = pull0, \
176 .pull_type[1] = pull1, \
177 .pull_type[2] = pull2, \
178 .pull_type[3] = pull3, \
181 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
186 .route_offset = REG, \
188 .route_location = FLAG, \
191 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
192 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
194 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
195 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
197 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
198 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
200 static struct regmap_config rockchip_regmap_config = {
206 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
207 const struct rockchip_pinctrl *info,
212 for (i = 0; i < info->ngroups; i++) {
213 if (!strcmp(info->groups[i].name, name))
214 return &info->groups[i];
221 * given a pin number that is local to a pin controller, find out the pin bank
222 * and the register base of the pin bank.
224 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
227 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
229 while (pin >= (b->pin_base + b->nr_pins))
235 static struct rockchip_pin_bank *bank_num_to_bank(
236 struct rockchip_pinctrl *info,
239 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
242 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
243 if (b->bank_num == num)
247 return ERR_PTR(-EINVAL);
251 * Pinctrl_ops handling
254 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
256 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
258 return info->ngroups;
261 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
264 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
266 return info->groups[selector].name;
269 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
270 unsigned selector, const unsigned **pins,
273 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
275 if (selector >= info->ngroups)
278 *pins = info->groups[selector].pins;
279 *npins = info->groups[selector].npins;
284 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
285 struct device_node *np,
286 struct pinctrl_map **map, unsigned *num_maps)
288 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
289 const struct rockchip_pin_group *grp;
290 struct device *dev = info->dev;
291 struct pinctrl_map *new_map;
292 struct device_node *parent;
297 * first find the group of this node and check if we need to create
298 * config maps for pins
300 grp = pinctrl_name_to_group(info, np->name);
302 dev_err(dev, "unable to find group for node %pOFn\n", np);
306 map_num += grp->npins;
308 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
316 parent = of_get_parent(np);
321 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
322 new_map[0].data.mux.function = parent->name;
323 new_map[0].data.mux.group = np->name;
326 /* create config map */
328 for (i = 0; i < grp->npins; i++) {
329 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
330 new_map[i].data.configs.group_or_pin =
331 pin_get_name(pctldev, grp->pins[i]);
332 new_map[i].data.configs.configs = grp->data[i].configs;
333 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
336 dev_dbg(dev, "maps: function %s group %s num %d\n",
337 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
342 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
343 struct pinctrl_map *map, unsigned num_maps)
348 static const struct pinctrl_ops rockchip_pctrl_ops = {
349 .get_groups_count = rockchip_get_groups_count,
350 .get_group_name = rockchip_get_group_name,
351 .get_group_pins = rockchip_get_group_pins,
352 .dt_node_to_map = rockchip_dt_node_to_map,
353 .dt_free_map = rockchip_dt_free_map,
360 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
424 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
458 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
567 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
589 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
590 int *reg, u8 *bit, int *mask)
592 struct rockchip_pinctrl *info = bank->drvdata;
593 struct rockchip_pin_ctrl *ctrl = info->ctrl;
594 struct rockchip_mux_recalced_data *data;
597 for (i = 0; i < ctrl->niomux_recalced; i++) {
598 data = &ctrl->iomux_recalced[i];
599 if (data->num == bank->bank_num &&
604 if (i >= ctrl->niomux_recalced)
612 static struct rockchip_mux_route_data px30_mux_route_data[] = {
613 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
614 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
615 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
616 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
617 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
618 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
619 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
620 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
623 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
624 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
625 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
626 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
627 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
628 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
629 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
630 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
633 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
634 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
635 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
638 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
639 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
640 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
641 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
642 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
643 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
644 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
645 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
646 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
647 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
648 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
649 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
650 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
651 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
652 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
653 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
654 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
655 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
656 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
659 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
660 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
661 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
664 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
665 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
666 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
667 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
668 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
669 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
670 RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
671 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
672 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
673 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
674 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
675 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
676 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
677 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
678 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
679 RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
680 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
681 RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
682 RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
683 RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
684 RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
685 RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
686 RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
687 RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
688 RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
689 RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
690 RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
693 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
694 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
695 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
696 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
697 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
698 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
699 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
700 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
701 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
702 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
703 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
704 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
705 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
708 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
709 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
710 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
711 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
712 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
713 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
716 static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
717 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
718 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
719 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
720 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
721 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
722 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
723 RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
724 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
725 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
726 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
727 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
728 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
729 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
730 RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
731 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
732 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
733 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
734 RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
735 RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
736 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
737 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
738 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
739 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
740 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
741 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
742 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
743 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
744 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
745 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
746 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
747 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
748 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
749 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
750 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
751 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
752 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
753 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
754 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
755 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
756 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
757 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
758 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
759 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
760 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
761 RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
762 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
763 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
764 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
765 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
766 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
767 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
768 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
769 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
770 RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
771 RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
772 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
773 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
774 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
775 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
776 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
777 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
778 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
779 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
780 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
781 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
782 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
783 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
784 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
785 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
786 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
787 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
788 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
789 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
790 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
791 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
792 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
793 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
794 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
795 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
796 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
797 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
798 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
799 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
800 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
801 RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
802 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
803 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
804 RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
805 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
806 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
807 RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
808 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
809 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
812 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
813 int mux, u32 *loc, u32 *reg, u32 *value)
815 struct rockchip_pinctrl *info = bank->drvdata;
816 struct rockchip_pin_ctrl *ctrl = info->ctrl;
817 struct rockchip_mux_route_data *data;
820 for (i = 0; i < ctrl->niomux_routes; i++) {
821 data = &ctrl->iomux_routes[i];
822 if ((data->bank_num == bank->bank_num) &&
823 (data->pin == pin) && (data->func == mux))
827 if (i >= ctrl->niomux_routes)
830 *loc = data->route_location;
831 *reg = data->route_offset;
832 *value = data->route_val;
837 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
839 struct rockchip_pinctrl *info = bank->drvdata;
840 int iomux_num = (pin / 8);
841 struct regmap *regmap;
843 int reg, ret, mask, mux_type;
849 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
850 dev_err(info->dev, "pin %d is unrouted\n", pin);
854 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
857 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
858 ? info->regmap_pmu : info->regmap_base;
860 /* get basic quadrupel of mux registers and the correct reg inside */
861 mux_type = bank->iomux[iomux_num].type;
862 reg = bank->iomux[iomux_num].offset;
863 if (mux_type & IOMUX_WIDTH_4BIT) {
868 } else if (mux_type & IOMUX_WIDTH_3BIT) {
871 bit = (pin % 8 % 5) * 3;
878 if (bank->recalced_mask & BIT(pin))
879 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
881 ret = regmap_read(regmap, reg, &val);
885 return ((val >> bit) & mask);
888 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
891 struct rockchip_pinctrl *info = bank->drvdata;
892 struct device *dev = info->dev;
893 int iomux_num = (pin / 8);
898 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
899 dev_err(dev, "pin %d is unrouted\n", pin);
903 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
904 if (mux != RK_FUNC_GPIO) {
905 dev_err(dev, "pin %d only supports a gpio mux\n", pin);
914 * Set a new mux function for a pin.
916 * The register is divided into the upper and lower 16 bit. When changing
917 * a value, the previous register value is not read and changed. Instead
918 * it seems the changed bits are marked in the upper 16 bit, while the
919 * changed value gets set in the same offset in the lower 16 bit.
920 * All pin settings seem to be 2 bit wide in both the upper and lower
922 * @bank: pin bank to change
923 * @pin: pin to change
924 * @mux: new mux function to set
926 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
928 struct rockchip_pinctrl *info = bank->drvdata;
929 struct device *dev = info->dev;
930 int iomux_num = (pin / 8);
931 struct regmap *regmap;
932 int reg, ret, mask, mux_type;
934 u32 data, rmask, route_location, route_reg, route_val;
936 ret = rockchip_verify_mux(bank, pin, mux);
940 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
943 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
945 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
946 ? info->regmap_pmu : info->regmap_base;
948 /* get basic quadrupel of mux registers and the correct reg inside */
949 mux_type = bank->iomux[iomux_num].type;
950 reg = bank->iomux[iomux_num].offset;
951 if (mux_type & IOMUX_WIDTH_4BIT) {
956 } else if (mux_type & IOMUX_WIDTH_3BIT) {
959 bit = (pin % 8 % 5) * 3;
966 if (bank->recalced_mask & BIT(pin))
967 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
969 if (bank->route_mask & BIT(pin)) {
970 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
971 &route_reg, &route_val)) {
972 struct regmap *route_regmap = regmap;
974 /* handle special locations */
975 switch (route_location) {
976 case ROCKCHIP_ROUTE_PMU:
977 route_regmap = info->regmap_pmu;
979 case ROCKCHIP_ROUTE_GRF:
980 route_regmap = info->regmap_base;
984 ret = regmap_write(route_regmap, route_reg, route_val);
990 data = (mask << (bit + 16));
991 rmask = data | (data >> 16);
992 data |= (mux & mask) << bit;
993 ret = regmap_update_bits(regmap, reg, rmask, data);
998 #define PX30_PULL_PMU_OFFSET 0x10
999 #define PX30_PULL_GRF_OFFSET 0x60
1000 #define PX30_PULL_BITS_PER_PIN 2
1001 #define PX30_PULL_PINS_PER_REG 8
1002 #define PX30_PULL_BANK_STRIDE 16
1004 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1005 int pin_num, struct regmap **regmap,
1008 struct rockchip_pinctrl *info = bank->drvdata;
1010 /* The first 32 pins of the first bank are located in PMU */
1011 if (bank->bank_num == 0) {
1012 *regmap = info->regmap_pmu;
1013 *reg = PX30_PULL_PMU_OFFSET;
1015 *regmap = info->regmap_base;
1016 *reg = PX30_PULL_GRF_OFFSET;
1018 /* correct the offset, as we're starting with the 2nd bank */
1020 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1023 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1024 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1025 *bit *= PX30_PULL_BITS_PER_PIN;
1028 #define PX30_DRV_PMU_OFFSET 0x20
1029 #define PX30_DRV_GRF_OFFSET 0xf0
1030 #define PX30_DRV_BITS_PER_PIN 2
1031 #define PX30_DRV_PINS_PER_REG 8
1032 #define PX30_DRV_BANK_STRIDE 16
1034 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1035 int pin_num, struct regmap **regmap,
1038 struct rockchip_pinctrl *info = bank->drvdata;
1040 /* The first 32 pins of the first bank are located in PMU */
1041 if (bank->bank_num == 0) {
1042 *regmap = info->regmap_pmu;
1043 *reg = PX30_DRV_PMU_OFFSET;
1045 *regmap = info->regmap_base;
1046 *reg = PX30_DRV_GRF_OFFSET;
1048 /* correct the offset, as we're starting with the 2nd bank */
1050 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1053 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1054 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1055 *bit *= PX30_DRV_BITS_PER_PIN;
1058 #define PX30_SCHMITT_PMU_OFFSET 0x38
1059 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1060 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1061 #define PX30_SCHMITT_BANK_STRIDE 16
1062 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1064 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1066 struct regmap **regmap,
1069 struct rockchip_pinctrl *info = bank->drvdata;
1072 if (bank->bank_num == 0) {
1073 *regmap = info->regmap_pmu;
1074 *reg = PX30_SCHMITT_PMU_OFFSET;
1075 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1077 *regmap = info->regmap_base;
1078 *reg = PX30_SCHMITT_GRF_OFFSET;
1079 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1080 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1083 *reg += ((pin_num / pins_per_reg) * 4);
1084 *bit = pin_num % pins_per_reg;
1089 #define RV1108_PULL_PMU_OFFSET 0x10
1090 #define RV1108_PULL_OFFSET 0x110
1091 #define RV1108_PULL_PINS_PER_REG 8
1092 #define RV1108_PULL_BITS_PER_PIN 2
1093 #define RV1108_PULL_BANK_STRIDE 16
1095 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1096 int pin_num, struct regmap **regmap,
1099 struct rockchip_pinctrl *info = bank->drvdata;
1101 /* The first 24 pins of the first bank are located in PMU */
1102 if (bank->bank_num == 0) {
1103 *regmap = info->regmap_pmu;
1104 *reg = RV1108_PULL_PMU_OFFSET;
1106 *reg = RV1108_PULL_OFFSET;
1107 *regmap = info->regmap_base;
1108 /* correct the offset, as we're starting with the 2nd bank */
1110 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1113 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1114 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1115 *bit *= RV1108_PULL_BITS_PER_PIN;
1118 #define RV1108_DRV_PMU_OFFSET 0x20
1119 #define RV1108_DRV_GRF_OFFSET 0x210
1120 #define RV1108_DRV_BITS_PER_PIN 2
1121 #define RV1108_DRV_PINS_PER_REG 8
1122 #define RV1108_DRV_BANK_STRIDE 16
1124 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1125 int pin_num, struct regmap **regmap,
1128 struct rockchip_pinctrl *info = bank->drvdata;
1130 /* The first 24 pins of the first bank are located in PMU */
1131 if (bank->bank_num == 0) {
1132 *regmap = info->regmap_pmu;
1133 *reg = RV1108_DRV_PMU_OFFSET;
1135 *regmap = info->regmap_base;
1136 *reg = RV1108_DRV_GRF_OFFSET;
1138 /* correct the offset, as we're starting with the 2nd bank */
1140 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1143 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1144 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1145 *bit *= RV1108_DRV_BITS_PER_PIN;
1148 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1149 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1150 #define RV1108_SCHMITT_BANK_STRIDE 8
1151 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1152 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1154 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1156 struct regmap **regmap,
1159 struct rockchip_pinctrl *info = bank->drvdata;
1162 if (bank->bank_num == 0) {
1163 *regmap = info->regmap_pmu;
1164 *reg = RV1108_SCHMITT_PMU_OFFSET;
1165 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1167 *regmap = info->regmap_base;
1168 *reg = RV1108_SCHMITT_GRF_OFFSET;
1169 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1170 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1172 *reg += ((pin_num / pins_per_reg) * 4);
1173 *bit = pin_num % pins_per_reg;
1178 #define RK3308_SCHMITT_PINS_PER_REG 8
1179 #define RK3308_SCHMITT_BANK_STRIDE 16
1180 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
1182 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1183 int pin_num, struct regmap **regmap,
1186 struct rockchip_pinctrl *info = bank->drvdata;
1188 *regmap = info->regmap_base;
1189 *reg = RK3308_SCHMITT_GRF_OFFSET;
1191 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1192 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1193 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1198 #define RK2928_PULL_OFFSET 0x118
1199 #define RK2928_PULL_PINS_PER_REG 16
1200 #define RK2928_PULL_BANK_STRIDE 8
1202 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1203 int pin_num, struct regmap **regmap,
1206 struct rockchip_pinctrl *info = bank->drvdata;
1208 *regmap = info->regmap_base;
1209 *reg = RK2928_PULL_OFFSET;
1210 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1211 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1213 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1216 #define RK3128_PULL_OFFSET 0x118
1218 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1219 int pin_num, struct regmap **regmap,
1222 struct rockchip_pinctrl *info = bank->drvdata;
1224 *regmap = info->regmap_base;
1225 *reg = RK3128_PULL_OFFSET;
1226 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1227 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1229 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1232 #define RK3188_PULL_OFFSET 0x164
1233 #define RK3188_PULL_BITS_PER_PIN 2
1234 #define RK3188_PULL_PINS_PER_REG 8
1235 #define RK3188_PULL_BANK_STRIDE 16
1236 #define RK3188_PULL_PMU_OFFSET 0x64
1238 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1239 int pin_num, struct regmap **regmap,
1242 struct rockchip_pinctrl *info = bank->drvdata;
1244 /* The first 12 pins of the first bank are located elsewhere */
1245 if (bank->bank_num == 0 && pin_num < 12) {
1246 *regmap = info->regmap_pmu ? info->regmap_pmu
1247 : bank->regmap_pull;
1248 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1249 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1250 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1251 *bit *= RK3188_PULL_BITS_PER_PIN;
1253 *regmap = info->regmap_pull ? info->regmap_pull
1254 : info->regmap_base;
1255 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1257 /* correct the offset, as it is the 2nd pull register */
1259 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1260 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1263 * The bits in these registers have an inverse ordering
1264 * with the lowest pin being in bits 15:14 and the highest
1267 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1268 *bit *= RK3188_PULL_BITS_PER_PIN;
1272 #define RK3288_PULL_OFFSET 0x140
1273 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1274 int pin_num, struct regmap **regmap,
1277 struct rockchip_pinctrl *info = bank->drvdata;
1279 /* The first 24 pins of the first bank are located in PMU */
1280 if (bank->bank_num == 0) {
1281 *regmap = info->regmap_pmu;
1282 *reg = RK3188_PULL_PMU_OFFSET;
1284 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1285 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1286 *bit *= RK3188_PULL_BITS_PER_PIN;
1288 *regmap = info->regmap_base;
1289 *reg = RK3288_PULL_OFFSET;
1291 /* correct the offset, as we're starting with the 2nd bank */
1293 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1294 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1296 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1297 *bit *= RK3188_PULL_BITS_PER_PIN;
1301 #define RK3288_DRV_PMU_OFFSET 0x70
1302 #define RK3288_DRV_GRF_OFFSET 0x1c0
1303 #define RK3288_DRV_BITS_PER_PIN 2
1304 #define RK3288_DRV_PINS_PER_REG 8
1305 #define RK3288_DRV_BANK_STRIDE 16
1307 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1308 int pin_num, struct regmap **regmap,
1311 struct rockchip_pinctrl *info = bank->drvdata;
1313 /* The first 24 pins of the first bank are located in PMU */
1314 if (bank->bank_num == 0) {
1315 *regmap = info->regmap_pmu;
1316 *reg = RK3288_DRV_PMU_OFFSET;
1318 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1319 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1320 *bit *= RK3288_DRV_BITS_PER_PIN;
1322 *regmap = info->regmap_base;
1323 *reg = RK3288_DRV_GRF_OFFSET;
1325 /* correct the offset, as we're starting with the 2nd bank */
1327 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1328 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1330 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1331 *bit *= RK3288_DRV_BITS_PER_PIN;
1335 #define RK3228_PULL_OFFSET 0x100
1337 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1338 int pin_num, struct regmap **regmap,
1341 struct rockchip_pinctrl *info = bank->drvdata;
1343 *regmap = info->regmap_base;
1344 *reg = RK3228_PULL_OFFSET;
1345 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1346 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1348 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1349 *bit *= RK3188_PULL_BITS_PER_PIN;
1352 #define RK3228_DRV_GRF_OFFSET 0x200
1354 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1355 int pin_num, struct regmap **regmap,
1358 struct rockchip_pinctrl *info = bank->drvdata;
1360 *regmap = info->regmap_base;
1361 *reg = RK3228_DRV_GRF_OFFSET;
1362 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1363 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1365 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1366 *bit *= RK3288_DRV_BITS_PER_PIN;
1369 #define RK3308_PULL_OFFSET 0xa0
1371 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1372 int pin_num, struct regmap **regmap,
1375 struct rockchip_pinctrl *info = bank->drvdata;
1377 *regmap = info->regmap_base;
1378 *reg = RK3308_PULL_OFFSET;
1379 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1380 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1382 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1383 *bit *= RK3188_PULL_BITS_PER_PIN;
1386 #define RK3308_DRV_GRF_OFFSET 0x100
1388 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1389 int pin_num, struct regmap **regmap,
1392 struct rockchip_pinctrl *info = bank->drvdata;
1394 *regmap = info->regmap_base;
1395 *reg = RK3308_DRV_GRF_OFFSET;
1396 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1397 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1399 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1400 *bit *= RK3288_DRV_BITS_PER_PIN;
1403 #define RK3368_PULL_GRF_OFFSET 0x100
1404 #define RK3368_PULL_PMU_OFFSET 0x10
1406 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1407 int pin_num, struct regmap **regmap,
1410 struct rockchip_pinctrl *info = bank->drvdata;
1412 /* The first 32 pins of the first bank are located in PMU */
1413 if (bank->bank_num == 0) {
1414 *regmap = info->regmap_pmu;
1415 *reg = RK3368_PULL_PMU_OFFSET;
1417 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1418 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1419 *bit *= RK3188_PULL_BITS_PER_PIN;
1421 *regmap = info->regmap_base;
1422 *reg = RK3368_PULL_GRF_OFFSET;
1424 /* correct the offset, as we're starting with the 2nd bank */
1426 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1427 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1429 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1430 *bit *= RK3188_PULL_BITS_PER_PIN;
1434 #define RK3368_DRV_PMU_OFFSET 0x20
1435 #define RK3368_DRV_GRF_OFFSET 0x200
1437 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1438 int pin_num, struct regmap **regmap,
1441 struct rockchip_pinctrl *info = bank->drvdata;
1443 /* The first 32 pins of the first bank are located in PMU */
1444 if (bank->bank_num == 0) {
1445 *regmap = info->regmap_pmu;
1446 *reg = RK3368_DRV_PMU_OFFSET;
1448 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1449 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1450 *bit *= RK3288_DRV_BITS_PER_PIN;
1452 *regmap = info->regmap_base;
1453 *reg = RK3368_DRV_GRF_OFFSET;
1455 /* correct the offset, as we're starting with the 2nd bank */
1457 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1458 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1460 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1461 *bit *= RK3288_DRV_BITS_PER_PIN;
1465 #define RK3399_PULL_GRF_OFFSET 0xe040
1466 #define RK3399_PULL_PMU_OFFSET 0x40
1467 #define RK3399_DRV_3BITS_PER_PIN 3
1469 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1470 int pin_num, struct regmap **regmap,
1473 struct rockchip_pinctrl *info = bank->drvdata;
1475 /* The bank0:16 and bank1:32 pins are located in PMU */
1476 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1477 *regmap = info->regmap_pmu;
1478 *reg = RK3399_PULL_PMU_OFFSET;
1480 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1482 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1483 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1484 *bit *= RK3188_PULL_BITS_PER_PIN;
1486 *regmap = info->regmap_base;
1487 *reg = RK3399_PULL_GRF_OFFSET;
1489 /* correct the offset, as we're starting with the 3rd bank */
1491 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1492 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1494 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1495 *bit *= RK3188_PULL_BITS_PER_PIN;
1499 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1500 int pin_num, struct regmap **regmap,
1503 struct rockchip_pinctrl *info = bank->drvdata;
1504 int drv_num = (pin_num / 8);
1506 /* The bank0:16 and bank1:32 pins are located in PMU */
1507 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1508 *regmap = info->regmap_pmu;
1510 *regmap = info->regmap_base;
1512 *reg = bank->drv[drv_num].offset;
1513 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1514 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1515 *bit = (pin_num % 8) * 3;
1517 *bit = (pin_num % 8) * 2;
1520 #define RK3568_PULL_PMU_OFFSET 0x20
1521 #define RK3568_PULL_GRF_OFFSET 0x80
1522 #define RK3568_PULL_BITS_PER_PIN 2
1523 #define RK3568_PULL_PINS_PER_REG 8
1524 #define RK3568_PULL_BANK_STRIDE 0x10
1526 static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1527 int pin_num, struct regmap **regmap,
1530 struct rockchip_pinctrl *info = bank->drvdata;
1532 if (bank->bank_num == 0) {
1533 *regmap = info->regmap_pmu;
1534 *reg = RK3568_PULL_PMU_OFFSET;
1535 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
1536 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1538 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
1539 *bit *= RK3568_PULL_BITS_PER_PIN;
1541 *regmap = info->regmap_base;
1542 *reg = RK3568_PULL_GRF_OFFSET;
1543 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
1544 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1546 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
1547 *bit *= RK3568_PULL_BITS_PER_PIN;
1551 #define RK3568_DRV_PMU_OFFSET 0x70
1552 #define RK3568_DRV_GRF_OFFSET 0x200
1553 #define RK3568_DRV_BITS_PER_PIN 8
1554 #define RK3568_DRV_PINS_PER_REG 2
1555 #define RK3568_DRV_BANK_STRIDE 0x40
1557 static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1558 int pin_num, struct regmap **regmap,
1561 struct rockchip_pinctrl *info = bank->drvdata;
1563 /* The first 32 pins of the first bank are located in PMU */
1564 if (bank->bank_num == 0) {
1565 *regmap = info->regmap_pmu;
1566 *reg = RK3568_DRV_PMU_OFFSET;
1567 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1569 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
1570 *bit *= RK3568_DRV_BITS_PER_PIN;
1572 *regmap = info->regmap_base;
1573 *reg = RK3568_DRV_GRF_OFFSET;
1574 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
1575 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1577 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
1578 *bit *= RK3568_DRV_BITS_PER_PIN;
1582 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1583 { 2, 4, 8, 12, -1, -1, -1, -1 },
1584 { 3, 6, 9, 12, -1, -1, -1, -1 },
1585 { 5, 10, 15, 20, -1, -1, -1, -1 },
1586 { 4, 6, 8, 10, 12, 14, 16, 18 },
1587 { 4, 7, 10, 13, 16, 19, 22, 26 }
1590 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1593 struct rockchip_pinctrl *info = bank->drvdata;
1594 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1595 struct device *dev = info->dev;
1596 struct regmap *regmap;
1598 u32 data, temp, rmask_bits;
1600 int drv_type = bank->drv[pin_num / 8].drv_type;
1602 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1605 case DRV_TYPE_IO_1V8_3V0_AUTO:
1606 case DRV_TYPE_IO_3V3_ONLY:
1607 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1610 /* regular case, nothing to do */
1614 * drive-strength offset is special, as it is
1615 * spread over 2 registers
1617 ret = regmap_read(regmap, reg, &data);
1621 ret = regmap_read(regmap, reg + 0x4, &temp);
1626 * the bit data[15] contains bit 0 of the value
1627 * while temp[1:0] contains bits 2 and 1
1634 return rockchip_perpin_drv_list[drv_type][data];
1636 /* setting fully enclosed in the second register */
1641 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1647 case DRV_TYPE_IO_DEFAULT:
1648 case DRV_TYPE_IO_1V8_OR_3V0:
1649 case DRV_TYPE_IO_1V8_ONLY:
1650 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1653 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
1657 ret = regmap_read(regmap, reg, &data);
1662 data &= (1 << rmask_bits) - 1;
1664 return rockchip_perpin_drv_list[drv_type][data];
1667 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1668 int pin_num, int strength)
1670 struct rockchip_pinctrl *info = bank->drvdata;
1671 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1672 struct device *dev = info->dev;
1673 struct regmap *regmap;
1675 u32 data, rmask, rmask_bits, temp;
1677 int drv_type = bank->drv[pin_num / 8].drv_type;
1679 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
1680 bank->bank_num, pin_num, strength);
1682 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1683 if (ctrl->type == RK3568) {
1684 rmask_bits = RK3568_DRV_BITS_PER_PIN;
1685 ret = (1 << (strength + 1)) - 1;
1690 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1691 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1694 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1695 ret = rockchip_perpin_drv_list[drv_type][i];
1701 dev_err(dev, "unsupported driver strength %d\n", strength);
1706 case DRV_TYPE_IO_1V8_3V0_AUTO:
1707 case DRV_TYPE_IO_3V3_ONLY:
1708 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1711 /* regular case, nothing to do */
1715 * drive-strength offset is special, as it is spread
1716 * over 2 registers, the bit data[15] contains bit 0
1717 * of the value while temp[1:0] contains bits 2 and 1
1719 data = (ret & 0x1) << 15;
1720 temp = (ret >> 0x1) & 0x3;
1722 rmask = BIT(15) | BIT(31);
1724 ret = regmap_update_bits(regmap, reg, rmask, data);
1728 rmask = 0x3 | (0x3 << 16);
1729 temp |= (0x3 << 16);
1731 ret = regmap_update_bits(regmap, reg, rmask, temp);
1735 /* setting fully enclosed in the second register */
1740 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1745 case DRV_TYPE_IO_DEFAULT:
1746 case DRV_TYPE_IO_1V8_OR_3V0:
1747 case DRV_TYPE_IO_1V8_ONLY:
1748 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1751 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
1756 /* enable the write to the equivalent lower bits */
1757 data = ((1 << rmask_bits) - 1) << (bit + 16);
1758 rmask = data | (data >> 16);
1759 data |= (ret << bit);
1761 ret = regmap_update_bits(regmap, reg, rmask, data);
1766 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1768 PIN_CONFIG_BIAS_DISABLE,
1769 PIN_CONFIG_BIAS_PULL_UP,
1770 PIN_CONFIG_BIAS_PULL_DOWN,
1771 PIN_CONFIG_BIAS_BUS_HOLD
1774 PIN_CONFIG_BIAS_DISABLE,
1775 PIN_CONFIG_BIAS_PULL_DOWN,
1776 PIN_CONFIG_BIAS_DISABLE,
1777 PIN_CONFIG_BIAS_PULL_UP
1781 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1783 struct rockchip_pinctrl *info = bank->drvdata;
1784 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1785 struct device *dev = info->dev;
1786 struct regmap *regmap;
1787 int reg, ret, pull_type;
1791 /* rk3066b does support any pulls */
1792 if (ctrl->type == RK3066B)
1793 return PIN_CONFIG_BIAS_DISABLE;
1795 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1797 ret = regmap_read(regmap, reg, &data);
1801 switch (ctrl->type) {
1804 return !(data & BIT(bit))
1805 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1806 : PIN_CONFIG_BIAS_DISABLE;
1814 pull_type = bank->pull_type[pin_num / 8];
1816 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1818 return rockchip_pull_list[pull_type][data];
1820 dev_err(dev, "unsupported pinctrl type\n");
1825 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1826 int pin_num, int pull)
1828 struct rockchip_pinctrl *info = bank->drvdata;
1829 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1830 struct device *dev = info->dev;
1831 struct regmap *regmap;
1832 int reg, ret, i, pull_type;
1836 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
1838 /* rk3066b does support any pulls */
1839 if (ctrl->type == RK3066B)
1840 return pull ? -EINVAL : 0;
1842 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1844 switch (ctrl->type) {
1847 data = BIT(bit + 16);
1848 if (pull == PIN_CONFIG_BIAS_DISABLE)
1850 ret = regmap_write(regmap, reg, data);
1860 pull_type = bank->pull_type[pin_num / 8];
1862 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1864 if (rockchip_pull_list[pull_type][i] == pull) {
1870 * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6,
1871 * where that pull up value becomes 3.
1873 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
1879 dev_err(dev, "unsupported pull setting %d\n", pull);
1883 /* enable the write to the equivalent lower bits */
1884 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1885 rmask = data | (data >> 16);
1886 data |= (ret << bit);
1888 ret = regmap_update_bits(regmap, reg, rmask, data);
1891 dev_err(dev, "unsupported pinctrl type\n");
1898 #define RK3328_SCHMITT_BITS_PER_PIN 1
1899 #define RK3328_SCHMITT_PINS_PER_REG 16
1900 #define RK3328_SCHMITT_BANK_STRIDE 8
1901 #define RK3328_SCHMITT_GRF_OFFSET 0x380
1903 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1905 struct regmap **regmap,
1908 struct rockchip_pinctrl *info = bank->drvdata;
1910 *regmap = info->regmap_base;
1911 *reg = RK3328_SCHMITT_GRF_OFFSET;
1913 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
1914 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
1915 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
1920 #define RK3568_SCHMITT_BITS_PER_PIN 2
1921 #define RK3568_SCHMITT_PINS_PER_REG 8
1922 #define RK3568_SCHMITT_BANK_STRIDE 0x10
1923 #define RK3568_SCHMITT_GRF_OFFSET 0xc0
1924 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
1926 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1928 struct regmap **regmap,
1931 struct rockchip_pinctrl *info = bank->drvdata;
1933 if (bank->bank_num == 0) {
1934 *regmap = info->regmap_pmu;
1935 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
1937 *regmap = info->regmap_base;
1938 *reg = RK3568_SCHMITT_GRF_OFFSET;
1939 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
1942 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
1943 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
1944 *bit *= RK3568_SCHMITT_BITS_PER_PIN;
1949 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
1951 struct rockchip_pinctrl *info = bank->drvdata;
1952 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1953 struct regmap *regmap;
1958 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
1962 ret = regmap_read(regmap, reg, &data);
1967 switch (ctrl->type) {
1969 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
1977 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
1978 int pin_num, int enable)
1980 struct rockchip_pinctrl *info = bank->drvdata;
1981 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1982 struct device *dev = info->dev;
1983 struct regmap *regmap;
1988 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
1989 bank->bank_num, pin_num, enable);
1991 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
1995 /* enable the write to the equivalent lower bits */
1996 switch (ctrl->type) {
1998 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
1999 rmask = data | (data >> 16);
2000 data |= ((enable ? 0x2 : 0x1) << bit);
2003 data = BIT(bit + 16) | (enable << bit);
2004 rmask = BIT(bit + 16) | BIT(bit);
2008 return regmap_update_bits(regmap, reg, rmask, data);
2012 * Pinmux_ops handling
2015 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2017 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2019 return info->nfunctions;
2022 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2025 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2027 return info->functions[selector].name;
2030 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2031 unsigned selector, const char * const **groups,
2032 unsigned * const num_groups)
2034 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2036 *groups = info->functions[selector].groups;
2037 *num_groups = info->functions[selector].ngroups;
2042 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2045 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2046 const unsigned int *pins = info->groups[group].pins;
2047 const struct rockchip_pin_config *data = info->groups[group].data;
2048 struct device *dev = info->dev;
2049 struct rockchip_pin_bank *bank;
2052 dev_dbg(dev, "enable function %s group %s\n",
2053 info->functions[selector].name, info->groups[group].name);
2056 * for each pin in the pin group selected, program the corresponding
2057 * pin function number in the config register.
2059 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2060 bank = pin_to_bank(info, pins[cnt]);
2061 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2068 /* revert the already done pin settings */
2069 for (cnt--; cnt >= 0; cnt--)
2070 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2078 static const struct pinmux_ops rockchip_pmx_ops = {
2079 .get_functions_count = rockchip_pmx_get_funcs_count,
2080 .get_function_name = rockchip_pmx_get_func_name,
2081 .get_function_groups = rockchip_pmx_get_groups,
2082 .set_mux = rockchip_pmx_set,
2086 * Pinconf_ops handling
2089 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2090 enum pin_config_param pull)
2092 switch (ctrl->type) {
2095 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2096 pull == PIN_CONFIG_BIAS_DISABLE);
2098 return pull ? false : true;
2107 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2113 static int rockchip_pinconf_defer_output(struct rockchip_pin_bank *bank,
2114 unsigned int pin, u32 arg)
2116 struct rockchip_pin_output_deferred *cfg;
2118 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
2125 list_add_tail(&cfg->head, &bank->deferred_output);
2130 /* set the pin config settings for a specified pin */
2131 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2132 unsigned long *configs, unsigned num_configs)
2134 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2135 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2136 struct gpio_chip *gpio = &bank->gpio_chip;
2137 enum pin_config_param param;
2142 for (i = 0; i < num_configs; i++) {
2143 param = pinconf_to_config_param(configs[i]);
2144 arg = pinconf_to_config_argument(configs[i]);
2147 case PIN_CONFIG_BIAS_DISABLE:
2148 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2153 case PIN_CONFIG_BIAS_PULL_UP:
2154 case PIN_CONFIG_BIAS_PULL_DOWN:
2155 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2156 case PIN_CONFIG_BIAS_BUS_HOLD:
2157 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2163 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2168 case PIN_CONFIG_OUTPUT:
2169 rc = rockchip_set_mux(bank, pin - bank->pin_base,
2171 if (rc != RK_FUNC_GPIO)
2175 * Check for gpio driver not being probed yet.
2176 * The lock makes sure that either gpio-probe has completed
2177 * or the gpio driver hasn't probed yet.
2179 mutex_lock(&bank->deferred_lock);
2180 if (!gpio || !gpio->direction_output) {
2181 rc = rockchip_pinconf_defer_output(bank, pin - bank->pin_base, arg);
2182 mutex_unlock(&bank->deferred_lock);
2188 mutex_unlock(&bank->deferred_lock);
2190 rc = gpio->direction_output(gpio, pin - bank->pin_base,
2195 case PIN_CONFIG_DRIVE_STRENGTH:
2196 /* rk3288 is the first with per-pin drive-strength */
2197 if (!info->ctrl->drv_calc_reg)
2200 rc = rockchip_set_drive_perpin(bank,
2201 pin - bank->pin_base, arg);
2205 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2206 if (!info->ctrl->schmitt_calc_reg)
2209 rc = rockchip_set_schmitt(bank,
2210 pin - bank->pin_base, arg);
2218 } /* for each config */
2223 /* get the pin config settings for a specified pin */
2224 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2225 unsigned long *config)
2227 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2228 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2229 struct gpio_chip *gpio = &bank->gpio_chip;
2230 enum pin_config_param param = pinconf_to_config_param(*config);
2235 case PIN_CONFIG_BIAS_DISABLE:
2236 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2241 case PIN_CONFIG_BIAS_PULL_UP:
2242 case PIN_CONFIG_BIAS_PULL_DOWN:
2243 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2244 case PIN_CONFIG_BIAS_BUS_HOLD:
2245 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2248 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2253 case PIN_CONFIG_OUTPUT:
2254 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2255 if (rc != RK_FUNC_GPIO)
2258 if (!gpio || !gpio->get) {
2263 rc = gpio->get(gpio, pin - bank->pin_base);
2269 case PIN_CONFIG_DRIVE_STRENGTH:
2270 /* rk3288 is the first with per-pin drive-strength */
2271 if (!info->ctrl->drv_calc_reg)
2274 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2280 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2281 if (!info->ctrl->schmitt_calc_reg)
2284 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2295 *config = pinconf_to_config_packed(param, arg);
2300 static const struct pinconf_ops rockchip_pinconf_ops = {
2301 .pin_config_get = rockchip_pinconf_get,
2302 .pin_config_set = rockchip_pinconf_set,
2306 static const struct of_device_id rockchip_bank_match[] = {
2307 { .compatible = "rockchip,gpio-bank" },
2308 { .compatible = "rockchip,rk3188-gpio-bank0" },
2312 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2313 struct device_node *np)
2315 struct device_node *child;
2317 for_each_child_of_node(np, child) {
2318 if (of_match_node(rockchip_bank_match, child))
2322 info->ngroups += of_get_child_count(child);
2326 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2327 struct rockchip_pin_group *grp,
2328 struct rockchip_pinctrl *info,
2331 struct device *dev = info->dev;
2332 struct rockchip_pin_bank *bank;
2339 dev_dbg(dev, "group(%d): %pOFn\n", index, np);
2341 /* Initialise group */
2342 grp->name = np->name;
2345 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2346 * do sanity check and calculate pins number
2348 list = of_get_property(np, "rockchip,pins", &size);
2349 /* we do not check return since it's safe node passed down */
2350 size /= sizeof(*list);
2351 if (!size || size % 4)
2352 return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n");
2354 grp->npins = size / 4;
2356 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
2357 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
2358 if (!grp->pins || !grp->data)
2361 for (i = 0, j = 0; i < size; i += 4, j++) {
2362 const __be32 *phandle;
2363 struct device_node *np_config;
2365 num = be32_to_cpu(*list++);
2366 bank = bank_num_to_bank(info, num);
2368 return PTR_ERR(bank);
2370 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2371 grp->data[j].func = be32_to_cpu(*list++);
2377 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2378 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2379 &grp->data[j].configs, &grp->data[j].nconfigs);
2387 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2388 struct rockchip_pinctrl *info,
2391 struct device *dev = info->dev;
2392 struct device_node *child;
2393 struct rockchip_pmx_func *func;
2394 struct rockchip_pin_group *grp;
2396 static u32 grp_index;
2399 dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
2401 func = &info->functions[index];
2403 /* Initialise function */
2404 func->name = np->name;
2405 func->ngroups = of_get_child_count(np);
2406 if (func->ngroups <= 0)
2409 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
2413 for_each_child_of_node(np, child) {
2414 func->groups[i] = child->name;
2415 grp = &info->groups[grp_index++];
2416 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2426 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2427 struct rockchip_pinctrl *info)
2429 struct device *dev = &pdev->dev;
2430 struct device_node *np = dev->of_node;
2431 struct device_node *child;
2435 rockchip_pinctrl_child_count(info, np);
2437 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
2438 dev_dbg(dev, "ngroups = %d\n", info->ngroups);
2440 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
2441 if (!info->functions)
2444 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
2450 for_each_child_of_node(np, child) {
2451 if (of_match_node(rockchip_bank_match, child))
2454 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2456 dev_err(dev, "failed to parse function\n");
2465 static int rockchip_pinctrl_register(struct platform_device *pdev,
2466 struct rockchip_pinctrl *info)
2468 struct pinctrl_desc *ctrldesc = &info->pctl;
2469 struct pinctrl_pin_desc *pindesc, *pdesc;
2470 struct rockchip_pin_bank *pin_bank;
2471 struct device *dev = &pdev->dev;
2476 ctrldesc->name = "rockchip-pinctrl";
2477 ctrldesc->owner = THIS_MODULE;
2478 ctrldesc->pctlops = &rockchip_pctrl_ops;
2479 ctrldesc->pmxops = &rockchip_pmx_ops;
2480 ctrldesc->confops = &rockchip_pinconf_ops;
2482 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
2486 ctrldesc->pins = pindesc;
2487 ctrldesc->npins = info->ctrl->nr_pins;
2490 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
2491 pin_bank = &info->ctrl->pin_banks[bank];
2493 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins);
2494 if (IS_ERR(pin_names))
2495 return PTR_ERR(pin_names);
2497 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2499 pdesc->name = pin_names[pin];
2503 INIT_LIST_HEAD(&pin_bank->deferred_output);
2504 mutex_init(&pin_bank->deferred_lock);
2507 ret = rockchip_pinctrl_parse_dt(pdev, info);
2511 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
2512 if (IS_ERR(info->pctl_dev))
2513 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
2518 static const struct of_device_id rockchip_pinctrl_dt_match[];
2520 /* retrieve the soc specific data */
2521 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2522 struct rockchip_pinctrl *d,
2523 struct platform_device *pdev)
2525 struct device *dev = &pdev->dev;
2526 struct device_node *node = dev->of_node;
2527 const struct of_device_id *match;
2528 struct rockchip_pin_ctrl *ctrl;
2529 struct rockchip_pin_bank *bank;
2530 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2532 match = of_match_node(rockchip_pinctrl_dt_match, node);
2533 ctrl = (struct rockchip_pin_ctrl *)match->data;
2535 grf_offs = ctrl->grf_mux_offset;
2536 pmu_offs = ctrl->pmu_mux_offset;
2537 drv_pmu_offs = ctrl->pmu_drv_offset;
2538 drv_grf_offs = ctrl->grf_drv_offset;
2539 bank = ctrl->pin_banks;
2540 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2543 raw_spin_lock_init(&bank->slock);
2545 bank->pin_base = ctrl->nr_pins;
2546 ctrl->nr_pins += bank->nr_pins;
2548 /* calculate iomux and drv offsets */
2549 for (j = 0; j < 4; j++) {
2550 struct rockchip_iomux *iom = &bank->iomux[j];
2551 struct rockchip_drv *drv = &bank->drv[j];
2554 if (bank_pins >= bank->nr_pins)
2557 /* preset iomux offset value, set new start value */
2558 if (iom->offset >= 0) {
2559 if (iom->type & IOMUX_SOURCE_PMU)
2560 pmu_offs = iom->offset;
2562 grf_offs = iom->offset;
2563 } else { /* set current iomux offset */
2564 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2565 pmu_offs : grf_offs;
2568 /* preset drv offset value, set new start value */
2569 if (drv->offset >= 0) {
2570 if (iom->type & IOMUX_SOURCE_PMU)
2571 drv_pmu_offs = drv->offset;
2573 drv_grf_offs = drv->offset;
2574 } else { /* set current drv offset */
2575 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2576 drv_pmu_offs : drv_grf_offs;
2579 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2580 i, j, iom->offset, drv->offset);
2583 * Increase offset according to iomux width.
2584 * 4bit iomux'es are spread over two registers.
2586 inc = (iom->type & (IOMUX_WIDTH_4BIT |
2588 IOMUX_WIDTH_2BIT)) ? 8 : 4;
2589 if (iom->type & IOMUX_SOURCE_PMU)
2595 * Increase offset according to drv width.
2596 * 3bit drive-strenth'es are spread over two registers.
2598 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2599 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2604 if (iom->type & IOMUX_SOURCE_PMU)
2605 drv_pmu_offs += inc;
2607 drv_grf_offs += inc;
2612 /* calculate the per-bank recalced_mask */
2613 for (j = 0; j < ctrl->niomux_recalced; j++) {
2616 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
2617 pin = ctrl->iomux_recalced[j].pin;
2618 bank->recalced_mask |= BIT(pin);
2622 /* calculate the per-bank route_mask */
2623 for (j = 0; j < ctrl->niomux_routes; j++) {
2626 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
2627 pin = ctrl->iomux_routes[j].pin;
2628 bank->route_mask |= BIT(pin);
2636 #define RK3288_GRF_GPIO6C_IOMUX 0x64
2637 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
2639 static u32 rk3288_grf_gpio6c_iomux;
2641 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2643 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2644 int ret = pinctrl_force_sleep(info->pctl_dev);
2650 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2651 * the setting here, and restore it at resume.
2653 if (info->ctrl->type == RK3288) {
2654 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2655 &rk3288_grf_gpio6c_iomux);
2657 pinctrl_force_default(info->pctl_dev);
2665 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2667 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2670 if (info->ctrl->type == RK3288) {
2671 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2672 rk3288_grf_gpio6c_iomux |
2673 GPIO6C6_SEL_WRITE_ENABLE);
2678 return pinctrl_force_default(info->pctl_dev);
2681 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2682 rockchip_pinctrl_resume);
2684 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2686 struct rockchip_pinctrl *info;
2687 struct device *dev = &pdev->dev;
2688 struct device_node *np = dev->of_node, *node;
2689 struct rockchip_pin_ctrl *ctrl;
2690 struct resource *res;
2695 return dev_err_probe(dev, -ENODEV, "device tree node not found\n");
2697 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
2703 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2705 return dev_err_probe(dev, -EINVAL, "driver data not available\n");
2708 node = of_parse_phandle(np, "rockchip,grf", 0);
2710 info->regmap_base = syscon_node_to_regmap(node);
2712 if (IS_ERR(info->regmap_base))
2713 return PTR_ERR(info->regmap_base);
2715 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2717 return PTR_ERR(base);
2719 rockchip_regmap_config.max_register = resource_size(res) - 4;
2720 rockchip_regmap_config.name = "rockchip,pinctrl";
2722 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
2724 /* to check for the old dt-bindings */
2725 info->reg_size = resource_size(res);
2727 /* Honor the old binding, with pull registers as 2nd resource */
2728 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2729 base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
2731 return PTR_ERR(base);
2733 rockchip_regmap_config.max_register = resource_size(res) - 4;
2734 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2736 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
2740 /* try to find the optional reference to the pmu syscon */
2741 node = of_parse_phandle(np, "rockchip,pmu", 0);
2743 info->regmap_pmu = syscon_node_to_regmap(node);
2745 if (IS_ERR(info->regmap_pmu))
2746 return PTR_ERR(info->regmap_pmu);
2749 ret = rockchip_pinctrl_register(pdev, info);
2753 platform_set_drvdata(pdev, info);
2755 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
2757 return dev_err_probe(dev, ret, "failed to register gpio device\n");
2762 static int rockchip_pinctrl_remove(struct platform_device *pdev)
2764 struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
2765 struct rockchip_pin_bank *bank;
2766 struct rockchip_pin_output_deferred *cfg;
2769 of_platform_depopulate(&pdev->dev);
2771 for (i = 0; i < info->ctrl->nr_banks; i++) {
2772 bank = &info->ctrl->pin_banks[i];
2774 mutex_lock(&bank->deferred_lock);
2775 while (!list_empty(&bank->deferred_output)) {
2776 cfg = list_first_entry(&bank->deferred_output,
2777 struct rockchip_pin_output_deferred, head);
2778 list_del(&cfg->head);
2781 mutex_unlock(&bank->deferred_lock);
2787 static struct rockchip_pin_bank px30_pin_banks[] = {
2788 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2793 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
2798 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
2803 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
2810 static struct rockchip_pin_ctrl px30_pin_ctrl = {
2811 .pin_banks = px30_pin_banks,
2812 .nr_banks = ARRAY_SIZE(px30_pin_banks),
2813 .label = "PX30-GPIO",
2815 .grf_mux_offset = 0x0,
2816 .pmu_mux_offset = 0x0,
2817 .iomux_routes = px30_mux_route_data,
2818 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
2819 .pull_calc_reg = px30_calc_pull_reg_and_bit,
2820 .drv_calc_reg = px30_calc_drv_reg_and_bit,
2821 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
2824 static struct rockchip_pin_bank rv1108_pin_banks[] = {
2825 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2829 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2830 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2831 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2834 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
2835 .pin_banks = rv1108_pin_banks,
2836 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
2837 .label = "RV1108-GPIO",
2839 .grf_mux_offset = 0x10,
2840 .pmu_mux_offset = 0x0,
2841 .iomux_recalced = rv1108_mux_recalced_data,
2842 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
2843 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
2844 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
2845 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
2848 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2849 PIN_BANK(0, 32, "gpio0"),
2850 PIN_BANK(1, 32, "gpio1"),
2851 PIN_BANK(2, 32, "gpio2"),
2852 PIN_BANK(3, 32, "gpio3"),
2855 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2856 .pin_banks = rk2928_pin_banks,
2857 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
2858 .label = "RK2928-GPIO",
2860 .grf_mux_offset = 0xa8,
2861 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2864 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2865 PIN_BANK(0, 32, "gpio0"),
2866 PIN_BANK(1, 32, "gpio1"),
2867 PIN_BANK(2, 32, "gpio2"),
2870 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2871 .pin_banks = rk3036_pin_banks,
2872 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
2873 .label = "RK3036-GPIO",
2875 .grf_mux_offset = 0xa8,
2876 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2879 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2880 PIN_BANK(0, 32, "gpio0"),
2881 PIN_BANK(1, 32, "gpio1"),
2882 PIN_BANK(2, 32, "gpio2"),
2883 PIN_BANK(3, 32, "gpio3"),
2884 PIN_BANK(4, 32, "gpio4"),
2885 PIN_BANK(6, 16, "gpio6"),
2888 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2889 .pin_banks = rk3066a_pin_banks,
2890 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
2891 .label = "RK3066a-GPIO",
2893 .grf_mux_offset = 0xa8,
2894 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2897 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2898 PIN_BANK(0, 32, "gpio0"),
2899 PIN_BANK(1, 32, "gpio1"),
2900 PIN_BANK(2, 32, "gpio2"),
2901 PIN_BANK(3, 32, "gpio3"),
2904 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2905 .pin_banks = rk3066b_pin_banks,
2906 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
2907 .label = "RK3066b-GPIO",
2909 .grf_mux_offset = 0x60,
2912 static struct rockchip_pin_bank rk3128_pin_banks[] = {
2913 PIN_BANK(0, 32, "gpio0"),
2914 PIN_BANK(1, 32, "gpio1"),
2915 PIN_BANK(2, 32, "gpio2"),
2916 PIN_BANK(3, 32, "gpio3"),
2919 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
2920 .pin_banks = rk3128_pin_banks,
2921 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
2922 .label = "RK3128-GPIO",
2924 .grf_mux_offset = 0xa8,
2925 .iomux_recalced = rk3128_mux_recalced_data,
2926 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
2927 .iomux_routes = rk3128_mux_route_data,
2928 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
2929 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
2932 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2933 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2934 PIN_BANK(1, 32, "gpio1"),
2935 PIN_BANK(2, 32, "gpio2"),
2936 PIN_BANK(3, 32, "gpio3"),
2939 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2940 .pin_banks = rk3188_pin_banks,
2941 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
2942 .label = "RK3188-GPIO",
2944 .grf_mux_offset = 0x60,
2945 .iomux_routes = rk3188_mux_route_data,
2946 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
2947 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
2950 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2951 PIN_BANK(0, 32, "gpio0"),
2952 PIN_BANK(1, 32, "gpio1"),
2953 PIN_BANK(2, 32, "gpio2"),
2954 PIN_BANK(3, 32, "gpio3"),
2957 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2958 .pin_banks = rk3228_pin_banks,
2959 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
2960 .label = "RK3228-GPIO",
2962 .grf_mux_offset = 0x0,
2963 .iomux_routes = rk3228_mux_route_data,
2964 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
2965 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
2966 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
2969 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2970 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2975 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2980 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2981 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2982 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2987 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2992 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2993 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2998 PIN_BANK(8, 16, "gpio8"),
3001 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3002 .pin_banks = rk3288_pin_banks,
3003 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3004 .label = "RK3288-GPIO",
3006 .grf_mux_offset = 0x0,
3007 .pmu_mux_offset = 0x84,
3008 .iomux_routes = rk3288_mux_route_data,
3009 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
3010 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
3011 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3014 static struct rockchip_pin_bank rk3308_pin_banks[] = {
3015 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
3019 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
3023 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
3027 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
3031 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
3037 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
3038 .pin_banks = rk3308_pin_banks,
3039 .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
3040 .label = "RK3308-GPIO",
3042 .grf_mux_offset = 0x0,
3043 .iomux_recalced = rk3308_mux_recalced_data,
3044 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
3045 .iomux_routes = rk3308_mux_route_data,
3046 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
3047 .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
3048 .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
3049 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
3052 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3053 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3054 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3055 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3059 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3066 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3067 .pin_banks = rk3328_pin_banks,
3068 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3069 .label = "RK3328-GPIO",
3071 .grf_mux_offset = 0x0,
3072 .iomux_recalced = rk3328_mux_recalced_data,
3073 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
3074 .iomux_routes = rk3328_mux_route_data,
3075 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3076 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3077 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3078 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3081 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3082 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3087 PIN_BANK(1, 32, "gpio1"),
3088 PIN_BANK(2, 32, "gpio2"),
3089 PIN_BANK(3, 32, "gpio3"),
3092 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3093 .pin_banks = rk3368_pin_banks,
3094 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3095 .label = "RK3368-GPIO",
3097 .grf_mux_offset = 0x0,
3098 .pmu_mux_offset = 0x0,
3099 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3100 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3103 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3104 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3109 DRV_TYPE_IO_1V8_ONLY,
3110 DRV_TYPE_IO_1V8_ONLY,
3111 DRV_TYPE_IO_DEFAULT,
3112 DRV_TYPE_IO_DEFAULT,
3117 PULL_TYPE_IO_1V8_ONLY,
3118 PULL_TYPE_IO_1V8_ONLY,
3119 PULL_TYPE_IO_DEFAULT,
3120 PULL_TYPE_IO_DEFAULT
3122 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3126 DRV_TYPE_IO_1V8_OR_3V0,
3127 DRV_TYPE_IO_1V8_OR_3V0,
3128 DRV_TYPE_IO_1V8_OR_3V0,
3129 DRV_TYPE_IO_1V8_OR_3V0,
3135 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3136 DRV_TYPE_IO_1V8_OR_3V0,
3137 DRV_TYPE_IO_1V8_ONLY,
3138 DRV_TYPE_IO_1V8_ONLY,
3139 PULL_TYPE_IO_DEFAULT,
3140 PULL_TYPE_IO_DEFAULT,
3141 PULL_TYPE_IO_1V8_ONLY,
3142 PULL_TYPE_IO_1V8_ONLY
3144 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3145 DRV_TYPE_IO_3V3_ONLY,
3146 DRV_TYPE_IO_3V3_ONLY,
3147 DRV_TYPE_IO_1V8_OR_3V0
3149 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3150 DRV_TYPE_IO_1V8_3V0_AUTO,
3151 DRV_TYPE_IO_1V8_OR_3V0,
3152 DRV_TYPE_IO_1V8_OR_3V0
3156 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3157 .pin_banks = rk3399_pin_banks,
3158 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3159 .label = "RK3399-GPIO",
3161 .grf_mux_offset = 0xe000,
3162 .pmu_mux_offset = 0x0,
3163 .grf_drv_offset = 0xe100,
3164 .pmu_drv_offset = 0x80,
3165 .iomux_routes = rk3399_mux_route_data,
3166 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
3167 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3168 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3171 static struct rockchip_pin_bank rk3568_pin_banks[] = {
3172 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3173 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3174 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3175 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
3176 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3180 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3184 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3188 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3194 static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
3195 .pin_banks = rk3568_pin_banks,
3196 .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
3197 .label = "RK3568-GPIO",
3199 .grf_mux_offset = 0x0,
3200 .pmu_mux_offset = 0x0,
3201 .grf_drv_offset = 0x0200,
3202 .pmu_drv_offset = 0x0070,
3203 .iomux_routes = rk3568_mux_route_data,
3204 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
3205 .pull_calc_reg = rk3568_calc_pull_reg_and_bit,
3206 .drv_calc_reg = rk3568_calc_drv_reg_and_bit,
3207 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
3210 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3211 { .compatible = "rockchip,px30-pinctrl",
3212 .data = &px30_pin_ctrl },
3213 { .compatible = "rockchip,rv1108-pinctrl",
3214 .data = &rv1108_pin_ctrl },
3215 { .compatible = "rockchip,rk2928-pinctrl",
3216 .data = &rk2928_pin_ctrl },
3217 { .compatible = "rockchip,rk3036-pinctrl",
3218 .data = &rk3036_pin_ctrl },
3219 { .compatible = "rockchip,rk3066a-pinctrl",
3220 .data = &rk3066a_pin_ctrl },
3221 { .compatible = "rockchip,rk3066b-pinctrl",
3222 .data = &rk3066b_pin_ctrl },
3223 { .compatible = "rockchip,rk3128-pinctrl",
3224 .data = (void *)&rk3128_pin_ctrl },
3225 { .compatible = "rockchip,rk3188-pinctrl",
3226 .data = &rk3188_pin_ctrl },
3227 { .compatible = "rockchip,rk3228-pinctrl",
3228 .data = &rk3228_pin_ctrl },
3229 { .compatible = "rockchip,rk3288-pinctrl",
3230 .data = &rk3288_pin_ctrl },
3231 { .compatible = "rockchip,rk3308-pinctrl",
3232 .data = &rk3308_pin_ctrl },
3233 { .compatible = "rockchip,rk3328-pinctrl",
3234 .data = &rk3328_pin_ctrl },
3235 { .compatible = "rockchip,rk3368-pinctrl",
3236 .data = &rk3368_pin_ctrl },
3237 { .compatible = "rockchip,rk3399-pinctrl",
3238 .data = &rk3399_pin_ctrl },
3239 { .compatible = "rockchip,rk3568-pinctrl",
3240 .data = &rk3568_pin_ctrl },
3244 static struct platform_driver rockchip_pinctrl_driver = {
3245 .probe = rockchip_pinctrl_probe,
3246 .remove = rockchip_pinctrl_remove,
3248 .name = "rockchip-pinctrl",
3249 .pm = &rockchip_pinctrl_dev_pm_ops,
3250 .of_match_table = rockchip_pinctrl_dt_match,
3254 static int __init rockchip_pinctrl_drv_register(void)
3256 return platform_driver_register(&rockchip_pinctrl_driver);
3258 postcore_initcall(rockchip_pinctrl_drv_register);
3260 static void __exit rockchip_pinctrl_drv_unregister(void)
3262 platform_driver_unregister(&rockchip_pinctrl_driver);
3264 module_exit(rockchip_pinctrl_drv_unregister);
3266 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
3267 MODULE_LICENSE("GPL");
3268 MODULE_ALIAS("platform:pinctrl-rockchip");
3269 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);