1 // SPDX-License-Identifier: GPL-2.0-only
3 * Pinctrl driver for Rockchip SoCs
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
22 #include <linux/bitops.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/of_address.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/irqchip/chained_irq.h>
33 #include <linux/clk.h>
34 #include <linux/regmap.h>
35 #include <linux/mfd/syscon.h>
36 #include <linux/string_helpers.h>
38 #include <dt-bindings/pinctrl/rockchip.h>
42 #include "pinctrl-rockchip.h"
45 * Generate a bitmask for setting a value (v) with a write mask bit in hiword
46 * register 31:16 area.
48 #define WRITE_MASK_VAL(h, l, v) \
49 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
52 * Encode variants of iomux registers into a type variable
54 #define IOMUX_GPIO_ONLY BIT(0)
55 #define IOMUX_WIDTH_4BIT BIT(1)
56 #define IOMUX_SOURCE_PMU BIT(2)
57 #define IOMUX_UNROUTED BIT(3)
58 #define IOMUX_WIDTH_3BIT BIT(4)
59 #define IOMUX_WIDTH_2BIT BIT(5)
61 #define PIN_BANK(id, pins, label) \
74 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
80 { .type = iom0, .offset = -1 }, \
81 { .type = iom1, .offset = -1 }, \
82 { .type = iom2, .offset = -1 }, \
83 { .type = iom3, .offset = -1 }, \
87 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
99 { .drv_type = type0, .offset = -1 }, \
100 { .drv_type = type1, .offset = -1 }, \
101 { .drv_type = type2, .offset = -1 }, \
102 { .drv_type = type3, .offset = -1 }, \
106 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
107 drv2, drv3, pull0, pull1, \
120 { .drv_type = drv0, .offset = -1 }, \
121 { .drv_type = drv1, .offset = -1 }, \
122 { .drv_type = drv2, .offset = -1 }, \
123 { .drv_type = drv3, .offset = -1 }, \
125 .pull_type[0] = pull0, \
126 .pull_type[1] = pull1, \
127 .pull_type[2] = pull2, \
128 .pull_type[3] = pull3, \
131 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
132 iom2, iom3, drv0, drv1, drv2, \
133 drv3, offset0, offset1, \
140 { .type = iom0, .offset = -1 }, \
141 { .type = iom1, .offset = -1 }, \
142 { .type = iom2, .offset = -1 }, \
143 { .type = iom3, .offset = -1 }, \
146 { .drv_type = drv0, .offset = offset0 }, \
147 { .drv_type = drv1, .offset = offset1 }, \
148 { .drv_type = drv2, .offset = offset2 }, \
149 { .drv_type = drv3, .offset = offset3 }, \
153 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
154 label, iom0, iom1, iom2, \
155 iom3, drv0, drv1, drv2, \
156 drv3, offset0, offset1, \
157 offset2, offset3, pull0, \
158 pull1, pull2, pull3) \
164 { .type = iom0, .offset = -1 }, \
165 { .type = iom1, .offset = -1 }, \
166 { .type = iom2, .offset = -1 }, \
167 { .type = iom3, .offset = -1 }, \
170 { .drv_type = drv0, .offset = offset0 }, \
171 { .drv_type = drv1, .offset = offset1 }, \
172 { .drv_type = drv2, .offset = offset2 }, \
173 { .drv_type = drv3, .offset = offset3 }, \
175 .pull_type[0] = pull0, \
176 .pull_type[1] = pull1, \
177 .pull_type[2] = pull2, \
178 .pull_type[3] = pull3, \
181 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
186 .route_offset = REG, \
188 .route_location = FLAG, \
191 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
192 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
194 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
195 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
197 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
198 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
200 static struct regmap_config rockchip_regmap_config = {
206 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
207 const struct rockchip_pinctrl *info,
212 for (i = 0; i < info->ngroups; i++) {
213 if (!strcmp(info->groups[i].name, name))
214 return &info->groups[i];
221 * given a pin number that is local to a pin controller, find out the pin bank
222 * and the register base of the pin bank.
224 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
227 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
229 while (pin >= (b->pin_base + b->nr_pins))
235 static struct rockchip_pin_bank *bank_num_to_bank(
236 struct rockchip_pinctrl *info,
239 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
242 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
243 if (b->bank_num == num)
247 return ERR_PTR(-EINVAL);
251 * Pinctrl_ops handling
254 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
256 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
258 return info->ngroups;
261 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
264 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
266 return info->groups[selector].name;
269 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
270 unsigned selector, const unsigned **pins,
273 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
275 if (selector >= info->ngroups)
278 *pins = info->groups[selector].pins;
279 *npins = info->groups[selector].npins;
284 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
285 struct device_node *np,
286 struct pinctrl_map **map, unsigned *num_maps)
288 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
289 const struct rockchip_pin_group *grp;
290 struct device *dev = info->dev;
291 struct pinctrl_map *new_map;
292 struct device_node *parent;
297 * first find the group of this node and check if we need to create
298 * config maps for pins
300 grp = pinctrl_name_to_group(info, np->name);
302 dev_err(dev, "unable to find group for node %pOFn\n", np);
306 map_num += grp->npins;
308 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
316 parent = of_get_parent(np);
321 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
322 new_map[0].data.mux.function = parent->name;
323 new_map[0].data.mux.group = np->name;
326 /* create config map */
328 for (i = 0; i < grp->npins; i++) {
329 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
330 new_map[i].data.configs.group_or_pin =
331 pin_get_name(pctldev, grp->pins[i]);
332 new_map[i].data.configs.configs = grp->data[i].configs;
333 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
336 dev_dbg(dev, "maps: function %s group %s num %d\n",
337 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
342 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
343 struct pinctrl_map *map, unsigned num_maps)
348 static const struct pinctrl_ops rockchip_pctrl_ops = {
349 .get_groups_count = rockchip_get_groups_count,
350 .get_group_name = rockchip_get_group_name,
351 .get_group_pins = rockchip_get_group_pins,
352 .dt_node_to_map = rockchip_dt_node_to_map,
353 .dt_free_map = rockchip_dt_free_map,
360 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
424 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
458 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
552 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
574 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
575 int *reg, u8 *bit, int *mask)
577 struct rockchip_pinctrl *info = bank->drvdata;
578 struct rockchip_pin_ctrl *ctrl = info->ctrl;
579 struct rockchip_mux_recalced_data *data;
582 for (i = 0; i < ctrl->niomux_recalced; i++) {
583 data = &ctrl->iomux_recalced[i];
584 if (data->num == bank->bank_num &&
589 if (i >= ctrl->niomux_recalced)
597 static struct rockchip_mux_route_data px30_mux_route_data[] = {
598 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
599 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
600 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
601 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
602 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
603 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
604 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
605 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
608 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
609 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
610 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
611 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
612 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
613 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
614 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
615 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
618 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
619 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
620 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
623 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
624 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
625 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
626 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
627 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
628 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
629 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
630 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
631 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
632 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
633 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
634 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
635 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
636 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
637 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
638 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
639 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
640 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
641 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
644 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
645 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
646 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
649 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
650 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
651 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
652 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
653 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
654 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
655 RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
656 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
657 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
658 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
659 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
660 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
661 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
662 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
663 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
664 RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
665 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
666 RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
667 RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
668 RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
669 RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
670 RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
671 RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
672 RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
673 RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
674 RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
675 RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
678 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
679 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
680 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
681 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
682 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
683 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
684 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
685 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
686 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
687 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
688 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
689 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
690 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
693 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
694 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
695 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
696 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
697 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
698 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
701 static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
702 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
703 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
704 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
705 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
706 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
707 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
708 RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
709 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
710 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
711 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
712 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
713 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
714 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
715 RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
716 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
717 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
718 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
719 RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
720 RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
721 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
722 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
723 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
724 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
725 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
726 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
727 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
728 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
729 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
730 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
731 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
732 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
733 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
734 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
735 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
736 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
737 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
738 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
739 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
740 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
741 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
742 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
743 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
744 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
745 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
746 RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
747 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
748 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
749 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
750 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
751 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
752 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
753 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
754 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
755 RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
756 RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
757 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
758 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
759 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
760 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
761 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
762 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
763 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
764 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
765 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
766 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
767 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
768 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
769 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
770 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
771 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
772 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
773 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
774 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
775 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
776 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
777 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
778 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
779 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
780 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
781 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
782 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
783 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
784 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
785 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
786 RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
787 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
788 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
789 RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
790 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
791 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
792 RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
793 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
794 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
797 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
798 int mux, u32 *loc, u32 *reg, u32 *value)
800 struct rockchip_pinctrl *info = bank->drvdata;
801 struct rockchip_pin_ctrl *ctrl = info->ctrl;
802 struct rockchip_mux_route_data *data;
805 for (i = 0; i < ctrl->niomux_routes; i++) {
806 data = &ctrl->iomux_routes[i];
807 if ((data->bank_num == bank->bank_num) &&
808 (data->pin == pin) && (data->func == mux))
812 if (i >= ctrl->niomux_routes)
815 *loc = data->route_location;
816 *reg = data->route_offset;
817 *value = data->route_val;
822 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
824 struct rockchip_pinctrl *info = bank->drvdata;
825 int iomux_num = (pin / 8);
826 struct regmap *regmap;
828 int reg, ret, mask, mux_type;
834 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
835 dev_err(info->dev, "pin %d is unrouted\n", pin);
839 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
842 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
843 ? info->regmap_pmu : info->regmap_base;
845 /* get basic quadrupel of mux registers and the correct reg inside */
846 mux_type = bank->iomux[iomux_num].type;
847 reg = bank->iomux[iomux_num].offset;
848 if (mux_type & IOMUX_WIDTH_4BIT) {
853 } else if (mux_type & IOMUX_WIDTH_3BIT) {
856 bit = (pin % 8 % 5) * 3;
863 if (bank->recalced_mask & BIT(pin))
864 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
866 ret = regmap_read(regmap, reg, &val);
870 return ((val >> bit) & mask);
873 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
876 struct rockchip_pinctrl *info = bank->drvdata;
877 struct device *dev = info->dev;
878 int iomux_num = (pin / 8);
883 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
884 dev_err(dev, "pin %d is unrouted\n", pin);
888 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
889 if (mux != RK_FUNC_GPIO) {
890 dev_err(dev, "pin %d only supports a gpio mux\n", pin);
899 * Set a new mux function for a pin.
901 * The register is divided into the upper and lower 16 bit. When changing
902 * a value, the previous register value is not read and changed. Instead
903 * it seems the changed bits are marked in the upper 16 bit, while the
904 * changed value gets set in the same offset in the lower 16 bit.
905 * All pin settings seem to be 2 bit wide in both the upper and lower
907 * @bank: pin bank to change
908 * @pin: pin to change
909 * @mux: new mux function to set
911 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
913 struct rockchip_pinctrl *info = bank->drvdata;
914 struct device *dev = info->dev;
915 int iomux_num = (pin / 8);
916 struct regmap *regmap;
917 int reg, ret, mask, mux_type;
919 u32 data, rmask, route_location, route_reg, route_val;
921 ret = rockchip_verify_mux(bank, pin, mux);
925 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
928 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
930 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
931 ? info->regmap_pmu : info->regmap_base;
933 /* get basic quadrupel of mux registers and the correct reg inside */
934 mux_type = bank->iomux[iomux_num].type;
935 reg = bank->iomux[iomux_num].offset;
936 if (mux_type & IOMUX_WIDTH_4BIT) {
941 } else if (mux_type & IOMUX_WIDTH_3BIT) {
944 bit = (pin % 8 % 5) * 3;
951 if (bank->recalced_mask & BIT(pin))
952 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
954 if (bank->route_mask & BIT(pin)) {
955 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
956 &route_reg, &route_val)) {
957 struct regmap *route_regmap = regmap;
959 /* handle special locations */
960 switch (route_location) {
961 case ROCKCHIP_ROUTE_PMU:
962 route_regmap = info->regmap_pmu;
964 case ROCKCHIP_ROUTE_GRF:
965 route_regmap = info->regmap_base;
969 ret = regmap_write(route_regmap, route_reg, route_val);
975 data = (mask << (bit + 16));
976 rmask = data | (data >> 16);
977 data |= (mux & mask) << bit;
978 ret = regmap_update_bits(regmap, reg, rmask, data);
983 #define PX30_PULL_PMU_OFFSET 0x10
984 #define PX30_PULL_GRF_OFFSET 0x60
985 #define PX30_PULL_BITS_PER_PIN 2
986 #define PX30_PULL_PINS_PER_REG 8
987 #define PX30_PULL_BANK_STRIDE 16
989 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
990 int pin_num, struct regmap **regmap,
993 struct rockchip_pinctrl *info = bank->drvdata;
995 /* The first 32 pins of the first bank are located in PMU */
996 if (bank->bank_num == 0) {
997 *regmap = info->regmap_pmu;
998 *reg = PX30_PULL_PMU_OFFSET;
1000 *regmap = info->regmap_base;
1001 *reg = PX30_PULL_GRF_OFFSET;
1003 /* correct the offset, as we're starting with the 2nd bank */
1005 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1008 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1009 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1010 *bit *= PX30_PULL_BITS_PER_PIN;
1013 #define PX30_DRV_PMU_OFFSET 0x20
1014 #define PX30_DRV_GRF_OFFSET 0xf0
1015 #define PX30_DRV_BITS_PER_PIN 2
1016 #define PX30_DRV_PINS_PER_REG 8
1017 #define PX30_DRV_BANK_STRIDE 16
1019 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1020 int pin_num, struct regmap **regmap,
1023 struct rockchip_pinctrl *info = bank->drvdata;
1025 /* The first 32 pins of the first bank are located in PMU */
1026 if (bank->bank_num == 0) {
1027 *regmap = info->regmap_pmu;
1028 *reg = PX30_DRV_PMU_OFFSET;
1030 *regmap = info->regmap_base;
1031 *reg = PX30_DRV_GRF_OFFSET;
1033 /* correct the offset, as we're starting with the 2nd bank */
1035 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1038 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1039 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1040 *bit *= PX30_DRV_BITS_PER_PIN;
1043 #define PX30_SCHMITT_PMU_OFFSET 0x38
1044 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1045 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1046 #define PX30_SCHMITT_BANK_STRIDE 16
1047 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1049 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1051 struct regmap **regmap,
1054 struct rockchip_pinctrl *info = bank->drvdata;
1057 if (bank->bank_num == 0) {
1058 *regmap = info->regmap_pmu;
1059 *reg = PX30_SCHMITT_PMU_OFFSET;
1060 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1062 *regmap = info->regmap_base;
1063 *reg = PX30_SCHMITT_GRF_OFFSET;
1064 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1065 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1068 *reg += ((pin_num / pins_per_reg) * 4);
1069 *bit = pin_num % pins_per_reg;
1074 #define RV1108_PULL_PMU_OFFSET 0x10
1075 #define RV1108_PULL_OFFSET 0x110
1076 #define RV1108_PULL_PINS_PER_REG 8
1077 #define RV1108_PULL_BITS_PER_PIN 2
1078 #define RV1108_PULL_BANK_STRIDE 16
1080 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1081 int pin_num, struct regmap **regmap,
1084 struct rockchip_pinctrl *info = bank->drvdata;
1086 /* The first 24 pins of the first bank are located in PMU */
1087 if (bank->bank_num == 0) {
1088 *regmap = info->regmap_pmu;
1089 *reg = RV1108_PULL_PMU_OFFSET;
1091 *reg = RV1108_PULL_OFFSET;
1092 *regmap = info->regmap_base;
1093 /* correct the offset, as we're starting with the 2nd bank */
1095 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1098 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1099 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1100 *bit *= RV1108_PULL_BITS_PER_PIN;
1103 #define RV1108_DRV_PMU_OFFSET 0x20
1104 #define RV1108_DRV_GRF_OFFSET 0x210
1105 #define RV1108_DRV_BITS_PER_PIN 2
1106 #define RV1108_DRV_PINS_PER_REG 8
1107 #define RV1108_DRV_BANK_STRIDE 16
1109 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1110 int pin_num, struct regmap **regmap,
1113 struct rockchip_pinctrl *info = bank->drvdata;
1115 /* The first 24 pins of the first bank are located in PMU */
1116 if (bank->bank_num == 0) {
1117 *regmap = info->regmap_pmu;
1118 *reg = RV1108_DRV_PMU_OFFSET;
1120 *regmap = info->regmap_base;
1121 *reg = RV1108_DRV_GRF_OFFSET;
1123 /* correct the offset, as we're starting with the 2nd bank */
1125 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1128 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1129 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1130 *bit *= RV1108_DRV_BITS_PER_PIN;
1133 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1134 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1135 #define RV1108_SCHMITT_BANK_STRIDE 8
1136 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1137 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1139 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1141 struct regmap **regmap,
1144 struct rockchip_pinctrl *info = bank->drvdata;
1147 if (bank->bank_num == 0) {
1148 *regmap = info->regmap_pmu;
1149 *reg = RV1108_SCHMITT_PMU_OFFSET;
1150 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1152 *regmap = info->regmap_base;
1153 *reg = RV1108_SCHMITT_GRF_OFFSET;
1154 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1155 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1157 *reg += ((pin_num / pins_per_reg) * 4);
1158 *bit = pin_num % pins_per_reg;
1163 #define RK3308_SCHMITT_PINS_PER_REG 8
1164 #define RK3308_SCHMITT_BANK_STRIDE 16
1165 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
1167 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1168 int pin_num, struct regmap **regmap,
1171 struct rockchip_pinctrl *info = bank->drvdata;
1173 *regmap = info->regmap_base;
1174 *reg = RK3308_SCHMITT_GRF_OFFSET;
1176 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1177 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1178 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1183 #define RK2928_PULL_OFFSET 0x118
1184 #define RK2928_PULL_PINS_PER_REG 16
1185 #define RK2928_PULL_BANK_STRIDE 8
1187 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1188 int pin_num, struct regmap **regmap,
1191 struct rockchip_pinctrl *info = bank->drvdata;
1193 *regmap = info->regmap_base;
1194 *reg = RK2928_PULL_OFFSET;
1195 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1196 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1198 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1201 #define RK3128_PULL_OFFSET 0x118
1203 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1204 int pin_num, struct regmap **regmap,
1207 struct rockchip_pinctrl *info = bank->drvdata;
1209 *regmap = info->regmap_base;
1210 *reg = RK3128_PULL_OFFSET;
1211 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1212 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1214 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1217 #define RK3188_PULL_OFFSET 0x164
1218 #define RK3188_PULL_BITS_PER_PIN 2
1219 #define RK3188_PULL_PINS_PER_REG 8
1220 #define RK3188_PULL_BANK_STRIDE 16
1221 #define RK3188_PULL_PMU_OFFSET 0x64
1223 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1224 int pin_num, struct regmap **regmap,
1227 struct rockchip_pinctrl *info = bank->drvdata;
1229 /* The first 12 pins of the first bank are located elsewhere */
1230 if (bank->bank_num == 0 && pin_num < 12) {
1231 *regmap = info->regmap_pmu ? info->regmap_pmu
1232 : bank->regmap_pull;
1233 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1234 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1235 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1236 *bit *= RK3188_PULL_BITS_PER_PIN;
1238 *regmap = info->regmap_pull ? info->regmap_pull
1239 : info->regmap_base;
1240 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1242 /* correct the offset, as it is the 2nd pull register */
1244 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1245 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1248 * The bits in these registers have an inverse ordering
1249 * with the lowest pin being in bits 15:14 and the highest
1252 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1253 *bit *= RK3188_PULL_BITS_PER_PIN;
1257 #define RK3288_PULL_OFFSET 0x140
1258 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1259 int pin_num, struct regmap **regmap,
1262 struct rockchip_pinctrl *info = bank->drvdata;
1264 /* The first 24 pins of the first bank are located in PMU */
1265 if (bank->bank_num == 0) {
1266 *regmap = info->regmap_pmu;
1267 *reg = RK3188_PULL_PMU_OFFSET;
1269 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1270 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1271 *bit *= RK3188_PULL_BITS_PER_PIN;
1273 *regmap = info->regmap_base;
1274 *reg = RK3288_PULL_OFFSET;
1276 /* correct the offset, as we're starting with the 2nd bank */
1278 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1279 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1281 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1282 *bit *= RK3188_PULL_BITS_PER_PIN;
1286 #define RK3288_DRV_PMU_OFFSET 0x70
1287 #define RK3288_DRV_GRF_OFFSET 0x1c0
1288 #define RK3288_DRV_BITS_PER_PIN 2
1289 #define RK3288_DRV_PINS_PER_REG 8
1290 #define RK3288_DRV_BANK_STRIDE 16
1292 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1293 int pin_num, struct regmap **regmap,
1296 struct rockchip_pinctrl *info = bank->drvdata;
1298 /* The first 24 pins of the first bank are located in PMU */
1299 if (bank->bank_num == 0) {
1300 *regmap = info->regmap_pmu;
1301 *reg = RK3288_DRV_PMU_OFFSET;
1303 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1304 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1305 *bit *= RK3288_DRV_BITS_PER_PIN;
1307 *regmap = info->regmap_base;
1308 *reg = RK3288_DRV_GRF_OFFSET;
1310 /* correct the offset, as we're starting with the 2nd bank */
1312 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1313 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1315 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1316 *bit *= RK3288_DRV_BITS_PER_PIN;
1320 #define RK3228_PULL_OFFSET 0x100
1322 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1323 int pin_num, struct regmap **regmap,
1326 struct rockchip_pinctrl *info = bank->drvdata;
1328 *regmap = info->regmap_base;
1329 *reg = RK3228_PULL_OFFSET;
1330 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1331 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1333 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1334 *bit *= RK3188_PULL_BITS_PER_PIN;
1337 #define RK3228_DRV_GRF_OFFSET 0x200
1339 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1340 int pin_num, struct regmap **regmap,
1343 struct rockchip_pinctrl *info = bank->drvdata;
1345 *regmap = info->regmap_base;
1346 *reg = RK3228_DRV_GRF_OFFSET;
1347 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1348 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1350 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1351 *bit *= RK3288_DRV_BITS_PER_PIN;
1354 #define RK3308_PULL_OFFSET 0xa0
1356 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1357 int pin_num, struct regmap **regmap,
1360 struct rockchip_pinctrl *info = bank->drvdata;
1362 *regmap = info->regmap_base;
1363 *reg = RK3308_PULL_OFFSET;
1364 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1365 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1367 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1368 *bit *= RK3188_PULL_BITS_PER_PIN;
1371 #define RK3308_DRV_GRF_OFFSET 0x100
1373 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1374 int pin_num, struct regmap **regmap,
1377 struct rockchip_pinctrl *info = bank->drvdata;
1379 *regmap = info->regmap_base;
1380 *reg = RK3308_DRV_GRF_OFFSET;
1381 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1382 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1384 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1385 *bit *= RK3288_DRV_BITS_PER_PIN;
1388 #define RK3368_PULL_GRF_OFFSET 0x100
1389 #define RK3368_PULL_PMU_OFFSET 0x10
1391 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1392 int pin_num, struct regmap **regmap,
1395 struct rockchip_pinctrl *info = bank->drvdata;
1397 /* The first 32 pins of the first bank are located in PMU */
1398 if (bank->bank_num == 0) {
1399 *regmap = info->regmap_pmu;
1400 *reg = RK3368_PULL_PMU_OFFSET;
1402 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1403 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1404 *bit *= RK3188_PULL_BITS_PER_PIN;
1406 *regmap = info->regmap_base;
1407 *reg = RK3368_PULL_GRF_OFFSET;
1409 /* correct the offset, as we're starting with the 2nd bank */
1411 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1412 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1414 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1415 *bit *= RK3188_PULL_BITS_PER_PIN;
1419 #define RK3368_DRV_PMU_OFFSET 0x20
1420 #define RK3368_DRV_GRF_OFFSET 0x200
1422 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1423 int pin_num, struct regmap **regmap,
1426 struct rockchip_pinctrl *info = bank->drvdata;
1428 /* The first 32 pins of the first bank are located in PMU */
1429 if (bank->bank_num == 0) {
1430 *regmap = info->regmap_pmu;
1431 *reg = RK3368_DRV_PMU_OFFSET;
1433 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1434 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1435 *bit *= RK3288_DRV_BITS_PER_PIN;
1437 *regmap = info->regmap_base;
1438 *reg = RK3368_DRV_GRF_OFFSET;
1440 /* correct the offset, as we're starting with the 2nd bank */
1442 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1443 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1445 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1446 *bit *= RK3288_DRV_BITS_PER_PIN;
1450 #define RK3399_PULL_GRF_OFFSET 0xe040
1451 #define RK3399_PULL_PMU_OFFSET 0x40
1452 #define RK3399_DRV_3BITS_PER_PIN 3
1454 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1455 int pin_num, struct regmap **regmap,
1458 struct rockchip_pinctrl *info = bank->drvdata;
1460 /* The bank0:16 and bank1:32 pins are located in PMU */
1461 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1462 *regmap = info->regmap_pmu;
1463 *reg = RK3399_PULL_PMU_OFFSET;
1465 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1467 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1468 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1469 *bit *= RK3188_PULL_BITS_PER_PIN;
1471 *regmap = info->regmap_base;
1472 *reg = RK3399_PULL_GRF_OFFSET;
1474 /* correct the offset, as we're starting with the 3rd bank */
1476 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1477 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1479 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1480 *bit *= RK3188_PULL_BITS_PER_PIN;
1484 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1485 int pin_num, struct regmap **regmap,
1488 struct rockchip_pinctrl *info = bank->drvdata;
1489 int drv_num = (pin_num / 8);
1491 /* The bank0:16 and bank1:32 pins are located in PMU */
1492 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1493 *regmap = info->regmap_pmu;
1495 *regmap = info->regmap_base;
1497 *reg = bank->drv[drv_num].offset;
1498 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1499 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1500 *bit = (pin_num % 8) * 3;
1502 *bit = (pin_num % 8) * 2;
1505 #define RK3568_PULL_PMU_OFFSET 0x20
1506 #define RK3568_PULL_GRF_OFFSET 0x80
1507 #define RK3568_PULL_BITS_PER_PIN 2
1508 #define RK3568_PULL_PINS_PER_REG 8
1509 #define RK3568_PULL_BANK_STRIDE 0x10
1511 static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1512 int pin_num, struct regmap **regmap,
1515 struct rockchip_pinctrl *info = bank->drvdata;
1517 if (bank->bank_num == 0) {
1518 *regmap = info->regmap_pmu;
1519 *reg = RK3568_PULL_PMU_OFFSET;
1520 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
1521 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1523 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
1524 *bit *= RK3568_PULL_BITS_PER_PIN;
1526 *regmap = info->regmap_base;
1527 *reg = RK3568_PULL_GRF_OFFSET;
1528 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
1529 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1531 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
1532 *bit *= RK3568_PULL_BITS_PER_PIN;
1536 #define RK3568_DRV_PMU_OFFSET 0x70
1537 #define RK3568_DRV_GRF_OFFSET 0x200
1538 #define RK3568_DRV_BITS_PER_PIN 8
1539 #define RK3568_DRV_PINS_PER_REG 2
1540 #define RK3568_DRV_BANK_STRIDE 0x40
1542 static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1543 int pin_num, struct regmap **regmap,
1546 struct rockchip_pinctrl *info = bank->drvdata;
1548 /* The first 32 pins of the first bank are located in PMU */
1549 if (bank->bank_num == 0) {
1550 *regmap = info->regmap_pmu;
1551 *reg = RK3568_DRV_PMU_OFFSET;
1552 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1554 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
1555 *bit *= RK3568_DRV_BITS_PER_PIN;
1557 *regmap = info->regmap_base;
1558 *reg = RK3568_DRV_GRF_OFFSET;
1559 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
1560 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1562 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
1563 *bit *= RK3568_DRV_BITS_PER_PIN;
1567 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1568 { 2, 4, 8, 12, -1, -1, -1, -1 },
1569 { 3, 6, 9, 12, -1, -1, -1, -1 },
1570 { 5, 10, 15, 20, -1, -1, -1, -1 },
1571 { 4, 6, 8, 10, 12, 14, 16, 18 },
1572 { 4, 7, 10, 13, 16, 19, 22, 26 }
1575 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1578 struct rockchip_pinctrl *info = bank->drvdata;
1579 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1580 struct device *dev = info->dev;
1581 struct regmap *regmap;
1583 u32 data, temp, rmask_bits;
1585 int drv_type = bank->drv[pin_num / 8].drv_type;
1587 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1590 case DRV_TYPE_IO_1V8_3V0_AUTO:
1591 case DRV_TYPE_IO_3V3_ONLY:
1592 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1595 /* regular case, nothing to do */
1599 * drive-strength offset is special, as it is
1600 * spread over 2 registers
1602 ret = regmap_read(regmap, reg, &data);
1606 ret = regmap_read(regmap, reg + 0x4, &temp);
1611 * the bit data[15] contains bit 0 of the value
1612 * while temp[1:0] contains bits 2 and 1
1619 return rockchip_perpin_drv_list[drv_type][data];
1621 /* setting fully enclosed in the second register */
1626 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1632 case DRV_TYPE_IO_DEFAULT:
1633 case DRV_TYPE_IO_1V8_OR_3V0:
1634 case DRV_TYPE_IO_1V8_ONLY:
1635 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1638 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
1642 ret = regmap_read(regmap, reg, &data);
1647 data &= (1 << rmask_bits) - 1;
1649 return rockchip_perpin_drv_list[drv_type][data];
1652 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1653 int pin_num, int strength)
1655 struct rockchip_pinctrl *info = bank->drvdata;
1656 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1657 struct device *dev = info->dev;
1658 struct regmap *regmap;
1660 u32 data, rmask, rmask_bits, temp;
1662 int drv_type = bank->drv[pin_num / 8].drv_type;
1664 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
1665 bank->bank_num, pin_num, strength);
1667 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1668 if (ctrl->type == RK3568) {
1669 rmask_bits = RK3568_DRV_BITS_PER_PIN;
1670 ret = (1 << (strength + 1)) - 1;
1675 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1676 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1679 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1680 ret = rockchip_perpin_drv_list[drv_type][i];
1686 dev_err(dev, "unsupported driver strength %d\n", strength);
1691 case DRV_TYPE_IO_1V8_3V0_AUTO:
1692 case DRV_TYPE_IO_3V3_ONLY:
1693 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1696 /* regular case, nothing to do */
1700 * drive-strength offset is special, as it is spread
1701 * over 2 registers, the bit data[15] contains bit 0
1702 * of the value while temp[1:0] contains bits 2 and 1
1704 data = (ret & 0x1) << 15;
1705 temp = (ret >> 0x1) & 0x3;
1707 rmask = BIT(15) | BIT(31);
1709 ret = regmap_update_bits(regmap, reg, rmask, data);
1713 rmask = 0x3 | (0x3 << 16);
1714 temp |= (0x3 << 16);
1716 ret = regmap_update_bits(regmap, reg, rmask, temp);
1720 /* setting fully enclosed in the second register */
1725 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1730 case DRV_TYPE_IO_DEFAULT:
1731 case DRV_TYPE_IO_1V8_OR_3V0:
1732 case DRV_TYPE_IO_1V8_ONLY:
1733 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1736 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
1741 /* enable the write to the equivalent lower bits */
1742 data = ((1 << rmask_bits) - 1) << (bit + 16);
1743 rmask = data | (data >> 16);
1744 data |= (ret << bit);
1746 ret = regmap_update_bits(regmap, reg, rmask, data);
1751 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1753 PIN_CONFIG_BIAS_DISABLE,
1754 PIN_CONFIG_BIAS_PULL_UP,
1755 PIN_CONFIG_BIAS_PULL_DOWN,
1756 PIN_CONFIG_BIAS_BUS_HOLD
1759 PIN_CONFIG_BIAS_DISABLE,
1760 PIN_CONFIG_BIAS_PULL_DOWN,
1761 PIN_CONFIG_BIAS_DISABLE,
1762 PIN_CONFIG_BIAS_PULL_UP
1766 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1768 struct rockchip_pinctrl *info = bank->drvdata;
1769 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1770 struct device *dev = info->dev;
1771 struct regmap *regmap;
1772 int reg, ret, pull_type;
1776 /* rk3066b does support any pulls */
1777 if (ctrl->type == RK3066B)
1778 return PIN_CONFIG_BIAS_DISABLE;
1780 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1782 ret = regmap_read(regmap, reg, &data);
1786 switch (ctrl->type) {
1789 return !(data & BIT(bit))
1790 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1791 : PIN_CONFIG_BIAS_DISABLE;
1799 pull_type = bank->pull_type[pin_num / 8];
1801 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1803 return rockchip_pull_list[pull_type][data];
1805 dev_err(dev, "unsupported pinctrl type\n");
1810 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1811 int pin_num, int pull)
1813 struct rockchip_pinctrl *info = bank->drvdata;
1814 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1815 struct device *dev = info->dev;
1816 struct regmap *regmap;
1817 int reg, ret, i, pull_type;
1821 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
1823 /* rk3066b does support any pulls */
1824 if (ctrl->type == RK3066B)
1825 return pull ? -EINVAL : 0;
1827 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1829 switch (ctrl->type) {
1832 data = BIT(bit + 16);
1833 if (pull == PIN_CONFIG_BIAS_DISABLE)
1835 ret = regmap_write(regmap, reg, data);
1845 pull_type = bank->pull_type[pin_num / 8];
1847 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1849 if (rockchip_pull_list[pull_type][i] == pull) {
1855 * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6,
1856 * where that pull up value becomes 3.
1858 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
1864 dev_err(dev, "unsupported pull setting %d\n", pull);
1868 /* enable the write to the equivalent lower bits */
1869 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1870 rmask = data | (data >> 16);
1871 data |= (ret << bit);
1873 ret = regmap_update_bits(regmap, reg, rmask, data);
1876 dev_err(dev, "unsupported pinctrl type\n");
1883 #define RK3328_SCHMITT_BITS_PER_PIN 1
1884 #define RK3328_SCHMITT_PINS_PER_REG 16
1885 #define RK3328_SCHMITT_BANK_STRIDE 8
1886 #define RK3328_SCHMITT_GRF_OFFSET 0x380
1888 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1890 struct regmap **regmap,
1893 struct rockchip_pinctrl *info = bank->drvdata;
1895 *regmap = info->regmap_base;
1896 *reg = RK3328_SCHMITT_GRF_OFFSET;
1898 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
1899 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
1900 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
1905 #define RK3568_SCHMITT_BITS_PER_PIN 2
1906 #define RK3568_SCHMITT_PINS_PER_REG 8
1907 #define RK3568_SCHMITT_BANK_STRIDE 0x10
1908 #define RK3568_SCHMITT_GRF_OFFSET 0xc0
1909 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
1911 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1913 struct regmap **regmap,
1916 struct rockchip_pinctrl *info = bank->drvdata;
1918 if (bank->bank_num == 0) {
1919 *regmap = info->regmap_pmu;
1920 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
1922 *regmap = info->regmap_base;
1923 *reg = RK3568_SCHMITT_GRF_OFFSET;
1924 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
1927 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
1928 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
1929 *bit *= RK3568_SCHMITT_BITS_PER_PIN;
1934 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
1936 struct rockchip_pinctrl *info = bank->drvdata;
1937 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1938 struct regmap *regmap;
1943 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
1947 ret = regmap_read(regmap, reg, &data);
1952 switch (ctrl->type) {
1954 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
1962 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
1963 int pin_num, int enable)
1965 struct rockchip_pinctrl *info = bank->drvdata;
1966 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1967 struct device *dev = info->dev;
1968 struct regmap *regmap;
1973 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
1974 bank->bank_num, pin_num, enable);
1976 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
1980 /* enable the write to the equivalent lower bits */
1981 switch (ctrl->type) {
1983 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
1984 rmask = data | (data >> 16);
1985 data |= ((enable ? 0x2 : 0x1) << bit);
1988 data = BIT(bit + 16) | (enable << bit);
1989 rmask = BIT(bit + 16) | BIT(bit);
1993 return regmap_update_bits(regmap, reg, rmask, data);
1997 * Pinmux_ops handling
2000 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2002 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2004 return info->nfunctions;
2007 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2010 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2012 return info->functions[selector].name;
2015 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2016 unsigned selector, const char * const **groups,
2017 unsigned * const num_groups)
2019 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2021 *groups = info->functions[selector].groups;
2022 *num_groups = info->functions[selector].ngroups;
2027 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2030 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2031 const unsigned int *pins = info->groups[group].pins;
2032 const struct rockchip_pin_config *data = info->groups[group].data;
2033 struct device *dev = info->dev;
2034 struct rockchip_pin_bank *bank;
2037 dev_dbg(dev, "enable function %s group %s\n",
2038 info->functions[selector].name, info->groups[group].name);
2041 * for each pin in the pin group selected, program the corresponding
2042 * pin function number in the config register.
2044 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2045 bank = pin_to_bank(info, pins[cnt]);
2046 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2053 /* revert the already done pin settings */
2054 for (cnt--; cnt >= 0; cnt--)
2055 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2063 static const struct pinmux_ops rockchip_pmx_ops = {
2064 .get_functions_count = rockchip_pmx_get_funcs_count,
2065 .get_function_name = rockchip_pmx_get_func_name,
2066 .get_function_groups = rockchip_pmx_get_groups,
2067 .set_mux = rockchip_pmx_set,
2071 * Pinconf_ops handling
2074 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2075 enum pin_config_param pull)
2077 switch (ctrl->type) {
2080 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2081 pull == PIN_CONFIG_BIAS_DISABLE);
2083 return pull ? false : true;
2092 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2098 static int rockchip_pinconf_defer_output(struct rockchip_pin_bank *bank,
2099 unsigned int pin, u32 arg)
2101 struct rockchip_pin_output_deferred *cfg;
2103 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
2110 list_add_tail(&cfg->head, &bank->deferred_output);
2115 /* set the pin config settings for a specified pin */
2116 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2117 unsigned long *configs, unsigned num_configs)
2119 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2120 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2121 struct gpio_chip *gpio = &bank->gpio_chip;
2122 enum pin_config_param param;
2127 for (i = 0; i < num_configs; i++) {
2128 param = pinconf_to_config_param(configs[i]);
2129 arg = pinconf_to_config_argument(configs[i]);
2132 case PIN_CONFIG_BIAS_DISABLE:
2133 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2138 case PIN_CONFIG_BIAS_PULL_UP:
2139 case PIN_CONFIG_BIAS_PULL_DOWN:
2140 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2141 case PIN_CONFIG_BIAS_BUS_HOLD:
2142 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2148 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2153 case PIN_CONFIG_OUTPUT:
2154 rc = rockchip_set_mux(bank, pin - bank->pin_base,
2156 if (rc != RK_FUNC_GPIO)
2160 * Check for gpio driver not being probed yet.
2161 * The lock makes sure that either gpio-probe has completed
2162 * or the gpio driver hasn't probed yet.
2164 mutex_lock(&bank->deferred_lock);
2165 if (!gpio || !gpio->direction_output) {
2166 rc = rockchip_pinconf_defer_output(bank, pin - bank->pin_base, arg);
2167 mutex_unlock(&bank->deferred_lock);
2173 mutex_unlock(&bank->deferred_lock);
2175 rc = gpio->direction_output(gpio, pin - bank->pin_base,
2180 case PIN_CONFIG_DRIVE_STRENGTH:
2181 /* rk3288 is the first with per-pin drive-strength */
2182 if (!info->ctrl->drv_calc_reg)
2185 rc = rockchip_set_drive_perpin(bank,
2186 pin - bank->pin_base, arg);
2190 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2191 if (!info->ctrl->schmitt_calc_reg)
2194 rc = rockchip_set_schmitt(bank,
2195 pin - bank->pin_base, arg);
2203 } /* for each config */
2208 /* get the pin config settings for a specified pin */
2209 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2210 unsigned long *config)
2212 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2213 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2214 struct gpio_chip *gpio = &bank->gpio_chip;
2215 enum pin_config_param param = pinconf_to_config_param(*config);
2220 case PIN_CONFIG_BIAS_DISABLE:
2221 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2226 case PIN_CONFIG_BIAS_PULL_UP:
2227 case PIN_CONFIG_BIAS_PULL_DOWN:
2228 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2229 case PIN_CONFIG_BIAS_BUS_HOLD:
2230 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2233 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2238 case PIN_CONFIG_OUTPUT:
2239 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2240 if (rc != RK_FUNC_GPIO)
2243 if (!gpio || !gpio->get) {
2248 rc = gpio->get(gpio, pin - bank->pin_base);
2254 case PIN_CONFIG_DRIVE_STRENGTH:
2255 /* rk3288 is the first with per-pin drive-strength */
2256 if (!info->ctrl->drv_calc_reg)
2259 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2265 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2266 if (!info->ctrl->schmitt_calc_reg)
2269 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2280 *config = pinconf_to_config_packed(param, arg);
2285 static const struct pinconf_ops rockchip_pinconf_ops = {
2286 .pin_config_get = rockchip_pinconf_get,
2287 .pin_config_set = rockchip_pinconf_set,
2291 static const struct of_device_id rockchip_bank_match[] = {
2292 { .compatible = "rockchip,gpio-bank" },
2293 { .compatible = "rockchip,rk3188-gpio-bank0" },
2297 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2298 struct device_node *np)
2300 struct device_node *child;
2302 for_each_child_of_node(np, child) {
2303 if (of_match_node(rockchip_bank_match, child))
2307 info->ngroups += of_get_child_count(child);
2311 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2312 struct rockchip_pin_group *grp,
2313 struct rockchip_pinctrl *info,
2316 struct device *dev = info->dev;
2317 struct rockchip_pin_bank *bank;
2324 dev_dbg(dev, "group(%d): %pOFn\n", index, np);
2326 /* Initialise group */
2327 grp->name = np->name;
2330 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2331 * do sanity check and calculate pins number
2333 list = of_get_property(np, "rockchip,pins", &size);
2334 /* we do not check return since it's safe node passed down */
2335 size /= sizeof(*list);
2336 if (!size || size % 4)
2337 return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n");
2339 grp->npins = size / 4;
2341 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
2342 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
2343 if (!grp->pins || !grp->data)
2346 for (i = 0, j = 0; i < size; i += 4, j++) {
2347 const __be32 *phandle;
2348 struct device_node *np_config;
2350 num = be32_to_cpu(*list++);
2351 bank = bank_num_to_bank(info, num);
2353 return PTR_ERR(bank);
2355 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2356 grp->data[j].func = be32_to_cpu(*list++);
2362 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2363 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2364 &grp->data[j].configs, &grp->data[j].nconfigs);
2372 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2373 struct rockchip_pinctrl *info,
2376 struct device *dev = info->dev;
2377 struct device_node *child;
2378 struct rockchip_pmx_func *func;
2379 struct rockchip_pin_group *grp;
2381 static u32 grp_index;
2384 dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
2386 func = &info->functions[index];
2388 /* Initialise function */
2389 func->name = np->name;
2390 func->ngroups = of_get_child_count(np);
2391 if (func->ngroups <= 0)
2394 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
2398 for_each_child_of_node(np, child) {
2399 func->groups[i] = child->name;
2400 grp = &info->groups[grp_index++];
2401 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2411 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2412 struct rockchip_pinctrl *info)
2414 struct device *dev = &pdev->dev;
2415 struct device_node *np = dev->of_node;
2416 struct device_node *child;
2420 rockchip_pinctrl_child_count(info, np);
2422 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
2423 dev_dbg(dev, "ngroups = %d\n", info->ngroups);
2425 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
2426 if (!info->functions)
2429 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
2435 for_each_child_of_node(np, child) {
2436 if (of_match_node(rockchip_bank_match, child))
2439 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2441 dev_err(dev, "failed to parse function\n");
2450 static int rockchip_pinctrl_register(struct platform_device *pdev,
2451 struct rockchip_pinctrl *info)
2453 struct pinctrl_desc *ctrldesc = &info->pctl;
2454 struct pinctrl_pin_desc *pindesc, *pdesc;
2455 struct rockchip_pin_bank *pin_bank;
2456 struct device *dev = &pdev->dev;
2461 ctrldesc->name = "rockchip-pinctrl";
2462 ctrldesc->owner = THIS_MODULE;
2463 ctrldesc->pctlops = &rockchip_pctrl_ops;
2464 ctrldesc->pmxops = &rockchip_pmx_ops;
2465 ctrldesc->confops = &rockchip_pinconf_ops;
2467 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
2471 ctrldesc->pins = pindesc;
2472 ctrldesc->npins = info->ctrl->nr_pins;
2475 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
2476 pin_bank = &info->ctrl->pin_banks[bank];
2478 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins);
2479 if (IS_ERR(pin_names))
2480 return PTR_ERR(pin_names);
2482 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2484 pdesc->name = pin_names[pin];
2488 INIT_LIST_HEAD(&pin_bank->deferred_output);
2489 mutex_init(&pin_bank->deferred_lock);
2492 ret = rockchip_pinctrl_parse_dt(pdev, info);
2496 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
2497 if (IS_ERR(info->pctl_dev))
2498 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
2503 static const struct of_device_id rockchip_pinctrl_dt_match[];
2505 /* retrieve the soc specific data */
2506 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2507 struct rockchip_pinctrl *d,
2508 struct platform_device *pdev)
2510 struct device *dev = &pdev->dev;
2511 struct device_node *node = dev->of_node;
2512 const struct of_device_id *match;
2513 struct rockchip_pin_ctrl *ctrl;
2514 struct rockchip_pin_bank *bank;
2515 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2517 match = of_match_node(rockchip_pinctrl_dt_match, node);
2518 ctrl = (struct rockchip_pin_ctrl *)match->data;
2520 grf_offs = ctrl->grf_mux_offset;
2521 pmu_offs = ctrl->pmu_mux_offset;
2522 drv_pmu_offs = ctrl->pmu_drv_offset;
2523 drv_grf_offs = ctrl->grf_drv_offset;
2524 bank = ctrl->pin_banks;
2525 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2528 raw_spin_lock_init(&bank->slock);
2530 bank->pin_base = ctrl->nr_pins;
2531 ctrl->nr_pins += bank->nr_pins;
2533 /* calculate iomux and drv offsets */
2534 for (j = 0; j < 4; j++) {
2535 struct rockchip_iomux *iom = &bank->iomux[j];
2536 struct rockchip_drv *drv = &bank->drv[j];
2539 if (bank_pins >= bank->nr_pins)
2542 /* preset iomux offset value, set new start value */
2543 if (iom->offset >= 0) {
2544 if (iom->type & IOMUX_SOURCE_PMU)
2545 pmu_offs = iom->offset;
2547 grf_offs = iom->offset;
2548 } else { /* set current iomux offset */
2549 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2550 pmu_offs : grf_offs;
2553 /* preset drv offset value, set new start value */
2554 if (drv->offset >= 0) {
2555 if (iom->type & IOMUX_SOURCE_PMU)
2556 drv_pmu_offs = drv->offset;
2558 drv_grf_offs = drv->offset;
2559 } else { /* set current drv offset */
2560 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2561 drv_pmu_offs : drv_grf_offs;
2564 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2565 i, j, iom->offset, drv->offset);
2568 * Increase offset according to iomux width.
2569 * 4bit iomux'es are spread over two registers.
2571 inc = (iom->type & (IOMUX_WIDTH_4BIT |
2573 IOMUX_WIDTH_2BIT)) ? 8 : 4;
2574 if (iom->type & IOMUX_SOURCE_PMU)
2580 * Increase offset according to drv width.
2581 * 3bit drive-strenth'es are spread over two registers.
2583 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2584 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2589 if (iom->type & IOMUX_SOURCE_PMU)
2590 drv_pmu_offs += inc;
2592 drv_grf_offs += inc;
2597 /* calculate the per-bank recalced_mask */
2598 for (j = 0; j < ctrl->niomux_recalced; j++) {
2601 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
2602 pin = ctrl->iomux_recalced[j].pin;
2603 bank->recalced_mask |= BIT(pin);
2607 /* calculate the per-bank route_mask */
2608 for (j = 0; j < ctrl->niomux_routes; j++) {
2611 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
2612 pin = ctrl->iomux_routes[j].pin;
2613 bank->route_mask |= BIT(pin);
2621 #define RK3288_GRF_GPIO6C_IOMUX 0x64
2622 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
2624 static u32 rk3288_grf_gpio6c_iomux;
2626 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2628 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2629 int ret = pinctrl_force_sleep(info->pctl_dev);
2635 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2636 * the setting here, and restore it at resume.
2638 if (info->ctrl->type == RK3288) {
2639 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2640 &rk3288_grf_gpio6c_iomux);
2642 pinctrl_force_default(info->pctl_dev);
2650 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2652 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2655 if (info->ctrl->type == RK3288) {
2656 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2657 rk3288_grf_gpio6c_iomux |
2658 GPIO6C6_SEL_WRITE_ENABLE);
2663 return pinctrl_force_default(info->pctl_dev);
2666 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2667 rockchip_pinctrl_resume);
2669 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2671 struct rockchip_pinctrl *info;
2672 struct device *dev = &pdev->dev;
2673 struct device_node *np = dev->of_node, *node;
2674 struct rockchip_pin_ctrl *ctrl;
2675 struct resource *res;
2680 return dev_err_probe(dev, -ENODEV, "device tree node not found\n");
2682 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
2688 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2690 return dev_err_probe(dev, -EINVAL, "driver data not available\n");
2693 node = of_parse_phandle(np, "rockchip,grf", 0);
2695 info->regmap_base = syscon_node_to_regmap(node);
2697 if (IS_ERR(info->regmap_base))
2698 return PTR_ERR(info->regmap_base);
2700 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2702 return PTR_ERR(base);
2704 rockchip_regmap_config.max_register = resource_size(res) - 4;
2705 rockchip_regmap_config.name = "rockchip,pinctrl";
2707 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
2709 /* to check for the old dt-bindings */
2710 info->reg_size = resource_size(res);
2712 /* Honor the old binding, with pull registers as 2nd resource */
2713 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2714 base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
2716 return PTR_ERR(base);
2718 rockchip_regmap_config.max_register = resource_size(res) - 4;
2719 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2721 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
2725 /* try to find the optional reference to the pmu syscon */
2726 node = of_parse_phandle(np, "rockchip,pmu", 0);
2728 info->regmap_pmu = syscon_node_to_regmap(node);
2730 if (IS_ERR(info->regmap_pmu))
2731 return PTR_ERR(info->regmap_pmu);
2734 ret = rockchip_pinctrl_register(pdev, info);
2738 platform_set_drvdata(pdev, info);
2740 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
2742 return dev_err_probe(dev, ret, "failed to register gpio device\n");
2747 static int rockchip_pinctrl_remove(struct platform_device *pdev)
2749 struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
2750 struct rockchip_pin_bank *bank;
2751 struct rockchip_pin_output_deferred *cfg;
2754 of_platform_depopulate(&pdev->dev);
2756 for (i = 0; i < info->ctrl->nr_banks; i++) {
2757 bank = &info->ctrl->pin_banks[i];
2759 mutex_lock(&bank->deferred_lock);
2760 while (!list_empty(&bank->deferred_output)) {
2761 cfg = list_first_entry(&bank->deferred_output,
2762 struct rockchip_pin_output_deferred, head);
2763 list_del(&cfg->head);
2766 mutex_unlock(&bank->deferred_lock);
2772 static struct rockchip_pin_bank px30_pin_banks[] = {
2773 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2778 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
2783 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
2788 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
2795 static struct rockchip_pin_ctrl px30_pin_ctrl = {
2796 .pin_banks = px30_pin_banks,
2797 .nr_banks = ARRAY_SIZE(px30_pin_banks),
2798 .label = "PX30-GPIO",
2800 .grf_mux_offset = 0x0,
2801 .pmu_mux_offset = 0x0,
2802 .iomux_routes = px30_mux_route_data,
2803 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
2804 .pull_calc_reg = px30_calc_pull_reg_and_bit,
2805 .drv_calc_reg = px30_calc_drv_reg_and_bit,
2806 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
2809 static struct rockchip_pin_bank rv1108_pin_banks[] = {
2810 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2814 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2815 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2816 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2819 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
2820 .pin_banks = rv1108_pin_banks,
2821 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
2822 .label = "RV1108-GPIO",
2824 .grf_mux_offset = 0x10,
2825 .pmu_mux_offset = 0x0,
2826 .iomux_recalced = rv1108_mux_recalced_data,
2827 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
2828 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
2829 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
2830 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
2833 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2834 PIN_BANK(0, 32, "gpio0"),
2835 PIN_BANK(1, 32, "gpio1"),
2836 PIN_BANK(2, 32, "gpio2"),
2837 PIN_BANK(3, 32, "gpio3"),
2840 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2841 .pin_banks = rk2928_pin_banks,
2842 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
2843 .label = "RK2928-GPIO",
2845 .grf_mux_offset = 0xa8,
2846 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2849 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2850 PIN_BANK(0, 32, "gpio0"),
2851 PIN_BANK(1, 32, "gpio1"),
2852 PIN_BANK(2, 32, "gpio2"),
2855 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2856 .pin_banks = rk3036_pin_banks,
2857 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
2858 .label = "RK3036-GPIO",
2860 .grf_mux_offset = 0xa8,
2861 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2864 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2865 PIN_BANK(0, 32, "gpio0"),
2866 PIN_BANK(1, 32, "gpio1"),
2867 PIN_BANK(2, 32, "gpio2"),
2868 PIN_BANK(3, 32, "gpio3"),
2869 PIN_BANK(4, 32, "gpio4"),
2870 PIN_BANK(6, 16, "gpio6"),
2873 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2874 .pin_banks = rk3066a_pin_banks,
2875 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
2876 .label = "RK3066a-GPIO",
2878 .grf_mux_offset = 0xa8,
2879 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2882 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2883 PIN_BANK(0, 32, "gpio0"),
2884 PIN_BANK(1, 32, "gpio1"),
2885 PIN_BANK(2, 32, "gpio2"),
2886 PIN_BANK(3, 32, "gpio3"),
2889 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2890 .pin_banks = rk3066b_pin_banks,
2891 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
2892 .label = "RK3066b-GPIO",
2894 .grf_mux_offset = 0x60,
2897 static struct rockchip_pin_bank rk3128_pin_banks[] = {
2898 PIN_BANK(0, 32, "gpio0"),
2899 PIN_BANK(1, 32, "gpio1"),
2900 PIN_BANK(2, 32, "gpio2"),
2901 PIN_BANK(3, 32, "gpio3"),
2904 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
2905 .pin_banks = rk3128_pin_banks,
2906 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
2907 .label = "RK3128-GPIO",
2909 .grf_mux_offset = 0xa8,
2910 .iomux_recalced = rk3128_mux_recalced_data,
2911 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
2912 .iomux_routes = rk3128_mux_route_data,
2913 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
2914 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
2917 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2918 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2919 PIN_BANK(1, 32, "gpio1"),
2920 PIN_BANK(2, 32, "gpio2"),
2921 PIN_BANK(3, 32, "gpio3"),
2924 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2925 .pin_banks = rk3188_pin_banks,
2926 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
2927 .label = "RK3188-GPIO",
2929 .grf_mux_offset = 0x60,
2930 .iomux_routes = rk3188_mux_route_data,
2931 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
2932 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
2935 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2936 PIN_BANK(0, 32, "gpio0"),
2937 PIN_BANK(1, 32, "gpio1"),
2938 PIN_BANK(2, 32, "gpio2"),
2939 PIN_BANK(3, 32, "gpio3"),
2942 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2943 .pin_banks = rk3228_pin_banks,
2944 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
2945 .label = "RK3228-GPIO",
2947 .grf_mux_offset = 0x0,
2948 .iomux_routes = rk3228_mux_route_data,
2949 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
2950 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
2951 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
2954 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2955 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2960 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2965 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2966 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2967 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2972 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2977 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2978 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2983 PIN_BANK(8, 16, "gpio8"),
2986 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2987 .pin_banks = rk3288_pin_banks,
2988 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
2989 .label = "RK3288-GPIO",
2991 .grf_mux_offset = 0x0,
2992 .pmu_mux_offset = 0x84,
2993 .iomux_routes = rk3288_mux_route_data,
2994 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
2995 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
2996 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
2999 static struct rockchip_pin_bank rk3308_pin_banks[] = {
3000 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
3004 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
3008 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
3012 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
3016 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
3022 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
3023 .pin_banks = rk3308_pin_banks,
3024 .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
3025 .label = "RK3308-GPIO",
3027 .grf_mux_offset = 0x0,
3028 .iomux_recalced = rk3308_mux_recalced_data,
3029 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
3030 .iomux_routes = rk3308_mux_route_data,
3031 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
3032 .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
3033 .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
3034 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
3037 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3038 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3039 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3040 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3044 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3051 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3052 .pin_banks = rk3328_pin_banks,
3053 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3054 .label = "RK3328-GPIO",
3056 .grf_mux_offset = 0x0,
3057 .iomux_recalced = rk3328_mux_recalced_data,
3058 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
3059 .iomux_routes = rk3328_mux_route_data,
3060 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3061 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3062 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3063 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3066 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3067 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3072 PIN_BANK(1, 32, "gpio1"),
3073 PIN_BANK(2, 32, "gpio2"),
3074 PIN_BANK(3, 32, "gpio3"),
3077 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3078 .pin_banks = rk3368_pin_banks,
3079 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3080 .label = "RK3368-GPIO",
3082 .grf_mux_offset = 0x0,
3083 .pmu_mux_offset = 0x0,
3084 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3085 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3088 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3089 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3094 DRV_TYPE_IO_1V8_ONLY,
3095 DRV_TYPE_IO_1V8_ONLY,
3096 DRV_TYPE_IO_DEFAULT,
3097 DRV_TYPE_IO_DEFAULT,
3102 PULL_TYPE_IO_1V8_ONLY,
3103 PULL_TYPE_IO_1V8_ONLY,
3104 PULL_TYPE_IO_DEFAULT,
3105 PULL_TYPE_IO_DEFAULT
3107 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3111 DRV_TYPE_IO_1V8_OR_3V0,
3112 DRV_TYPE_IO_1V8_OR_3V0,
3113 DRV_TYPE_IO_1V8_OR_3V0,
3114 DRV_TYPE_IO_1V8_OR_3V0,
3120 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3121 DRV_TYPE_IO_1V8_OR_3V0,
3122 DRV_TYPE_IO_1V8_ONLY,
3123 DRV_TYPE_IO_1V8_ONLY,
3124 PULL_TYPE_IO_DEFAULT,
3125 PULL_TYPE_IO_DEFAULT,
3126 PULL_TYPE_IO_1V8_ONLY,
3127 PULL_TYPE_IO_1V8_ONLY
3129 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3130 DRV_TYPE_IO_3V3_ONLY,
3131 DRV_TYPE_IO_3V3_ONLY,
3132 DRV_TYPE_IO_1V8_OR_3V0
3134 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3135 DRV_TYPE_IO_1V8_3V0_AUTO,
3136 DRV_TYPE_IO_1V8_OR_3V0,
3137 DRV_TYPE_IO_1V8_OR_3V0
3141 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3142 .pin_banks = rk3399_pin_banks,
3143 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3144 .label = "RK3399-GPIO",
3146 .grf_mux_offset = 0xe000,
3147 .pmu_mux_offset = 0x0,
3148 .grf_drv_offset = 0xe100,
3149 .pmu_drv_offset = 0x80,
3150 .iomux_routes = rk3399_mux_route_data,
3151 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
3152 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3153 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3156 static struct rockchip_pin_bank rk3568_pin_banks[] = {
3157 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3158 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3159 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3160 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
3161 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3165 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3169 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3173 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3179 static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
3180 .pin_banks = rk3568_pin_banks,
3181 .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
3182 .label = "RK3568-GPIO",
3184 .grf_mux_offset = 0x0,
3185 .pmu_mux_offset = 0x0,
3186 .grf_drv_offset = 0x0200,
3187 .pmu_drv_offset = 0x0070,
3188 .iomux_routes = rk3568_mux_route_data,
3189 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
3190 .pull_calc_reg = rk3568_calc_pull_reg_and_bit,
3191 .drv_calc_reg = rk3568_calc_drv_reg_and_bit,
3192 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
3195 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3196 { .compatible = "rockchip,px30-pinctrl",
3197 .data = &px30_pin_ctrl },
3198 { .compatible = "rockchip,rv1108-pinctrl",
3199 .data = &rv1108_pin_ctrl },
3200 { .compatible = "rockchip,rk2928-pinctrl",
3201 .data = &rk2928_pin_ctrl },
3202 { .compatible = "rockchip,rk3036-pinctrl",
3203 .data = &rk3036_pin_ctrl },
3204 { .compatible = "rockchip,rk3066a-pinctrl",
3205 .data = &rk3066a_pin_ctrl },
3206 { .compatible = "rockchip,rk3066b-pinctrl",
3207 .data = &rk3066b_pin_ctrl },
3208 { .compatible = "rockchip,rk3128-pinctrl",
3209 .data = (void *)&rk3128_pin_ctrl },
3210 { .compatible = "rockchip,rk3188-pinctrl",
3211 .data = &rk3188_pin_ctrl },
3212 { .compatible = "rockchip,rk3228-pinctrl",
3213 .data = &rk3228_pin_ctrl },
3214 { .compatible = "rockchip,rk3288-pinctrl",
3215 .data = &rk3288_pin_ctrl },
3216 { .compatible = "rockchip,rk3308-pinctrl",
3217 .data = &rk3308_pin_ctrl },
3218 { .compatible = "rockchip,rk3328-pinctrl",
3219 .data = &rk3328_pin_ctrl },
3220 { .compatible = "rockchip,rk3368-pinctrl",
3221 .data = &rk3368_pin_ctrl },
3222 { .compatible = "rockchip,rk3399-pinctrl",
3223 .data = &rk3399_pin_ctrl },
3224 { .compatible = "rockchip,rk3568-pinctrl",
3225 .data = &rk3568_pin_ctrl },
3229 static struct platform_driver rockchip_pinctrl_driver = {
3230 .probe = rockchip_pinctrl_probe,
3231 .remove = rockchip_pinctrl_remove,
3233 .name = "rockchip-pinctrl",
3234 .pm = &rockchip_pinctrl_dev_pm_ops,
3235 .of_match_table = rockchip_pinctrl_dt_match,
3239 static int __init rockchip_pinctrl_drv_register(void)
3241 return platform_driver_register(&rockchip_pinctrl_driver);
3243 postcore_initcall(rockchip_pinctrl_drv_register);
3245 static void __exit rockchip_pinctrl_drv_unregister(void)
3247 platform_driver_unregister(&rockchip_pinctrl_driver);
3249 module_exit(rockchip_pinctrl_drv_unregister);
3251 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
3252 MODULE_LICENSE("GPL");
3253 MODULE_ALIAS("platform:pinctrl-rockchip");
3254 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);