drivers/pinctrl/pinctrl-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Pinctrl driver for Rockchip SoCs
   4  *
   5  * Copyright (c) 2013 MundoReader S.L.
   6  * Author: Heiko Stuebner <heiko@sntech.de>
   7  *
   8  * With some ideas taken from pinctrl-samsung:
   9  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  10  *              http://www.samsung.com
  11  * Copyright (c) 2012 Linaro Ltd
  12  *              https://www.linaro.org
  13  *
  14  * and pinctrl-at91:
  15  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/io.h>
  22 #include <linux/bitops.h>
  23 #include <linux/gpio/driver.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/pinctrl/machine.h>
  28 #include <linux/pinctrl/pinconf.h>
  29 #include <linux/pinctrl/pinctrl.h>
  30 #include <linux/pinctrl/pinmux.h>
  31 #include <linux/pinctrl/pinconf-generic.h>
  32 #include <linux/irqchip/chained_irq.h>
  33 #include <linux/clk.h>
  34 #include <linux/regmap.h>
  35 #include <linux/mfd/syscon.h>
  36 #include <dt-bindings/pinctrl/rockchip.h>
  37
  38 #include "core.h"
  39 #include "pinconf.h"
  40 #include "pinctrl-rockchip.h"
  41
  42 /**
  43  * Generate a bitmask for setting a value (v) with a write mask bit in hiword
  44  * register 31:16 area.
  45  */
  46 #define WRITE_MASK_VAL(h, l, v) \
  47         (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
  48
  49 /*
  50  * Encode variants of iomux registers into a type variable
  51  */
  52 #define IOMUX_GPIO_ONLY         BIT(0)
  53 #define IOMUX_WIDTH_4BIT        BIT(1)
  54 #define IOMUX_SOURCE_PMU        BIT(2)
  55 #define IOMUX_UNROUTED          BIT(3)
  56 #define IOMUX_WIDTH_3BIT        BIT(4)
  57 #define IOMUX_WIDTH_2BIT        BIT(5)
  58
  59 #define PIN_BANK(id, pins, label)                       \
  60         {                                               \
  61                 .bank_num       = id,                   \
  62                 .nr_pins        = pins,                 \
  63                 .name           = label,                \
  64                 .iomux          = {                     \
  65                         { .offset = -1 },               \
  66                         { .offset = -1 },               \
  67                         { .offset = -1 },               \
  68                         { .offset = -1 },               \
  69                 },                                      \
  70         }
  71
  72 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
  73         {                                                               \
  74                 .bank_num       = id,                                   \
  75                 .nr_pins        = pins,                                 \
  76                 .name           = label,                                \
  77                 .iomux          = {                                     \
  78                         { .type = iom0, .offset = -1 },                 \
  79                         { .type = iom1, .offset = -1 },                 \
  80                         { .type = iom2, .offset = -1 },                 \
  81                         { .type = iom3, .offset = -1 },                 \
  82                 },                                                      \
  83         }
  84
  85 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
  86         {                                                               \
  87                 .bank_num       = id,                                   \
  88                 .nr_pins        = pins,                                 \
  89                 .name           = label,                                \
  90                 .iomux          = {                                     \
  91                         { .offset = -1 },                               \
  92                         { .offset = -1 },                               \
  93                         { .offset = -1 },                               \
  94                         { .offset = -1 },                               \
  95                 },                                                      \
  96                 .drv            = {                                     \
  97                         { .drv_type = type0, .offset = -1 },            \
  98                         { .drv_type = type1, .offset = -1 },            \
  99                         { .drv_type = type2, .offset = -1 },            \
 100                         { .drv_type = type3, .offset = -1 },            \
 101                 },                                                      \
 102         }
 103
 104 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,      \
 105                                       drv2, drv3, pull0, pull1,         \
 106                                       pull2, pull3)                     \
 107         {                                                               \
 108                 .bank_num       = id,                                   \
 109                 .nr_pins        = pins,                                 \
 110                 .name           = label,                                \
 111                 .iomux          = {                                     \
 112                         { .offset = -1 },                               \
 113                         { .offset = -1 },                               \
 114                         { .offset = -1 },                               \
 115                         { .offset = -1 },                               \
 116                 },                                                      \
 117                 .drv            = {                                     \
 118                         { .drv_type = drv0, .offset = -1 },             \
 119                         { .drv_type = drv1, .offset = -1 },             \
 120                         { .drv_type = drv2, .offset = -1 },             \
 121                         { .drv_type = drv3, .offset = -1 },             \
 122                 },                                                      \
 123                 .pull_type[0] = pull0,                                  \
 124                 .pull_type[1] = pull1,                                  \
 125                 .pull_type[2] = pull2,                                  \
 126                 .pull_type[3] = pull3,                                  \
 127         }
 128
 129 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
 130                                         iom2, iom3, drv0, drv1, drv2,   \
 131                                         drv3, offset0, offset1,         \
 132                                         offset2, offset3)               \
 133         {                                                               \
 134                 .bank_num       = id,                                   \
 135                 .nr_pins        = pins,                                 \
 136                 .name           = label,                                \
 137                 .iomux          = {                                     \
 138                         { .type = iom0, .offset = -1 },                 \
 139                         { .type = iom1, .offset = -1 },                 \
 140                         { .type = iom2, .offset = -1 },                 \
 141                         { .type = iom3, .offset = -1 },                 \
 142                 },                                                      \
 143                 .drv            = {                                     \
 144                         { .drv_type = drv0, .offset = offset0 },        \
 145                         { .drv_type = drv1, .offset = offset1 },        \
 146                         { .drv_type = drv2, .offset = offset2 },        \
 147                         { .drv_type = drv3, .offset = offset3 },        \
 148                 },                                                      \
 149         }
 150
 151 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 152                                               label, iom0, iom1, iom2,  \
 153                                               iom3, drv0, drv1, drv2,   \
 154                                               drv3, offset0, offset1,   \
 155                                               offset2, offset3, pull0,  \
 156                                               pull1, pull2, pull3)      \
 157         {                                                               \
 158                 .bank_num       = id,                                   \
 159                 .nr_pins        = pins,                                 \
 160                 .name           = label,                                \
 161                 .iomux          = {                                     \
 162                         { .type = iom0, .offset = -1 },                 \
 163                         { .type = iom1, .offset = -1 },                 \
 164                         { .type = iom2, .offset = -1 },                 \
 165                         { .type = iom3, .offset = -1 },                 \
 166                 },                                                      \
 167                 .drv            = {                                     \
 168                         { .drv_type = drv0, .offset = offset0 },        \
 169                         { .drv_type = drv1, .offset = offset1 },        \
 170                         { .drv_type = drv2, .offset = offset2 },        \
 171                         { .drv_type = drv3, .offset = offset3 },        \
 172                 },                                                      \
 173                 .pull_type[0] = pull0,                                  \
 174                 .pull_type[1] = pull1,                                  \
 175                 .pull_type[2] = pull2,                                  \
 176                 .pull_type[3] = pull3,                                  \
 177         }
 178
 179 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG)         \
 180         {                                                               \
 181                 .bank_num       = ID,                                   \
 182                 .pin            = PIN,                                  \
 183                 .func           = FUNC,                                 \
 184                 .route_offset   = REG,                                  \
 185                 .route_val      = VAL,                                  \
 186                 .route_location = FLAG,                                 \
 187         }
 188
 189 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL)       \
 190         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
 191
 192 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL)        \
 193         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
 194
 195 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL)        \
 196         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
 197
 198 static struct regmap_config rockchip_regmap_config = {
 199         .reg_bits = 32,
 200         .val_bits = 32,
 201         .reg_stride = 4,
 202 };
 203
 204 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
 205                                         const struct rockchip_pinctrl *info,
 206                                         const char *name)
 207 {
 208         int i;
 209
 210         for (i = 0; i < info->ngroups; i++) {
 211                 if (!strcmp(info->groups[i].name, name))
 212                         return &info->groups[i];
 213         }
 214
 215         return NULL;
 216 }
 217
 218 /*
 219  * given a pin number that is local to a pin controller, find out the pin bank
 220  * and the register base of the pin bank.
 221  */
 222 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 223                                                                 unsigned pin)
 224 {
 225         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 226
 227         while (pin >= (b->pin_base + b->nr_pins))
 228                 b++;
 229
 230         return b;
 231 }
 232
 233 static struct rockchip_pin_bank *bank_num_to_bank(
 234                                         struct rockchip_pinctrl *info,
 235                                         unsigned num)
 236 {
 237         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 238         int i;
 239
 240         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 241                 if (b->bank_num == num)
 242                         return b;
 243         }
 244
 245         return ERR_PTR(-EINVAL);
 246 }
 247
 248 /*
 249  * Pinctrl_ops handling
 250  */
 251
 252 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 253 {
 254         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 255
 256         return info->ngroups;
 257 }
 258
 259 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 260                                                         unsigned selector)
 261 {
 262         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 263
 264         return info->groups[selector].name;
 265 }
 266
 267 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 268                                       unsigned selector, const unsigned **pins,
 269                                       unsigned *npins)
 270 {
 271         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 272
 273         if (selector >= info->ngroups)
 274                 return -EINVAL;
 275
 276         *pins = info->groups[selector].pins;
 277         *npins = info->groups[selector].npins;
 278
 279         return 0;
 280 }
 281
 282 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 283                                  struct device_node *np,
 284                                  struct pinctrl_map **map, unsigned *num_maps)
 285 {
 286         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 287         const struct rockchip_pin_group *grp;
 288         struct pinctrl_map *new_map;
 289         struct device_node *parent;
 290         int map_num = 1;
 291         int i;
 292
 293         /*
 294          * first find the group of this node and check if we need to create
 295          * config maps for pins
 296          */
 297         grp = pinctrl_name_to_group(info, np->name);
 298         if (!grp) {
 299                 dev_err(info->dev, "unable to find group for node %pOFn\n",
 300                         np);
 301                 return -EINVAL;
 302         }
 303
 304         map_num += grp->npins;
 305
 306         new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
 307         if (!new_map)
 308                 return -ENOMEM;
 309
 310         *map = new_map;
 311         *num_maps = map_num;
 312
 313         /* create mux map */
 314         parent = of_get_parent(np);
 315         if (!parent) {
 316                 kfree(new_map);
 317                 return -EINVAL;
 318         }
 319         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 320         new_map[0].data.mux.function = parent->name;
 321         new_map[0].data.mux.group = np->name;
 322         of_node_put(parent);
 323
 324         /* create config map */
 325         new_map++;
 326         for (i = 0; i < grp->npins; i++) {
 327                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 328                 new_map[i].data.configs.group_or_pin =
 329                                 pin_get_name(pctldev, grp->pins[i]);
 330                 new_map[i].data.configs.configs = grp->data[i].configs;
 331                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 332         }
 333
 334         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 335                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 336
 337         return 0;
 338 }
 339
 340 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 341                                     struct pinctrl_map *map, unsigned num_maps)
 342 {
 343         kfree(map);
 344 }
 345
 346 static const struct pinctrl_ops rockchip_pctrl_ops = {
 347         .get_groups_count       = rockchip_get_groups_count,
 348         .get_group_name         = rockchip_get_group_name,
 349         .get_group_pins         = rockchip_get_group_pins,
 350         .dt_node_to_map         = rockchip_dt_node_to_map,
 351         .dt_free_map            = rockchip_dt_free_map,
 352 };
 353
 354 /*
 355  * Hardware access
 356  */
 357
 358 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
 359         {
 360                 .num = 1,
 361                 .pin = 0,
 362                 .reg = 0x418,
 363                 .bit = 0,
 364                 .mask = 0x3
 365         }, {
 366                 .num = 1,
 367                 .pin = 1,
 368                 .reg = 0x418,
 369                 .bit = 2,
 370                 .mask = 0x3
 371         }, {
 372                 .num = 1,
 373                 .pin = 2,
 374                 .reg = 0x418,
 375                 .bit = 4,
 376                 .mask = 0x3
 377         }, {
 378                 .num = 1,
 379                 .pin = 3,
 380                 .reg = 0x418,
 381                 .bit = 6,
 382                 .mask = 0x3
 383         }, {
 384                 .num = 1,
 385                 .pin = 4,
 386                 .reg = 0x418,
 387                 .bit = 8,
 388                 .mask = 0x3
 389         }, {
 390                 .num = 1,
 391                 .pin = 5,
 392                 .reg = 0x418,
 393                 .bit = 10,
 394                 .mask = 0x3
 395         }, {
 396                 .num = 1,
 397                 .pin = 6,
 398                 .reg = 0x418,
 399                 .bit = 12,
 400                 .mask = 0x3
 401         }, {
 402                 .num = 1,
 403                 .pin = 7,
 404                 .reg = 0x418,
 405                 .bit = 14,
 406                 .mask = 0x3
 407         }, {
 408                 .num = 1,
 409                 .pin = 8,
 410                 .reg = 0x41c,
 411                 .bit = 0,
 412                 .mask = 0x3
 413         }, {
 414                 .num = 1,
 415                 .pin = 9,
 416                 .reg = 0x41c,
 417                 .bit = 2,
 418                 .mask = 0x3
 419         },
 420 };
 421
 422 static  struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
 423         {
 424                 .num = 2,
 425                 .pin = 20,
 426                 .reg = 0xe8,
 427                 .bit = 0,
 428                 .mask = 0x7
 429         }, {
 430                 .num = 2,
 431                 .pin = 21,
 432                 .reg = 0xe8,
 433                 .bit = 4,
 434                 .mask = 0x7
 435         }, {
 436                 .num = 2,
 437                 .pin = 22,
 438                 .reg = 0xe8,
 439                 .bit = 8,
 440                 .mask = 0x7
 441         }, {
 442                 .num = 2,
 443                 .pin = 23,
 444                 .reg = 0xe8,
 445                 .bit = 12,
 446                 .mask = 0x7
 447         }, {
 448                 .num = 2,
 449                 .pin = 24,
 450                 .reg = 0xd4,
 451                 .bit = 12,
 452                 .mask = 0x7
 453         },
 454 };
 455
 456 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
 457         {
 458                 /* gpio1b6_sel */
 459                 .num = 1,
 460                 .pin = 14,
 461                 .reg = 0x28,
 462                 .bit = 12,
 463                 .mask = 0xf
 464         }, {
 465                 /* gpio1b7_sel */
 466                 .num = 1,
 467                 .pin = 15,
 468                 .reg = 0x2c,
 469                 .bit = 0,
 470                 .mask = 0x3
 471         }, {
 472                 /* gpio1c2_sel */
 473                 .num = 1,
 474                 .pin = 18,
 475                 .reg = 0x30,
 476                 .bit = 4,
 477                 .mask = 0xf
 478         }, {
 479                 /* gpio1c3_sel */
 480                 .num = 1,
 481                 .pin = 19,
 482                 .reg = 0x30,
 483                 .bit = 8,
 484                 .mask = 0xf
 485         }, {
 486                 /* gpio1c4_sel */
 487                 .num = 1,
 488                 .pin = 20,
 489                 .reg = 0x30,
 490                 .bit = 12,
 491                 .mask = 0xf
 492         }, {
 493                 /* gpio1c5_sel */
 494                 .num = 1,
 495                 .pin = 21,
 496                 .reg = 0x34,
 497                 .bit = 0,
 498                 .mask = 0xf
 499         }, {
 500                 /* gpio1c6_sel */
 501                 .num = 1,
 502                 .pin = 22,
 503                 .reg = 0x34,
 504                 .bit = 4,
 505                 .mask = 0xf
 506         }, {
 507                 /* gpio1c7_sel */
 508                 .num = 1,
 509                 .pin = 23,
 510                 .reg = 0x34,
 511                 .bit = 8,
 512                 .mask = 0xf
 513         }, {
 514                 /* gpio3b4_sel */
 515                 .num = 3,
 516                 .pin = 12,
 517                 .reg = 0x68,
 518                 .bit = 8,
 519                 .mask = 0xf
 520         }, {
 521                 /* gpio3b5_sel */
 522                 .num = 3,
 523                 .pin = 13,
 524                 .reg = 0x68,
 525                 .bit = 12,
 526                 .mask = 0xf
 527         }, {
 528                 /* gpio2a2_sel */
 529                 .num = 2,
 530                 .pin = 2,
 531                 .reg = 0x40,
 532                 .bit = 4,
 533                 .mask = 0x3
 534         }, {
 535                 /* gpio2a3_sel */
 536                 .num = 2,
 537                 .pin = 3,
 538                 .reg = 0x40,
 539                 .bit = 6,
 540                 .mask = 0x3
 541         }, {
 542                 /* gpio2c0_sel */
 543                 .num = 2,
 544                 .pin = 16,
 545                 .reg = 0x50,
 546                 .bit = 0,
 547                 .mask = 0x3
 548         }, {
 549                 /* gpio3b2_sel */
 550                 .num = 3,
 551                 .pin = 10,
 552                 .reg = 0x68,
 553                 .bit = 4,
 554                 .mask = 0x3
 555         }, {
 556                 /* gpio3b3_sel */
 557                 .num = 3,
 558                 .pin = 11,
 559                 .reg = 0x68,
 560                 .bit = 6,
 561                 .mask = 0x3
 562         },
 563 };
 564
 565 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 566         {
 567                 .num = 2,
 568                 .pin = 12,
 569                 .reg = 0x24,
 570                 .bit = 8,
 571                 .mask = 0x3
 572         }, {
 573                 .num = 2,
 574                 .pin = 15,
 575                 .reg = 0x28,
 576                 .bit = 0,
 577                 .mask = 0x7
 578         }, {
 579                 .num = 2,
 580                 .pin = 23,
 581                 .reg = 0x30,
 582                 .bit = 14,
 583                 .mask = 0x3
 584         },
 585 };
 586
 587 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
 588                                       int *reg, u8 *bit, int *mask)
 589 {
 590         struct rockchip_pinctrl *info = bank->drvdata;
 591         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 592         struct rockchip_mux_recalced_data *data;
 593         int i;
 594
 595         for (i = 0; i < ctrl->niomux_recalced; i++) {
 596                 data = &ctrl->iomux_recalced[i];
 597                 if (data->num == bank->bank_num &&
 598                     data->pin == pin)
 599                         break;
 600         }
 601
 602         if (i >= ctrl->niomux_recalced)
 603                 return;
 604
 605         *reg = data->reg;
 606         *mask = data->mask;
 607         *bit = data->bit;
 608 }
 609
 610 static struct rockchip_mux_route_data px30_mux_route_data[] = {
 611         RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
 612         RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
 613         RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
 614         RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
 615         RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
 616         RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
 617         RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
 618         RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
 619 };
 620
 621 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
 622         RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
 623         RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
 624         RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
 625         RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
 626         RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
 627         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
 628         RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
 629 };
 630
 631 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
 632         RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
 633         RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
 634 };
 635
 636 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
 637         RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
 638         RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
 639         RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
 640         RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
 641         RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
 642         RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
 643         RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
 644         RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
 645         RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
 646         RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
 647         RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
 648         RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
 649         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
 650         RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
 651         RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
 652         RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
 653         RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
 654         RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
 655 };
 656
 657 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
 658         RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
 659         RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
 660 };
 661
 662 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
 663         RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
 664         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
 665         RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
 666         RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
 667         RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
 668         RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
 669         RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
 670         RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
 671         RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
 672         RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
 673         RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
 674         RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
 675         RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
 676         RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
 677         RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
 678         RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
 679         RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
 680         RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
 681         RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
 682         RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
 683         RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
 684         RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
 685         RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
 686         RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
 687         RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
 688         RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
 689 };
 690
 691 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
 692         RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
 693         RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
 694         RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
 695         RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
 696         RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
 697         RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
 698         RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
 699         RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
 700         RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
 701         RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
 702         RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
 703         RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
 704 };
 705
 706 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
 707         RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
 708         RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
 709         RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
 710         RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
 711         RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
 712 };
 713
 714 static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
 715         RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
 716         RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
 717         RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
 718         RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
 719         RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
 720         RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
 721         RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
 722         RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
 723         RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
 724         RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
 725         RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
 726         RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
 727         RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
 728         RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
 729         RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
 730         RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
 731         RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
 732         RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
 733         RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
 734         RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
 735         RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
 736         RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
 737         RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
 738         RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
 739         RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
 740         RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
 741         RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
 742         RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
 743         RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
 744         RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
 745         RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
 746         RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
 747         RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
 748         RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
 749         RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
 750         RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
 751         RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
 752         RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
 753         RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
 754         RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
 755         RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
 756         RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
 757         RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
 758         RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
 759         RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
 760         RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
 761         RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
 762         RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
 763         RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
 764         RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
 765         RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
 766         RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
 767         RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
 768         RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
 769         RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
 770         RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
 771         RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
 772         RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
 773         RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
 774         RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
 775         RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
 776         RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
 777         RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
 778         RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
 779         RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
 780         RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
 781         RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
 782         RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
 783         RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
 784         RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
 785         RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
 786         RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
 787         RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
 788         RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
 789         RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
 790         RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
 791         RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
 792         RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
 793         RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
 794         RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
 795         RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
 796         RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
 797         RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
 798         RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
 799         RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
 800         RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
 801         RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
 802         RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
 803         RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
 804         RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
 805         RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
 806         RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
 807         RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
 808 };
 809
 810 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
 811                                    int mux, u32 *loc, u32 *reg, u32 *value)
 812 {
 813         struct rockchip_pinctrl *info = bank->drvdata;
 814         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 815         struct rockchip_mux_route_data *data;
 816         int i;
 817
 818         for (i = 0; i < ctrl->niomux_routes; i++) {
 819                 data = &ctrl->iomux_routes[i];
 820                 if ((data->bank_num == bank->bank_num) &&
 821                     (data->pin == pin) && (data->func == mux))
 822                         break;
 823         }
 824
 825         if (i >= ctrl->niomux_routes)
 826                 return false;
 827
 828         *loc = data->route_location;
 829         *reg = data->route_offset;
 830         *value = data->route_val;
 831
 832         return true;
 833 }
 834
 835 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 836 {
 837         struct rockchip_pinctrl *info = bank->drvdata;
 838         int iomux_num = (pin / 8);
 839         struct regmap *regmap;
 840         unsigned int val;
 841         int reg, ret, mask, mux_type;
 842         u8 bit;
 843
 844         if (iomux_num > 3)
 845                 return -EINVAL;
 846
 847         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 848                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 849                 return -EINVAL;
 850         }
 851
 852         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 853                 return RK_FUNC_GPIO;
 854
 855         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 856                                 ? info->regmap_pmu : info->regmap_base;
 857
 858         /* get basic quadrupel of mux registers and the correct reg inside */
 859         mux_type = bank->iomux[iomux_num].type;
 860         reg = bank->iomux[iomux_num].offset;
 861         if (mux_type & IOMUX_WIDTH_4BIT) {
 862                 if ((pin % 8) >= 4)
 863                         reg += 0x4;
 864                 bit = (pin % 4) * 4;
 865                 mask = 0xf;
 866         } else if (mux_type & IOMUX_WIDTH_3BIT) {
 867                 if ((pin % 8) >= 5)
 868                         reg += 0x4;
 869                 bit = (pin % 8 % 5) * 3;
 870                 mask = 0x7;
 871         } else {
 872                 bit = (pin % 8) * 2;
 873                 mask = 0x3;
 874         }
 875
 876         if (bank->recalced_mask & BIT(pin))
 877                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
 878
 879         ret = regmap_read(regmap, reg, &val);
 880         if (ret)
 881                 return ret;
 882
 883         return ((val >> bit) & mask);
 884 }
 885
 886 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
 887                                int pin, int mux)
 888 {
 889         struct rockchip_pinctrl *info = bank->drvdata;
 890         int iomux_num = (pin / 8);
 891
 892         if (iomux_num > 3)
 893                 return -EINVAL;
 894
 895         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 896                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 897                 return -EINVAL;
 898         }
 899
 900         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 901                 if (mux != RK_FUNC_GPIO) {
 902                         dev_err(info->dev,
 903                                 "pin %d only supports a gpio mux\n", pin);
 904                         return -ENOTSUPP;
 905                 }
 906         }
 907
 908         return 0;
 909 }
 910
 911 /*
 912  * Set a new mux function for a pin.
 913  *
 914  * The register is divided into the upper and lower 16 bit. When changing
 915  * a value, the previous register value is not read and changed. Instead
 916  * it seems the changed bits are marked in the upper 16 bit, while the
 917  * changed value gets set in the same offset in the lower 16 bit.
 918  * All pin settings seem to be 2 bit wide in both the upper and lower
 919  * parts.
 920  * @bank: pin bank to change
 921  * @pin: pin to change
 922  * @mux: new mux function to set
 923  */
 924 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 925 {
 926         struct rockchip_pinctrl *info = bank->drvdata;
 927         int iomux_num = (pin / 8);
 928         struct regmap *regmap;
 929         int reg, ret, mask, mux_type;
 930         u8 bit;
 931         u32 data, rmask, route_location, route_reg, route_val;
 932
 933         ret = rockchip_verify_mux(bank, pin, mux);
 934         if (ret < 0)
 935                 return ret;
 936
 937         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 938                 return 0;
 939
 940         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 941                                                 bank->bank_num, pin, mux);
 942
 943         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 944                                 ? info->regmap_pmu : info->regmap_base;
 945
 946         /* get basic quadrupel of mux registers and the correct reg inside */
 947         mux_type = bank->iomux[iomux_num].type;
 948         reg = bank->iomux[iomux_num].offset;
 949         if (mux_type & IOMUX_WIDTH_4BIT) {
 950                 if ((pin % 8) >= 4)
 951                         reg += 0x4;
 952                 bit = (pin % 4) * 4;
 953                 mask = 0xf;
 954         } else if (mux_type & IOMUX_WIDTH_3BIT) {
 955                 if ((pin % 8) >= 5)
 956                         reg += 0x4;
 957                 bit = (pin % 8 % 5) * 3;
 958                 mask = 0x7;
 959         } else {
 960                 bit = (pin % 8) * 2;
 961                 mask = 0x3;
 962         }
 963
 964         if (bank->recalced_mask & BIT(pin))
 965                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
 966
 967         if (bank->route_mask & BIT(pin)) {
 968                 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
 969                                            &route_reg, &route_val)) {
 970                         struct regmap *route_regmap = regmap;
 971
 972                         /* handle special locations */
 973                         switch (route_location) {
 974                         case ROCKCHIP_ROUTE_PMU:
 975                                 route_regmap = info->regmap_pmu;
 976                                 break;
 977                         case ROCKCHIP_ROUTE_GRF:
 978                                 route_regmap = info->regmap_base;
 979                                 break;
 980                         }
 981
 982                         ret = regmap_write(route_regmap, route_reg, route_val);
 983                         if (ret)
 984                                 return ret;
 985                 }
 986         }
 987
 988         data = (mask << (bit + 16));
 989         rmask = data | (data >> 16);
 990         data |= (mux & mask) << bit;
 991         ret = regmap_update_bits(regmap, reg, rmask, data);
 992
 993         return ret;
 994 }
 995
 996 #define PX30_PULL_PMU_OFFSET            0x10
 997 #define PX30_PULL_GRF_OFFSET            0x60
 998 #define PX30_PULL_BITS_PER_PIN          2
 999 #define PX30_PULL_PINS_PER_REG          8
1000 #define PX30_PULL_BANK_STRIDE           16
1001
1002 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1003                                        int pin_num, struct regmap **regmap,
1004                                        int *reg, u8 *bit)
1005 {
1006         struct rockchip_pinctrl *info = bank->drvdata;
1007
1008         /* The first 32 pins of the first bank are located in PMU */
1009         if (bank->bank_num == 0) {
1010                 *regmap = info->regmap_pmu;
1011                 *reg = PX30_PULL_PMU_OFFSET;
1012         } else {
1013                 *regmap = info->regmap_base;
1014                 *reg = PX30_PULL_GRF_OFFSET;
1015
1016                 /* correct the offset, as we're starting with the 2nd bank */
1017                 *reg -= 0x10;
1018                 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1019         }
1020
1021         *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1022         *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1023         *bit *= PX30_PULL_BITS_PER_PIN;
1024 }
1025
1026 #define PX30_DRV_PMU_OFFSET             0x20
1027 #define PX30_DRV_GRF_OFFSET             0xf0
1028 #define PX30_DRV_BITS_PER_PIN           2
1029 #define PX30_DRV_PINS_PER_REG           8
1030 #define PX30_DRV_BANK_STRIDE            16
1031
1032 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1033                                       int pin_num, struct regmap **regmap,
1034                                       int *reg, u8 *bit)
1035 {
1036         struct rockchip_pinctrl *info = bank->drvdata;
1037
1038         /* The first 32 pins of the first bank are located in PMU */
1039         if (bank->bank_num == 0) {
1040                 *regmap = info->regmap_pmu;
1041                 *reg = PX30_DRV_PMU_OFFSET;
1042         } else {
1043                 *regmap = info->regmap_base;
1044                 *reg = PX30_DRV_GRF_OFFSET;
1045
1046                 /* correct the offset, as we're starting with the 2nd bank */
1047                 *reg -= 0x10;
1048                 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1049         }
1050
1051         *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1052         *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1053         *bit *= PX30_DRV_BITS_PER_PIN;
1054 }
1055
1056 #define PX30_SCHMITT_PMU_OFFSET                 0x38
1057 #define PX30_SCHMITT_GRF_OFFSET                 0xc0
1058 #define PX30_SCHMITT_PINS_PER_PMU_REG           16
1059 #define PX30_SCHMITT_BANK_STRIDE                16
1060 #define PX30_SCHMITT_PINS_PER_GRF_REG           8
1061
1062 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1063                                          int pin_num,
1064                                          struct regmap **regmap,
1065                                          int *reg, u8 *bit)
1066 {
1067         struct rockchip_pinctrl *info = bank->drvdata;
1068         int pins_per_reg;
1069
1070         if (bank->bank_num == 0) {
1071                 *regmap = info->regmap_pmu;
1072                 *reg = PX30_SCHMITT_PMU_OFFSET;
1073                 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1074         } else {
1075                 *regmap = info->regmap_base;
1076                 *reg = PX30_SCHMITT_GRF_OFFSET;
1077                 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1078                 *reg += (bank->bank_num  - 1) * PX30_SCHMITT_BANK_STRIDE;
1079         }
1080
1081         *reg += ((pin_num / pins_per_reg) * 4);
1082         *bit = pin_num % pins_per_reg;
1083
1084         return 0;
1085 }
1086
1087 #define RV1108_PULL_PMU_OFFSET          0x10
1088 #define RV1108_PULL_OFFSET              0x110
1089 #define RV1108_PULL_PINS_PER_REG        8
1090 #define RV1108_PULL_BITS_PER_PIN        2
1091 #define RV1108_PULL_BANK_STRIDE         16
1092
1093 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1094                                          int pin_num, struct regmap **regmap,
1095                                          int *reg, u8 *bit)
1096 {
1097         struct rockchip_pinctrl *info = bank->drvdata;
1098
1099         /* The first 24 pins of the first bank are located in PMU */
1100         if (bank->bank_num == 0) {
1101                 *regmap = info->regmap_pmu;
1102                 *reg = RV1108_PULL_PMU_OFFSET;
1103         } else {
1104                 *reg = RV1108_PULL_OFFSET;
1105                 *regmap = info->regmap_base;
1106                 /* correct the offset, as we're starting with the 2nd bank */
1107                 *reg -= 0x10;
1108                 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1109         }
1110
1111         *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1112         *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1113         *bit *= RV1108_PULL_BITS_PER_PIN;
1114 }
1115
1116 #define RV1108_DRV_PMU_OFFSET           0x20
1117 #define RV1108_DRV_GRF_OFFSET           0x210
1118 #define RV1108_DRV_BITS_PER_PIN         2
1119 #define RV1108_DRV_PINS_PER_REG         8
1120 #define RV1108_DRV_BANK_STRIDE          16
1121
1122 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1123                                         int pin_num, struct regmap **regmap,
1124                                         int *reg, u8 *bit)
1125 {
1126         struct rockchip_pinctrl *info = bank->drvdata;
1127
1128         /* The first 24 pins of the first bank are located in PMU */
1129         if (bank->bank_num == 0) {
1130                 *regmap = info->regmap_pmu;
1131                 *reg = RV1108_DRV_PMU_OFFSET;
1132         } else {
1133                 *regmap = info->regmap_base;
1134                 *reg = RV1108_DRV_GRF_OFFSET;
1135
1136                 /* correct the offset, as we're starting with the 2nd bank */
1137                 *reg -= 0x10;
1138                 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1139         }
1140
1141         *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1142         *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1143         *bit *= RV1108_DRV_BITS_PER_PIN;
1144 }
1145
1146 #define RV1108_SCHMITT_PMU_OFFSET               0x30
1147 #define RV1108_SCHMITT_GRF_OFFSET               0x388
1148 #define RV1108_SCHMITT_BANK_STRIDE              8
1149 #define RV1108_SCHMITT_PINS_PER_GRF_REG         16
1150 #define RV1108_SCHMITT_PINS_PER_PMU_REG         8
1151
1152 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1153                                            int pin_num,
1154                                            struct regmap **regmap,
1155                                            int *reg, u8 *bit)
1156 {
1157         struct rockchip_pinctrl *info = bank->drvdata;
1158         int pins_per_reg;
1159
1160         if (bank->bank_num == 0) {
1161                 *regmap = info->regmap_pmu;
1162                 *reg = RV1108_SCHMITT_PMU_OFFSET;
1163                 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1164         } else {
1165                 *regmap = info->regmap_base;
1166                 *reg = RV1108_SCHMITT_GRF_OFFSET;
1167                 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1168                 *reg += (bank->bank_num  - 1) * RV1108_SCHMITT_BANK_STRIDE;
1169         }
1170         *reg += ((pin_num / pins_per_reg) * 4);
1171         *bit = pin_num % pins_per_reg;
1172
1173         return 0;
1174 }
1175
1176 #define RK3308_SCHMITT_PINS_PER_REG             8
1177 #define RK3308_SCHMITT_BANK_STRIDE              16
1178 #define RK3308_SCHMITT_GRF_OFFSET               0x1a0
1179
1180 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1181                                     int pin_num, struct regmap **regmap,
1182                                     int *reg, u8 *bit)
1183 {
1184         struct rockchip_pinctrl *info = bank->drvdata;
1185
1186         *regmap = info->regmap_base;
1187         *reg = RK3308_SCHMITT_GRF_OFFSET;
1188
1189         *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1190         *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1191         *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1192
1193         return 0;
1194 }
1195
1196 #define RK2928_PULL_OFFSET              0x118
1197 #define RK2928_PULL_PINS_PER_REG        16
1198 #define RK2928_PULL_BANK_STRIDE         8
1199
1200 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1201                                     int pin_num, struct regmap **regmap,
1202                                     int *reg, u8 *bit)
1203 {
1204         struct rockchip_pinctrl *info = bank->drvdata;
1205
1206         *regmap = info->regmap_base;
1207         *reg = RK2928_PULL_OFFSET;
1208         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1209         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1210
1211         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1212 };
1213
1214 #define RK3128_PULL_OFFSET      0x118
1215
1216 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1217                                          int pin_num, struct regmap **regmap,
1218                                          int *reg, u8 *bit)
1219 {
1220         struct rockchip_pinctrl *info = bank->drvdata;
1221
1222         *regmap = info->regmap_base;
1223         *reg = RK3128_PULL_OFFSET;
1224         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1225         *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1226
1227         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1228 }
1229
1230 #define RK3188_PULL_OFFSET              0x164
1231 #define RK3188_PULL_BITS_PER_PIN        2
1232 #define RK3188_PULL_PINS_PER_REG        8
1233 #define RK3188_PULL_BANK_STRIDE         16
1234 #define RK3188_PULL_PMU_OFFSET          0x64
1235
1236 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1237                                     int pin_num, struct regmap **regmap,
1238                                     int *reg, u8 *bit)
1239 {
1240         struct rockchip_pinctrl *info = bank->drvdata;
1241
1242         /* The first 12 pins of the first bank are located elsewhere */
1243         if (bank->bank_num == 0 && pin_num < 12) {
1244                 *regmap = info->regmap_pmu ? info->regmap_pmu
1245                                            : bank->regmap_pull;
1246                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1247                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1248                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1249                 *bit *= RK3188_PULL_BITS_PER_PIN;
1250         } else {
1251                 *regmap = info->regmap_pull ? info->regmap_pull
1252                                             : info->regmap_base;
1253                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1254
1255                 /* correct the offset, as it is the 2nd pull register */
1256                 *reg -= 4;
1257                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1258                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1259
1260                 /*
1261                  * The bits in these registers have an inverse ordering
1262                  * with the lowest pin being in bits 15:14 and the highest
1263                  * pin in bits 1:0
1264                  */
1265                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1266                 *bit *= RK3188_PULL_BITS_PER_PIN;
1267         }
1268 }
1269
1270 #define RK3288_PULL_OFFSET              0x140
1271 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1272                                     int pin_num, struct regmap **regmap,
1273                                     int *reg, u8 *bit)
1274 {
1275         struct rockchip_pinctrl *info = bank->drvdata;
1276
1277         /* The first 24 pins of the first bank are located in PMU */
1278         if (bank->bank_num == 0) {
1279                 *regmap = info->regmap_pmu;
1280                 *reg = RK3188_PULL_PMU_OFFSET;
1281
1282                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1283                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1284                 *bit *= RK3188_PULL_BITS_PER_PIN;
1285         } else {
1286                 *regmap = info->regmap_base;
1287                 *reg = RK3288_PULL_OFFSET;
1288
1289                 /* correct the offset, as we're starting with the 2nd bank */
1290                 *reg -= 0x10;
1291                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1292                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1293
1294                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1295                 *bit *= RK3188_PULL_BITS_PER_PIN;
1296         }
1297 }
1298
1299 #define RK3288_DRV_PMU_OFFSET           0x70
1300 #define RK3288_DRV_GRF_OFFSET           0x1c0
1301 #define RK3288_DRV_BITS_PER_PIN         2
1302 #define RK3288_DRV_PINS_PER_REG         8
1303 #define RK3288_DRV_BANK_STRIDE          16
1304
1305 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1306                                     int pin_num, struct regmap **regmap,
1307                                     int *reg, u8 *bit)
1308 {
1309         struct rockchip_pinctrl *info = bank->drvdata;
1310
1311         /* The first 24 pins of the first bank are located in PMU */
1312         if (bank->bank_num == 0) {
1313                 *regmap = info->regmap_pmu;
1314                 *reg = RK3288_DRV_PMU_OFFSET;
1315
1316                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1317                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1318                 *bit *= RK3288_DRV_BITS_PER_PIN;
1319         } else {
1320                 *regmap = info->regmap_base;
1321                 *reg = RK3288_DRV_GRF_OFFSET;
1322
1323                 /* correct the offset, as we're starting with the 2nd bank */
1324                 *reg -= 0x10;
1325                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1326                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1327
1328                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1329                 *bit *= RK3288_DRV_BITS_PER_PIN;
1330         }
1331 }
1332
1333 #define RK3228_PULL_OFFSET              0x100
1334
1335 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1336                                     int pin_num, struct regmap **regmap,
1337                                     int *reg, u8 *bit)
1338 {
1339         struct rockchip_pinctrl *info = bank->drvdata;
1340
1341         *regmap = info->regmap_base;
1342         *reg = RK3228_PULL_OFFSET;
1343         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1344         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1345
1346         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1347         *bit *= RK3188_PULL_BITS_PER_PIN;
1348 }
1349
1350 #define RK3228_DRV_GRF_OFFSET           0x200
1351
1352 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1353                                     int pin_num, struct regmap **regmap,
1354                                     int *reg, u8 *bit)
1355 {
1356         struct rockchip_pinctrl *info = bank->drvdata;
1357
1358         *regmap = info->regmap_base;
1359         *reg = RK3228_DRV_GRF_OFFSET;
1360         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1361         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1362
1363         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1364         *bit *= RK3288_DRV_BITS_PER_PIN;
1365 }
1366
1367 #define RK3308_PULL_OFFSET              0xa0
1368
1369 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1370                                     int pin_num, struct regmap **regmap,
1371                                     int *reg, u8 *bit)
1372 {
1373         struct rockchip_pinctrl *info = bank->drvdata;
1374
1375         *regmap = info->regmap_base;
1376         *reg = RK3308_PULL_OFFSET;
1377         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1378         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1379
1380         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1381         *bit *= RK3188_PULL_BITS_PER_PIN;
1382 }
1383
1384 #define RK3308_DRV_GRF_OFFSET           0x100
1385
1386 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1387                                     int pin_num, struct regmap **regmap,
1388                                     int *reg, u8 *bit)
1389 {
1390         struct rockchip_pinctrl *info = bank->drvdata;
1391
1392         *regmap = info->regmap_base;
1393         *reg = RK3308_DRV_GRF_OFFSET;
1394         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1395         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1396
1397         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1398         *bit *= RK3288_DRV_BITS_PER_PIN;
1399 }
1400
1401 #define RK3368_PULL_GRF_OFFSET          0x100
1402 #define RK3368_PULL_PMU_OFFSET          0x10
1403
1404 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1405                                     int pin_num, struct regmap **regmap,
1406                                     int *reg, u8 *bit)
1407 {
1408         struct rockchip_pinctrl *info = bank->drvdata;
1409
1410         /* The first 32 pins of the first bank are located in PMU */
1411         if (bank->bank_num == 0) {
1412                 *regmap = info->regmap_pmu;
1413                 *reg = RK3368_PULL_PMU_OFFSET;
1414
1415                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1416                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1417                 *bit *= RK3188_PULL_BITS_PER_PIN;
1418         } else {
1419                 *regmap = info->regmap_base;
1420                 *reg = RK3368_PULL_GRF_OFFSET;
1421
1422                 /* correct the offset, as we're starting with the 2nd bank */
1423                 *reg -= 0x10;
1424                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1425                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1426
1427                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1428                 *bit *= RK3188_PULL_BITS_PER_PIN;
1429         }
1430 }
1431
1432 #define RK3368_DRV_PMU_OFFSET           0x20
1433 #define RK3368_DRV_GRF_OFFSET           0x200
1434
1435 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1436                                     int pin_num, struct regmap **regmap,
1437                                     int *reg, u8 *bit)
1438 {
1439         struct rockchip_pinctrl *info = bank->drvdata;
1440
1441         /* The first 32 pins of the first bank are located in PMU */
1442         if (bank->bank_num == 0) {
1443                 *regmap = info->regmap_pmu;
1444                 *reg = RK3368_DRV_PMU_OFFSET;
1445
1446                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1447                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1448                 *bit *= RK3288_DRV_BITS_PER_PIN;
1449         } else {
1450                 *regmap = info->regmap_base;
1451                 *reg = RK3368_DRV_GRF_OFFSET;
1452
1453                 /* correct the offset, as we're starting with the 2nd bank */
1454                 *reg -= 0x10;
1455                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1456                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1457
1458                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1459                 *bit *= RK3288_DRV_BITS_PER_PIN;
1460         }
1461 }
1462
1463 #define RK3399_PULL_GRF_OFFSET          0xe040
1464 #define RK3399_PULL_PMU_OFFSET          0x40
1465 #define RK3399_DRV_3BITS_PER_PIN        3
1466
1467 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1468                                          int pin_num, struct regmap **regmap,
1469                                          int *reg, u8 *bit)
1470 {
1471         struct rockchip_pinctrl *info = bank->drvdata;
1472
1473         /* The bank0:16 and bank1:32 pins are located in PMU */
1474         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1475                 *regmap = info->regmap_pmu;
1476                 *reg = RK3399_PULL_PMU_OFFSET;
1477
1478                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1479
1480                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1481                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1482                 *bit *= RK3188_PULL_BITS_PER_PIN;
1483         } else {
1484                 *regmap = info->regmap_base;
1485                 *reg = RK3399_PULL_GRF_OFFSET;
1486
1487                 /* correct the offset, as we're starting with the 3rd bank */
1488                 *reg -= 0x20;
1489                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1490                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1491
1492                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1493                 *bit *= RK3188_PULL_BITS_PER_PIN;
1494         }
1495 }
1496
1497 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1498                                         int pin_num, struct regmap **regmap,
1499                                         int *reg, u8 *bit)
1500 {
1501         struct rockchip_pinctrl *info = bank->drvdata;
1502         int drv_num = (pin_num / 8);
1503
1504         /*  The bank0:16 and bank1:32 pins are located in PMU */
1505         if ((bank->bank_num == 0) || (bank->bank_num == 1))
1506                 *regmap = info->regmap_pmu;
1507         else
1508                 *regmap = info->regmap_base;
1509
1510         *reg = bank->drv[drv_num].offset;
1511         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1512             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1513                 *bit = (pin_num % 8) * 3;
1514         else
1515                 *bit = (pin_num % 8) * 2;
1516 }
1517
1518 #define RK3568_PULL_PMU_OFFSET          0x20
1519 #define RK3568_PULL_GRF_OFFSET          0x80
1520 #define RK3568_PULL_BITS_PER_PIN        2
1521 #define RK3568_PULL_PINS_PER_REG        8
1522 #define RK3568_PULL_BANK_STRIDE         0x10
1523
1524 static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1525                                          int pin_num, struct regmap **regmap,
1526                                          int *reg, u8 *bit)
1527 {
1528         struct rockchip_pinctrl *info = bank->drvdata;
1529
1530         if (bank->bank_num == 0) {
1531                 *regmap = info->regmap_pmu;
1532                 *reg = RK3568_PULL_PMU_OFFSET;
1533                 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
1534                 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1535
1536                 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
1537                 *bit *= RK3568_PULL_BITS_PER_PIN;
1538         } else {
1539                 *regmap = info->regmap_base;
1540                 *reg = RK3568_PULL_GRF_OFFSET;
1541                 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
1542                 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1543
1544                 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
1545                 *bit *= RK3568_PULL_BITS_PER_PIN;
1546         }
1547 }
1548
1549 #define RK3568_DRV_PMU_OFFSET           0x70
1550 #define RK3568_DRV_GRF_OFFSET           0x200
1551 #define RK3568_DRV_BITS_PER_PIN         8
1552 #define RK3568_DRV_PINS_PER_REG         2
1553 #define RK3568_DRV_BANK_STRIDE          0x40
1554
1555 static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1556                                         int pin_num, struct regmap **regmap,
1557                                         int *reg, u8 *bit)
1558 {
1559         struct rockchip_pinctrl *info = bank->drvdata;
1560
1561         /* The first 32 pins of the first bank are located in PMU */
1562         if (bank->bank_num == 0) {
1563                 *regmap = info->regmap_pmu;
1564                 *reg = RK3568_DRV_PMU_OFFSET;
1565                 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1566
1567                 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
1568                 *bit *= RK3568_DRV_BITS_PER_PIN;
1569         } else {
1570                 *regmap = info->regmap_base;
1571                 *reg = RK3568_DRV_GRF_OFFSET;
1572                 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
1573                 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1574
1575                 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
1576                 *bit *= RK3568_DRV_BITS_PER_PIN;
1577         }
1578 }
1579
1580 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1581         { 2, 4, 8, 12, -1, -1, -1, -1 },
1582         { 3, 6, 9, 12, -1, -1, -1, -1 },
1583         { 5, 10, 15, 20, -1, -1, -1, -1 },
1584         { 4, 6, 8, 10, 12, 14, 16, 18 },
1585         { 4, 7, 10, 13, 16, 19, 22, 26 }
1586 };
1587
1588 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1589                                      int pin_num)
1590 {
1591         struct rockchip_pinctrl *info = bank->drvdata;
1592         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1593         struct regmap *regmap;
1594         int reg, ret;
1595         u32 data, temp, rmask_bits;
1596         u8 bit;
1597         int drv_type = bank->drv[pin_num / 8].drv_type;
1598
1599         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1600
1601         switch (drv_type) {
1602         case DRV_TYPE_IO_1V8_3V0_AUTO:
1603         case DRV_TYPE_IO_3V3_ONLY:
1604                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1605                 switch (bit) {
1606                 case 0 ... 12:
1607                         /* regular case, nothing to do */
1608                         break;
1609                 case 15:
1610                         /*
1611                          * drive-strength offset is special, as it is
1612                          * spread over 2 registers
1613                          */
1614                         ret = regmap_read(regmap, reg, &data);
1615                         if (ret)
1616                                 return ret;
1617
1618                         ret = regmap_read(regmap, reg + 0x4, &temp);
1619                         if (ret)
1620                                 return ret;
1621
1622                         /*
1623                          * the bit data[15] contains bit 0 of the value
1624                          * while temp[1:0] contains bits 2 and 1
1625                          */
1626                         data >>= 15;
1627                         temp &= 0x3;
1628                         temp <<= 1;
1629                         data |= temp;
1630
1631                         return rockchip_perpin_drv_list[drv_type][data];
1632                 case 18 ... 21:
1633                         /* setting fully enclosed in the second register */
1634                         reg += 4;
1635                         bit -= 16;
1636                         break;
1637                 default:
1638                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1639                                 bit, drv_type);
1640                         return -EINVAL;
1641                 }
1642
1643                 break;
1644         case DRV_TYPE_IO_DEFAULT:
1645         case DRV_TYPE_IO_1V8_OR_3V0:
1646         case DRV_TYPE_IO_1V8_ONLY:
1647                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1648                 break;
1649         default:
1650                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1651                         drv_type);
1652                 return -EINVAL;
1653         }
1654
1655         ret = regmap_read(regmap, reg, &data);
1656         if (ret)
1657                 return ret;
1658
1659         data >>= bit;
1660         data &= (1 << rmask_bits) - 1;
1661
1662         return rockchip_perpin_drv_list[drv_type][data];
1663 }
1664
1665 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1666                                      int pin_num, int strength)
1667 {
1668         struct rockchip_pinctrl *info = bank->drvdata;
1669         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1670         struct regmap *regmap;
1671         int reg, ret, i;
1672         u32 data, rmask, rmask_bits, temp;
1673         u8 bit;
1674         int drv_type = bank->drv[pin_num / 8].drv_type;
1675
1676         dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1677                 bank->bank_num, pin_num, strength);
1678
1679         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1680         if (ctrl->type == RK3568) {
1681                 rmask_bits = RK3568_DRV_BITS_PER_PIN;
1682                 ret = (1 << (strength + 1)) - 1;
1683                 goto config;
1684         }
1685
1686         ret = -EINVAL;
1687         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1688                 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1689                         ret = i;
1690                         break;
1691                 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1692                         ret = rockchip_perpin_drv_list[drv_type][i];
1693                         break;
1694                 }
1695         }
1696
1697         if (ret < 0) {
1698                 dev_err(info->dev, "unsupported driver strength %d\n",
1699                         strength);
1700                 return ret;
1701         }
1702
1703         switch (drv_type) {
1704         case DRV_TYPE_IO_1V8_3V0_AUTO:
1705         case DRV_TYPE_IO_3V3_ONLY:
1706                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1707                 switch (bit) {
1708                 case 0 ... 12:
1709                         /* regular case, nothing to do */
1710                         break;
1711                 case 15:
1712                         /*
1713                          * drive-strength offset is special, as it is spread
1714                          * over 2 registers, the bit data[15] contains bit 0
1715                          * of the value while temp[1:0] contains bits 2 and 1
1716                          */
1717                         data = (ret & 0x1) << 15;
1718                         temp = (ret >> 0x1) & 0x3;
1719
1720                         rmask = BIT(15) | BIT(31);
1721                         data |= BIT(31);
1722                         ret = regmap_update_bits(regmap, reg, rmask, data);
1723                         if (ret)
1724                                 return ret;
1725
1726                         rmask = 0x3 | (0x3 << 16);
1727                         temp |= (0x3 << 16);
1728                         reg += 0x4;
1729                         ret = regmap_update_bits(regmap, reg, rmask, temp);
1730
1731                         return ret;
1732                 case 18 ... 21:
1733                         /* setting fully enclosed in the second register */
1734                         reg += 4;
1735                         bit -= 16;
1736                         break;
1737                 default:
1738                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1739                                 bit, drv_type);
1740                         return -EINVAL;
1741                 }
1742                 break;
1743         case DRV_TYPE_IO_DEFAULT:
1744         case DRV_TYPE_IO_1V8_OR_3V0:
1745         case DRV_TYPE_IO_1V8_ONLY:
1746                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1747                 break;
1748         default:
1749                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1750                         drv_type);
1751                 return -EINVAL;
1752         }
1753
1754 config:
1755         /* enable the write to the equivalent lower bits */
1756         data = ((1 << rmask_bits) - 1) << (bit + 16);
1757         rmask = data | (data >> 16);
1758         data |= (ret << bit);
1759
1760         ret = regmap_update_bits(regmap, reg, rmask, data);
1761
1762         return ret;
1763 }
1764
1765 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1766         {
1767                 PIN_CONFIG_BIAS_DISABLE,
1768                 PIN_CONFIG_BIAS_PULL_UP,
1769                 PIN_CONFIG_BIAS_PULL_DOWN,
1770                 PIN_CONFIG_BIAS_BUS_HOLD
1771         },
1772         {
1773                 PIN_CONFIG_BIAS_DISABLE,
1774                 PIN_CONFIG_BIAS_PULL_DOWN,
1775                 PIN_CONFIG_BIAS_DISABLE,
1776                 PIN_CONFIG_BIAS_PULL_UP
1777         },
1778 };
1779
1780 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1781 {
1782         struct rockchip_pinctrl *info = bank->drvdata;
1783         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1784         struct regmap *regmap;
1785         int reg, ret, pull_type;
1786         u8 bit;
1787         u32 data;
1788
1789         /* rk3066b does support any pulls */
1790         if (ctrl->type == RK3066B)
1791                 return PIN_CONFIG_BIAS_DISABLE;
1792
1793         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1794
1795         ret = regmap_read(regmap, reg, &data);
1796         if (ret)
1797                 return ret;
1798
1799         switch (ctrl->type) {
1800         case RK2928:
1801         case RK3128:
1802                 return !(data & BIT(bit))
1803                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1804                                 : PIN_CONFIG_BIAS_DISABLE;
1805         case PX30:
1806         case RV1108:
1807         case RK3188:
1808         case RK3288:
1809         case RK3308:
1810         case RK3368:
1811         case RK3399:
1812                 pull_type = bank->pull_type[pin_num / 8];
1813                 data >>= bit;
1814                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1815
1816                 return rockchip_pull_list[pull_type][data];
1817         default:
1818                 dev_err(info->dev, "unsupported pinctrl type\n");
1819                 return -EINVAL;
1820         };
1821 }
1822
1823 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1824                                         int pin_num, int pull)
1825 {
1826         struct rockchip_pinctrl *info = bank->drvdata;
1827         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1828         struct regmap *regmap;
1829         int reg, ret, i, pull_type;
1830         u8 bit;
1831         u32 data, rmask;
1832
1833         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1834                  bank->bank_num, pin_num, pull);
1835
1836         /* rk3066b does support any pulls */
1837         if (ctrl->type == RK3066B)
1838                 return pull ? -EINVAL : 0;
1839
1840         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1841
1842         switch (ctrl->type) {
1843         case RK2928:
1844         case RK3128:
1845                 data = BIT(bit + 16);
1846                 if (pull == PIN_CONFIG_BIAS_DISABLE)
1847                         data |= BIT(bit);
1848                 ret = regmap_write(regmap, reg, data);
1849                 break;
1850         case PX30:
1851         case RV1108:
1852         case RK3188:
1853         case RK3288:
1854         case RK3308:
1855         case RK3368:
1856         case RK3399:
1857         case RK3568:
1858                 pull_type = bank->pull_type[pin_num / 8];
1859                 ret = -EINVAL;
1860                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1861                         i++) {
1862                         if (rockchip_pull_list[pull_type][i] == pull) {
1863                                 ret = i;
1864                                 break;
1865                         }
1866                 }
1867                 /*
1868                  * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6,
1869                  * where that pull up value becomes 3.
1870                  */
1871                 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
1872                         if (ret == 1)
1873                                 ret = 3;
1874                 }
1875
1876                 if (ret < 0) {
1877                         dev_err(info->dev, "unsupported pull setting %d\n",
1878                                 pull);
1879                         return ret;
1880                 }
1881
1882                 /* enable the write to the equivalent lower bits */
1883                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1884                 rmask = data | (data >> 16);
1885                 data |= (ret << bit);
1886
1887                 ret = regmap_update_bits(regmap, reg, rmask, data);
1888                 break;
1889         default:
1890                 dev_err(info->dev, "unsupported pinctrl type\n");
1891                 return -EINVAL;
1892         }
1893
1894         return ret;
1895 }
1896
1897 #define RK3328_SCHMITT_BITS_PER_PIN             1
1898 #define RK3328_SCHMITT_PINS_PER_REG             16
1899 #define RK3328_SCHMITT_BANK_STRIDE              8
1900 #define RK3328_SCHMITT_GRF_OFFSET               0x380
1901
1902 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1903                                            int pin_num,
1904                                            struct regmap **regmap,
1905                                            int *reg, u8 *bit)
1906 {
1907         struct rockchip_pinctrl *info = bank->drvdata;
1908
1909         *regmap = info->regmap_base;
1910         *reg = RK3328_SCHMITT_GRF_OFFSET;
1911
1912         *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
1913         *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
1914         *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
1915
1916         return 0;
1917 }
1918
1919 #define RK3568_SCHMITT_BITS_PER_PIN             2
1920 #define RK3568_SCHMITT_PINS_PER_REG             8
1921 #define RK3568_SCHMITT_BANK_STRIDE              0x10
1922 #define RK3568_SCHMITT_GRF_OFFSET               0xc0
1923 #define RK3568_SCHMITT_PMUGRF_OFFSET            0x30
1924
1925 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1926                                            int pin_num,
1927                                            struct regmap **regmap,
1928                                            int *reg, u8 *bit)
1929 {
1930         struct rockchip_pinctrl *info = bank->drvdata;
1931
1932         if (bank->bank_num == 0) {
1933                 *regmap = info->regmap_pmu;
1934                 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
1935         } else {
1936                 *regmap = info->regmap_base;
1937                 *reg = RK3568_SCHMITT_GRF_OFFSET;
1938                 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
1939         }
1940
1941         *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
1942         *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
1943         *bit *= RK3568_SCHMITT_BITS_PER_PIN;
1944
1945         return 0;
1946 }
1947
1948 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
1949 {
1950         struct rockchip_pinctrl *info = bank->drvdata;
1951         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1952         struct regmap *regmap;
1953         int reg, ret;
1954         u8 bit;
1955         u32 data;
1956
1957         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1958         if (ret)
1959                 return ret;
1960
1961         ret = regmap_read(regmap, reg, &data);
1962         if (ret)
1963                 return ret;
1964
1965         data >>= bit;
1966         switch (ctrl->type) {
1967         case RK3568:
1968                 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
1969         default:
1970                 break;
1971         }
1972
1973         return data & 0x1;
1974 }
1975
1976 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
1977                                 int pin_num, int enable)
1978 {
1979         struct rockchip_pinctrl *info = bank->drvdata;
1980         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1981         struct regmap *regmap;
1982         int reg, ret;
1983         u8 bit;
1984         u32 data, rmask;
1985
1986         dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
1987                 bank->bank_num, pin_num, enable);
1988
1989         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1990         if (ret)
1991                 return ret;
1992
1993         /* enable the write to the equivalent lower bits */
1994         switch (ctrl->type) {
1995         case RK3568:
1996                 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
1997                 rmask = data | (data >> 16);
1998                 data |= ((enable ? 0x2 : 0x1) << bit);
1999                 break;
2000         default:
2001                 data = BIT(bit + 16) | (enable << bit);
2002                 rmask = BIT(bit + 16) | BIT(bit);
2003                 break;
2004         }
2005
2006         return regmap_update_bits(regmap, reg, rmask, data);
2007 }
2008
2009 /*
2010  * Pinmux_ops handling
2011  */
2012
2013 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2014 {
2015         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2016
2017         return info->nfunctions;
2018 }
2019
2020 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2021                                           unsigned selector)
2022 {
2023         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2024
2025         return info->functions[selector].name;
2026 }
2027
2028 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2029                                 unsigned selector, const char * const **groups,
2030                                 unsigned * const num_groups)
2031 {
2032         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2033
2034         *groups = info->functions[selector].groups;
2035         *num_groups = info->functions[selector].ngroups;
2036
2037         return 0;
2038 }
2039
2040 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2041                             unsigned group)
2042 {
2043         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2044         const unsigned int *pins = info->groups[group].pins;
2045         const struct rockchip_pin_config *data = info->groups[group].data;
2046         struct rockchip_pin_bank *bank;
2047         int cnt, ret = 0;
2048
2049         dev_dbg(info->dev, "enable function %s group %s\n",
2050                 info->functions[selector].name, info->groups[group].name);
2051
2052         /*
2053          * for each pin in the pin group selected, program the corresponding
2054          * pin function number in the config register.
2055          */
2056         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2057                 bank = pin_to_bank(info, pins[cnt]);
2058                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2059                                        data[cnt].func);
2060                 if (ret)
2061                         break;
2062         }
2063
2064         if (ret) {
2065                 /* revert the already done pin settings */
2066                 for (cnt--; cnt >= 0; cnt--)
2067                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2068
2069                 return ret;
2070         }
2071
2072         return 0;
2073 }
2074
2075 static const struct pinmux_ops rockchip_pmx_ops = {
2076         .get_functions_count    = rockchip_pmx_get_funcs_count,
2077         .get_function_name      = rockchip_pmx_get_func_name,
2078         .get_function_groups    = rockchip_pmx_get_groups,
2079         .set_mux                = rockchip_pmx_set,
2080 };
2081
2082 /*
2083  * Pinconf_ops handling
2084  */
2085
2086 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2087                                         enum pin_config_param pull)
2088 {
2089         switch (ctrl->type) {
2090         case RK2928:
2091         case RK3128:
2092                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2093                                         pull == PIN_CONFIG_BIAS_DISABLE);
2094         case RK3066B:
2095                 return pull ? false : true;
2096         case PX30:
2097         case RV1108:
2098         case RK3188:
2099         case RK3288:
2100         case RK3308:
2101         case RK3368:
2102         case RK3399:
2103         case RK3568:
2104                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2105         }
2106
2107         return false;
2108 }
2109
2110 static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
2111                                          unsigned int pin, u32 param, u32 arg)
2112 {
2113         struct rockchip_pin_deferred *cfg;
2114
2115         cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
2116         if (!cfg)
2117                 return -ENOMEM;
2118
2119         cfg->pin = pin;
2120         cfg->param = param;
2121         cfg->arg = arg;
2122
2123         list_add_tail(&cfg->head, &bank->deferred_pins);
2124
2125         return 0;
2126 }
2127
2128 /* set the pin config settings for a specified pin */
2129 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2130                                 unsigned long *configs, unsigned num_configs)
2131 {
2132         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2133         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2134         struct gpio_chip *gpio = &bank->gpio_chip;
2135         enum pin_config_param param;
2136         u32 arg;
2137         int i;
2138         int rc;
2139
2140         for (i = 0; i < num_configs; i++) {
2141                 param = pinconf_to_config_param(configs[i]);
2142                 arg = pinconf_to_config_argument(configs[i]);
2143
2144                 if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) {
2145                         /*
2146                          * Check for gpio driver not being probed yet.
2147                          * The lock makes sure that either gpio-probe has completed
2148                          * or the gpio driver hasn't probed yet.
2149                          */
2150                         mutex_lock(&bank->deferred_lock);
2151                         if (!gpio || !gpio->direction_output) {
2152                                 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param,
2153                                                                 arg);
2154                                 mutex_unlock(&bank->deferred_lock);
2155                                 if (rc)
2156                                         return rc;
2157
2158                                 break;
2159                         }
2160                         mutex_unlock(&bank->deferred_lock);
2161                 }
2162
2163                 switch (param) {
2164                 case PIN_CONFIG_BIAS_DISABLE:
2165                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
2166                                 param);
2167                         if (rc)
2168                                 return rc;
2169                         break;
2170                 case PIN_CONFIG_BIAS_PULL_UP:
2171                 case PIN_CONFIG_BIAS_PULL_DOWN:
2172                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2173                 case PIN_CONFIG_BIAS_BUS_HOLD:
2174                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2175                                 return -ENOTSUPP;
2176
2177                         if (!arg)
2178                                 return -EINVAL;
2179
2180                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
2181                                 param);
2182                         if (rc)
2183                                 return rc;
2184                         break;
2185                 case PIN_CONFIG_OUTPUT:
2186                         rc = rockchip_set_mux(bank, pin - bank->pin_base,
2187                                               RK_FUNC_GPIO);
2188                         if (rc != RK_FUNC_GPIO)
2189                                 return -EINVAL;
2190
2191                         rc = gpio->direction_output(gpio, pin - bank->pin_base,
2192                                                     arg);
2193                         if (rc)
2194                                 return rc;
2195                         break;
2196                 case PIN_CONFIG_INPUT_ENABLE:
2197                         rc = rockchip_set_mux(bank, pin - bank->pin_base,
2198                                               RK_FUNC_GPIO);
2199                         if (rc != RK_FUNC_GPIO)
2200                                 return -EINVAL;
2201
2202                         rc = gpio->direction_input(gpio, pin - bank->pin_base);
2203                         if (rc)
2204                                 return rc;
2205                         break;
2206                 case PIN_CONFIG_DRIVE_STRENGTH:
2207                         /* rk3288 is the first with per-pin drive-strength */
2208                         if (!info->ctrl->drv_calc_reg)
2209                                 return -ENOTSUPP;
2210
2211                         rc = rockchip_set_drive_perpin(bank,
2212                                                 pin - bank->pin_base, arg);
2213                         if (rc < 0)
2214                                 return rc;
2215                         break;
2216                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2217                         if (!info->ctrl->schmitt_calc_reg)
2218                                 return -ENOTSUPP;
2219
2220                         rc = rockchip_set_schmitt(bank,
2221                                                   pin - bank->pin_base, arg);
2222                         if (rc < 0)
2223                                 return rc;
2224                         break;
2225                 default:
2226                         return -ENOTSUPP;
2227                         break;
2228                 }
2229         } /* for each config */
2230
2231         return 0;
2232 }
2233
2234 /* get the pin config settings for a specified pin */
2235 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2236                                                         unsigned long *config)
2237 {
2238         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2239         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2240         struct gpio_chip *gpio = &bank->gpio_chip;
2241         enum pin_config_param param = pinconf_to_config_param(*config);
2242         u16 arg;
2243         int rc;
2244
2245         switch (param) {
2246         case PIN_CONFIG_BIAS_DISABLE:
2247                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2248                         return -EINVAL;
2249
2250                 arg = 0;
2251                 break;
2252         case PIN_CONFIG_BIAS_PULL_UP:
2253         case PIN_CONFIG_BIAS_PULL_DOWN:
2254         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2255         case PIN_CONFIG_BIAS_BUS_HOLD:
2256                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2257                         return -ENOTSUPP;
2258
2259                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2260                         return -EINVAL;
2261
2262                 arg = 1;
2263                 break;
2264         case PIN_CONFIG_OUTPUT:
2265                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2266                 if (rc != RK_FUNC_GPIO)
2267                         return -EINVAL;
2268
2269                 if (!gpio || !gpio->get) {
2270                         arg = 0;
2271                         break;
2272                 }
2273
2274                 rc = gpio->get(gpio, pin - bank->pin_base);
2275                 if (rc < 0)
2276                         return rc;
2277
2278                 arg = rc ? 1 : 0;
2279                 break;
2280         case PIN_CONFIG_DRIVE_STRENGTH:
2281                 /* rk3288 is the first with per-pin drive-strength */
2282                 if (!info->ctrl->drv_calc_reg)
2283                         return -ENOTSUPP;
2284
2285                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2286                 if (rc < 0)
2287                         return rc;
2288
2289                 arg = rc;
2290                 break;
2291         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2292                 if (!info->ctrl->schmitt_calc_reg)
2293                         return -ENOTSUPP;
2294
2295                 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2296                 if (rc < 0)
2297                         return rc;
2298
2299                 arg = rc;
2300                 break;
2301         default:
2302                 return -ENOTSUPP;
2303                 break;
2304         }
2305
2306         *config = pinconf_to_config_packed(param, arg);
2307
2308         return 0;
2309 }
2310
2311 static const struct pinconf_ops rockchip_pinconf_ops = {
2312         .pin_config_get                 = rockchip_pinconf_get,
2313         .pin_config_set                 = rockchip_pinconf_set,
2314         .is_generic                     = true,
2315 };
2316
2317 static const struct of_device_id rockchip_bank_match[] = {
2318         { .compatible = "rockchip,gpio-bank" },
2319         { .compatible = "rockchip,rk3188-gpio-bank0" },
2320         {},
2321 };
2322
2323 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2324                                                 struct device_node *np)
2325 {
2326         struct device_node *child;
2327
2328         for_each_child_of_node(np, child) {
2329                 if (of_match_node(rockchip_bank_match, child))
2330                         continue;
2331
2332                 info->nfunctions++;
2333                 info->ngroups += of_get_child_count(child);
2334         }
2335 }
2336
2337 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2338                                               struct rockchip_pin_group *grp,
2339                                               struct rockchip_pinctrl *info,
2340                                               u32 index)
2341 {
2342         struct rockchip_pin_bank *bank;
2343         int size;
2344         const __be32 *list;
2345         int num;
2346         int i, j;
2347         int ret;
2348
2349         dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
2350
2351         /* Initialise group */
2352         grp->name = np->name;
2353
2354         /*
2355          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2356          * do sanity check and calculate pins number
2357          */
2358         list = of_get_property(np, "rockchip,pins", &size);
2359         /* we do not check return since it's safe node passed down */
2360         size /= sizeof(*list);
2361         if (!size || size % 4) {
2362                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2363                 return -EINVAL;
2364         }
2365
2366         grp->npins = size / 4;
2367
2368         grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2369                                                 GFP_KERNEL);
2370         grp->data = devm_kcalloc(info->dev,
2371                                         grp->npins,
2372                                         sizeof(struct rockchip_pin_config),
2373                                         GFP_KERNEL);
2374         if (!grp->pins || !grp->data)
2375                 return -ENOMEM;
2376
2377         for (i = 0, j = 0; i < size; i += 4, j++) {
2378                 const __be32 *phandle;
2379                 struct device_node *np_config;
2380
2381                 num = be32_to_cpu(*list++);
2382                 bank = bank_num_to_bank(info, num);
2383                 if (IS_ERR(bank))
2384                         return PTR_ERR(bank);
2385
2386                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2387                 grp->data[j].func = be32_to_cpu(*list++);
2388
2389                 phandle = list++;
2390                 if (!phandle)
2391                         return -EINVAL;
2392
2393                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2394                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2395                                 &grp->data[j].configs, &grp->data[j].nconfigs);
2396                 if (ret)
2397                         return ret;
2398         }
2399
2400         return 0;
2401 }
2402
2403 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2404                                                 struct rockchip_pinctrl *info,
2405                                                 u32 index)
2406 {
2407         struct device_node *child;
2408         struct rockchip_pmx_func *func;
2409         struct rockchip_pin_group *grp;
2410         int ret;
2411         static u32 grp_index;
2412         u32 i = 0;
2413
2414         dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
2415
2416         func = &info->functions[index];
2417
2418         /* Initialise function */
2419         func->name = np->name;
2420         func->ngroups = of_get_child_count(np);
2421         if (func->ngroups <= 0)
2422                 return 0;
2423
2424         func->groups = devm_kcalloc(info->dev,
2425                         func->ngroups, sizeof(char *), GFP_KERNEL);
2426         if (!func->groups)
2427                 return -ENOMEM;
2428
2429         for_each_child_of_node(np, child) {
2430                 func->groups[i] = child->name;
2431                 grp = &info->groups[grp_index++];
2432                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2433                 if (ret) {
2434                         of_node_put(child);
2435                         return ret;
2436                 }
2437         }
2438
2439         return 0;
2440 }
2441
2442 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2443                                               struct rockchip_pinctrl *info)
2444 {
2445         struct device *dev = &pdev->dev;
2446         struct device_node *np = dev->of_node;
2447         struct device_node *child;
2448         int ret;
2449         int i;
2450
2451         rockchip_pinctrl_child_count(info, np);
2452
2453         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2454         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2455
2456         info->functions = devm_kcalloc(dev,
2457                                               info->nfunctions,
2458                                               sizeof(struct rockchip_pmx_func),
2459                                               GFP_KERNEL);
2460         if (!info->functions)
2461                 return -ENOMEM;
2462
2463         info->groups = devm_kcalloc(dev,
2464                                             info->ngroups,
2465                                             sizeof(struct rockchip_pin_group),
2466                                             GFP_KERNEL);
2467         if (!info->groups)
2468                 return -ENOMEM;
2469
2470         i = 0;
2471
2472         for_each_child_of_node(np, child) {
2473                 if (of_match_node(rockchip_bank_match, child))
2474                         continue;
2475
2476                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2477                 if (ret) {
2478                         dev_err(&pdev->dev, "failed to parse function\n");
2479                         of_node_put(child);
2480                         return ret;
2481                 }
2482         }
2483
2484         return 0;
2485 }
2486
2487 static int rockchip_pinctrl_register(struct platform_device *pdev,
2488                                         struct rockchip_pinctrl *info)
2489 {
2490         struct pinctrl_desc *ctrldesc = &info->pctl;
2491         struct pinctrl_pin_desc *pindesc, *pdesc;
2492         struct rockchip_pin_bank *pin_bank;
2493         int pin, bank, ret;
2494         int k;
2495
2496         ctrldesc->name = "rockchip-pinctrl";
2497         ctrldesc->owner = THIS_MODULE;
2498         ctrldesc->pctlops = &rockchip_pctrl_ops;
2499         ctrldesc->pmxops = &rockchip_pmx_ops;
2500         ctrldesc->confops = &rockchip_pinconf_ops;
2501
2502         pindesc = devm_kcalloc(&pdev->dev,
2503                                info->ctrl->nr_pins, sizeof(*pindesc),
2504                                GFP_KERNEL);
2505         if (!pindesc)
2506                 return -ENOMEM;
2507
2508         ctrldesc->pins = pindesc;
2509         ctrldesc->npins = info->ctrl->nr_pins;
2510
2511         pdesc = pindesc;
2512         for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
2513                 pin_bank = &info->ctrl->pin_banks[bank];
2514                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2515                         pdesc->number = k;
2516                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2517                                                 pin_bank->name, pin);
2518                         pdesc++;
2519                 }
2520
2521                 INIT_LIST_HEAD(&pin_bank->deferred_pins);
2522                 mutex_init(&pin_bank->deferred_lock);
2523         }
2524
2525         ret = rockchip_pinctrl_parse_dt(pdev, info);
2526         if (ret)
2527                 return ret;
2528
2529         info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
2530         if (IS_ERR(info->pctl_dev)) {
2531                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2532                 return PTR_ERR(info->pctl_dev);
2533         }
2534
2535         return 0;
2536 }
2537
2538 static const struct of_device_id rockchip_pinctrl_dt_match[];
2539
2540 /* retrieve the soc specific data */
2541 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2542                                                 struct rockchip_pinctrl *d,
2543                                                 struct platform_device *pdev)
2544 {
2545         const struct of_device_id *match;
2546         struct device_node *node = pdev->dev.of_node;
2547         struct rockchip_pin_ctrl *ctrl;
2548         struct rockchip_pin_bank *bank;
2549         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2550
2551         match = of_match_node(rockchip_pinctrl_dt_match, node);
2552         ctrl = (struct rockchip_pin_ctrl *)match->data;
2553
2554         grf_offs = ctrl->grf_mux_offset;
2555         pmu_offs = ctrl->pmu_mux_offset;
2556         drv_pmu_offs = ctrl->pmu_drv_offset;
2557         drv_grf_offs = ctrl->grf_drv_offset;
2558         bank = ctrl->pin_banks;
2559         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2560                 int bank_pins = 0;
2561
2562                 raw_spin_lock_init(&bank->slock);
2563                 bank->drvdata = d;
2564                 bank->pin_base = ctrl->nr_pins;
2565                 ctrl->nr_pins += bank->nr_pins;
2566
2567                 /* calculate iomux and drv offsets */
2568                 for (j = 0; j < 4; j++) {
2569                         struct rockchip_iomux *iom = &bank->iomux[j];
2570                         struct rockchip_drv *drv = &bank->drv[j];
2571                         int inc;
2572
2573                         if (bank_pins >= bank->nr_pins)
2574                                 break;
2575
2576                         /* preset iomux offset value, set new start value */
2577                         if (iom->offset >= 0) {
2578                                 if (iom->type & IOMUX_SOURCE_PMU)
2579                                         pmu_offs = iom->offset;
2580                                 else
2581                                         grf_offs = iom->offset;
2582                         } else { /* set current iomux offset */
2583                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2584                                                         pmu_offs : grf_offs;
2585                         }
2586
2587                         /* preset drv offset value, set new start value */
2588                         if (drv->offset >= 0) {
2589                                 if (iom->type & IOMUX_SOURCE_PMU)
2590                                         drv_pmu_offs = drv->offset;
2591                                 else
2592                                         drv_grf_offs = drv->offset;
2593                         } else { /* set current drv offset */
2594                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2595                                                 drv_pmu_offs : drv_grf_offs;
2596                         }
2597
2598                         dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2599                                 i, j, iom->offset, drv->offset);
2600
2601                         /*
2602                          * Increase offset according to iomux width.
2603                          * 4bit iomux'es are spread over two registers.
2604                          */
2605                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
2606                                             IOMUX_WIDTH_3BIT |
2607                                             IOMUX_WIDTH_2BIT)) ? 8 : 4;
2608                         if (iom->type & IOMUX_SOURCE_PMU)
2609                                 pmu_offs += inc;
2610                         else
2611                                 grf_offs += inc;
2612
2613                         /*
2614                          * Increase offset according to drv width.
2615                          * 3bit drive-strenth'es are spread over two registers.
2616                          */
2617                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2618                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2619                                 inc = 8;
2620                         else
2621                                 inc = 4;
2622
2623                         if (iom->type & IOMUX_SOURCE_PMU)
2624                                 drv_pmu_offs += inc;
2625                         else
2626                                 drv_grf_offs += inc;
2627
2628                         bank_pins += 8;
2629                 }
2630
2631                 /* calculate the per-bank recalced_mask */
2632                 for (j = 0; j < ctrl->niomux_recalced; j++) {
2633                         int pin = 0;
2634
2635                         if (ctrl->iomux_recalced[j].num == bank->bank_num) {
2636                                 pin = ctrl->iomux_recalced[j].pin;
2637                                 bank->recalced_mask |= BIT(pin);
2638                         }
2639                 }
2640
2641                 /* calculate the per-bank route_mask */
2642                 for (j = 0; j < ctrl->niomux_routes; j++) {
2643                         int pin = 0;
2644
2645                         if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
2646                                 pin = ctrl->iomux_routes[j].pin;
2647                                 bank->route_mask |= BIT(pin);
2648                         }
2649                 }
2650         }
2651
2652         return ctrl;
2653 }
2654
2655 #define RK3288_GRF_GPIO6C_IOMUX         0x64
2656 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
2657
2658 static u32 rk3288_grf_gpio6c_iomux;
2659
2660 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2661 {
2662         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2663         int ret = pinctrl_force_sleep(info->pctl_dev);
2664
2665         if (ret)
2666                 return ret;
2667
2668         /*
2669          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2670          * the setting here, and restore it at resume.
2671          */
2672         if (info->ctrl->type == RK3288) {
2673                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2674                                   &rk3288_grf_gpio6c_iomux);
2675                 if (ret) {
2676                         pinctrl_force_default(info->pctl_dev);
2677                         return ret;
2678                 }
2679         }
2680
2681         return 0;
2682 }
2683
2684 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2685 {
2686         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2687         int ret;
2688
2689         if (info->ctrl->type == RK3288) {
2690                 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2691                                    rk3288_grf_gpio6c_iomux |
2692                                    GPIO6C6_SEL_WRITE_ENABLE);
2693                 if (ret)
2694                         return ret;
2695         }
2696
2697         return pinctrl_force_default(info->pctl_dev);
2698 }
2699
2700 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2701                          rockchip_pinctrl_resume);
2702
2703 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2704 {
2705         struct rockchip_pinctrl *info;
2706         struct device *dev = &pdev->dev;
2707         struct rockchip_pin_ctrl *ctrl;
2708         struct device_node *np = pdev->dev.of_node, *node;
2709         struct resource *res;
2710         void __iomem *base;
2711         int ret;
2712
2713         if (!dev->of_node) {
2714                 dev_err(dev, "device tree node not found\n");
2715                 return -ENODEV;
2716         }
2717
2718         info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
2719         if (!info)
2720                 return -ENOMEM;
2721
2722         info->dev = dev;
2723
2724         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2725         if (!ctrl) {
2726                 dev_err(dev, "driver data not available\n");
2727                 return -EINVAL;
2728         }
2729         info->ctrl = ctrl;
2730
2731         node = of_parse_phandle(np, "rockchip,grf", 0);
2732         if (node) {
2733                 info->regmap_base = syscon_node_to_regmap(node);
2734                 of_node_put(node);
2735                 if (IS_ERR(info->regmap_base))
2736                         return PTR_ERR(info->regmap_base);
2737         } else {
2738                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2739                 base = devm_ioremap_resource(&pdev->dev, res);
2740                 if (IS_ERR(base))
2741                         return PTR_ERR(base);
2742
2743                 rockchip_regmap_config.max_register = resource_size(res) - 4;
2744                 rockchip_regmap_config.name = "rockchip,pinctrl";
2745                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2746                                                     &rockchip_regmap_config);
2747
2748                 /* to check for the old dt-bindings */
2749                 info->reg_size = resource_size(res);
2750
2751                 /* Honor the old binding, with pull registers as 2nd resource */
2752                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2753                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2754                         base = devm_ioremap_resource(&pdev->dev, res);
2755                         if (IS_ERR(base))
2756                                 return PTR_ERR(base);
2757
2758                         rockchip_regmap_config.max_register =
2759                                                         resource_size(res) - 4;
2760                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2761                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2762                                                     base,
2763                                                     &rockchip_regmap_config);
2764                 }
2765         }
2766
2767         /* try to find the optional reference to the pmu syscon */
2768         node = of_parse_phandle(np, "rockchip,pmu", 0);
2769         if (node) {
2770                 info->regmap_pmu = syscon_node_to_regmap(node);
2771                 of_node_put(node);
2772                 if (IS_ERR(info->regmap_pmu))
2773                         return PTR_ERR(info->regmap_pmu);
2774         }
2775
2776         ret = rockchip_pinctrl_register(pdev, info);
2777         if (ret)
2778                 return ret;
2779
2780         platform_set_drvdata(pdev, info);
2781
2782         ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
2783         if (ret) {
2784                 dev_err(&pdev->dev, "failed to register gpio device\n");
2785                 return ret;
2786         }
2787
2788         return 0;
2789 }
2790
2791 static int rockchip_pinctrl_remove(struct platform_device *pdev)
2792 {
2793         struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
2794         struct rockchip_pin_bank *bank;
2795         struct rockchip_pin_deferred *cfg;
2796         int i;
2797
2798         of_platform_depopulate(&pdev->dev);
2799
2800         for (i = 0; i < info->ctrl->nr_banks; i++) {
2801                 bank = &info->ctrl->pin_banks[i];
2802
2803                 mutex_lock(&bank->deferred_lock);
2804                 while (!list_empty(&bank->deferred_pins)) {
2805                         cfg = list_first_entry(&bank->deferred_pins,
2806                                                struct rockchip_pin_deferred, head);
2807                         list_del(&cfg->head);
2808                         kfree(cfg);
2809                 }
2810                 mutex_unlock(&bank->deferred_lock);
2811         }
2812
2813         return 0;
2814 }
2815
2816 static struct rockchip_pin_bank px30_pin_banks[] = {
2817         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2818                                              IOMUX_SOURCE_PMU,
2819                                              IOMUX_SOURCE_PMU,
2820                                              IOMUX_SOURCE_PMU
2821                             ),
2822         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
2823                                              IOMUX_WIDTH_4BIT,
2824                                              IOMUX_WIDTH_4BIT,
2825                                              IOMUX_WIDTH_4BIT
2826                             ),
2827         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
2828                                              IOMUX_WIDTH_4BIT,
2829                                              IOMUX_WIDTH_4BIT,
2830                                              IOMUX_WIDTH_4BIT
2831                             ),
2832         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
2833                                              IOMUX_WIDTH_4BIT,
2834                                              IOMUX_WIDTH_4BIT,
2835                                              IOMUX_WIDTH_4BIT
2836                             ),
2837 };
2838
2839 static struct rockchip_pin_ctrl px30_pin_ctrl = {
2840                 .pin_banks              = px30_pin_banks,
2841                 .nr_banks               = ARRAY_SIZE(px30_pin_banks),
2842                 .label                  = "PX30-GPIO",
2843                 .type                   = PX30,
2844                 .grf_mux_offset         = 0x0,
2845                 .pmu_mux_offset         = 0x0,
2846                 .iomux_routes           = px30_mux_route_data,
2847                 .niomux_routes          = ARRAY_SIZE(px30_mux_route_data),
2848                 .pull_calc_reg          = px30_calc_pull_reg_and_bit,
2849                 .drv_calc_reg           = px30_calc_drv_reg_and_bit,
2850                 .schmitt_calc_reg       = px30_calc_schmitt_reg_and_bit,
2851 };
2852
2853 static struct rockchip_pin_bank rv1108_pin_banks[] = {
2854         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2855                                              IOMUX_SOURCE_PMU,
2856                                              IOMUX_SOURCE_PMU,
2857                                              IOMUX_SOURCE_PMU),
2858         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2859         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2860         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2861 };
2862
2863 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
2864         .pin_banks              = rv1108_pin_banks,
2865         .nr_banks               = ARRAY_SIZE(rv1108_pin_banks),
2866         .label                  = "RV1108-GPIO",
2867         .type                   = RV1108,
2868         .grf_mux_offset         = 0x10,
2869         .pmu_mux_offset         = 0x0,
2870         .iomux_recalced         = rv1108_mux_recalced_data,
2871         .niomux_recalced        = ARRAY_SIZE(rv1108_mux_recalced_data),
2872         .pull_calc_reg          = rv1108_calc_pull_reg_and_bit,
2873         .drv_calc_reg           = rv1108_calc_drv_reg_and_bit,
2874         .schmitt_calc_reg       = rv1108_calc_schmitt_reg_and_bit,
2875 };
2876
2877 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2878         PIN_BANK(0, 32, "gpio0"),
2879         PIN_BANK(1, 32, "gpio1"),
2880         PIN_BANK(2, 32, "gpio2"),
2881         PIN_BANK(3, 32, "gpio3"),
2882 };
2883
2884 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2885                 .pin_banks              = rk2928_pin_banks,
2886                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
2887                 .label                  = "RK2928-GPIO",
2888                 .type                   = RK2928,
2889                 .grf_mux_offset         = 0xa8,
2890                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2891 };
2892
2893 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2894         PIN_BANK(0, 32, "gpio0"),
2895         PIN_BANK(1, 32, "gpio1"),
2896         PIN_BANK(2, 32, "gpio2"),
2897 };
2898
2899 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2900                 .pin_banks              = rk3036_pin_banks,
2901                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
2902                 .label                  = "RK3036-GPIO",
2903                 .type                   = RK2928,
2904                 .grf_mux_offset         = 0xa8,
2905                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2906 };
2907
2908 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2909         PIN_BANK(0, 32, "gpio0"),
2910         PIN_BANK(1, 32, "gpio1"),
2911         PIN_BANK(2, 32, "gpio2"),
2912         PIN_BANK(3, 32, "gpio3"),
2913         PIN_BANK(4, 32, "gpio4"),
2914         PIN_BANK(6, 16, "gpio6"),
2915 };
2916
2917 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2918                 .pin_banks              = rk3066a_pin_banks,
2919                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
2920                 .label                  = "RK3066a-GPIO",
2921                 .type                   = RK2928,
2922                 .grf_mux_offset         = 0xa8,
2923                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2924 };
2925
2926 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2927         PIN_BANK(0, 32, "gpio0"),
2928         PIN_BANK(1, 32, "gpio1"),
2929         PIN_BANK(2, 32, "gpio2"),
2930         PIN_BANK(3, 32, "gpio3"),
2931 };
2932
2933 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2934                 .pin_banks      = rk3066b_pin_banks,
2935                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
2936                 .label          = "RK3066b-GPIO",
2937                 .type           = RK3066B,
2938                 .grf_mux_offset = 0x60,
2939 };
2940
2941 static struct rockchip_pin_bank rk3128_pin_banks[] = {
2942         PIN_BANK(0, 32, "gpio0"),
2943         PIN_BANK(1, 32, "gpio1"),
2944         PIN_BANK(2, 32, "gpio2"),
2945         PIN_BANK(3, 32, "gpio3"),
2946 };
2947
2948 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
2949                 .pin_banks              = rk3128_pin_banks,
2950                 .nr_banks               = ARRAY_SIZE(rk3128_pin_banks),
2951                 .label                  = "RK3128-GPIO",
2952                 .type                   = RK3128,
2953                 .grf_mux_offset         = 0xa8,
2954                 .iomux_recalced         = rk3128_mux_recalced_data,
2955                 .niomux_recalced        = ARRAY_SIZE(rk3128_mux_recalced_data),
2956                 .iomux_routes           = rk3128_mux_route_data,
2957                 .niomux_routes          = ARRAY_SIZE(rk3128_mux_route_data),
2958                 .pull_calc_reg          = rk3128_calc_pull_reg_and_bit,
2959 };
2960
2961 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2962         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2963         PIN_BANK(1, 32, "gpio1"),
2964         PIN_BANK(2, 32, "gpio2"),
2965         PIN_BANK(3, 32, "gpio3"),
2966 };
2967
2968 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2969                 .pin_banks              = rk3188_pin_banks,
2970                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
2971                 .label                  = "RK3188-GPIO",
2972                 .type                   = RK3188,
2973                 .grf_mux_offset         = 0x60,
2974                 .iomux_routes           = rk3188_mux_route_data,
2975                 .niomux_routes          = ARRAY_SIZE(rk3188_mux_route_data),
2976                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
2977 };
2978
2979 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2980         PIN_BANK(0, 32, "gpio0"),
2981         PIN_BANK(1, 32, "gpio1"),
2982         PIN_BANK(2, 32, "gpio2"),
2983         PIN_BANK(3, 32, "gpio3"),
2984 };
2985
2986 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2987                 .pin_banks              = rk3228_pin_banks,
2988                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
2989                 .label                  = "RK3228-GPIO",
2990                 .type                   = RK3288,
2991                 .grf_mux_offset         = 0x0,
2992                 .iomux_routes           = rk3228_mux_route_data,
2993                 .niomux_routes          = ARRAY_SIZE(rk3228_mux_route_data),
2994                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
2995                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
2996 };
2997
2998 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2999         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3000                                              IOMUX_SOURCE_PMU,
3001                                              IOMUX_SOURCE_PMU,
3002                                              IOMUX_UNROUTED
3003                             ),
3004         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3005                                              IOMUX_UNROUTED,
3006                                              IOMUX_UNROUTED,
3007                                              0
3008                             ),
3009         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3010         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3011         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3012                                              IOMUX_WIDTH_4BIT,
3013                                              0,
3014                                              0
3015                             ),
3016         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3017                                              0,
3018                                              0,
3019                                              IOMUX_UNROUTED
3020                             ),
3021         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3022         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3023                                              0,
3024                                              IOMUX_WIDTH_4BIT,
3025                                              IOMUX_UNROUTED
3026                             ),
3027         PIN_BANK(8, 16, "gpio8"),
3028 };
3029
3030 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3031                 .pin_banks              = rk3288_pin_banks,
3032                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
3033                 .label                  = "RK3288-GPIO",
3034                 .type                   = RK3288,
3035                 .grf_mux_offset         = 0x0,
3036                 .pmu_mux_offset         = 0x84,
3037                 .iomux_routes           = rk3288_mux_route_data,
3038                 .niomux_routes          = ARRAY_SIZE(rk3288_mux_route_data),
3039                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
3040                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
3041 };
3042
3043 static struct rockchip_pin_bank rk3308_pin_banks[] = {
3044         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
3045                                              IOMUX_WIDTH_2BIT,
3046                                              IOMUX_WIDTH_2BIT,
3047                                              IOMUX_WIDTH_2BIT),
3048         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
3049                                              IOMUX_WIDTH_2BIT,
3050                                              IOMUX_WIDTH_2BIT,
3051                                              IOMUX_WIDTH_2BIT),
3052         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
3053                                              IOMUX_WIDTH_2BIT,
3054                                              IOMUX_WIDTH_2BIT,
3055                                              IOMUX_WIDTH_2BIT),
3056         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
3057                                              IOMUX_WIDTH_2BIT,
3058                                              IOMUX_WIDTH_2BIT,
3059                                              IOMUX_WIDTH_2BIT),
3060         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
3061                                              IOMUX_WIDTH_2BIT,
3062                                              IOMUX_WIDTH_2BIT,
3063                                              IOMUX_WIDTH_2BIT),
3064 };
3065
3066 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
3067                 .pin_banks              = rk3308_pin_banks,
3068                 .nr_banks               = ARRAY_SIZE(rk3308_pin_banks),
3069                 .label                  = "RK3308-GPIO",
3070                 .type                   = RK3308,
3071                 .grf_mux_offset         = 0x0,
3072                 .iomux_recalced         = rk3308_mux_recalced_data,
3073                 .niomux_recalced        = ARRAY_SIZE(rk3308_mux_recalced_data),
3074                 .iomux_routes           = rk3308_mux_route_data,
3075                 .niomux_routes          = ARRAY_SIZE(rk3308_mux_route_data),
3076                 .pull_calc_reg          = rk3308_calc_pull_reg_and_bit,
3077                 .drv_calc_reg           = rk3308_calc_drv_reg_and_bit,
3078                 .schmitt_calc_reg       = rk3308_calc_schmitt_reg_and_bit,
3079 };
3080
3081 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3082         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3083         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3084         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3085                              IOMUX_WIDTH_3BIT,
3086                              IOMUX_WIDTH_3BIT,
3087                              0),
3088         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3089                              IOMUX_WIDTH_3BIT,
3090                              IOMUX_WIDTH_3BIT,
3091                              0,
3092                              0),
3093 };
3094
3095 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3096                 .pin_banks              = rk3328_pin_banks,
3097                 .nr_banks               = ARRAY_SIZE(rk3328_pin_banks),
3098                 .label                  = "RK3328-GPIO",
3099                 .type                   = RK3288,
3100                 .grf_mux_offset         = 0x0,
3101                 .iomux_recalced         = rk3328_mux_recalced_data,
3102                 .niomux_recalced        = ARRAY_SIZE(rk3328_mux_recalced_data),
3103                 .iomux_routes           = rk3328_mux_route_data,
3104                 .niomux_routes          = ARRAY_SIZE(rk3328_mux_route_data),
3105                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3106                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3107                 .schmitt_calc_reg       = rk3328_calc_schmitt_reg_and_bit,
3108 };
3109
3110 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3111         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3112                                              IOMUX_SOURCE_PMU,
3113                                              IOMUX_SOURCE_PMU,
3114                                              IOMUX_SOURCE_PMU
3115                             ),
3116         PIN_BANK(1, 32, "gpio1"),
3117         PIN_BANK(2, 32, "gpio2"),
3118         PIN_BANK(3, 32, "gpio3"),
3119 };
3120
3121 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3122                 .pin_banks              = rk3368_pin_banks,
3123                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
3124                 .label                  = "RK3368-GPIO",
3125                 .type                   = RK3368,
3126                 .grf_mux_offset         = 0x0,
3127                 .pmu_mux_offset         = 0x0,
3128                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
3129                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
3130 };
3131
3132 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3133         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3134                                                          IOMUX_SOURCE_PMU,
3135                                                          IOMUX_SOURCE_PMU,
3136                                                          IOMUX_SOURCE_PMU,
3137                                                          IOMUX_SOURCE_PMU,
3138                                                          DRV_TYPE_IO_1V8_ONLY,
3139                                                          DRV_TYPE_IO_1V8_ONLY,
3140                                                          DRV_TYPE_IO_DEFAULT,
3141                                                          DRV_TYPE_IO_DEFAULT,
3142                                                          0x80,
3143                                                          0x88,
3144                                                          -1,
3145                                                          -1,
3146                                                          PULL_TYPE_IO_1V8_ONLY,
3147                                                          PULL_TYPE_IO_1V8_ONLY,
3148                                                          PULL_TYPE_IO_DEFAULT,
3149                                                          PULL_TYPE_IO_DEFAULT
3150                                                         ),
3151         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3152                                         IOMUX_SOURCE_PMU,
3153                                         IOMUX_SOURCE_PMU,
3154                                         IOMUX_SOURCE_PMU,
3155                                         DRV_TYPE_IO_1V8_OR_3V0,
3156                                         DRV_TYPE_IO_1V8_OR_3V0,
3157                                         DRV_TYPE_IO_1V8_OR_3V0,
3158                                         DRV_TYPE_IO_1V8_OR_3V0,
3159                                         0xa0,
3160                                         0xa8,
3161                                         0xb0,
3162                                         0xb8
3163                                         ),
3164         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3165                                       DRV_TYPE_IO_1V8_OR_3V0,
3166                                       DRV_TYPE_IO_1V8_ONLY,
3167                                       DRV_TYPE_IO_1V8_ONLY,
3168                                       PULL_TYPE_IO_DEFAULT,
3169                                       PULL_TYPE_IO_DEFAULT,
3170                                       PULL_TYPE_IO_1V8_ONLY,
3171                                       PULL_TYPE_IO_1V8_ONLY
3172                                       ),
3173         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3174                            DRV_TYPE_IO_3V3_ONLY,
3175                            DRV_TYPE_IO_3V3_ONLY,
3176                            DRV_TYPE_IO_1V8_OR_3V0
3177                            ),
3178         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3179                            DRV_TYPE_IO_1V8_3V0_AUTO,
3180                            DRV_TYPE_IO_1V8_OR_3V0,
3181                            DRV_TYPE_IO_1V8_OR_3V0
3182                            ),
3183 };
3184
3185 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3186                 .pin_banks              = rk3399_pin_banks,
3187                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
3188                 .label                  = "RK3399-GPIO",
3189                 .type                   = RK3399,
3190                 .grf_mux_offset         = 0xe000,
3191                 .pmu_mux_offset         = 0x0,
3192                 .grf_drv_offset         = 0xe100,
3193                 .pmu_drv_offset         = 0x80,
3194                 .iomux_routes           = rk3399_mux_route_data,
3195                 .niomux_routes          = ARRAY_SIZE(rk3399_mux_route_data),
3196                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
3197                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
3198 };
3199
3200 static struct rockchip_pin_bank rk3568_pin_banks[] = {
3201         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3202                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3203                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3204                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
3205         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3206                                              IOMUX_WIDTH_4BIT,
3207                                              IOMUX_WIDTH_4BIT,
3208                                              IOMUX_WIDTH_4BIT),
3209         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3210                                              IOMUX_WIDTH_4BIT,
3211                                              IOMUX_WIDTH_4BIT,
3212                                              IOMUX_WIDTH_4BIT),
3213         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3214                                              IOMUX_WIDTH_4BIT,
3215                                              IOMUX_WIDTH_4BIT,
3216                                              IOMUX_WIDTH_4BIT),
3217         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3218                                              IOMUX_WIDTH_4BIT,
3219                                              IOMUX_WIDTH_4BIT,
3220                                              IOMUX_WIDTH_4BIT),
3221 };
3222
3223 static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
3224         .pin_banks              = rk3568_pin_banks,
3225         .nr_banks               = ARRAY_SIZE(rk3568_pin_banks),
3226         .label                  = "RK3568-GPIO",
3227         .type                   = RK3568,
3228         .grf_mux_offset         = 0x0,
3229         .pmu_mux_offset         = 0x0,
3230         .grf_drv_offset         = 0x0200,
3231         .pmu_drv_offset         = 0x0070,
3232         .iomux_routes           = rk3568_mux_route_data,
3233         .niomux_routes          = ARRAY_SIZE(rk3568_mux_route_data),
3234         .pull_calc_reg          = rk3568_calc_pull_reg_and_bit,
3235         .drv_calc_reg           = rk3568_calc_drv_reg_and_bit,
3236         .schmitt_calc_reg       = rk3568_calc_schmitt_reg_and_bit,
3237 };
3238
3239 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3240         { .compatible = "rockchip,px30-pinctrl",
3241                 .data = &px30_pin_ctrl },
3242         { .compatible = "rockchip,rv1108-pinctrl",
3243                 .data = &rv1108_pin_ctrl },
3244         { .compatible = "rockchip,rk2928-pinctrl",
3245                 .data = &rk2928_pin_ctrl },
3246         { .compatible = "rockchip,rk3036-pinctrl",
3247                 .data = &rk3036_pin_ctrl },
3248         { .compatible = "rockchip,rk3066a-pinctrl",
3249                 .data = &rk3066a_pin_ctrl },
3250         { .compatible = "rockchip,rk3066b-pinctrl",
3251                 .data = &rk3066b_pin_ctrl },
3252         { .compatible = "rockchip,rk3128-pinctrl",
3253                 .data = (void *)&rk3128_pin_ctrl },
3254         { .compatible = "rockchip,rk3188-pinctrl",
3255                 .data = &rk3188_pin_ctrl },
3256         { .compatible = "rockchip,rk3228-pinctrl",
3257                 .data = &rk3228_pin_ctrl },
3258         { .compatible = "rockchip,rk3288-pinctrl",
3259                 .data = &rk3288_pin_ctrl },
3260         { .compatible = "rockchip,rk3308-pinctrl",
3261                 .data = &rk3308_pin_ctrl },
3262         { .compatible = "rockchip,rk3328-pinctrl",
3263                 .data = &rk3328_pin_ctrl },
3264         { .compatible = "rockchip,rk3368-pinctrl",
3265                 .data = &rk3368_pin_ctrl },
3266         { .compatible = "rockchip,rk3399-pinctrl",
3267                 .data = &rk3399_pin_ctrl },
3268         { .compatible = "rockchip,rk3568-pinctrl",
3269                 .data = &rk3568_pin_ctrl },
3270         {},
3271 };
3272
3273 static struct platform_driver rockchip_pinctrl_driver = {
3274         .probe          = rockchip_pinctrl_probe,
3275         .remove         = rockchip_pinctrl_remove,
3276         .driver = {
3277                 .name   = "rockchip-pinctrl",
3278                 .pm = &rockchip_pinctrl_dev_pm_ops,
3279                 .of_match_table = rockchip_pinctrl_dt_match,
3280         },
3281 };
3282
3283 static int __init rockchip_pinctrl_drv_register(void)
3284 {
3285         return platform_driver_register(&rockchip_pinctrl_driver);
3286 }
3287 postcore_initcall(rockchip_pinctrl_drv_register);
3288
3289 static void __exit rockchip_pinctrl_drv_unregister(void)
3290 {
3291         platform_driver_unregister(&rockchip_pinctrl_driver);
3292 }
3293 module_exit(rockchip_pinctrl_drv_unregister);
3294
3295 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
3296 MODULE_LICENSE("GPL");
3297 MODULE_ALIAS("platform:pinctrl-rockchip");
3298 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);