drivers/pinctrl/pinctrl-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Pinctrl driver for Rockchip SoCs
   4  *
   5  * Copyright (c) 2013 MundoReader S.L.
   6  * Author: Heiko Stuebner <heiko@sntech.de>
   7  *
   8  * With some ideas taken from pinctrl-samsung:
   9  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  10  *              http://www.samsung.com
  11  * Copyright (c) 2012 Linaro Ltd
  12  *              https://www.linaro.org
  13  *
  14  * and pinctrl-at91:
  15  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/io.h>
  22 #include <linux/bitops.h>
  23 #include <linux/gpio/driver.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/pinctrl/machine.h>
  28 #include <linux/pinctrl/pinconf.h>
  29 #include <linux/pinctrl/pinctrl.h>
  30 #include <linux/pinctrl/pinmux.h>
  31 #include <linux/pinctrl/pinconf-generic.h>
  32 #include <linux/irqchip/chained_irq.h>
  33 #include <linux/clk.h>
  34 #include <linux/regmap.h>
  35 #include <linux/mfd/syscon.h>
  36 #include <dt-bindings/pinctrl/rockchip.h>
  37
  38 #include "core.h"
  39 #include "pinconf.h"
  40 #include "pinctrl-rockchip.h"
  41
  42 /**
  43  * Generate a bitmask for setting a value (v) with a write mask bit in hiword
  44  * register 31:16 area.
  45  */
  46 #define WRITE_MASK_VAL(h, l, v) \
  47         (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
  48
  49 /*
  50  * Encode variants of iomux registers into a type variable
  51  */
  52 #define IOMUX_GPIO_ONLY         BIT(0)
  53 #define IOMUX_WIDTH_4BIT        BIT(1)
  54 #define IOMUX_SOURCE_PMU        BIT(2)
  55 #define IOMUX_UNROUTED          BIT(3)
  56 #define IOMUX_WIDTH_3BIT        BIT(4)
  57 #define IOMUX_WIDTH_2BIT        BIT(5)
  58
  59 #define PIN_BANK(id, pins, label)                       \
  60         {                                               \
  61                 .bank_num       = id,                   \
  62                 .nr_pins        = pins,                 \
  63                 .name           = label,                \
  64                 .iomux          = {                     \
  65                         { .offset = -1 },               \
  66                         { .offset = -1 },               \
  67                         { .offset = -1 },               \
  68                         { .offset = -1 },               \
  69                 },                                      \
  70         }
  71
  72 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
  73         {                                                               \
  74                 .bank_num       = id,                                   \
  75                 .nr_pins        = pins,                                 \
  76                 .name           = label,                                \
  77                 .iomux          = {                                     \
  78                         { .type = iom0, .offset = -1 },                 \
  79                         { .type = iom1, .offset = -1 },                 \
  80                         { .type = iom2, .offset = -1 },                 \
  81                         { .type = iom3, .offset = -1 },                 \
  82                 },                                                      \
  83         }
  84
  85 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
  86         {                                                               \
  87                 .bank_num       = id,                                   \
  88                 .nr_pins        = pins,                                 \
  89                 .name           = label,                                \
  90                 .iomux          = {                                     \
  91                         { .offset = -1 },                               \
  92                         { .offset = -1 },                               \
  93                         { .offset = -1 },                               \
  94                         { .offset = -1 },                               \
  95                 },                                                      \
  96                 .drv            = {                                     \
  97                         { .drv_type = type0, .offset = -1 },            \
  98                         { .drv_type = type1, .offset = -1 },            \
  99                         { .drv_type = type2, .offset = -1 },            \
 100                         { .drv_type = type3, .offset = -1 },            \
 101                 },                                                      \
 102         }
 103
 104 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,      \
 105                                       drv2, drv3, pull0, pull1,         \
 106                                       pull2, pull3)                     \
 107         {                                                               \
 108                 .bank_num       = id,                                   \
 109                 .nr_pins        = pins,                                 \
 110                 .name           = label,                                \
 111                 .iomux          = {                                     \
 112                         { .offset = -1 },                               \
 113                         { .offset = -1 },                               \
 114                         { .offset = -1 },                               \
 115                         { .offset = -1 },                               \
 116                 },                                                      \
 117                 .drv            = {                                     \
 118                         { .drv_type = drv0, .offset = -1 },             \
 119                         { .drv_type = drv1, .offset = -1 },             \
 120                         { .drv_type = drv2, .offset = -1 },             \
 121                         { .drv_type = drv3, .offset = -1 },             \
 122                 },                                                      \
 123                 .pull_type[0] = pull0,                                  \
 124                 .pull_type[1] = pull1,                                  \
 125                 .pull_type[2] = pull2,                                  \
 126                 .pull_type[3] = pull3,                                  \
 127         }
 128
 129 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
 130                                         iom2, iom3, drv0, drv1, drv2,   \
 131                                         drv3, offset0, offset1,         \
 132                                         offset2, offset3)               \
 133         {                                                               \
 134                 .bank_num       = id,                                   \
 135                 .nr_pins        = pins,                                 \
 136                 .name           = label,                                \
 137                 .iomux          = {                                     \
 138                         { .type = iom0, .offset = -1 },                 \
 139                         { .type = iom1, .offset = -1 },                 \
 140                         { .type = iom2, .offset = -1 },                 \
 141                         { .type = iom3, .offset = -1 },                 \
 142                 },                                                      \
 143                 .drv            = {                                     \
 144                         { .drv_type = drv0, .offset = offset0 },        \
 145                         { .drv_type = drv1, .offset = offset1 },        \
 146                         { .drv_type = drv2, .offset = offset2 },        \
 147                         { .drv_type = drv3, .offset = offset3 },        \
 148                 },                                                      \
 149         }
 150
 151 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 152                                               label, iom0, iom1, iom2,  \
 153                                               iom3, drv0, drv1, drv2,   \
 154                                               drv3, offset0, offset1,   \
 155                                               offset2, offset3, pull0,  \
 156                                               pull1, pull2, pull3)      \
 157         {                                                               \
 158                 .bank_num       = id,                                   \
 159                 .nr_pins        = pins,                                 \
 160                 .name           = label,                                \
 161                 .iomux          = {                                     \
 162                         { .type = iom0, .offset = -1 },                 \
 163                         { .type = iom1, .offset = -1 },                 \
 164                         { .type = iom2, .offset = -1 },                 \
 165                         { .type = iom3, .offset = -1 },                 \
 166                 },                                                      \
 167                 .drv            = {                                     \
 168                         { .drv_type = drv0, .offset = offset0 },        \
 169                         { .drv_type = drv1, .offset = offset1 },        \
 170                         { .drv_type = drv2, .offset = offset2 },        \
 171                         { .drv_type = drv3, .offset = offset3 },        \
 172                 },                                                      \
 173                 .pull_type[0] = pull0,                                  \
 174                 .pull_type[1] = pull1,                                  \
 175                 .pull_type[2] = pull2,                                  \
 176                 .pull_type[3] = pull3,                                  \
 177         }
 178
 179 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG)         \
 180         {                                                               \
 181                 .bank_num       = ID,                                   \
 182                 .pin            = PIN,                                  \
 183                 .func           = FUNC,                                 \
 184                 .route_offset   = REG,                                  \
 185                 .route_val      = VAL,                                  \
 186                 .route_location = FLAG,                                 \
 187         }
 188
 189 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL)       \
 190         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
 191
 192 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL)        \
 193         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
 194
 195 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL)        \
 196         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
 197
 198 static struct regmap_config rockchip_regmap_config = {
 199         .reg_bits = 32,
 200         .val_bits = 32,
 201         .reg_stride = 4,
 202 };
 203
 204 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
 205                                         const struct rockchip_pinctrl *info,
 206                                         const char *name)
 207 {
 208         int i;
 209
 210         for (i = 0; i < info->ngroups; i++) {
 211                 if (!strcmp(info->groups[i].name, name))
 212                         return &info->groups[i];
 213         }
 214
 215         return NULL;
 216 }
 217
 218 /*
 219  * given a pin number that is local to a pin controller, find out the pin bank
 220  * and the register base of the pin bank.
 221  */
 222 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 223                                                                 unsigned pin)
 224 {
 225         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 226
 227         while (pin >= (b->pin_base + b->nr_pins))
 228                 b++;
 229
 230         return b;
 231 }
 232
 233 static struct rockchip_pin_bank *bank_num_to_bank(
 234                                         struct rockchip_pinctrl *info,
 235                                         unsigned num)
 236 {
 237         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 238         int i;
 239
 240         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 241                 if (b->bank_num == num)
 242                         return b;
 243         }
 244
 245         return ERR_PTR(-EINVAL);
 246 }
 247
 248 /*
 249  * Pinctrl_ops handling
 250  */
 251
 252 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 253 {
 254         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 255
 256         return info->ngroups;
 257 }
 258
 259 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 260                                                         unsigned selector)
 261 {
 262         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 263
 264         return info->groups[selector].name;
 265 }
 266
 267 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 268                                       unsigned selector, const unsigned **pins,
 269                                       unsigned *npins)
 270 {
 271         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 272
 273         if (selector >= info->ngroups)
 274                 return -EINVAL;
 275
 276         *pins = info->groups[selector].pins;
 277         *npins = info->groups[selector].npins;
 278
 279         return 0;
 280 }
 281
 282 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 283                                  struct device_node *np,
 284                                  struct pinctrl_map **map, unsigned *num_maps)
 285 {
 286         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 287         const struct rockchip_pin_group *grp;
 288         struct pinctrl_map *new_map;
 289         struct device_node *parent;
 290         int map_num = 1;
 291         int i;
 292
 293         /*
 294          * first find the group of this node and check if we need to create
 295          * config maps for pins
 296          */
 297         grp = pinctrl_name_to_group(info, np->name);
 298         if (!grp) {
 299                 dev_err(info->dev, "unable to find group for node %pOFn\n",
 300                         np);
 301                 return -EINVAL;
 302         }
 303
 304         map_num += grp->npins;
 305
 306         new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
 307         if (!new_map)
 308                 return -ENOMEM;
 309
 310         *map = new_map;
 311         *num_maps = map_num;
 312
 313         /* create mux map */
 314         parent = of_get_parent(np);
 315         if (!parent) {
 316                 kfree(new_map);
 317                 return -EINVAL;
 318         }
 319         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 320         new_map[0].data.mux.function = parent->name;
 321         new_map[0].data.mux.group = np->name;
 322         of_node_put(parent);
 323
 324         /* create config map */
 325         new_map++;
 326         for (i = 0; i < grp->npins; i++) {
 327                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 328                 new_map[i].data.configs.group_or_pin =
 329                                 pin_get_name(pctldev, grp->pins[i]);
 330                 new_map[i].data.configs.configs = grp->data[i].configs;
 331                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 332         }
 333
 334         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 335                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 336
 337         return 0;
 338 }
 339
 340 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 341                                     struct pinctrl_map *map, unsigned num_maps)
 342 {
 343         kfree(map);
 344 }
 345
 346 static const struct pinctrl_ops rockchip_pctrl_ops = {
 347         .get_groups_count       = rockchip_get_groups_count,
 348         .get_group_name         = rockchip_get_group_name,
 349         .get_group_pins         = rockchip_get_group_pins,
 350         .dt_node_to_map         = rockchip_dt_node_to_map,
 351         .dt_free_map            = rockchip_dt_free_map,
 352 };
 353
 354 /*
 355  * Hardware access
 356  */
 357
 358 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
 359         {
 360                 .num = 1,
 361                 .pin = 0,
 362                 .reg = 0x418,
 363                 .bit = 0,
 364                 .mask = 0x3
 365         }, {
 366                 .num = 1,
 367                 .pin = 1,
 368                 .reg = 0x418,
 369                 .bit = 2,
 370                 .mask = 0x3
 371         }, {
 372                 .num = 1,
 373                 .pin = 2,
 374                 .reg = 0x418,
 375                 .bit = 4,
 376                 .mask = 0x3
 377         }, {
 378                 .num = 1,
 379                 .pin = 3,
 380                 .reg = 0x418,
 381                 .bit = 6,
 382                 .mask = 0x3
 383         }, {
 384                 .num = 1,
 385                 .pin = 4,
 386                 .reg = 0x418,
 387                 .bit = 8,
 388                 .mask = 0x3
 389         }, {
 390                 .num = 1,
 391                 .pin = 5,
 392                 .reg = 0x418,
 393                 .bit = 10,
 394                 .mask = 0x3
 395         }, {
 396                 .num = 1,
 397                 .pin = 6,
 398                 .reg = 0x418,
 399                 .bit = 12,
 400                 .mask = 0x3
 401         }, {
 402                 .num = 1,
 403                 .pin = 7,
 404                 .reg = 0x418,
 405                 .bit = 14,
 406                 .mask = 0x3
 407         }, {
 408                 .num = 1,
 409                 .pin = 8,
 410                 .reg = 0x41c,
 411                 .bit = 0,
 412                 .mask = 0x3
 413         }, {
 414                 .num = 1,
 415                 .pin = 9,
 416                 .reg = 0x41c,
 417                 .bit = 2,
 418                 .mask = 0x3
 419         },
 420 };
 421
 422 static  struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
 423         {
 424                 .num = 2,
 425                 .pin = 20,
 426                 .reg = 0xe8,
 427                 .bit = 0,
 428                 .mask = 0x7
 429         }, {
 430                 .num = 2,
 431                 .pin = 21,
 432                 .reg = 0xe8,
 433                 .bit = 4,
 434                 .mask = 0x7
 435         }, {
 436                 .num = 2,
 437                 .pin = 22,
 438                 .reg = 0xe8,
 439                 .bit = 8,
 440                 .mask = 0x7
 441         }, {
 442                 .num = 2,
 443                 .pin = 23,
 444                 .reg = 0xe8,
 445                 .bit = 12,
 446                 .mask = 0x7
 447         }, {
 448                 .num = 2,
 449                 .pin = 24,
 450                 .reg = 0xd4,
 451                 .bit = 12,
 452                 .mask = 0x7
 453         },
 454 };
 455
 456 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
 457         {
 458                 /* gpio1b6_sel */
 459                 .num = 1,
 460                 .pin = 14,
 461                 .reg = 0x28,
 462                 .bit = 12,
 463                 .mask = 0xf
 464         }, {
 465                 /* gpio1b7_sel */
 466                 .num = 1,
 467                 .pin = 15,
 468                 .reg = 0x2c,
 469                 .bit = 0,
 470                 .mask = 0x3
 471         }, {
 472                 /* gpio1c2_sel */
 473                 .num = 1,
 474                 .pin = 18,
 475                 .reg = 0x30,
 476                 .bit = 4,
 477                 .mask = 0xf
 478         }, {
 479                 /* gpio1c3_sel */
 480                 .num = 1,
 481                 .pin = 19,
 482                 .reg = 0x30,
 483                 .bit = 8,
 484                 .mask = 0xf
 485         }, {
 486                 /* gpio1c4_sel */
 487                 .num = 1,
 488                 .pin = 20,
 489                 .reg = 0x30,
 490                 .bit = 12,
 491                 .mask = 0xf
 492         }, {
 493                 /* gpio1c5_sel */
 494                 .num = 1,
 495                 .pin = 21,
 496                 .reg = 0x34,
 497                 .bit = 0,
 498                 .mask = 0xf
 499         }, {
 500                 /* gpio1c6_sel */
 501                 .num = 1,
 502                 .pin = 22,
 503                 .reg = 0x34,
 504                 .bit = 4,
 505                 .mask = 0xf
 506         }, {
 507                 /* gpio1c7_sel */
 508                 .num = 1,
 509                 .pin = 23,
 510                 .reg = 0x34,
 511                 .bit = 8,
 512                 .mask = 0xf
 513         }, {
 514                 /* gpio3b4_sel */
 515                 .num = 3,
 516                 .pin = 12,
 517                 .reg = 0x68,
 518                 .bit = 8,
 519                 .mask = 0xf
 520         }, {
 521                 /* gpio3b5_sel */
 522                 .num = 3,
 523                 .pin = 13,
 524                 .reg = 0x68,
 525                 .bit = 12,
 526                 .mask = 0xf
 527         }, {
 528                 /* gpio2a2_sel */
 529                 .num = 2,
 530                 .pin = 2,
 531                 .reg = 0x40,
 532                 .bit = 4,
 533                 .mask = 0x3
 534         }, {
 535                 /* gpio2a3_sel */
 536                 .num = 2,
 537                 .pin = 3,
 538                 .reg = 0x40,
 539                 .bit = 6,
 540                 .mask = 0x3
 541         }, {
 542                 /* gpio2c0_sel */
 543                 .num = 2,
 544                 .pin = 16,
 545                 .reg = 0x50,
 546                 .bit = 0,
 547                 .mask = 0x3
 548         }, {
 549                 /* gpio3b2_sel */
 550                 .num = 3,
 551                 .pin = 10,
 552                 .reg = 0x68,
 553                 .bit = 4,
 554                 .mask = 0x3
 555         }, {
 556                 /* gpio3b3_sel */
 557                 .num = 3,
 558                 .pin = 11,
 559                 .reg = 0x68,
 560                 .bit = 6,
 561                 .mask = 0x3
 562         },
 563 };
 564
 565 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 566         {
 567                 .num = 2,
 568                 .pin = 12,
 569                 .reg = 0x24,
 570                 .bit = 8,
 571                 .mask = 0x3
 572         }, {
 573                 .num = 2,
 574                 .pin = 15,
 575                 .reg = 0x28,
 576                 .bit = 0,
 577                 .mask = 0x7
 578         }, {
 579                 .num = 2,
 580                 .pin = 23,
 581                 .reg = 0x30,
 582                 .bit = 14,
 583                 .mask = 0x3
 584         },
 585 };
 586
 587 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
 588                                       int *reg, u8 *bit, int *mask)
 589 {
 590         struct rockchip_pinctrl *info = bank->drvdata;
 591         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 592         struct rockchip_mux_recalced_data *data;
 593         int i;
 594
 595         for (i = 0; i < ctrl->niomux_recalced; i++) {
 596                 data = &ctrl->iomux_recalced[i];
 597                 if (data->num == bank->bank_num &&
 598                     data->pin == pin)
 599                         break;
 600         }
 601
 602         if (i >= ctrl->niomux_recalced)
 603                 return;
 604
 605         *reg = data->reg;
 606         *mask = data->mask;
 607         *bit = data->bit;
 608 }
 609
 610 static struct rockchip_mux_route_data px30_mux_route_data[] = {
 611         RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
 612         RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
 613         RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
 614         RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
 615         RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
 616         RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
 617         RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
 618         RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
 619         RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
 620         RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
 621         RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
 622         RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
 623         RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
 624         RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
 625         RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
 626         RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
 627         RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
 628         RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
 629         RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
 630         RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
 631         RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
 632         RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
 633         RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
 634         RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
 635         RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
 636         RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
 637         RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
 638         RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
 639         RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
 640         RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
 641         RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
 642         RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
 643         RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
 644         RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
 645         RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
 646         RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
 647         RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
 648         RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
 649         RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
 650         RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
 651         RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
 652         RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
 653         RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
 654         RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
 655         RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
 656         RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
 657         RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
 658         RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
 659 };
 660
 661 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
 662         RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
 663         RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
 664         RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
 665         RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
 666         RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
 667         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
 668         RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
 669 };
 670
 671 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
 672         RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
 673         RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
 674 };
 675
 676 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
 677         RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
 678         RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
 679         RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
 680         RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
 681         RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
 682         RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
 683         RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
 684         RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
 685         RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
 686         RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
 687         RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
 688         RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
 689         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
 690         RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
 691         RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
 692         RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
 693         RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
 694         RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
 695 };
 696
 697 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
 698         RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
 699         RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
 700 };
 701
 702 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
 703         RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
 704         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
 705         RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
 706         RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
 707         RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
 708         RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
 709         RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
 710         RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
 711         RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
 712         RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
 713         RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
 714         RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
 715         RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
 716         RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
 717         RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
 718         RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
 719         RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
 720         RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
 721         RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
 722         RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
 723         RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
 724         RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
 725         RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
 726         RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
 727         RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
 728         RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
 729 };
 730
 731 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
 732         RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
 733         RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
 734         RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
 735         RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
 736         RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
 737         RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
 738         RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
 739         RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
 740         RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
 741         RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
 742         RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
 743         RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
 744 };
 745
 746 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
 747         RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
 748         RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
 749         RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
 750         RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
 751         RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
 752 };
 753
 754 static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
 755         RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
 756         RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
 757         RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
 758         RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
 759         RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
 760         RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
 761         RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
 762         RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
 763         RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
 764         RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
 765         RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
 766         RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
 767         RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
 768         RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
 769         RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
 770         RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
 771         RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
 772         RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
 773         RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
 774         RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
 775         RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
 776         RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
 777         RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
 778         RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
 779         RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
 780         RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
 781         RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
 782         RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
 783         RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
 784         RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
 785         RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
 786         RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
 787         RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
 788         RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
 789         RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
 790         RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
 791         RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
 792         RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
 793         RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
 794         RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
 795         RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
 796         RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
 797         RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
 798         RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
 799         RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
 800         RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
 801         RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
 802         RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
 803         RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
 804         RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
 805         RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
 806         RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
 807         RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
 808         RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
 809         RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
 810         RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
 811         RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
 812         RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
 813         RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
 814         RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
 815         RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
 816         RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
 817         RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
 818         RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
 819         RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
 820         RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
 821         RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
 822         RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
 823         RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
 824         RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
 825         RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
 826         RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
 827         RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
 828         RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
 829         RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
 830         RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
 831         RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
 832         RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
 833         RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
 834         RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
 835         RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
 836         RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
 837         RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
 838         RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
 839         RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
 840         RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
 841         RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
 842         RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
 843         RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
 844         RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
 845         RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
 846         RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
 847         RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
 848 };
 849
 850 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
 851                                    int mux, u32 *loc, u32 *reg, u32 *value)
 852 {
 853         struct rockchip_pinctrl *info = bank->drvdata;
 854         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 855         struct rockchip_mux_route_data *data;
 856         int i;
 857
 858         for (i = 0; i < ctrl->niomux_routes; i++) {
 859                 data = &ctrl->iomux_routes[i];
 860                 if ((data->bank_num == bank->bank_num) &&
 861                     (data->pin == pin) && (data->func == mux))
 862                         break;
 863         }
 864
 865         if (i >= ctrl->niomux_routes)
 866                 return false;
 867
 868         *loc = data->route_location;
 869         *reg = data->route_offset;
 870         *value = data->route_val;
 871
 872         return true;
 873 }
 874
 875 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 876 {
 877         struct rockchip_pinctrl *info = bank->drvdata;
 878         int iomux_num = (pin / 8);
 879         struct regmap *regmap;
 880         unsigned int val;
 881         int reg, ret, mask, mux_type;
 882         u8 bit;
 883
 884         if (iomux_num > 3)
 885                 return -EINVAL;
 886
 887         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 888                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 889                 return -EINVAL;
 890         }
 891
 892         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 893                 return RK_FUNC_GPIO;
 894
 895         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 896                                 ? info->regmap_pmu : info->regmap_base;
 897
 898         /* get basic quadrupel of mux registers and the correct reg inside */
 899         mux_type = bank->iomux[iomux_num].type;
 900         reg = bank->iomux[iomux_num].offset;
 901         if (mux_type & IOMUX_WIDTH_4BIT) {
 902                 if ((pin % 8) >= 4)
 903                         reg += 0x4;
 904                 bit = (pin % 4) * 4;
 905                 mask = 0xf;
 906         } else if (mux_type & IOMUX_WIDTH_3BIT) {
 907                 if ((pin % 8) >= 5)
 908                         reg += 0x4;
 909                 bit = (pin % 8 % 5) * 3;
 910                 mask = 0x7;
 911         } else {
 912                 bit = (pin % 8) * 2;
 913                 mask = 0x3;
 914         }
 915
 916         if (bank->recalced_mask & BIT(pin))
 917                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
 918
 919         ret = regmap_read(regmap, reg, &val);
 920         if (ret)
 921                 return ret;
 922
 923         return ((val >> bit) & mask);
 924 }
 925
 926 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
 927                                int pin, int mux)
 928 {
 929         struct rockchip_pinctrl *info = bank->drvdata;
 930         int iomux_num = (pin / 8);
 931
 932         if (iomux_num > 3)
 933                 return -EINVAL;
 934
 935         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 936                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 937                 return -EINVAL;
 938         }
 939
 940         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 941                 if (mux != RK_FUNC_GPIO) {
 942                         dev_err(info->dev,
 943                                 "pin %d only supports a gpio mux\n", pin);
 944                         return -ENOTSUPP;
 945                 }
 946         }
 947
 948         return 0;
 949 }
 950
 951 /*
 952  * Set a new mux function for a pin.
 953  *
 954  * The register is divided into the upper and lower 16 bit. When changing
 955  * a value, the previous register value is not read and changed. Instead
 956  * it seems the changed bits are marked in the upper 16 bit, while the
 957  * changed value gets set in the same offset in the lower 16 bit.
 958  * All pin settings seem to be 2 bit wide in both the upper and lower
 959  * parts.
 960  * @bank: pin bank to change
 961  * @pin: pin to change
 962  * @mux: new mux function to set
 963  */
 964 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 965 {
 966         struct rockchip_pinctrl *info = bank->drvdata;
 967         int iomux_num = (pin / 8);
 968         struct regmap *regmap;
 969         int reg, ret, mask, mux_type;
 970         u8 bit;
 971         u32 data, rmask, route_location, route_reg, route_val;
 972
 973         ret = rockchip_verify_mux(bank, pin, mux);
 974         if (ret < 0)
 975                 return ret;
 976
 977         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 978                 return 0;
 979
 980         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 981                                                 bank->bank_num, pin, mux);
 982
 983         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 984                                 ? info->regmap_pmu : info->regmap_base;
 985
 986         /* get basic quadrupel of mux registers and the correct reg inside */
 987         mux_type = bank->iomux[iomux_num].type;
 988         reg = bank->iomux[iomux_num].offset;
 989         if (mux_type & IOMUX_WIDTH_4BIT) {
 990                 if ((pin % 8) >= 4)
 991                         reg += 0x4;
 992                 bit = (pin % 4) * 4;
 993                 mask = 0xf;
 994         } else if (mux_type & IOMUX_WIDTH_3BIT) {
 995                 if ((pin % 8) >= 5)
 996                         reg += 0x4;
 997                 bit = (pin % 8 % 5) * 3;
 998                 mask = 0x7;
 999         } else {
1000                 bit = (pin % 8) * 2;
1001                 mask = 0x3;
1002         }
1003
1004         if (bank->recalced_mask & BIT(pin))
1005                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1006
1007         if (bank->route_mask & BIT(pin)) {
1008                 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1009                                            &route_reg, &route_val)) {
1010                         struct regmap *route_regmap = regmap;
1011
1012                         /* handle special locations */
1013                         switch (route_location) {
1014                         case ROCKCHIP_ROUTE_PMU:
1015                                 route_regmap = info->regmap_pmu;
1016                                 break;
1017                         case ROCKCHIP_ROUTE_GRF:
1018                                 route_regmap = info->regmap_base;
1019                                 break;
1020                         }
1021
1022                         ret = regmap_write(route_regmap, route_reg, route_val);
1023                         if (ret)
1024                                 return ret;
1025                 }
1026         }
1027
1028         data = (mask << (bit + 16));
1029         rmask = data | (data >> 16);
1030         data |= (mux & mask) << bit;
1031         ret = regmap_update_bits(regmap, reg, rmask, data);
1032
1033         return ret;
1034 }
1035
1036 #define PX30_PULL_PMU_OFFSET            0x10
1037 #define PX30_PULL_GRF_OFFSET            0x60
1038 #define PX30_PULL_BITS_PER_PIN          2
1039 #define PX30_PULL_PINS_PER_REG          8
1040 #define PX30_PULL_BANK_STRIDE           16
1041
1042 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1043                                        int pin_num, struct regmap **regmap,
1044                                        int *reg, u8 *bit)
1045 {
1046         struct rockchip_pinctrl *info = bank->drvdata;
1047
1048         /* The first 32 pins of the first bank are located in PMU */
1049         if (bank->bank_num == 0) {
1050                 *regmap = info->regmap_pmu;
1051                 *reg = PX30_PULL_PMU_OFFSET;
1052         } else {
1053                 *regmap = info->regmap_base;
1054                 *reg = PX30_PULL_GRF_OFFSET;
1055
1056                 /* correct the offset, as we're starting with the 2nd bank */
1057                 *reg -= 0x10;
1058                 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1059         }
1060
1061         *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1062         *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1063         *bit *= PX30_PULL_BITS_PER_PIN;
1064 }
1065
1066 #define PX30_DRV_PMU_OFFSET             0x20
1067 #define PX30_DRV_GRF_OFFSET             0xf0
1068 #define PX30_DRV_BITS_PER_PIN           2
1069 #define PX30_DRV_PINS_PER_REG           8
1070 #define PX30_DRV_BANK_STRIDE            16
1071
1072 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1073                                       int pin_num, struct regmap **regmap,
1074                                       int *reg, u8 *bit)
1075 {
1076         struct rockchip_pinctrl *info = bank->drvdata;
1077
1078         /* The first 32 pins of the first bank are located in PMU */
1079         if (bank->bank_num == 0) {
1080                 *regmap = info->regmap_pmu;
1081                 *reg = PX30_DRV_PMU_OFFSET;
1082         } else {
1083                 *regmap = info->regmap_base;
1084                 *reg = PX30_DRV_GRF_OFFSET;
1085
1086                 /* correct the offset, as we're starting with the 2nd bank */
1087                 *reg -= 0x10;
1088                 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1089         }
1090
1091         *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1092         *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1093         *bit *= PX30_DRV_BITS_PER_PIN;
1094 }
1095
1096 #define PX30_SCHMITT_PMU_OFFSET                 0x38
1097 #define PX30_SCHMITT_GRF_OFFSET                 0xc0
1098 #define PX30_SCHMITT_PINS_PER_PMU_REG           16
1099 #define PX30_SCHMITT_BANK_STRIDE                16
1100 #define PX30_SCHMITT_PINS_PER_GRF_REG           8
1101
1102 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1103                                          int pin_num,
1104                                          struct regmap **regmap,
1105                                          int *reg, u8 *bit)
1106 {
1107         struct rockchip_pinctrl *info = bank->drvdata;
1108         int pins_per_reg;
1109
1110         if (bank->bank_num == 0) {
1111                 *regmap = info->regmap_pmu;
1112                 *reg = PX30_SCHMITT_PMU_OFFSET;
1113                 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1114         } else {
1115                 *regmap = info->regmap_base;
1116                 *reg = PX30_SCHMITT_GRF_OFFSET;
1117                 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1118                 *reg += (bank->bank_num  - 1) * PX30_SCHMITT_BANK_STRIDE;
1119         }
1120
1121         *reg += ((pin_num / pins_per_reg) * 4);
1122         *bit = pin_num % pins_per_reg;
1123
1124         return 0;
1125 }
1126
1127 #define RV1108_PULL_PMU_OFFSET          0x10
1128 #define RV1108_PULL_OFFSET              0x110
1129 #define RV1108_PULL_PINS_PER_REG        8
1130 #define RV1108_PULL_BITS_PER_PIN        2
1131 #define RV1108_PULL_BANK_STRIDE         16
1132
1133 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1134                                          int pin_num, struct regmap **regmap,
1135                                          int *reg, u8 *bit)
1136 {
1137         struct rockchip_pinctrl *info = bank->drvdata;
1138
1139         /* The first 24 pins of the first bank are located in PMU */
1140         if (bank->bank_num == 0) {
1141                 *regmap = info->regmap_pmu;
1142                 *reg = RV1108_PULL_PMU_OFFSET;
1143         } else {
1144                 *reg = RV1108_PULL_OFFSET;
1145                 *regmap = info->regmap_base;
1146                 /* correct the offset, as we're starting with the 2nd bank */
1147                 *reg -= 0x10;
1148                 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1149         }
1150
1151         *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1152         *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1153         *bit *= RV1108_PULL_BITS_PER_PIN;
1154 }
1155
1156 #define RV1108_DRV_PMU_OFFSET           0x20
1157 #define RV1108_DRV_GRF_OFFSET           0x210
1158 #define RV1108_DRV_BITS_PER_PIN         2
1159 #define RV1108_DRV_PINS_PER_REG         8
1160 #define RV1108_DRV_BANK_STRIDE          16
1161
1162 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1163                                         int pin_num, struct regmap **regmap,
1164                                         int *reg, u8 *bit)
1165 {
1166         struct rockchip_pinctrl *info = bank->drvdata;
1167
1168         /* The first 24 pins of the first bank are located in PMU */
1169         if (bank->bank_num == 0) {
1170                 *regmap = info->regmap_pmu;
1171                 *reg = RV1108_DRV_PMU_OFFSET;
1172         } else {
1173                 *regmap = info->regmap_base;
1174                 *reg = RV1108_DRV_GRF_OFFSET;
1175
1176                 /* correct the offset, as we're starting with the 2nd bank */
1177                 *reg -= 0x10;
1178                 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1179         }
1180
1181         *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1182         *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1183         *bit *= RV1108_DRV_BITS_PER_PIN;
1184 }
1185
1186 #define RV1108_SCHMITT_PMU_OFFSET               0x30
1187 #define RV1108_SCHMITT_GRF_OFFSET               0x388
1188 #define RV1108_SCHMITT_BANK_STRIDE              8
1189 #define RV1108_SCHMITT_PINS_PER_GRF_REG         16
1190 #define RV1108_SCHMITT_PINS_PER_PMU_REG         8
1191
1192 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1193                                            int pin_num,
1194                                            struct regmap **regmap,
1195                                            int *reg, u8 *bit)
1196 {
1197         struct rockchip_pinctrl *info = bank->drvdata;
1198         int pins_per_reg;
1199
1200         if (bank->bank_num == 0) {
1201                 *regmap = info->regmap_pmu;
1202                 *reg = RV1108_SCHMITT_PMU_OFFSET;
1203                 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1204         } else {
1205                 *regmap = info->regmap_base;
1206                 *reg = RV1108_SCHMITT_GRF_OFFSET;
1207                 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1208                 *reg += (bank->bank_num  - 1) * RV1108_SCHMITT_BANK_STRIDE;
1209         }
1210         *reg += ((pin_num / pins_per_reg) * 4);
1211         *bit = pin_num % pins_per_reg;
1212
1213         return 0;
1214 }
1215
1216 #define RK3308_SCHMITT_PINS_PER_REG             8
1217 #define RK3308_SCHMITT_BANK_STRIDE              16
1218 #define RK3308_SCHMITT_GRF_OFFSET               0x1a0
1219
1220 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1221                                     int pin_num, struct regmap **regmap,
1222                                     int *reg, u8 *bit)
1223 {
1224         struct rockchip_pinctrl *info = bank->drvdata;
1225
1226         *regmap = info->regmap_base;
1227         *reg = RK3308_SCHMITT_GRF_OFFSET;
1228
1229         *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1230         *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1231         *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1232
1233         return 0;
1234 }
1235
1236 #define RK2928_PULL_OFFSET              0x118
1237 #define RK2928_PULL_PINS_PER_REG        16
1238 #define RK2928_PULL_BANK_STRIDE         8
1239
1240 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1241                                     int pin_num, struct regmap **regmap,
1242                                     int *reg, u8 *bit)
1243 {
1244         struct rockchip_pinctrl *info = bank->drvdata;
1245
1246         *regmap = info->regmap_base;
1247         *reg = RK2928_PULL_OFFSET;
1248         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1249         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1250
1251         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1252 };
1253
1254 #define RK3128_PULL_OFFSET      0x118
1255
1256 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1257                                          int pin_num, struct regmap **regmap,
1258                                          int *reg, u8 *bit)
1259 {
1260         struct rockchip_pinctrl *info = bank->drvdata;
1261
1262         *regmap = info->regmap_base;
1263         *reg = RK3128_PULL_OFFSET;
1264         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1265         *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1266
1267         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1268 }
1269
1270 #define RK3188_PULL_OFFSET              0x164
1271 #define RK3188_PULL_BITS_PER_PIN        2
1272 #define RK3188_PULL_PINS_PER_REG        8
1273 #define RK3188_PULL_BANK_STRIDE         16
1274 #define RK3188_PULL_PMU_OFFSET          0x64
1275
1276 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1277                                     int pin_num, struct regmap **regmap,
1278                                     int *reg, u8 *bit)
1279 {
1280         struct rockchip_pinctrl *info = bank->drvdata;
1281
1282         /* The first 12 pins of the first bank are located elsewhere */
1283         if (bank->bank_num == 0 && pin_num < 12) {
1284                 *regmap = info->regmap_pmu ? info->regmap_pmu
1285                                            : bank->regmap_pull;
1286                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1287                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1288                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1289                 *bit *= RK3188_PULL_BITS_PER_PIN;
1290         } else {
1291                 *regmap = info->regmap_pull ? info->regmap_pull
1292                                             : info->regmap_base;
1293                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1294
1295                 /* correct the offset, as it is the 2nd pull register */
1296                 *reg -= 4;
1297                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1298                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1299
1300                 /*
1301                  * The bits in these registers have an inverse ordering
1302                  * with the lowest pin being in bits 15:14 and the highest
1303                  * pin in bits 1:0
1304                  */
1305                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1306                 *bit *= RK3188_PULL_BITS_PER_PIN;
1307         }
1308 }
1309
1310 #define RK3288_PULL_OFFSET              0x140
1311 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1312                                     int pin_num, struct regmap **regmap,
1313                                     int *reg, u8 *bit)
1314 {
1315         struct rockchip_pinctrl *info = bank->drvdata;
1316
1317         /* The first 24 pins of the first bank are located in PMU */
1318         if (bank->bank_num == 0) {
1319                 *regmap = info->regmap_pmu;
1320                 *reg = RK3188_PULL_PMU_OFFSET;
1321
1322                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1323                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1324                 *bit *= RK3188_PULL_BITS_PER_PIN;
1325         } else {
1326                 *regmap = info->regmap_base;
1327                 *reg = RK3288_PULL_OFFSET;
1328
1329                 /* correct the offset, as we're starting with the 2nd bank */
1330                 *reg -= 0x10;
1331                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1332                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1333
1334                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1335                 *bit *= RK3188_PULL_BITS_PER_PIN;
1336         }
1337 }
1338
1339 #define RK3288_DRV_PMU_OFFSET           0x70
1340 #define RK3288_DRV_GRF_OFFSET           0x1c0
1341 #define RK3288_DRV_BITS_PER_PIN         2
1342 #define RK3288_DRV_PINS_PER_REG         8
1343 #define RK3288_DRV_BANK_STRIDE          16
1344
1345 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1346                                     int pin_num, struct regmap **regmap,
1347                                     int *reg, u8 *bit)
1348 {
1349         struct rockchip_pinctrl *info = bank->drvdata;
1350
1351         /* The first 24 pins of the first bank are located in PMU */
1352         if (bank->bank_num == 0) {
1353                 *regmap = info->regmap_pmu;
1354                 *reg = RK3288_DRV_PMU_OFFSET;
1355
1356                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1357                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1358                 *bit *= RK3288_DRV_BITS_PER_PIN;
1359         } else {
1360                 *regmap = info->regmap_base;
1361                 *reg = RK3288_DRV_GRF_OFFSET;
1362
1363                 /* correct the offset, as we're starting with the 2nd bank */
1364                 *reg -= 0x10;
1365                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1366                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1367
1368                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1369                 *bit *= RK3288_DRV_BITS_PER_PIN;
1370         }
1371 }
1372
1373 #define RK3228_PULL_OFFSET              0x100
1374
1375 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1376                                     int pin_num, struct regmap **regmap,
1377                                     int *reg, u8 *bit)
1378 {
1379         struct rockchip_pinctrl *info = bank->drvdata;
1380
1381         *regmap = info->regmap_base;
1382         *reg = RK3228_PULL_OFFSET;
1383         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1384         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1385
1386         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1387         *bit *= RK3188_PULL_BITS_PER_PIN;
1388 }
1389
1390 #define RK3228_DRV_GRF_OFFSET           0x200
1391
1392 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1393                                     int pin_num, struct regmap **regmap,
1394                                     int *reg, u8 *bit)
1395 {
1396         struct rockchip_pinctrl *info = bank->drvdata;
1397
1398         *regmap = info->regmap_base;
1399         *reg = RK3228_DRV_GRF_OFFSET;
1400         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1401         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1402
1403         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1404         *bit *= RK3288_DRV_BITS_PER_PIN;
1405 }
1406
1407 #define RK3308_PULL_OFFSET              0xa0
1408
1409 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1410                                     int pin_num, struct regmap **regmap,
1411                                     int *reg, u8 *bit)
1412 {
1413         struct rockchip_pinctrl *info = bank->drvdata;
1414
1415         *regmap = info->regmap_base;
1416         *reg = RK3308_PULL_OFFSET;
1417         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1418         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1419
1420         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1421         *bit *= RK3188_PULL_BITS_PER_PIN;
1422 }
1423
1424 #define RK3308_DRV_GRF_OFFSET           0x100
1425
1426 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1427                                     int pin_num, struct regmap **regmap,
1428                                     int *reg, u8 *bit)
1429 {
1430         struct rockchip_pinctrl *info = bank->drvdata;
1431
1432         *regmap = info->regmap_base;
1433         *reg = RK3308_DRV_GRF_OFFSET;
1434         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1435         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1436
1437         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1438         *bit *= RK3288_DRV_BITS_PER_PIN;
1439 }
1440
1441 #define RK3368_PULL_GRF_OFFSET          0x100
1442 #define RK3368_PULL_PMU_OFFSET          0x10
1443
1444 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1445                                     int pin_num, struct regmap **regmap,
1446                                     int *reg, u8 *bit)
1447 {
1448         struct rockchip_pinctrl *info = bank->drvdata;
1449
1450         /* The first 32 pins of the first bank are located in PMU */
1451         if (bank->bank_num == 0) {
1452                 *regmap = info->regmap_pmu;
1453                 *reg = RK3368_PULL_PMU_OFFSET;
1454
1455                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1456                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1457                 *bit *= RK3188_PULL_BITS_PER_PIN;
1458         } else {
1459                 *regmap = info->regmap_base;
1460                 *reg = RK3368_PULL_GRF_OFFSET;
1461
1462                 /* correct the offset, as we're starting with the 2nd bank */
1463                 *reg -= 0x10;
1464                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1465                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1466
1467                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1468                 *bit *= RK3188_PULL_BITS_PER_PIN;
1469         }
1470 }
1471
1472 #define RK3368_DRV_PMU_OFFSET           0x20
1473 #define RK3368_DRV_GRF_OFFSET           0x200
1474
1475 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1476                                     int pin_num, struct regmap **regmap,
1477                                     int *reg, u8 *bit)
1478 {
1479         struct rockchip_pinctrl *info = bank->drvdata;
1480
1481         /* The first 32 pins of the first bank are located in PMU */
1482         if (bank->bank_num == 0) {
1483                 *regmap = info->regmap_pmu;
1484                 *reg = RK3368_DRV_PMU_OFFSET;
1485
1486                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1487                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1488                 *bit *= RK3288_DRV_BITS_PER_PIN;
1489         } else {
1490                 *regmap = info->regmap_base;
1491                 *reg = RK3368_DRV_GRF_OFFSET;
1492
1493                 /* correct the offset, as we're starting with the 2nd bank */
1494                 *reg -= 0x10;
1495                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1496                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1497
1498                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1499                 *bit *= RK3288_DRV_BITS_PER_PIN;
1500         }
1501 }
1502
1503 #define RK3399_PULL_GRF_OFFSET          0xe040
1504 #define RK3399_PULL_PMU_OFFSET          0x40
1505 #define RK3399_DRV_3BITS_PER_PIN        3
1506
1507 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1508                                          int pin_num, struct regmap **regmap,
1509                                          int *reg, u8 *bit)
1510 {
1511         struct rockchip_pinctrl *info = bank->drvdata;
1512
1513         /* The bank0:16 and bank1:32 pins are located in PMU */
1514         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1515                 *regmap = info->regmap_pmu;
1516                 *reg = RK3399_PULL_PMU_OFFSET;
1517
1518                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1519
1520                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1521                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1522                 *bit *= RK3188_PULL_BITS_PER_PIN;
1523         } else {
1524                 *regmap = info->regmap_base;
1525                 *reg = RK3399_PULL_GRF_OFFSET;
1526
1527                 /* correct the offset, as we're starting with the 3rd bank */
1528                 *reg -= 0x20;
1529                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1530                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1531
1532                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1533                 *bit *= RK3188_PULL_BITS_PER_PIN;
1534         }
1535 }
1536
1537 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1538                                         int pin_num, struct regmap **regmap,
1539                                         int *reg, u8 *bit)
1540 {
1541         struct rockchip_pinctrl *info = bank->drvdata;
1542         int drv_num = (pin_num / 8);
1543
1544         /*  The bank0:16 and bank1:32 pins are located in PMU */
1545         if ((bank->bank_num == 0) || (bank->bank_num == 1))
1546                 *regmap = info->regmap_pmu;
1547         else
1548                 *regmap = info->regmap_base;
1549
1550         *reg = bank->drv[drv_num].offset;
1551         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1552             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1553                 *bit = (pin_num % 8) * 3;
1554         else
1555                 *bit = (pin_num % 8) * 2;
1556 }
1557
1558 #define RK3568_PULL_PMU_OFFSET          0x20
1559 #define RK3568_PULL_GRF_OFFSET          0x80
1560 #define RK3568_PULL_BITS_PER_PIN        2
1561 #define RK3568_PULL_PINS_PER_REG        8
1562 #define RK3568_PULL_BANK_STRIDE         0x10
1563
1564 static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1565                                          int pin_num, struct regmap **regmap,
1566                                          int *reg, u8 *bit)
1567 {
1568         struct rockchip_pinctrl *info = bank->drvdata;
1569
1570         if (bank->bank_num == 0) {
1571                 *regmap = info->regmap_pmu;
1572                 *reg = RK3568_PULL_PMU_OFFSET;
1573                 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
1574                 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1575
1576                 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
1577                 *bit *= RK3568_PULL_BITS_PER_PIN;
1578         } else {
1579                 *regmap = info->regmap_base;
1580                 *reg = RK3568_PULL_GRF_OFFSET;
1581                 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
1582                 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1583
1584                 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
1585                 *bit *= RK3568_PULL_BITS_PER_PIN;
1586         }
1587 }
1588
1589 #define RK3568_DRV_PMU_OFFSET           0x70
1590 #define RK3568_DRV_GRF_OFFSET           0x200
1591 #define RK3568_DRV_BITS_PER_PIN         8
1592 #define RK3568_DRV_PINS_PER_REG         2
1593 #define RK3568_DRV_BANK_STRIDE          0x40
1594
1595 static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1596                                         int pin_num, struct regmap **regmap,
1597                                         int *reg, u8 *bit)
1598 {
1599         struct rockchip_pinctrl *info = bank->drvdata;
1600
1601         /* The first 32 pins of the first bank are located in PMU */
1602         if (bank->bank_num == 0) {
1603                 *regmap = info->regmap_pmu;
1604                 *reg = RK3568_DRV_PMU_OFFSET;
1605                 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1606
1607                 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
1608                 *bit *= RK3568_DRV_BITS_PER_PIN;
1609         } else {
1610                 *regmap = info->regmap_base;
1611                 *reg = RK3568_DRV_GRF_OFFSET;
1612                 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
1613                 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1614
1615                 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
1616                 *bit *= RK3568_DRV_BITS_PER_PIN;
1617         }
1618 }
1619
1620 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1621         { 2, 4, 8, 12, -1, -1, -1, -1 },
1622         { 3, 6, 9, 12, -1, -1, -1, -1 },
1623         { 5, 10, 15, 20, -1, -1, -1, -1 },
1624         { 4, 6, 8, 10, 12, 14, 16, 18 },
1625         { 4, 7, 10, 13, 16, 19, 22, 26 }
1626 };
1627
1628 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1629                                      int pin_num)
1630 {
1631         struct rockchip_pinctrl *info = bank->drvdata;
1632         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1633         struct regmap *regmap;
1634         int reg, ret;
1635         u32 data, temp, rmask_bits;
1636         u8 bit;
1637         int drv_type = bank->drv[pin_num / 8].drv_type;
1638
1639         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1640
1641         switch (drv_type) {
1642         case DRV_TYPE_IO_1V8_3V0_AUTO:
1643         case DRV_TYPE_IO_3V3_ONLY:
1644                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1645                 switch (bit) {
1646                 case 0 ... 12:
1647                         /* regular case, nothing to do */
1648                         break;
1649                 case 15:
1650                         /*
1651                          * drive-strength offset is special, as it is
1652                          * spread over 2 registers
1653                          */
1654                         ret = regmap_read(regmap, reg, &data);
1655                         if (ret)
1656                                 return ret;
1657
1658                         ret = regmap_read(regmap, reg + 0x4, &temp);
1659                         if (ret)
1660                                 return ret;
1661
1662                         /*
1663                          * the bit data[15] contains bit 0 of the value
1664                          * while temp[1:0] contains bits 2 and 1
1665                          */
1666                         data >>= 15;
1667                         temp &= 0x3;
1668                         temp <<= 1;
1669                         data |= temp;
1670
1671                         return rockchip_perpin_drv_list[drv_type][data];
1672                 case 18 ... 21:
1673                         /* setting fully enclosed in the second register */
1674                         reg += 4;
1675                         bit -= 16;
1676                         break;
1677                 default:
1678                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1679                                 bit, drv_type);
1680                         return -EINVAL;
1681                 }
1682
1683                 break;
1684         case DRV_TYPE_IO_DEFAULT:
1685         case DRV_TYPE_IO_1V8_OR_3V0:
1686         case DRV_TYPE_IO_1V8_ONLY:
1687                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1688                 break;
1689         default:
1690                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1691                         drv_type);
1692                 return -EINVAL;
1693         }
1694
1695         ret = regmap_read(regmap, reg, &data);
1696         if (ret)
1697                 return ret;
1698
1699         data >>= bit;
1700         data &= (1 << rmask_bits) - 1;
1701
1702         return rockchip_perpin_drv_list[drv_type][data];
1703 }
1704
1705 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1706                                      int pin_num, int strength)
1707 {
1708         struct rockchip_pinctrl *info = bank->drvdata;
1709         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1710         struct regmap *regmap;
1711         int reg, ret, i;
1712         u32 data, rmask, rmask_bits, temp;
1713         u8 bit;
1714         int drv_type = bank->drv[pin_num / 8].drv_type;
1715
1716         dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1717                 bank->bank_num, pin_num, strength);
1718
1719         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1720         if (ctrl->type == RK3568) {
1721                 rmask_bits = RK3568_DRV_BITS_PER_PIN;
1722                 ret = (1 << (strength + 1)) - 1;
1723                 goto config;
1724         }
1725
1726         ret = -EINVAL;
1727         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1728                 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1729                         ret = i;
1730                         break;
1731                 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1732                         ret = rockchip_perpin_drv_list[drv_type][i];
1733                         break;
1734                 }
1735         }
1736
1737         if (ret < 0) {
1738                 dev_err(info->dev, "unsupported driver strength %d\n",
1739                         strength);
1740                 return ret;
1741         }
1742
1743         switch (drv_type) {
1744         case DRV_TYPE_IO_1V8_3V0_AUTO:
1745         case DRV_TYPE_IO_3V3_ONLY:
1746                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1747                 switch (bit) {
1748                 case 0 ... 12:
1749                         /* regular case, nothing to do */
1750                         break;
1751                 case 15:
1752                         /*
1753                          * drive-strength offset is special, as it is spread
1754                          * over 2 registers, the bit data[15] contains bit 0
1755                          * of the value while temp[1:0] contains bits 2 and 1
1756                          */
1757                         data = (ret & 0x1) << 15;
1758                         temp = (ret >> 0x1) & 0x3;
1759
1760                         rmask = BIT(15) | BIT(31);
1761                         data |= BIT(31);
1762                         ret = regmap_update_bits(regmap, reg, rmask, data);
1763                         if (ret)
1764                                 return ret;
1765
1766                         rmask = 0x3 | (0x3 << 16);
1767                         temp |= (0x3 << 16);
1768                         reg += 0x4;
1769                         ret = regmap_update_bits(regmap, reg, rmask, temp);
1770
1771                         return ret;
1772                 case 18 ... 21:
1773                         /* setting fully enclosed in the second register */
1774                         reg += 4;
1775                         bit -= 16;
1776                         break;
1777                 default:
1778                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1779                                 bit, drv_type);
1780                         return -EINVAL;
1781                 }
1782                 break;
1783         case DRV_TYPE_IO_DEFAULT:
1784         case DRV_TYPE_IO_1V8_OR_3V0:
1785         case DRV_TYPE_IO_1V8_ONLY:
1786                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1787                 break;
1788         default:
1789                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1790                         drv_type);
1791                 return -EINVAL;
1792         }
1793
1794 config:
1795         /* enable the write to the equivalent lower bits */
1796         data = ((1 << rmask_bits) - 1) << (bit + 16);
1797         rmask = data | (data >> 16);
1798         data |= (ret << bit);
1799
1800         ret = regmap_update_bits(regmap, reg, rmask, data);
1801
1802         return ret;
1803 }
1804
1805 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1806         {
1807                 PIN_CONFIG_BIAS_DISABLE,
1808                 PIN_CONFIG_BIAS_PULL_UP,
1809                 PIN_CONFIG_BIAS_PULL_DOWN,
1810                 PIN_CONFIG_BIAS_BUS_HOLD
1811         },
1812         {
1813                 PIN_CONFIG_BIAS_DISABLE,
1814                 PIN_CONFIG_BIAS_PULL_DOWN,
1815                 PIN_CONFIG_BIAS_DISABLE,
1816                 PIN_CONFIG_BIAS_PULL_UP
1817         },
1818 };
1819
1820 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1821 {
1822         struct rockchip_pinctrl *info = bank->drvdata;
1823         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1824         struct regmap *regmap;
1825         int reg, ret, pull_type;
1826         u8 bit;
1827         u32 data;
1828
1829         /* rk3066b does support any pulls */
1830         if (ctrl->type == RK3066B)
1831                 return PIN_CONFIG_BIAS_DISABLE;
1832
1833         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1834
1835         ret = regmap_read(regmap, reg, &data);
1836         if (ret)
1837                 return ret;
1838
1839         switch (ctrl->type) {
1840         case RK2928:
1841         case RK3128:
1842                 return !(data & BIT(bit))
1843                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1844                                 : PIN_CONFIG_BIAS_DISABLE;
1845         case PX30:
1846         case RV1108:
1847         case RK3188:
1848         case RK3288:
1849         case RK3308:
1850         case RK3368:
1851         case RK3399:
1852                 pull_type = bank->pull_type[pin_num / 8];
1853                 data >>= bit;
1854                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1855
1856                 return rockchip_pull_list[pull_type][data];
1857         default:
1858                 dev_err(info->dev, "unsupported pinctrl type\n");
1859                 return -EINVAL;
1860         };
1861 }
1862
1863 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1864                                         int pin_num, int pull)
1865 {
1866         struct rockchip_pinctrl *info = bank->drvdata;
1867         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1868         struct regmap *regmap;
1869         int reg, ret, i, pull_type;
1870         u8 bit;
1871         u32 data, rmask;
1872
1873         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1874                  bank->bank_num, pin_num, pull);
1875
1876         /* rk3066b does support any pulls */
1877         if (ctrl->type == RK3066B)
1878                 return pull ? -EINVAL : 0;
1879
1880         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1881
1882         switch (ctrl->type) {
1883         case RK2928:
1884         case RK3128:
1885                 data = BIT(bit + 16);
1886                 if (pull == PIN_CONFIG_BIAS_DISABLE)
1887                         data |= BIT(bit);
1888                 ret = regmap_write(regmap, reg, data);
1889                 break;
1890         case PX30:
1891         case RV1108:
1892         case RK3188:
1893         case RK3288:
1894         case RK3308:
1895         case RK3368:
1896         case RK3399:
1897         case RK3568:
1898                 pull_type = bank->pull_type[pin_num / 8];
1899                 ret = -EINVAL;
1900                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1901                         i++) {
1902                         if (rockchip_pull_list[pull_type][i] == pull) {
1903                                 ret = i;
1904                                 break;
1905                         }
1906                 }
1907                 /*
1908                  * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6,
1909                  * where that pull up value becomes 3.
1910                  */
1911                 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
1912                         if (ret == 1)
1913                                 ret = 3;
1914                 }
1915
1916                 if (ret < 0) {
1917                         dev_err(info->dev, "unsupported pull setting %d\n",
1918                                 pull);
1919                         return ret;
1920                 }
1921
1922                 /* enable the write to the equivalent lower bits */
1923                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1924                 rmask = data | (data >> 16);
1925                 data |= (ret << bit);
1926
1927                 ret = regmap_update_bits(regmap, reg, rmask, data);
1928                 break;
1929         default:
1930                 dev_err(info->dev, "unsupported pinctrl type\n");
1931                 return -EINVAL;
1932         }
1933
1934         return ret;
1935 }
1936
1937 #define RK3328_SCHMITT_BITS_PER_PIN             1
1938 #define RK3328_SCHMITT_PINS_PER_REG             16
1939 #define RK3328_SCHMITT_BANK_STRIDE              8
1940 #define RK3328_SCHMITT_GRF_OFFSET               0x380
1941
1942 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1943                                            int pin_num,
1944                                            struct regmap **regmap,
1945                                            int *reg, u8 *bit)
1946 {
1947         struct rockchip_pinctrl *info = bank->drvdata;
1948
1949         *regmap = info->regmap_base;
1950         *reg = RK3328_SCHMITT_GRF_OFFSET;
1951
1952         *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
1953         *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
1954         *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
1955
1956         return 0;
1957 }
1958
1959 #define RK3568_SCHMITT_BITS_PER_PIN             2
1960 #define RK3568_SCHMITT_PINS_PER_REG             8
1961 #define RK3568_SCHMITT_BANK_STRIDE              0x10
1962 #define RK3568_SCHMITT_GRF_OFFSET               0xc0
1963 #define RK3568_SCHMITT_PMUGRF_OFFSET            0x30
1964
1965 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1966                                            int pin_num,
1967                                            struct regmap **regmap,
1968                                            int *reg, u8 *bit)
1969 {
1970         struct rockchip_pinctrl *info = bank->drvdata;
1971
1972         if (bank->bank_num == 0) {
1973                 *regmap = info->regmap_pmu;
1974                 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
1975         } else {
1976                 *regmap = info->regmap_base;
1977                 *reg = RK3568_SCHMITT_GRF_OFFSET;
1978                 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
1979         }
1980
1981         *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
1982         *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
1983         *bit *= RK3568_SCHMITT_BITS_PER_PIN;
1984
1985         return 0;
1986 }
1987
1988 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
1989 {
1990         struct rockchip_pinctrl *info = bank->drvdata;
1991         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1992         struct regmap *regmap;
1993         int reg, ret;
1994         u8 bit;
1995         u32 data;
1996
1997         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1998         if (ret)
1999                 return ret;
2000
2001         ret = regmap_read(regmap, reg, &data);
2002         if (ret)
2003                 return ret;
2004
2005         data >>= bit;
2006         switch (ctrl->type) {
2007         case RK3568:
2008                 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
2009         default:
2010                 break;
2011         }
2012
2013         return data & 0x1;
2014 }
2015
2016 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2017                                 int pin_num, int enable)
2018 {
2019         struct rockchip_pinctrl *info = bank->drvdata;
2020         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2021         struct regmap *regmap;
2022         int reg, ret;
2023         u8 bit;
2024         u32 data, rmask;
2025
2026         dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2027                 bank->bank_num, pin_num, enable);
2028
2029         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2030         if (ret)
2031                 return ret;
2032
2033         /* enable the write to the equivalent lower bits */
2034         switch (ctrl->type) {
2035         case RK3568:
2036                 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
2037                 rmask = data | (data >> 16);
2038                 data |= ((enable ? 0x2 : 0x1) << bit);
2039                 break;
2040         default:
2041                 data = BIT(bit + 16) | (enable << bit);
2042                 rmask = BIT(bit + 16) | BIT(bit);
2043                 break;
2044         }
2045
2046         return regmap_update_bits(regmap, reg, rmask, data);
2047 }
2048
2049 /*
2050  * Pinmux_ops handling
2051  */
2052
2053 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2054 {
2055         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2056
2057         return info->nfunctions;
2058 }
2059
2060 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2061                                           unsigned selector)
2062 {
2063         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2064
2065         return info->functions[selector].name;
2066 }
2067
2068 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2069                                 unsigned selector, const char * const **groups,
2070                                 unsigned * const num_groups)
2071 {
2072         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2073
2074         *groups = info->functions[selector].groups;
2075         *num_groups = info->functions[selector].ngroups;
2076
2077         return 0;
2078 }
2079
2080 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2081                             unsigned group)
2082 {
2083         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2084         const unsigned int *pins = info->groups[group].pins;
2085         const struct rockchip_pin_config *data = info->groups[group].data;
2086         struct rockchip_pin_bank *bank;
2087         int cnt, ret = 0;
2088
2089         dev_dbg(info->dev, "enable function %s group %s\n",
2090                 info->functions[selector].name, info->groups[group].name);
2091
2092         /*
2093          * for each pin in the pin group selected, program the corresponding
2094          * pin function number in the config register.
2095          */
2096         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2097                 bank = pin_to_bank(info, pins[cnt]);
2098                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2099                                        data[cnt].func);
2100                 if (ret)
2101                         break;
2102         }
2103
2104         if (ret) {
2105                 /* revert the already done pin settings */
2106                 for (cnt--; cnt >= 0; cnt--)
2107                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2108
2109                 return ret;
2110         }
2111
2112         return 0;
2113 }
2114
2115 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2116                                            struct pinctrl_gpio_range *range,
2117                                            unsigned offset,
2118                                            bool input)
2119 {
2120         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2121         struct rockchip_pin_bank *bank;
2122
2123         bank = pin_to_bank(info, offset);
2124         return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO);
2125 }
2126
2127 static const struct pinmux_ops rockchip_pmx_ops = {
2128         .get_functions_count    = rockchip_pmx_get_funcs_count,
2129         .get_function_name      = rockchip_pmx_get_func_name,
2130         .get_function_groups    = rockchip_pmx_get_groups,
2131         .set_mux                = rockchip_pmx_set,
2132         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
2133 };
2134
2135 /*
2136  * Pinconf_ops handling
2137  */
2138
2139 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2140                                         enum pin_config_param pull)
2141 {
2142         switch (ctrl->type) {
2143         case RK2928:
2144         case RK3128:
2145                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2146                                         pull == PIN_CONFIG_BIAS_DISABLE);
2147         case RK3066B:
2148                 return pull ? false : true;
2149         case PX30:
2150         case RV1108:
2151         case RK3188:
2152         case RK3288:
2153         case RK3308:
2154         case RK3368:
2155         case RK3399:
2156         case RK3568:
2157                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2158         }
2159
2160         return false;
2161 }
2162
2163 static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
2164                                          unsigned int pin, u32 param, u32 arg)
2165 {
2166         struct rockchip_pin_deferred *cfg;
2167
2168         cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
2169         if (!cfg)
2170                 return -ENOMEM;
2171
2172         cfg->pin = pin;
2173         cfg->param = param;
2174         cfg->arg = arg;
2175
2176         list_add_tail(&cfg->head, &bank->deferred_pins);
2177
2178         return 0;
2179 }
2180
2181 /* set the pin config settings for a specified pin */
2182 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2183                                 unsigned long *configs, unsigned num_configs)
2184 {
2185         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2186         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2187         struct gpio_chip *gpio = &bank->gpio_chip;
2188         enum pin_config_param param;
2189         u32 arg;
2190         int i;
2191         int rc;
2192
2193         for (i = 0; i < num_configs; i++) {
2194                 param = pinconf_to_config_param(configs[i]);
2195                 arg = pinconf_to_config_argument(configs[i]);
2196
2197                 if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) {
2198                         /*
2199                          * Check for gpio driver not being probed yet.
2200                          * The lock makes sure that either gpio-probe has completed
2201                          * or the gpio driver hasn't probed yet.
2202                          */
2203                         mutex_lock(&bank->deferred_lock);
2204                         if (!gpio || !gpio->direction_output) {
2205                                 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param,
2206                                                                 arg);
2207                                 mutex_unlock(&bank->deferred_lock);
2208                                 if (rc)
2209                                         return rc;
2210
2211                                 break;
2212                         }
2213                         mutex_unlock(&bank->deferred_lock);
2214                 }
2215
2216                 switch (param) {
2217                 case PIN_CONFIG_BIAS_DISABLE:
2218                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
2219                                 param);
2220                         if (rc)
2221                                 return rc;
2222                         break;
2223                 case PIN_CONFIG_BIAS_PULL_UP:
2224                 case PIN_CONFIG_BIAS_PULL_DOWN:
2225                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2226                 case PIN_CONFIG_BIAS_BUS_HOLD:
2227                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2228                                 return -ENOTSUPP;
2229
2230                         if (!arg)
2231                                 return -EINVAL;
2232
2233                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
2234                                 param);
2235                         if (rc)
2236                                 return rc;
2237                         break;
2238                 case PIN_CONFIG_OUTPUT:
2239                         rc = rockchip_set_mux(bank, pin - bank->pin_base,
2240                                               RK_FUNC_GPIO);
2241                         if (rc != RK_FUNC_GPIO)
2242                                 return -EINVAL;
2243
2244                         rc = gpio->direction_output(gpio, pin - bank->pin_base,
2245                                                     arg);
2246                         if (rc)
2247                                 return rc;
2248                         break;
2249                 case PIN_CONFIG_INPUT_ENABLE:
2250                         rc = rockchip_set_mux(bank, pin - bank->pin_base,
2251                                               RK_FUNC_GPIO);
2252                         if (rc != RK_FUNC_GPIO)
2253                                 return -EINVAL;
2254
2255                         rc = gpio->direction_input(gpio, pin - bank->pin_base);
2256                         if (rc)
2257                                 return rc;
2258                         break;
2259                 case PIN_CONFIG_DRIVE_STRENGTH:
2260                         /* rk3288 is the first with per-pin drive-strength */
2261                         if (!info->ctrl->drv_calc_reg)
2262                                 return -ENOTSUPP;
2263
2264                         rc = rockchip_set_drive_perpin(bank,
2265                                                 pin - bank->pin_base, arg);
2266                         if (rc < 0)
2267                                 return rc;
2268                         break;
2269                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2270                         if (!info->ctrl->schmitt_calc_reg)
2271                                 return -ENOTSUPP;
2272
2273                         rc = rockchip_set_schmitt(bank,
2274                                                   pin - bank->pin_base, arg);
2275                         if (rc < 0)
2276                                 return rc;
2277                         break;
2278                 default:
2279                         return -ENOTSUPP;
2280                         break;
2281                 }
2282         } /* for each config */
2283
2284         return 0;
2285 }
2286
2287 /* get the pin config settings for a specified pin */
2288 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2289                                                         unsigned long *config)
2290 {
2291         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2292         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2293         struct gpio_chip *gpio = &bank->gpio_chip;
2294         enum pin_config_param param = pinconf_to_config_param(*config);
2295         u16 arg;
2296         int rc;
2297
2298         switch (param) {
2299         case PIN_CONFIG_BIAS_DISABLE:
2300                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2301                         return -EINVAL;
2302
2303                 arg = 0;
2304                 break;
2305         case PIN_CONFIG_BIAS_PULL_UP:
2306         case PIN_CONFIG_BIAS_PULL_DOWN:
2307         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2308         case PIN_CONFIG_BIAS_BUS_HOLD:
2309                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2310                         return -ENOTSUPP;
2311
2312                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2313                         return -EINVAL;
2314
2315                 arg = 1;
2316                 break;
2317         case PIN_CONFIG_OUTPUT:
2318                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2319                 if (rc != RK_FUNC_GPIO)
2320                         return -EINVAL;
2321
2322                 if (!gpio || !gpio->get) {
2323                         arg = 0;
2324                         break;
2325                 }
2326
2327                 rc = gpio->get(gpio, pin - bank->pin_base);
2328                 if (rc < 0)
2329                         return rc;
2330
2331                 arg = rc ? 1 : 0;
2332                 break;
2333         case PIN_CONFIG_DRIVE_STRENGTH:
2334                 /* rk3288 is the first with per-pin drive-strength */
2335                 if (!info->ctrl->drv_calc_reg)
2336                         return -ENOTSUPP;
2337
2338                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2339                 if (rc < 0)
2340                         return rc;
2341
2342                 arg = rc;
2343                 break;
2344         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2345                 if (!info->ctrl->schmitt_calc_reg)
2346                         return -ENOTSUPP;
2347
2348                 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2349                 if (rc < 0)
2350                         return rc;
2351
2352                 arg = rc;
2353                 break;
2354         default:
2355                 return -ENOTSUPP;
2356                 break;
2357         }
2358
2359         *config = pinconf_to_config_packed(param, arg);
2360
2361         return 0;
2362 }
2363
2364 static const struct pinconf_ops rockchip_pinconf_ops = {
2365         .pin_config_get                 = rockchip_pinconf_get,
2366         .pin_config_set                 = rockchip_pinconf_set,
2367         .is_generic                     = true,
2368 };
2369
2370 static const struct of_device_id rockchip_bank_match[] = {
2371         { .compatible = "rockchip,gpio-bank" },
2372         { .compatible = "rockchip,rk3188-gpio-bank0" },
2373         {},
2374 };
2375
2376 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2377                                                 struct device_node *np)
2378 {
2379         struct device_node *child;
2380
2381         for_each_child_of_node(np, child) {
2382                 if (of_match_node(rockchip_bank_match, child))
2383                         continue;
2384
2385                 info->nfunctions++;
2386                 info->ngroups += of_get_child_count(child);
2387         }
2388 }
2389
2390 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2391                                               struct rockchip_pin_group *grp,
2392                                               struct rockchip_pinctrl *info,
2393                                               u32 index)
2394 {
2395         struct rockchip_pin_bank *bank;
2396         int size;
2397         const __be32 *list;
2398         int num;
2399         int i, j;
2400         int ret;
2401
2402         dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
2403
2404         /* Initialise group */
2405         grp->name = np->name;
2406
2407         /*
2408          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2409          * do sanity check and calculate pins number
2410          */
2411         list = of_get_property(np, "rockchip,pins", &size);
2412         /* we do not check return since it's safe node passed down */
2413         size /= sizeof(*list);
2414         if (!size || size % 4) {
2415                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2416                 return -EINVAL;
2417         }
2418
2419         grp->npins = size / 4;
2420
2421         grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2422                                                 GFP_KERNEL);
2423         grp->data = devm_kcalloc(info->dev,
2424                                         grp->npins,
2425                                         sizeof(struct rockchip_pin_config),
2426                                         GFP_KERNEL);
2427         if (!grp->pins || !grp->data)
2428                 return -ENOMEM;
2429
2430         for (i = 0, j = 0; i < size; i += 4, j++) {
2431                 const __be32 *phandle;
2432                 struct device_node *np_config;
2433
2434                 num = be32_to_cpu(*list++);
2435                 bank = bank_num_to_bank(info, num);
2436                 if (IS_ERR(bank))
2437                         return PTR_ERR(bank);
2438
2439                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2440                 grp->data[j].func = be32_to_cpu(*list++);
2441
2442                 phandle = list++;
2443                 if (!phandle)
2444                         return -EINVAL;
2445
2446                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2447                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2448                                 &grp->data[j].configs, &grp->data[j].nconfigs);
2449                 if (ret)
2450                         return ret;
2451         }
2452
2453         return 0;
2454 }
2455
2456 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2457                                                 struct rockchip_pinctrl *info,
2458                                                 u32 index)
2459 {
2460         struct device_node *child;
2461         struct rockchip_pmx_func *func;
2462         struct rockchip_pin_group *grp;
2463         int ret;
2464         static u32 grp_index;
2465         u32 i = 0;
2466
2467         dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
2468
2469         func = &info->functions[index];
2470
2471         /* Initialise function */
2472         func->name = np->name;
2473         func->ngroups = of_get_child_count(np);
2474         if (func->ngroups <= 0)
2475                 return 0;
2476
2477         func->groups = devm_kcalloc(info->dev,
2478                         func->ngroups, sizeof(char *), GFP_KERNEL);
2479         if (!func->groups)
2480                 return -ENOMEM;
2481
2482         for_each_child_of_node(np, child) {
2483                 func->groups[i] = child->name;
2484                 grp = &info->groups[grp_index++];
2485                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2486                 if (ret) {
2487                         of_node_put(child);
2488                         return ret;
2489                 }
2490         }
2491
2492         return 0;
2493 }
2494
2495 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2496                                               struct rockchip_pinctrl *info)
2497 {
2498         struct device *dev = &pdev->dev;
2499         struct device_node *np = dev->of_node;
2500         struct device_node *child;
2501         int ret;
2502         int i;
2503
2504         rockchip_pinctrl_child_count(info, np);
2505
2506         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2507         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2508
2509         info->functions = devm_kcalloc(dev,
2510                                               info->nfunctions,
2511                                               sizeof(struct rockchip_pmx_func),
2512                                               GFP_KERNEL);
2513         if (!info->functions)
2514                 return -ENOMEM;
2515
2516         info->groups = devm_kcalloc(dev,
2517                                             info->ngroups,
2518                                             sizeof(struct rockchip_pin_group),
2519                                             GFP_KERNEL);
2520         if (!info->groups)
2521                 return -ENOMEM;
2522
2523         i = 0;
2524
2525         for_each_child_of_node(np, child) {
2526                 if (of_match_node(rockchip_bank_match, child))
2527                         continue;
2528
2529                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2530                 if (ret) {
2531                         dev_err(&pdev->dev, "failed to parse function\n");
2532                         of_node_put(child);
2533                         return ret;
2534                 }
2535         }
2536
2537         return 0;
2538 }
2539
2540 static int rockchip_pinctrl_register(struct platform_device *pdev,
2541                                         struct rockchip_pinctrl *info)
2542 {
2543         struct pinctrl_desc *ctrldesc = &info->pctl;
2544         struct pinctrl_pin_desc *pindesc, *pdesc;
2545         struct rockchip_pin_bank *pin_bank;
2546         int pin, bank, ret;
2547         int k;
2548
2549         ctrldesc->name = "rockchip-pinctrl";
2550         ctrldesc->owner = THIS_MODULE;
2551         ctrldesc->pctlops = &rockchip_pctrl_ops;
2552         ctrldesc->pmxops = &rockchip_pmx_ops;
2553         ctrldesc->confops = &rockchip_pinconf_ops;
2554
2555         pindesc = devm_kcalloc(&pdev->dev,
2556                                info->ctrl->nr_pins, sizeof(*pindesc),
2557                                GFP_KERNEL);
2558         if (!pindesc)
2559                 return -ENOMEM;
2560
2561         ctrldesc->pins = pindesc;
2562         ctrldesc->npins = info->ctrl->nr_pins;
2563
2564         pdesc = pindesc;
2565         for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
2566                 pin_bank = &info->ctrl->pin_banks[bank];
2567                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2568                         pdesc->number = k;
2569                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2570                                                 pin_bank->name, pin);
2571                         pdesc++;
2572                 }
2573
2574                 INIT_LIST_HEAD(&pin_bank->deferred_pins);
2575                 mutex_init(&pin_bank->deferred_lock);
2576         }
2577
2578         ret = rockchip_pinctrl_parse_dt(pdev, info);
2579         if (ret)
2580                 return ret;
2581
2582         info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
2583         if (IS_ERR(info->pctl_dev)) {
2584                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2585                 return PTR_ERR(info->pctl_dev);
2586         }
2587
2588         return 0;
2589 }
2590
2591 static const struct of_device_id rockchip_pinctrl_dt_match[];
2592
2593 /* retrieve the soc specific data */
2594 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2595                                                 struct rockchip_pinctrl *d,
2596                                                 struct platform_device *pdev)
2597 {
2598         const struct of_device_id *match;
2599         struct device_node *node = pdev->dev.of_node;
2600         struct rockchip_pin_ctrl *ctrl;
2601         struct rockchip_pin_bank *bank;
2602         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2603
2604         match = of_match_node(rockchip_pinctrl_dt_match, node);
2605         ctrl = (struct rockchip_pin_ctrl *)match->data;
2606
2607         grf_offs = ctrl->grf_mux_offset;
2608         pmu_offs = ctrl->pmu_mux_offset;
2609         drv_pmu_offs = ctrl->pmu_drv_offset;
2610         drv_grf_offs = ctrl->grf_drv_offset;
2611         bank = ctrl->pin_banks;
2612         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2613                 int bank_pins = 0;
2614
2615                 raw_spin_lock_init(&bank->slock);
2616                 bank->drvdata = d;
2617                 bank->pin_base = ctrl->nr_pins;
2618                 ctrl->nr_pins += bank->nr_pins;
2619
2620                 /* calculate iomux and drv offsets */
2621                 for (j = 0; j < 4; j++) {
2622                         struct rockchip_iomux *iom = &bank->iomux[j];
2623                         struct rockchip_drv *drv = &bank->drv[j];
2624                         int inc;
2625
2626                         if (bank_pins >= bank->nr_pins)
2627                                 break;
2628
2629                         /* preset iomux offset value, set new start value */
2630                         if (iom->offset >= 0) {
2631                                 if (iom->type & IOMUX_SOURCE_PMU)
2632                                         pmu_offs = iom->offset;
2633                                 else
2634                                         grf_offs = iom->offset;
2635                         } else { /* set current iomux offset */
2636                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2637                                                         pmu_offs : grf_offs;
2638                         }
2639
2640                         /* preset drv offset value, set new start value */
2641                         if (drv->offset >= 0) {
2642                                 if (iom->type & IOMUX_SOURCE_PMU)
2643                                         drv_pmu_offs = drv->offset;
2644                                 else
2645                                         drv_grf_offs = drv->offset;
2646                         } else { /* set current drv offset */
2647                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2648                                                 drv_pmu_offs : drv_grf_offs;
2649                         }
2650
2651                         dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2652                                 i, j, iom->offset, drv->offset);
2653
2654                         /*
2655                          * Increase offset according to iomux width.
2656                          * 4bit iomux'es are spread over two registers.
2657                          */
2658                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
2659                                             IOMUX_WIDTH_3BIT |
2660                                             IOMUX_WIDTH_2BIT)) ? 8 : 4;
2661                         if (iom->type & IOMUX_SOURCE_PMU)
2662                                 pmu_offs += inc;
2663                         else
2664                                 grf_offs += inc;
2665
2666                         /*
2667                          * Increase offset according to drv width.
2668                          * 3bit drive-strenth'es are spread over two registers.
2669                          */
2670                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2671                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2672                                 inc = 8;
2673                         else
2674                                 inc = 4;
2675
2676                         if (iom->type & IOMUX_SOURCE_PMU)
2677                                 drv_pmu_offs += inc;
2678                         else
2679                                 drv_grf_offs += inc;
2680
2681                         bank_pins += 8;
2682                 }
2683
2684                 /* calculate the per-bank recalced_mask */
2685                 for (j = 0; j < ctrl->niomux_recalced; j++) {
2686                         int pin = 0;
2687
2688                         if (ctrl->iomux_recalced[j].num == bank->bank_num) {
2689                                 pin = ctrl->iomux_recalced[j].pin;
2690                                 bank->recalced_mask |= BIT(pin);
2691                         }
2692                 }
2693
2694                 /* calculate the per-bank route_mask */
2695                 for (j = 0; j < ctrl->niomux_routes; j++) {
2696                         int pin = 0;
2697
2698                         if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
2699                                 pin = ctrl->iomux_routes[j].pin;
2700                                 bank->route_mask |= BIT(pin);
2701                         }
2702                 }
2703         }
2704
2705         return ctrl;
2706 }
2707
2708 #define RK3288_GRF_GPIO6C_IOMUX         0x64
2709 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
2710
2711 static u32 rk3288_grf_gpio6c_iomux;
2712
2713 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2714 {
2715         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2716         int ret = pinctrl_force_sleep(info->pctl_dev);
2717
2718         if (ret)
2719                 return ret;
2720
2721         /*
2722          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2723          * the setting here, and restore it at resume.
2724          */
2725         if (info->ctrl->type == RK3288) {
2726                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2727                                   &rk3288_grf_gpio6c_iomux);
2728                 if (ret) {
2729                         pinctrl_force_default(info->pctl_dev);
2730                         return ret;
2731                 }
2732         }
2733
2734         return 0;
2735 }
2736
2737 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2738 {
2739         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2740         int ret;
2741
2742         if (info->ctrl->type == RK3288) {
2743                 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2744                                    rk3288_grf_gpio6c_iomux |
2745                                    GPIO6C6_SEL_WRITE_ENABLE);
2746                 if (ret)
2747                         return ret;
2748         }
2749
2750         return pinctrl_force_default(info->pctl_dev);
2751 }
2752
2753 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2754                          rockchip_pinctrl_resume);
2755
2756 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2757 {
2758         struct rockchip_pinctrl *info;
2759         struct device *dev = &pdev->dev;
2760         struct rockchip_pin_ctrl *ctrl;
2761         struct device_node *np = pdev->dev.of_node, *node;
2762         struct resource *res;
2763         void __iomem *base;
2764         int ret;
2765
2766         if (!dev->of_node) {
2767                 dev_err(dev, "device tree node not found\n");
2768                 return -ENODEV;
2769         }
2770
2771         info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
2772         if (!info)
2773                 return -ENOMEM;
2774
2775         info->dev = dev;
2776
2777         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2778         if (!ctrl) {
2779                 dev_err(dev, "driver data not available\n");
2780                 return -EINVAL;
2781         }
2782         info->ctrl = ctrl;
2783
2784         node = of_parse_phandle(np, "rockchip,grf", 0);
2785         if (node) {
2786                 info->regmap_base = syscon_node_to_regmap(node);
2787                 of_node_put(node);
2788                 if (IS_ERR(info->regmap_base))
2789                         return PTR_ERR(info->regmap_base);
2790         } else {
2791                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2792                 base = devm_ioremap_resource(&pdev->dev, res);
2793                 if (IS_ERR(base))
2794                         return PTR_ERR(base);
2795
2796                 rockchip_regmap_config.max_register = resource_size(res) - 4;
2797                 rockchip_regmap_config.name = "rockchip,pinctrl";
2798                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2799                                                     &rockchip_regmap_config);
2800
2801                 /* to check for the old dt-bindings */
2802                 info->reg_size = resource_size(res);
2803
2804                 /* Honor the old binding, with pull registers as 2nd resource */
2805                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2806                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2807                         base = devm_ioremap_resource(&pdev->dev, res);
2808                         if (IS_ERR(base))
2809                                 return PTR_ERR(base);
2810
2811                         rockchip_regmap_config.max_register =
2812                                                         resource_size(res) - 4;
2813                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2814                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2815                                                     base,
2816                                                     &rockchip_regmap_config);
2817                 }
2818         }
2819
2820         /* try to find the optional reference to the pmu syscon */
2821         node = of_parse_phandle(np, "rockchip,pmu", 0);
2822         if (node) {
2823                 info->regmap_pmu = syscon_node_to_regmap(node);
2824                 of_node_put(node);
2825                 if (IS_ERR(info->regmap_pmu))
2826                         return PTR_ERR(info->regmap_pmu);
2827         }
2828
2829         ret = rockchip_pinctrl_register(pdev, info);
2830         if (ret)
2831                 return ret;
2832
2833         platform_set_drvdata(pdev, info);
2834
2835         ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
2836         if (ret) {
2837                 dev_err(&pdev->dev, "failed to register gpio device\n");
2838                 return ret;
2839         }
2840
2841         return 0;
2842 }
2843
2844 static int rockchip_pinctrl_remove(struct platform_device *pdev)
2845 {
2846         struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
2847         struct rockchip_pin_bank *bank;
2848         struct rockchip_pin_deferred *cfg;
2849         int i;
2850
2851         of_platform_depopulate(&pdev->dev);
2852
2853         for (i = 0; i < info->ctrl->nr_banks; i++) {
2854                 bank = &info->ctrl->pin_banks[i];
2855
2856                 mutex_lock(&bank->deferred_lock);
2857                 while (!list_empty(&bank->deferred_pins)) {
2858                         cfg = list_first_entry(&bank->deferred_pins,
2859                                                struct rockchip_pin_deferred, head);
2860                         list_del(&cfg->head);
2861                         kfree(cfg);
2862                 }
2863                 mutex_unlock(&bank->deferred_lock);
2864         }
2865
2866         return 0;
2867 }
2868
2869 static struct rockchip_pin_bank px30_pin_banks[] = {
2870         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2871                                              IOMUX_SOURCE_PMU,
2872                                              IOMUX_SOURCE_PMU,
2873                                              IOMUX_SOURCE_PMU
2874                             ),
2875         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
2876                                              IOMUX_WIDTH_4BIT,
2877                                              IOMUX_WIDTH_4BIT,
2878                                              IOMUX_WIDTH_4BIT
2879                             ),
2880         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
2881                                              IOMUX_WIDTH_4BIT,
2882                                              IOMUX_WIDTH_4BIT,
2883                                              IOMUX_WIDTH_4BIT
2884                             ),
2885         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
2886                                              IOMUX_WIDTH_4BIT,
2887                                              IOMUX_WIDTH_4BIT,
2888                                              IOMUX_WIDTH_4BIT
2889                             ),
2890 };
2891
2892 static struct rockchip_pin_ctrl px30_pin_ctrl = {
2893                 .pin_banks              = px30_pin_banks,
2894                 .nr_banks               = ARRAY_SIZE(px30_pin_banks),
2895                 .label                  = "PX30-GPIO",
2896                 .type                   = PX30,
2897                 .grf_mux_offset         = 0x0,
2898                 .pmu_mux_offset         = 0x0,
2899                 .iomux_routes           = px30_mux_route_data,
2900                 .niomux_routes          = ARRAY_SIZE(px30_mux_route_data),
2901                 .pull_calc_reg          = px30_calc_pull_reg_and_bit,
2902                 .drv_calc_reg           = px30_calc_drv_reg_and_bit,
2903                 .schmitt_calc_reg       = px30_calc_schmitt_reg_and_bit,
2904 };
2905
2906 static struct rockchip_pin_bank rv1108_pin_banks[] = {
2907         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2908                                              IOMUX_SOURCE_PMU,
2909                                              IOMUX_SOURCE_PMU,
2910                                              IOMUX_SOURCE_PMU),
2911         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2912         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2913         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2914 };
2915
2916 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
2917         .pin_banks              = rv1108_pin_banks,
2918         .nr_banks               = ARRAY_SIZE(rv1108_pin_banks),
2919         .label                  = "RV1108-GPIO",
2920         .type                   = RV1108,
2921         .grf_mux_offset         = 0x10,
2922         .pmu_mux_offset         = 0x0,
2923         .iomux_recalced         = rv1108_mux_recalced_data,
2924         .niomux_recalced        = ARRAY_SIZE(rv1108_mux_recalced_data),
2925         .pull_calc_reg          = rv1108_calc_pull_reg_and_bit,
2926         .drv_calc_reg           = rv1108_calc_drv_reg_and_bit,
2927         .schmitt_calc_reg       = rv1108_calc_schmitt_reg_and_bit,
2928 };
2929
2930 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2931         PIN_BANK(0, 32, "gpio0"),
2932         PIN_BANK(1, 32, "gpio1"),
2933         PIN_BANK(2, 32, "gpio2"),
2934         PIN_BANK(3, 32, "gpio3"),
2935 };
2936
2937 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2938                 .pin_banks              = rk2928_pin_banks,
2939                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
2940                 .label                  = "RK2928-GPIO",
2941                 .type                   = RK2928,
2942                 .grf_mux_offset         = 0xa8,
2943                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2944 };
2945
2946 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2947         PIN_BANK(0, 32, "gpio0"),
2948         PIN_BANK(1, 32, "gpio1"),
2949         PIN_BANK(2, 32, "gpio2"),
2950 };
2951
2952 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2953                 .pin_banks              = rk3036_pin_banks,
2954                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
2955                 .label                  = "RK3036-GPIO",
2956                 .type                   = RK2928,
2957                 .grf_mux_offset         = 0xa8,
2958                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2959 };
2960
2961 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2962         PIN_BANK(0, 32, "gpio0"),
2963         PIN_BANK(1, 32, "gpio1"),
2964         PIN_BANK(2, 32, "gpio2"),
2965         PIN_BANK(3, 32, "gpio3"),
2966         PIN_BANK(4, 32, "gpio4"),
2967         PIN_BANK(6, 16, "gpio6"),
2968 };
2969
2970 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2971                 .pin_banks              = rk3066a_pin_banks,
2972                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
2973                 .label                  = "RK3066a-GPIO",
2974                 .type                   = RK2928,
2975                 .grf_mux_offset         = 0xa8,
2976                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2977 };
2978
2979 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2980         PIN_BANK(0, 32, "gpio0"),
2981         PIN_BANK(1, 32, "gpio1"),
2982         PIN_BANK(2, 32, "gpio2"),
2983         PIN_BANK(3, 32, "gpio3"),
2984 };
2985
2986 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2987                 .pin_banks      = rk3066b_pin_banks,
2988                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
2989                 .label          = "RK3066b-GPIO",
2990                 .type           = RK3066B,
2991                 .grf_mux_offset = 0x60,
2992 };
2993
2994 static struct rockchip_pin_bank rk3128_pin_banks[] = {
2995         PIN_BANK(0, 32, "gpio0"),
2996         PIN_BANK(1, 32, "gpio1"),
2997         PIN_BANK(2, 32, "gpio2"),
2998         PIN_BANK(3, 32, "gpio3"),
2999 };
3000
3001 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3002                 .pin_banks              = rk3128_pin_banks,
3003                 .nr_banks               = ARRAY_SIZE(rk3128_pin_banks),
3004                 .label                  = "RK3128-GPIO",
3005                 .type                   = RK3128,
3006                 .grf_mux_offset         = 0xa8,
3007                 .iomux_recalced         = rk3128_mux_recalced_data,
3008                 .niomux_recalced        = ARRAY_SIZE(rk3128_mux_recalced_data),
3009                 .iomux_routes           = rk3128_mux_route_data,
3010                 .niomux_routes          = ARRAY_SIZE(rk3128_mux_route_data),
3011                 .pull_calc_reg          = rk3128_calc_pull_reg_and_bit,
3012 };
3013
3014 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3015         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3016         PIN_BANK(1, 32, "gpio1"),
3017         PIN_BANK(2, 32, "gpio2"),
3018         PIN_BANK(3, 32, "gpio3"),
3019 };
3020
3021 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3022                 .pin_banks              = rk3188_pin_banks,
3023                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
3024                 .label                  = "RK3188-GPIO",
3025                 .type                   = RK3188,
3026                 .grf_mux_offset         = 0x60,
3027                 .iomux_routes           = rk3188_mux_route_data,
3028                 .niomux_routes          = ARRAY_SIZE(rk3188_mux_route_data),
3029                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
3030 };
3031
3032 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3033         PIN_BANK(0, 32, "gpio0"),
3034         PIN_BANK(1, 32, "gpio1"),
3035         PIN_BANK(2, 32, "gpio2"),
3036         PIN_BANK(3, 32, "gpio3"),
3037 };
3038
3039 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3040                 .pin_banks              = rk3228_pin_banks,
3041                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
3042                 .label                  = "RK3228-GPIO",
3043                 .type                   = RK3288,
3044                 .grf_mux_offset         = 0x0,
3045                 .iomux_routes           = rk3228_mux_route_data,
3046                 .niomux_routes          = ARRAY_SIZE(rk3228_mux_route_data),
3047                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3048                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3049 };
3050
3051 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3052         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3053                                              IOMUX_SOURCE_PMU,
3054                                              IOMUX_SOURCE_PMU,
3055                                              IOMUX_UNROUTED
3056                             ),
3057         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3058                                              IOMUX_UNROUTED,
3059                                              IOMUX_UNROUTED,
3060                                              0
3061                             ),
3062         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3063         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3064         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3065                                              IOMUX_WIDTH_4BIT,
3066                                              0,
3067                                              0
3068                             ),
3069         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3070                                              0,
3071                                              0,
3072                                              IOMUX_UNROUTED
3073                             ),
3074         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3075         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3076                                              0,
3077                                              IOMUX_WIDTH_4BIT,
3078                                              IOMUX_UNROUTED
3079                             ),
3080         PIN_BANK(8, 16, "gpio8"),
3081 };
3082
3083 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3084                 .pin_banks              = rk3288_pin_banks,
3085                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
3086                 .label                  = "RK3288-GPIO",
3087                 .type                   = RK3288,
3088                 .grf_mux_offset         = 0x0,
3089                 .pmu_mux_offset         = 0x84,
3090                 .iomux_routes           = rk3288_mux_route_data,
3091                 .niomux_routes          = ARRAY_SIZE(rk3288_mux_route_data),
3092                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
3093                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
3094 };
3095
3096 static struct rockchip_pin_bank rk3308_pin_banks[] = {
3097         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
3098                                              IOMUX_WIDTH_2BIT,
3099                                              IOMUX_WIDTH_2BIT,
3100                                              IOMUX_WIDTH_2BIT),
3101         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
3102                                              IOMUX_WIDTH_2BIT,
3103                                              IOMUX_WIDTH_2BIT,
3104                                              IOMUX_WIDTH_2BIT),
3105         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
3106                                              IOMUX_WIDTH_2BIT,
3107                                              IOMUX_WIDTH_2BIT,
3108                                              IOMUX_WIDTH_2BIT),
3109         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
3110                                              IOMUX_WIDTH_2BIT,
3111                                              IOMUX_WIDTH_2BIT,
3112                                              IOMUX_WIDTH_2BIT),
3113         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
3114                                              IOMUX_WIDTH_2BIT,
3115                                              IOMUX_WIDTH_2BIT,
3116                                              IOMUX_WIDTH_2BIT),
3117 };
3118
3119 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
3120                 .pin_banks              = rk3308_pin_banks,
3121                 .nr_banks               = ARRAY_SIZE(rk3308_pin_banks),
3122                 .label                  = "RK3308-GPIO",
3123                 .type                   = RK3308,
3124                 .grf_mux_offset         = 0x0,
3125                 .iomux_recalced         = rk3308_mux_recalced_data,
3126                 .niomux_recalced        = ARRAY_SIZE(rk3308_mux_recalced_data),
3127                 .iomux_routes           = rk3308_mux_route_data,
3128                 .niomux_routes          = ARRAY_SIZE(rk3308_mux_route_data),
3129                 .pull_calc_reg          = rk3308_calc_pull_reg_and_bit,
3130                 .drv_calc_reg           = rk3308_calc_drv_reg_and_bit,
3131                 .schmitt_calc_reg       = rk3308_calc_schmitt_reg_and_bit,
3132 };
3133
3134 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3135         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3136         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3137         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3138                              IOMUX_WIDTH_3BIT,
3139                              IOMUX_WIDTH_3BIT,
3140                              0),
3141         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3142                              IOMUX_WIDTH_3BIT,
3143                              IOMUX_WIDTH_3BIT,
3144                              0,
3145                              0),
3146 };
3147
3148 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3149                 .pin_banks              = rk3328_pin_banks,
3150                 .nr_banks               = ARRAY_SIZE(rk3328_pin_banks),
3151                 .label                  = "RK3328-GPIO",
3152                 .type                   = RK3288,
3153                 .grf_mux_offset         = 0x0,
3154                 .iomux_recalced         = rk3328_mux_recalced_data,
3155                 .niomux_recalced        = ARRAY_SIZE(rk3328_mux_recalced_data),
3156                 .iomux_routes           = rk3328_mux_route_data,
3157                 .niomux_routes          = ARRAY_SIZE(rk3328_mux_route_data),
3158                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3159                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3160                 .schmitt_calc_reg       = rk3328_calc_schmitt_reg_and_bit,
3161 };
3162
3163 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3164         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3165                                              IOMUX_SOURCE_PMU,
3166                                              IOMUX_SOURCE_PMU,
3167                                              IOMUX_SOURCE_PMU
3168                             ),
3169         PIN_BANK(1, 32, "gpio1"),
3170         PIN_BANK(2, 32, "gpio2"),
3171         PIN_BANK(3, 32, "gpio3"),
3172 };
3173
3174 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3175                 .pin_banks              = rk3368_pin_banks,
3176                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
3177                 .label                  = "RK3368-GPIO",
3178                 .type                   = RK3368,
3179                 .grf_mux_offset         = 0x0,
3180                 .pmu_mux_offset         = 0x0,
3181                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
3182                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
3183 };
3184
3185 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3186         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3187                                                          IOMUX_SOURCE_PMU,
3188                                                          IOMUX_SOURCE_PMU,
3189                                                          IOMUX_SOURCE_PMU,
3190                                                          IOMUX_SOURCE_PMU,
3191                                                          DRV_TYPE_IO_1V8_ONLY,
3192                                                          DRV_TYPE_IO_1V8_ONLY,
3193                                                          DRV_TYPE_IO_DEFAULT,
3194                                                          DRV_TYPE_IO_DEFAULT,
3195                                                          0x80,
3196                                                          0x88,
3197                                                          -1,
3198                                                          -1,
3199                                                          PULL_TYPE_IO_1V8_ONLY,
3200                                                          PULL_TYPE_IO_1V8_ONLY,
3201                                                          PULL_TYPE_IO_DEFAULT,
3202                                                          PULL_TYPE_IO_DEFAULT
3203                                                         ),
3204         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3205                                         IOMUX_SOURCE_PMU,
3206                                         IOMUX_SOURCE_PMU,
3207                                         IOMUX_SOURCE_PMU,
3208                                         DRV_TYPE_IO_1V8_OR_3V0,
3209                                         DRV_TYPE_IO_1V8_OR_3V0,
3210                                         DRV_TYPE_IO_1V8_OR_3V0,
3211                                         DRV_TYPE_IO_1V8_OR_3V0,
3212                                         0xa0,
3213                                         0xa8,
3214                                         0xb0,
3215                                         0xb8
3216                                         ),
3217         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3218                                       DRV_TYPE_IO_1V8_OR_3V0,
3219                                       DRV_TYPE_IO_1V8_ONLY,
3220                                       DRV_TYPE_IO_1V8_ONLY,
3221                                       PULL_TYPE_IO_DEFAULT,
3222                                       PULL_TYPE_IO_DEFAULT,
3223                                       PULL_TYPE_IO_1V8_ONLY,
3224                                       PULL_TYPE_IO_1V8_ONLY
3225                                       ),
3226         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3227                            DRV_TYPE_IO_3V3_ONLY,
3228                            DRV_TYPE_IO_3V3_ONLY,
3229                            DRV_TYPE_IO_1V8_OR_3V0
3230                            ),
3231         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3232                            DRV_TYPE_IO_1V8_3V0_AUTO,
3233                            DRV_TYPE_IO_1V8_OR_3V0,
3234                            DRV_TYPE_IO_1V8_OR_3V0
3235                            ),
3236 };
3237
3238 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3239                 .pin_banks              = rk3399_pin_banks,
3240                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
3241                 .label                  = "RK3399-GPIO",
3242                 .type                   = RK3399,
3243                 .grf_mux_offset         = 0xe000,
3244                 .pmu_mux_offset         = 0x0,
3245                 .grf_drv_offset         = 0xe100,
3246                 .pmu_drv_offset         = 0x80,
3247                 .iomux_routes           = rk3399_mux_route_data,
3248                 .niomux_routes          = ARRAY_SIZE(rk3399_mux_route_data),
3249                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
3250                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
3251 };
3252
3253 static struct rockchip_pin_bank rk3568_pin_banks[] = {
3254         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3255                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3256                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3257                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
3258         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3259                                              IOMUX_WIDTH_4BIT,
3260                                              IOMUX_WIDTH_4BIT,
3261                                              IOMUX_WIDTH_4BIT),
3262         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3263                                              IOMUX_WIDTH_4BIT,
3264                                              IOMUX_WIDTH_4BIT,
3265                                              IOMUX_WIDTH_4BIT),
3266         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3267                                              IOMUX_WIDTH_4BIT,
3268                                              IOMUX_WIDTH_4BIT,
3269                                              IOMUX_WIDTH_4BIT),
3270         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3271                                              IOMUX_WIDTH_4BIT,
3272                                              IOMUX_WIDTH_4BIT,
3273                                              IOMUX_WIDTH_4BIT),
3274 };
3275
3276 static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
3277         .pin_banks              = rk3568_pin_banks,
3278         .nr_banks               = ARRAY_SIZE(rk3568_pin_banks),
3279         .label                  = "RK3568-GPIO",
3280         .type                   = RK3568,
3281         .grf_mux_offset         = 0x0,
3282         .pmu_mux_offset         = 0x0,
3283         .grf_drv_offset         = 0x0200,
3284         .pmu_drv_offset         = 0x0070,
3285         .iomux_routes           = rk3568_mux_route_data,
3286         .niomux_routes          = ARRAY_SIZE(rk3568_mux_route_data),
3287         .pull_calc_reg          = rk3568_calc_pull_reg_and_bit,
3288         .drv_calc_reg           = rk3568_calc_drv_reg_and_bit,
3289         .schmitt_calc_reg       = rk3568_calc_schmitt_reg_and_bit,
3290 };
3291
3292 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3293         { .compatible = "rockchip,px30-pinctrl",
3294                 .data = &px30_pin_ctrl },
3295         { .compatible = "rockchip,rv1108-pinctrl",
3296                 .data = &rv1108_pin_ctrl },
3297         { .compatible = "rockchip,rk2928-pinctrl",
3298                 .data = &rk2928_pin_ctrl },
3299         { .compatible = "rockchip,rk3036-pinctrl",
3300                 .data = &rk3036_pin_ctrl },
3301         { .compatible = "rockchip,rk3066a-pinctrl",
3302                 .data = &rk3066a_pin_ctrl },
3303         { .compatible = "rockchip,rk3066b-pinctrl",
3304                 .data = &rk3066b_pin_ctrl },
3305         { .compatible = "rockchip,rk3128-pinctrl",
3306                 .data = (void *)&rk3128_pin_ctrl },
3307         { .compatible = "rockchip,rk3188-pinctrl",
3308                 .data = &rk3188_pin_ctrl },
3309         { .compatible = "rockchip,rk3228-pinctrl",
3310                 .data = &rk3228_pin_ctrl },
3311         { .compatible = "rockchip,rk3288-pinctrl",
3312                 .data = &rk3288_pin_ctrl },
3313         { .compatible = "rockchip,rk3308-pinctrl",
3314                 .data = &rk3308_pin_ctrl },
3315         { .compatible = "rockchip,rk3328-pinctrl",
3316                 .data = &rk3328_pin_ctrl },
3317         { .compatible = "rockchip,rk3368-pinctrl",
3318                 .data = &rk3368_pin_ctrl },
3319         { .compatible = "rockchip,rk3399-pinctrl",
3320                 .data = &rk3399_pin_ctrl },
3321         { .compatible = "rockchip,rk3568-pinctrl",
3322                 .data = &rk3568_pin_ctrl },
3323         {},
3324 };
3325
3326 static struct platform_driver rockchip_pinctrl_driver = {
3327         .probe          = rockchip_pinctrl_probe,
3328         .remove         = rockchip_pinctrl_remove,
3329         .driver = {
3330                 .name   = "rockchip-pinctrl",
3331                 .pm = &rockchip_pinctrl_dev_pm_ops,
3332                 .of_match_table = rockchip_pinctrl_dt_match,
3333         },
3334 };
3335
3336 static int __init rockchip_pinctrl_drv_register(void)
3337 {
3338         return platform_driver_register(&rockchip_pinctrl_driver);
3339 }
3340 postcore_initcall(rockchip_pinctrl_drv_register);
3341
3342 static void __exit rockchip_pinctrl_drv_unregister(void)
3343 {
3344         platform_driver_unregister(&rockchip_pinctrl_driver);
3345 }
3346 module_exit(rockchip_pinctrl_drv_unregister);
3347
3348 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
3349 MODULE_LICENSE("GPL");
3350 MODULE_ALIAS("platform:pinctrl-rockchip");
3351 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);