drivers/pinctrl/pinctrl-oxnas.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Oxford Semiconductor OXNAS SoC Family pinctrl driver
   4  *
   5  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
   6  *
   7  * Based on pinctrl-pic32.c
   8  * Joshua Henderson, <joshua.henderson@microchip.com>
   9  * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
  10  */
  11 #include <linux/gpio/driver.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/irq.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/pinctrl/pinconf.h>
  18 #include <linux/pinctrl/pinconf-generic.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23 #include <linux/regmap.h>
  24 #include <linux/mfd/syscon.h>
  25
  26 #include "pinctrl-utils.h"
  27
  28 #define PINS_PER_BANK           32
  29
  30 #define GPIO_BANK_START(bank)           ((bank) * PINS_PER_BANK)
  31
  32 /* OX810 Regmap Offsets */
  33 #define PINMUX_810_PRIMARY_SEL0         0x0c
  34 #define PINMUX_810_SECONDARY_SEL0       0x14
  35 #define PINMUX_810_TERTIARY_SEL0        0x8c
  36 #define PINMUX_810_PRIMARY_SEL1         0x10
  37 #define PINMUX_810_SECONDARY_SEL1       0x18
  38 #define PINMUX_810_TERTIARY_SEL1        0x90
  39 #define PINMUX_810_PULLUP_CTRL0         0xac
  40 #define PINMUX_810_PULLUP_CTRL1         0xb0
  41
  42 /* OX820 Regmap Offsets */
  43 #define PINMUX_820_BANK_OFFSET          0x100000
  44 #define PINMUX_820_SECONDARY_SEL        0x14
  45 #define PINMUX_820_TERTIARY_SEL         0x8c
  46 #define PINMUX_820_QUATERNARY_SEL       0x94
  47 #define PINMUX_820_DEBUG_SEL            0x9c
  48 #define PINMUX_820_ALTERNATIVE_SEL      0xa4
  49 #define PINMUX_820_PULLUP_CTRL          0xac
  50
  51 /* GPIO Registers */
  52 #define INPUT_VALUE     0x00
  53 #define OUTPUT_EN       0x04
  54 #define IRQ_PENDING     0x0c
  55 #define OUTPUT_SET      0x14
  56 #define OUTPUT_CLEAR    0x18
  57 #define OUTPUT_EN_SET   0x1c
  58 #define OUTPUT_EN_CLEAR 0x20
  59 #define RE_IRQ_ENABLE   0x28
  60 #define FE_IRQ_ENABLE   0x2c
  61
  62 struct oxnas_function {
  63         const char *name;
  64         const char * const *groups;
  65         unsigned int ngroups;
  66 };
  67
  68 struct oxnas_pin_group {
  69         const char *name;
  70         unsigned int pin;
  71         unsigned int bank;
  72         struct oxnas_desc_function *functions;
  73 };
  74
  75 struct oxnas_desc_function {
  76         const char *name;
  77         unsigned int fct;
  78 };
  79
  80 struct oxnas_gpio_bank {
  81         void __iomem *reg_base;
  82         struct gpio_chip gpio_chip;
  83         struct irq_chip irq_chip;
  84         unsigned int id;
  85 };
  86
  87 struct oxnas_pinctrl {
  88         struct regmap *regmap;
  89         struct device *dev;
  90         struct pinctrl_dev *pctldev;
  91         const struct oxnas_function *functions;
  92         unsigned int nfunctions;
  93         const struct oxnas_pin_group *groups;
  94         unsigned int ngroups;
  95         struct oxnas_gpio_bank *gpio_banks;
  96         unsigned int nbanks;
  97 };
  98
  99 struct oxnas_pinctrl_data {
 100         struct pinctrl_desc *desc;
 101         struct oxnas_pinctrl *pctl;
 102 };
 103
 104 static const struct pinctrl_pin_desc oxnas_ox810se_pins[] = {
 105         PINCTRL_PIN(0, "gpio0"),
 106         PINCTRL_PIN(1, "gpio1"),
 107         PINCTRL_PIN(2, "gpio2"),
 108         PINCTRL_PIN(3, "gpio3"),
 109         PINCTRL_PIN(4, "gpio4"),
 110         PINCTRL_PIN(5, "gpio5"),
 111         PINCTRL_PIN(6, "gpio6"),
 112         PINCTRL_PIN(7, "gpio7"),
 113         PINCTRL_PIN(8, "gpio8"),
 114         PINCTRL_PIN(9, "gpio9"),
 115         PINCTRL_PIN(10, "gpio10"),
 116         PINCTRL_PIN(11, "gpio11"),
 117         PINCTRL_PIN(12, "gpio12"),
 118         PINCTRL_PIN(13, "gpio13"),
 119         PINCTRL_PIN(14, "gpio14"),
 120         PINCTRL_PIN(15, "gpio15"),
 121         PINCTRL_PIN(16, "gpio16"),
 122         PINCTRL_PIN(17, "gpio17"),
 123         PINCTRL_PIN(18, "gpio18"),
 124         PINCTRL_PIN(19, "gpio19"),
 125         PINCTRL_PIN(20, "gpio20"),
 126         PINCTRL_PIN(21, "gpio21"),
 127         PINCTRL_PIN(22, "gpio22"),
 128         PINCTRL_PIN(23, "gpio23"),
 129         PINCTRL_PIN(24, "gpio24"),
 130         PINCTRL_PIN(25, "gpio25"),
 131         PINCTRL_PIN(26, "gpio26"),
 132         PINCTRL_PIN(27, "gpio27"),
 133         PINCTRL_PIN(28, "gpio28"),
 134         PINCTRL_PIN(29, "gpio29"),
 135         PINCTRL_PIN(30, "gpio30"),
 136         PINCTRL_PIN(31, "gpio31"),
 137         PINCTRL_PIN(32, "gpio32"),
 138         PINCTRL_PIN(33, "gpio33"),
 139         PINCTRL_PIN(34, "gpio34"),
 140 };
 141
 142 static const struct pinctrl_pin_desc oxnas_ox820_pins[] = {
 143         PINCTRL_PIN(0, "gpio0"),
 144         PINCTRL_PIN(1, "gpio1"),
 145         PINCTRL_PIN(2, "gpio2"),
 146         PINCTRL_PIN(3, "gpio3"),
 147         PINCTRL_PIN(4, "gpio4"),
 148         PINCTRL_PIN(5, "gpio5"),
 149         PINCTRL_PIN(6, "gpio6"),
 150         PINCTRL_PIN(7, "gpio7"),
 151         PINCTRL_PIN(8, "gpio8"),
 152         PINCTRL_PIN(9, "gpio9"),
 153         PINCTRL_PIN(10, "gpio10"),
 154         PINCTRL_PIN(11, "gpio11"),
 155         PINCTRL_PIN(12, "gpio12"),
 156         PINCTRL_PIN(13, "gpio13"),
 157         PINCTRL_PIN(14, "gpio14"),
 158         PINCTRL_PIN(15, "gpio15"),
 159         PINCTRL_PIN(16, "gpio16"),
 160         PINCTRL_PIN(17, "gpio17"),
 161         PINCTRL_PIN(18, "gpio18"),
 162         PINCTRL_PIN(19, "gpio19"),
 163         PINCTRL_PIN(20, "gpio20"),
 164         PINCTRL_PIN(21, "gpio21"),
 165         PINCTRL_PIN(22, "gpio22"),
 166         PINCTRL_PIN(23, "gpio23"),
 167         PINCTRL_PIN(24, "gpio24"),
 168         PINCTRL_PIN(25, "gpio25"),
 169         PINCTRL_PIN(26, "gpio26"),
 170         PINCTRL_PIN(27, "gpio27"),
 171         PINCTRL_PIN(28, "gpio28"),
 172         PINCTRL_PIN(29, "gpio29"),
 173         PINCTRL_PIN(30, "gpio30"),
 174         PINCTRL_PIN(31, "gpio31"),
 175         PINCTRL_PIN(32, "gpio32"),
 176         PINCTRL_PIN(33, "gpio33"),
 177         PINCTRL_PIN(34, "gpio34"),
 178         PINCTRL_PIN(35, "gpio35"),
 179         PINCTRL_PIN(36, "gpio36"),
 180         PINCTRL_PIN(37, "gpio37"),
 181         PINCTRL_PIN(38, "gpio38"),
 182         PINCTRL_PIN(39, "gpio39"),
 183         PINCTRL_PIN(40, "gpio40"),
 184         PINCTRL_PIN(41, "gpio41"),
 185         PINCTRL_PIN(42, "gpio42"),
 186         PINCTRL_PIN(43, "gpio43"),
 187         PINCTRL_PIN(44, "gpio44"),
 188         PINCTRL_PIN(45, "gpio45"),
 189         PINCTRL_PIN(46, "gpio46"),
 190         PINCTRL_PIN(47, "gpio47"),
 191         PINCTRL_PIN(48, "gpio48"),
 192         PINCTRL_PIN(49, "gpio49"),
 193 };
 194
 195 static const char * const oxnas_ox810se_fct0_group[] = {
 196         "gpio0",  "gpio1",  "gpio2",  "gpio3",
 197         "gpio4",  "gpio5",  "gpio6",  "gpio7",
 198         "gpio8",  "gpio9",  "gpio10", "gpio11",
 199         "gpio12", "gpio13", "gpio14", "gpio15",
 200         "gpio16", "gpio17", "gpio18", "gpio19",
 201         "gpio20", "gpio21", "gpio22", "gpio23",
 202         "gpio24", "gpio25", "gpio26", "gpio27",
 203         "gpio28", "gpio29", "gpio30", "gpio31",
 204         "gpio32", "gpio33", "gpio34"
 205 };
 206
 207 static const char * const oxnas_ox810se_fct3_group[] = {
 208         "gpio0",  "gpio1",  "gpio2",  "gpio3",
 209         "gpio4",  "gpio5",  "gpio6",  "gpio7",
 210         "gpio8",  "gpio9",
 211         "gpio20",
 212         "gpio22", "gpio23", "gpio24", "gpio25",
 213         "gpio26", "gpio27", "gpio28", "gpio29",
 214         "gpio30", "gpio31", "gpio32", "gpio33",
 215         "gpio34"
 216 };
 217
 218 static const char * const oxnas_ox820_fct0_group[] = {
 219         "gpio0",  "gpio1",  "gpio2",  "gpio3",
 220         "gpio4",  "gpio5",  "gpio6",  "gpio7",
 221         "gpio8",  "gpio9",  "gpio10", "gpio11",
 222         "gpio12", "gpio13", "gpio14", "gpio15",
 223         "gpio16", "gpio17", "gpio18", "gpio19",
 224         "gpio20", "gpio21", "gpio22", "gpio23",
 225         "gpio24", "gpio25", "gpio26", "gpio27",
 226         "gpio28", "gpio29", "gpio30", "gpio31",
 227         "gpio32", "gpio33", "gpio34", "gpio35",
 228         "gpio36", "gpio37", "gpio38", "gpio39",
 229         "gpio40", "gpio41", "gpio42", "gpio43",
 230         "gpio44", "gpio45", "gpio46", "gpio47",
 231         "gpio48", "gpio49"
 232 };
 233
 234 static const char * const oxnas_ox820_fct1_group[] = {
 235         "gpio3", "gpio4",
 236         "gpio12", "gpio13", "gpio14", "gpio15",
 237         "gpio16", "gpio17", "gpio18", "gpio19",
 238         "gpio20", "gpio21", "gpio22", "gpio23",
 239         "gpio24"
 240 };
 241
 242 static const char * const oxnas_ox820_fct4_group[] = {
 243         "gpio5", "gpio6", "gpio7", "gpio8",
 244         "gpio24", "gpio25", "gpio26", "gpio27",
 245         "gpio40", "gpio41", "gpio42", "gpio43"
 246 };
 247
 248 static const char * const oxnas_ox820_fct5_group[] = {
 249         "gpio28", "gpio29", "gpio30", "gpio31"
 250 };
 251
 252 #define FUNCTION(_name, _gr)                                    \
 253         {                                                       \
 254                 .name = #_name,                                 \
 255                 .groups = oxnas_##_gr##_group,                  \
 256                 .ngroups = ARRAY_SIZE(oxnas_##_gr##_group),     \
 257         }
 258
 259 static const struct oxnas_function oxnas_ox810se_functions[] = {
 260         FUNCTION(gpio, ox810se_fct0),
 261         FUNCTION(fct3, ox810se_fct3),
 262 };
 263
 264 static const struct oxnas_function oxnas_ox820_functions[] = {
 265         FUNCTION(gpio, ox820_fct0),
 266         FUNCTION(fct1, ox820_fct1),
 267         FUNCTION(fct4, ox820_fct4),
 268         FUNCTION(fct5, ox820_fct5),
 269 };
 270
 271 #define OXNAS_PINCTRL_GROUP(_pin, _name, ...)                           \
 272         {                                                               \
 273                 .name = #_name,                                         \
 274                 .pin = _pin,                                            \
 275                 .bank = _pin / PINS_PER_BANK,                           \
 276                 .functions = (struct oxnas_desc_function[]){            \
 277                         __VA_ARGS__, { } },                             \
 278         }
 279
 280 #define OXNAS_PINCTRL_FUNCTION(_name, _fct)             \
 281         {                                               \
 282                 .name = #_name,                         \
 283                 .fct = _fct,                            \
 284         }
 285
 286 static const struct oxnas_pin_group oxnas_ox810se_groups[] = {
 287         OXNAS_PINCTRL_GROUP(0, gpio0,
 288                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 289                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 290         OXNAS_PINCTRL_GROUP(1, gpio1,
 291                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 292                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 293         OXNAS_PINCTRL_GROUP(2, gpio2,
 294                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 295                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 296         OXNAS_PINCTRL_GROUP(3, gpio3,
 297                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 298                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 299         OXNAS_PINCTRL_GROUP(4, gpio4,
 300                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 301                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 302         OXNAS_PINCTRL_GROUP(5, gpio5,
 303                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 304                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 305         OXNAS_PINCTRL_GROUP(6, gpio6,
 306                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 307                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 308         OXNAS_PINCTRL_GROUP(7, gpio7,
 309                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 310                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 311         OXNAS_PINCTRL_GROUP(8, gpio8,
 312                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 313                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 314         OXNAS_PINCTRL_GROUP(9, gpio9,
 315                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 316                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 317         OXNAS_PINCTRL_GROUP(10, gpio10,
 318                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 319         OXNAS_PINCTRL_GROUP(11, gpio11,
 320                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 321         OXNAS_PINCTRL_GROUP(12, gpio12,
 322                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 323         OXNAS_PINCTRL_GROUP(13, gpio13,
 324                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 325         OXNAS_PINCTRL_GROUP(14, gpio14,
 326                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 327         OXNAS_PINCTRL_GROUP(15, gpio15,
 328                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 329         OXNAS_PINCTRL_GROUP(16, gpio16,
 330                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 331         OXNAS_PINCTRL_GROUP(17, gpio17,
 332                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 333         OXNAS_PINCTRL_GROUP(18, gpio18,
 334                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 335         OXNAS_PINCTRL_GROUP(19, gpio19,
 336                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 337         OXNAS_PINCTRL_GROUP(20, gpio20,
 338                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 339                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 340         OXNAS_PINCTRL_GROUP(21, gpio21,
 341                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 342         OXNAS_PINCTRL_GROUP(22, gpio22,
 343                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 344                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 345         OXNAS_PINCTRL_GROUP(23, gpio23,
 346                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 347                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 348         OXNAS_PINCTRL_GROUP(24, gpio24,
 349                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 350                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 351         OXNAS_PINCTRL_GROUP(25, gpio25,
 352                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 353                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 354         OXNAS_PINCTRL_GROUP(26, gpio26,
 355                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 356                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 357         OXNAS_PINCTRL_GROUP(27, gpio27,
 358                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 359                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 360         OXNAS_PINCTRL_GROUP(28, gpio28,
 361                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 362                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 363         OXNAS_PINCTRL_GROUP(29, gpio29,
 364                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 365                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 366         OXNAS_PINCTRL_GROUP(30, gpio30,
 367                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 368                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 369         OXNAS_PINCTRL_GROUP(31, gpio31,
 370                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 371                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 372         OXNAS_PINCTRL_GROUP(32, gpio32,
 373                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 374                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 375         OXNAS_PINCTRL_GROUP(33, gpio33,
 376                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 377                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 378         OXNAS_PINCTRL_GROUP(34, gpio34,
 379                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 380                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 381 };
 382
 383 static const struct oxnas_pin_group oxnas_ox820_groups[] = {
 384         OXNAS_PINCTRL_GROUP(0, gpio0,
 385                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 386         OXNAS_PINCTRL_GROUP(1, gpio1,
 387                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 388         OXNAS_PINCTRL_GROUP(2, gpio2,
 389                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 390         OXNAS_PINCTRL_GROUP(3, gpio3,
 391                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 392                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 393         OXNAS_PINCTRL_GROUP(4, gpio4,
 394                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 395                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 396         OXNAS_PINCTRL_GROUP(5, gpio5,
 397                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 398                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 399         OXNAS_PINCTRL_GROUP(6, gpio6,
 400                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 401                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 402         OXNAS_PINCTRL_GROUP(7, gpio7,
 403                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 404                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 405         OXNAS_PINCTRL_GROUP(8, gpio8,
 406                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 407                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 408         OXNAS_PINCTRL_GROUP(9, gpio9,
 409                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 410         OXNAS_PINCTRL_GROUP(10, gpio10,
 411                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 412         OXNAS_PINCTRL_GROUP(11, gpio11,
 413                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 414         OXNAS_PINCTRL_GROUP(12, gpio12,
 415                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 416                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 417         OXNAS_PINCTRL_GROUP(13, gpio13,
 418                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 419                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 420         OXNAS_PINCTRL_GROUP(14, gpio14,
 421                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 422                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 423         OXNAS_PINCTRL_GROUP(15, gpio15,
 424                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 425                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 426         OXNAS_PINCTRL_GROUP(16, gpio16,
 427                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 428                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 429         OXNAS_PINCTRL_GROUP(17, gpio17,
 430                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 431                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 432         OXNAS_PINCTRL_GROUP(18, gpio18,
 433                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 434                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 435         OXNAS_PINCTRL_GROUP(19, gpio19,
 436                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 437                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 438         OXNAS_PINCTRL_GROUP(20, gpio20,
 439                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 440                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 441         OXNAS_PINCTRL_GROUP(21, gpio21,
 442                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 443                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 444         OXNAS_PINCTRL_GROUP(22, gpio22,
 445                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 446                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 447         OXNAS_PINCTRL_GROUP(23, gpio23,
 448                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 449                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 450         OXNAS_PINCTRL_GROUP(24, gpio24,
 451                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 452                         OXNAS_PINCTRL_FUNCTION(fct1, 1),
 453                         OXNAS_PINCTRL_FUNCTION(fct4, 5)),
 454         OXNAS_PINCTRL_GROUP(25, gpio25,
 455                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 456                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 457         OXNAS_PINCTRL_GROUP(26, gpio26,
 458                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 459                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 460         OXNAS_PINCTRL_GROUP(27, gpio27,
 461                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 462                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 463         OXNAS_PINCTRL_GROUP(28, gpio28,
 464                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 465                         OXNAS_PINCTRL_FUNCTION(fct5, 5)),
 466         OXNAS_PINCTRL_GROUP(29, gpio29,
 467                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 468                         OXNAS_PINCTRL_FUNCTION(fct5, 5)),
 469         OXNAS_PINCTRL_GROUP(30, gpio30,
 470                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 471                         OXNAS_PINCTRL_FUNCTION(fct5, 5)),
 472         OXNAS_PINCTRL_GROUP(31, gpio31,
 473                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 474                         OXNAS_PINCTRL_FUNCTION(fct5, 5)),
 475         OXNAS_PINCTRL_GROUP(32, gpio32,
 476                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 477         OXNAS_PINCTRL_GROUP(33, gpio33,
 478                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 479         OXNAS_PINCTRL_GROUP(34, gpio34,
 480                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 481         OXNAS_PINCTRL_GROUP(35, gpio35,
 482                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 483         OXNAS_PINCTRL_GROUP(36, gpio36,
 484                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 485         OXNAS_PINCTRL_GROUP(37, gpio37,
 486                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 487         OXNAS_PINCTRL_GROUP(38, gpio38,
 488                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 489         OXNAS_PINCTRL_GROUP(39, gpio39,
 490                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 491         OXNAS_PINCTRL_GROUP(40, gpio40,
 492                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 493                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 494         OXNAS_PINCTRL_GROUP(41, gpio41,
 495                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 496                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 497         OXNAS_PINCTRL_GROUP(42, gpio42,
 498                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 499                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 500         OXNAS_PINCTRL_GROUP(43, gpio43,
 501                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 502                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 503         OXNAS_PINCTRL_GROUP(44, gpio44,
 504                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 505         OXNAS_PINCTRL_GROUP(45, gpio45,
 506                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 507         OXNAS_PINCTRL_GROUP(46, gpio46,
 508                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 509         OXNAS_PINCTRL_GROUP(47, gpio47,
 510                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 511         OXNAS_PINCTRL_GROUP(48, gpio48,
 512                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 513         OXNAS_PINCTRL_GROUP(49, gpio49,
 514                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 515 };
 516
 517 static inline struct oxnas_gpio_bank *pctl_to_bank(struct oxnas_pinctrl *pctl,
 518                                                    unsigned int pin)
 519 {
 520         return &pctl->gpio_banks[pin / PINS_PER_BANK];
 521 }
 522
 523 static int oxnas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 524 {
 525         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 526
 527         return pctl->ngroups;
 528 }
 529
 530 static const char *oxnas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 531                                                 unsigned int group)
 532 {
 533         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 534
 535         return pctl->groups[group].name;
 536 }
 537
 538 static int oxnas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 539                                         unsigned int group,
 540                                         const unsigned int **pins,
 541                                         unsigned int *num_pins)
 542 {
 543         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 544
 545         *pins = &pctl->groups[group].pin;
 546         *num_pins = 1;
 547
 548         return 0;
 549 }
 550
 551 static const struct pinctrl_ops oxnas_pinctrl_ops = {
 552         .get_groups_count = oxnas_pinctrl_get_groups_count,
 553         .get_group_name = oxnas_pinctrl_get_group_name,
 554         .get_group_pins = oxnas_pinctrl_get_group_pins,
 555         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 556         .dt_free_map = pinctrl_utils_free_map,
 557 };
 558
 559 static int oxnas_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
 560 {
 561         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 562
 563         return pctl->nfunctions;
 564 }
 565
 566 static const char *
 567 oxnas_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned int func)
 568 {
 569         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 570
 571         return pctl->functions[func].name;
 572 }
 573
 574 static int oxnas_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
 575                                             unsigned int func,
 576                                             const char * const **groups,
 577                                             unsigned int * const num_groups)
 578 {
 579         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 580
 581         *groups = pctl->functions[func].groups;
 582         *num_groups = pctl->functions[func].ngroups;
 583
 584         return 0;
 585 }
 586
 587 static int oxnas_ox810se_pinmux_enable(struct pinctrl_dev *pctldev,
 588                                        unsigned int func, unsigned int group)
 589 {
 590         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 591         const struct oxnas_pin_group *pg = &pctl->groups[group];
 592         const struct oxnas_function *pf = &pctl->functions[func];
 593         const char *fname = pf->name;
 594         struct oxnas_desc_function *functions = pg->functions;
 595         u32 mask = BIT(pg->pin);
 596
 597         while (functions->name) {
 598                 if (!strcmp(functions->name, fname)) {
 599                         dev_dbg(pctl->dev,
 600                                 "setting function %s bank %d pin %d fct %d mask %x\n",
 601                                 fname, pg->bank, pg->pin,
 602                                 functions->fct, mask);
 603
 604                         regmap_write_bits(pctl->regmap,
 605                                           (pg->bank ?
 606                                                 PINMUX_810_PRIMARY_SEL1 :
 607                                                 PINMUX_810_PRIMARY_SEL0),
 608                                           mask,
 609                                           (functions->fct == 1 ?
 610                                                 mask : 0));
 611                         regmap_write_bits(pctl->regmap,
 612                                           (pg->bank ?
 613                                                 PINMUX_810_SECONDARY_SEL1 :
 614                                                 PINMUX_810_SECONDARY_SEL0),
 615                                           mask,
 616                                           (functions->fct == 2 ?
 617                                                 mask : 0));
 618                         regmap_write_bits(pctl->regmap,
 619                                           (pg->bank ?
 620                                                 PINMUX_810_TERTIARY_SEL1 :
 621                                                 PINMUX_810_TERTIARY_SEL0),
 622                                           mask,
 623                                           (functions->fct == 3 ?
 624                                                 mask : 0));
 625
 626                         return 0;
 627                 }
 628
 629                 functions++;
 630         }
 631
 632         dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
 633
 634         return -EINVAL;
 635 }
 636
 637 static int oxnas_ox820_pinmux_enable(struct pinctrl_dev *pctldev,
 638                                      unsigned int func, unsigned int group)
 639 {
 640         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 641         const struct oxnas_pin_group *pg = &pctl->groups[group];
 642         const struct oxnas_function *pf = &pctl->functions[func];
 643         const char *fname = pf->name;
 644         struct oxnas_desc_function *functions = pg->functions;
 645         unsigned int offset = (pg->bank ? PINMUX_820_BANK_OFFSET : 0);
 646         u32 mask = BIT(pg->pin);
 647
 648         while (functions->name) {
 649                 if (!strcmp(functions->name, fname)) {
 650                         dev_dbg(pctl->dev,
 651                                 "setting function %s bank %d pin %d fct %d mask %x\n",
 652                                 fname, pg->bank, pg->pin,
 653                                 functions->fct, mask);
 654
 655                         regmap_write_bits(pctl->regmap,
 656                                           offset + PINMUX_820_SECONDARY_SEL,
 657                                           mask,
 658                                           (functions->fct == 1 ?
 659                                                 mask : 0));
 660                         regmap_write_bits(pctl->regmap,
 661                                           offset + PINMUX_820_TERTIARY_SEL,
 662                                           mask,
 663                                           (functions->fct == 2 ?
 664                                                 mask : 0));
 665                         regmap_write_bits(pctl->regmap,
 666                                           offset + PINMUX_820_QUATERNARY_SEL,
 667                                           mask,
 668                                           (functions->fct == 3 ?
 669                                                 mask : 0));
 670                         regmap_write_bits(pctl->regmap,
 671                                           offset + PINMUX_820_DEBUG_SEL,
 672                                           mask,
 673                                           (functions->fct == 4 ?
 674                                                 mask : 0));
 675                         regmap_write_bits(pctl->regmap,
 676                                           offset + PINMUX_820_ALTERNATIVE_SEL,
 677                                           mask,
 678                                           (functions->fct == 5 ?
 679                                                 mask : 0));
 680
 681                         return 0;
 682                 }
 683
 684                 functions++;
 685         }
 686
 687         dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
 688
 689         return -EINVAL;
 690 }
 691
 692 static int oxnas_ox810se_gpio_request_enable(struct pinctrl_dev *pctldev,
 693                                              struct pinctrl_gpio_range *range,
 694                                              unsigned int offset)
 695 {
 696         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 697         struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
 698         u32 mask = BIT(offset - bank->gpio_chip.base);
 699
 700         dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n",
 701                 offset, bank->gpio_chip.base, bank->id, mask);
 702
 703         regmap_write_bits(pctl->regmap,
 704                           (bank->id ?
 705                                 PINMUX_810_PRIMARY_SEL1 :
 706                                 PINMUX_810_PRIMARY_SEL0),
 707                           mask, 0);
 708         regmap_write_bits(pctl->regmap,
 709                           (bank->id ?
 710                                 PINMUX_810_SECONDARY_SEL1 :
 711                                 PINMUX_810_SECONDARY_SEL0),
 712                           mask, 0);
 713         regmap_write_bits(pctl->regmap,
 714                           (bank->id ?
 715                                 PINMUX_810_TERTIARY_SEL1 :
 716                                 PINMUX_810_TERTIARY_SEL0),
 717                           mask, 0);
 718
 719         return 0;
 720 }
 721
 722 static int oxnas_ox820_gpio_request_enable(struct pinctrl_dev *pctldev,
 723                                            struct pinctrl_gpio_range *range,
 724                                            unsigned int offset)
 725 {
 726         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 727         struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
 728         unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
 729         u32 mask = BIT(offset - bank->gpio_chip.base);
 730
 731         dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n",
 732                 offset, bank->gpio_chip.base, bank->id, mask);
 733
 734         regmap_write_bits(pctl->regmap,
 735                           bank_offset + PINMUX_820_SECONDARY_SEL,
 736                           mask, 0);
 737         regmap_write_bits(pctl->regmap,
 738                           bank_offset + PINMUX_820_TERTIARY_SEL,
 739                           mask, 0);
 740         regmap_write_bits(pctl->regmap,
 741                           bank_offset + PINMUX_820_QUATERNARY_SEL,
 742                           mask, 0);
 743         regmap_write_bits(pctl->regmap,
 744                           bank_offset + PINMUX_820_DEBUG_SEL,
 745                           mask, 0);
 746         regmap_write_bits(pctl->regmap,
 747                           bank_offset + PINMUX_820_ALTERNATIVE_SEL,
 748                           mask, 0);
 749
 750         return 0;
 751 }
 752
 753 static int oxnas_gpio_get_direction(struct gpio_chip *chip,
 754                                       unsigned int offset)
 755 {
 756         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
 757         u32 mask = BIT(offset);
 758
 759         if (readl_relaxed(bank->reg_base + OUTPUT_EN) & mask)
 760                 return GPIO_LINE_DIRECTION_OUT;
 761
 762         return GPIO_LINE_DIRECTION_IN;
 763 }
 764
 765 static int oxnas_gpio_direction_input(struct gpio_chip *chip,
 766                                       unsigned int offset)
 767 {
 768         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
 769         u32 mask = BIT(offset);
 770
 771         writel_relaxed(mask, bank->reg_base + OUTPUT_EN_CLEAR);
 772
 773         return 0;
 774 }
 775
 776 static int oxnas_gpio_get(struct gpio_chip *chip, unsigned int offset)
 777 {
 778         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
 779         u32 mask = BIT(offset);
 780
 781         return (readl_relaxed(bank->reg_base + INPUT_VALUE) & mask) != 0;
 782 }
 783
 784 static void oxnas_gpio_set(struct gpio_chip *chip, unsigned int offset,
 785                                int value)
 786 {
 787         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
 788         u32 mask = BIT(offset);
 789
 790         if (value)
 791                 writel_relaxed(mask, bank->reg_base + OUTPUT_SET);
 792         else
 793                 writel_relaxed(mask, bank->reg_base + OUTPUT_CLEAR);
 794 }
 795
 796 static int oxnas_gpio_direction_output(struct gpio_chip *chip,
 797                                        unsigned int offset, int value)
 798 {
 799         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
 800         u32 mask = BIT(offset);
 801
 802         oxnas_gpio_set(chip, offset, value);
 803         writel_relaxed(mask, bank->reg_base + OUTPUT_EN_SET);
 804
 805         return 0;
 806 }
 807
 808 static int oxnas_gpio_set_direction(struct pinctrl_dev *pctldev,
 809                                     struct pinctrl_gpio_range *range,
 810                                     unsigned int offset, bool input)
 811 {
 812         struct gpio_chip *chip = range->gc;
 813
 814         if (input)
 815                 oxnas_gpio_direction_input(chip, offset);
 816         else
 817                 oxnas_gpio_direction_output(chip, offset, 0);
 818
 819         return 0;
 820 }
 821
 822 static const struct pinmux_ops oxnas_ox810se_pinmux_ops = {
 823         .get_functions_count = oxnas_pinmux_get_functions_count,
 824         .get_function_name = oxnas_pinmux_get_function_name,
 825         .get_function_groups = oxnas_pinmux_get_function_groups,
 826         .set_mux = oxnas_ox810se_pinmux_enable,
 827         .gpio_request_enable = oxnas_ox810se_gpio_request_enable,
 828         .gpio_set_direction = oxnas_gpio_set_direction,
 829 };
 830
 831 static const struct pinmux_ops oxnas_ox820_pinmux_ops = {
 832         .get_functions_count = oxnas_pinmux_get_functions_count,
 833         .get_function_name = oxnas_pinmux_get_function_name,
 834         .get_function_groups = oxnas_pinmux_get_function_groups,
 835         .set_mux = oxnas_ox820_pinmux_enable,
 836         .gpio_request_enable = oxnas_ox820_gpio_request_enable,
 837         .gpio_set_direction = oxnas_gpio_set_direction,
 838 };
 839
 840 static int oxnas_ox810se_pinconf_get(struct pinctrl_dev *pctldev,
 841                                      unsigned int pin, unsigned long *config)
 842 {
 843         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 844         struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
 845         unsigned int param = pinconf_to_config_param(*config);
 846         u32 mask = BIT(pin - bank->gpio_chip.base);
 847         int ret;
 848         u32 arg;
 849
 850         switch (param) {
 851         case PIN_CONFIG_BIAS_PULL_UP:
 852                 ret = regmap_read(pctl->regmap,
 853                                   (bank->id ?
 854                                         PINMUX_810_PULLUP_CTRL1 :
 855                                         PINMUX_810_PULLUP_CTRL0),
 856                                   &arg);
 857                 if (ret)
 858                         return ret;
 859
 860                 arg = !!(arg & mask);
 861                 break;
 862         default:
 863                 return -ENOTSUPP;
 864         }
 865
 866         *config = pinconf_to_config_packed(param, arg);
 867
 868         return 0;
 869 }
 870
 871 static int oxnas_ox820_pinconf_get(struct pinctrl_dev *pctldev,
 872                                    unsigned int pin, unsigned long *config)
 873 {
 874         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 875         struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
 876         unsigned int param = pinconf_to_config_param(*config);
 877         unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
 878         u32 mask = BIT(pin - bank->gpio_chip.base);
 879         int ret;
 880         u32 arg;
 881
 882         switch (param) {
 883         case PIN_CONFIG_BIAS_PULL_UP:
 884                 ret = regmap_read(pctl->regmap,
 885                                   bank_offset + PINMUX_820_PULLUP_CTRL,
 886                                   &arg);
 887                 if (ret)
 888                         return ret;
 889
 890                 arg = !!(arg & mask);
 891                 break;
 892         default:
 893                 return -ENOTSUPP;
 894         }
 895
 896         *config = pinconf_to_config_packed(param, arg);
 897
 898         return 0;
 899 }
 900
 901 static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev,
 902                                      unsigned int pin, unsigned long *configs,
 903                                      unsigned int num_configs)
 904 {
 905         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 906         struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
 907         unsigned int param;
 908         unsigned int i;
 909         u32 offset = pin - bank->gpio_chip.base;
 910         u32 mask = BIT(offset);
 911
 912         dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
 913                 pin, bank->gpio_chip.base, mask);
 914
 915         for (i = 0; i < num_configs; i++) {
 916                 param = pinconf_to_config_param(configs[i]);
 917
 918                 switch (param) {
 919                 case PIN_CONFIG_BIAS_PULL_UP:
 920                         dev_dbg(pctl->dev, "   pullup\n");
 921                         regmap_write_bits(pctl->regmap,
 922                                           (bank->id ?
 923                                                 PINMUX_810_PULLUP_CTRL1 :
 924                                                 PINMUX_810_PULLUP_CTRL0),
 925                                           mask, mask);
 926                         break;
 927                 default:
 928                         dev_err(pctl->dev, "Property %u not supported\n",
 929                                 param);
 930                         return -ENOTSUPP;
 931                 }
 932         }
 933
 934         return 0;
 935 }
 936
 937 static int oxnas_ox820_pinconf_set(struct pinctrl_dev *pctldev,
 938                                    unsigned int pin, unsigned long *configs,
 939                                    unsigned int num_configs)
 940 {
 941         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 942         struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
 943         unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
 944         unsigned int param;
 945         unsigned int i;
 946         u32 offset = pin - bank->gpio_chip.base;
 947         u32 mask = BIT(offset);
 948
 949         dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
 950                 pin, bank->gpio_chip.base, mask);
 951
 952         for (i = 0; i < num_configs; i++) {
 953                 param = pinconf_to_config_param(configs[i]);
 954
 955                 switch (param) {
 956                 case PIN_CONFIG_BIAS_PULL_UP:
 957                         dev_dbg(pctl->dev, "   pullup\n");
 958                         regmap_write_bits(pctl->regmap,
 959                                           bank_offset + PINMUX_820_PULLUP_CTRL,
 960                                           mask, mask);
 961                         break;
 962                 default:
 963                         dev_err(pctl->dev, "Property %u not supported\n",
 964                                 param);
 965                         return -ENOTSUPP;
 966                 }
 967         }
 968
 969         return 0;
 970 }
 971
 972 static const struct pinconf_ops oxnas_ox810se_pinconf_ops = {
 973         .pin_config_get = oxnas_ox810se_pinconf_get,
 974         .pin_config_set = oxnas_ox810se_pinconf_set,
 975         .is_generic = true,
 976 };
 977
 978 static const struct pinconf_ops oxnas_ox820_pinconf_ops = {
 979         .pin_config_get = oxnas_ox820_pinconf_get,
 980         .pin_config_set = oxnas_ox820_pinconf_set,
 981         .is_generic = true,
 982 };
 983
 984 static void oxnas_gpio_irq_ack(struct irq_data *data)
 985 {
 986         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 987         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
 988         u32 mask = BIT(data->hwirq);
 989
 990         writel(mask, bank->reg_base + IRQ_PENDING);
 991 }
 992
 993 static void oxnas_gpio_irq_mask(struct irq_data *data)
 994 {
 995         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 996         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
 997         unsigned int type = irqd_get_trigger_type(data);
 998         u32 mask = BIT(data->hwirq);
 999
1000         if (type & IRQ_TYPE_EDGE_RISING)
1001                 writel(readl(bank->reg_base + RE_IRQ_ENABLE) & ~mask,
1002                        bank->reg_base + RE_IRQ_ENABLE);
1003
1004         if (type & IRQ_TYPE_EDGE_FALLING)
1005                 writel(readl(bank->reg_base + FE_IRQ_ENABLE) & ~mask,
1006                        bank->reg_base + FE_IRQ_ENABLE);
1007 }
1008
1009 static void oxnas_gpio_irq_unmask(struct irq_data *data)
1010 {
1011         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1012         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
1013         unsigned int type = irqd_get_trigger_type(data);
1014         u32 mask = BIT(data->hwirq);
1015
1016         if (type & IRQ_TYPE_EDGE_RISING)
1017                 writel(readl(bank->reg_base + RE_IRQ_ENABLE) | mask,
1018                        bank->reg_base + RE_IRQ_ENABLE);
1019
1020         if (type & IRQ_TYPE_EDGE_FALLING)
1021                 writel(readl(bank->reg_base + FE_IRQ_ENABLE) | mask,
1022                        bank->reg_base + FE_IRQ_ENABLE);
1023 }
1024
1025 static unsigned int oxnas_gpio_irq_startup(struct irq_data *data)
1026 {
1027         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1028
1029         oxnas_gpio_direction_input(chip, data->hwirq);
1030         oxnas_gpio_irq_unmask(data);
1031
1032         return 0;
1033 }
1034
1035 static int oxnas_gpio_irq_set_type(struct irq_data *data, unsigned int type)
1036 {
1037         if ((type & (IRQ_TYPE_EDGE_RISING|IRQ_TYPE_EDGE_FALLING)) == 0)
1038                 return -EINVAL;
1039
1040         irq_set_handler_locked(data, handle_edge_irq);
1041
1042         return 0;
1043 }
1044
1045 static void oxnas_gpio_irq_handler(struct irq_desc *desc)
1046 {
1047         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1048         struct oxnas_gpio_bank *bank = gpiochip_get_data(gc);
1049         struct irq_chip *chip = irq_desc_get_chip(desc);
1050         unsigned long stat;
1051         unsigned int pin;
1052
1053         chained_irq_enter(chip, desc);
1054
1055         stat = readl(bank->reg_base + IRQ_PENDING);
1056
1057         for_each_set_bit(pin, &stat, BITS_PER_LONG)
1058                 generic_handle_domain_irq(gc->irq.domain, pin);
1059
1060         chained_irq_exit(chip, desc);
1061 }
1062
1063 #define GPIO_BANK(_bank)                                                \
1064         {                                                               \
1065                 .gpio_chip = {                                          \
1066                         .label = "GPIO" #_bank,                         \
1067                         .request = gpiochip_generic_request,            \
1068                         .free = gpiochip_generic_free,                  \
1069                         .get_direction = oxnas_gpio_get_direction,      \
1070                         .direction_input = oxnas_gpio_direction_input,  \
1071                         .direction_output = oxnas_gpio_direction_output, \
1072                         .get = oxnas_gpio_get,                          \
1073                         .set = oxnas_gpio_set,                          \
1074                         .ngpio = PINS_PER_BANK,                         \
1075                         .base = GPIO_BANK_START(_bank),                 \
1076                         .owner = THIS_MODULE,                           \
1077                         .can_sleep = 0,                                 \
1078                 },                                                      \
1079                 .irq_chip = {                                           \
1080                         .name = "GPIO" #_bank,                          \
1081                         .irq_startup = oxnas_gpio_irq_startup,  \
1082                         .irq_ack = oxnas_gpio_irq_ack,          \
1083                         .irq_mask = oxnas_gpio_irq_mask,                \
1084                         .irq_unmask = oxnas_gpio_irq_unmask,            \
1085                         .irq_set_type = oxnas_gpio_irq_set_type,        \
1086                 },                                                      \
1087         }
1088
1089 static struct oxnas_gpio_bank oxnas_gpio_banks[] = {
1090         GPIO_BANK(0),
1091         GPIO_BANK(1),
1092 };
1093
1094 static struct oxnas_pinctrl ox810se_pinctrl = {
1095         .functions = oxnas_ox810se_functions,
1096         .nfunctions = ARRAY_SIZE(oxnas_ox810se_functions),
1097         .groups = oxnas_ox810se_groups,
1098         .ngroups = ARRAY_SIZE(oxnas_ox810se_groups),
1099         .gpio_banks = oxnas_gpio_banks,
1100         .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
1101 };
1102
1103 static struct pinctrl_desc oxnas_ox810se_pinctrl_desc = {
1104         .name = "oxnas-pinctrl",
1105         .pins = oxnas_ox810se_pins,
1106         .npins = ARRAY_SIZE(oxnas_ox810se_pins),
1107         .pctlops = &oxnas_pinctrl_ops,
1108         .pmxops = &oxnas_ox810se_pinmux_ops,
1109         .confops = &oxnas_ox810se_pinconf_ops,
1110         .owner = THIS_MODULE,
1111 };
1112
1113 static struct oxnas_pinctrl ox820_pinctrl = {
1114         .functions = oxnas_ox820_functions,
1115         .nfunctions = ARRAY_SIZE(oxnas_ox820_functions),
1116         .groups = oxnas_ox820_groups,
1117         .ngroups = ARRAY_SIZE(oxnas_ox820_groups),
1118         .gpio_banks = oxnas_gpio_banks,
1119         .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
1120 };
1121
1122 static struct pinctrl_desc oxnas_ox820_pinctrl_desc = {
1123         .name = "oxnas-pinctrl",
1124         .pins = oxnas_ox820_pins,
1125         .npins = ARRAY_SIZE(oxnas_ox820_pins),
1126         .pctlops = &oxnas_pinctrl_ops,
1127         .pmxops = &oxnas_ox820_pinmux_ops,
1128         .confops = &oxnas_ox820_pinconf_ops,
1129         .owner = THIS_MODULE,
1130 };
1131
1132 static struct oxnas_pinctrl_data oxnas_ox810se_pinctrl_data = {
1133         .desc = &oxnas_ox810se_pinctrl_desc,
1134         .pctl = &ox810se_pinctrl,
1135 };
1136
1137 static struct oxnas_pinctrl_data oxnas_ox820_pinctrl_data = {
1138         .desc = &oxnas_ox820_pinctrl_desc,
1139         .pctl = &ox820_pinctrl,
1140 };
1141
1142 static const struct of_device_id oxnas_pinctrl_of_match[] = {
1143         { .compatible = "oxsemi,ox810se-pinctrl",
1144           .data = &oxnas_ox810se_pinctrl_data
1145         },
1146         { .compatible = "oxsemi,ox820-pinctrl",
1147           .data = &oxnas_ox820_pinctrl_data,
1148         },
1149         { },
1150 };
1151
1152 static int oxnas_pinctrl_probe(struct platform_device *pdev)
1153 {
1154         const struct of_device_id *id;
1155         const struct oxnas_pinctrl_data *data;
1156         struct oxnas_pinctrl *pctl;
1157
1158         id = of_match_node(oxnas_pinctrl_of_match, pdev->dev.of_node);
1159         if (!id)
1160                 return -ENODEV;
1161
1162         data = id->data;
1163         if (!data || !data->pctl || !data->desc)
1164                 return -EINVAL;
1165
1166         pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1167         if (!pctl)
1168                 return -ENOMEM;
1169         pctl->dev = &pdev->dev;
1170         dev_set_drvdata(&pdev->dev, pctl);
1171
1172         pctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1173                                                        "oxsemi,sys-ctrl");
1174         if (IS_ERR(pctl->regmap)) {
1175                 dev_err(&pdev->dev, "failed to get sys ctrl regmap\n");
1176                 return -ENODEV;
1177         }
1178
1179         pctl->functions = data->pctl->functions;
1180         pctl->nfunctions = data->pctl->nfunctions;
1181         pctl->groups = data->pctl->groups;
1182         pctl->ngroups = data->pctl->ngroups;
1183         pctl->gpio_banks = data->pctl->gpio_banks;
1184         pctl->nbanks = data->pctl->nbanks;
1185
1186         pctl->pctldev = pinctrl_register(data->desc, &pdev->dev, pctl);
1187         if (IS_ERR(pctl->pctldev)) {
1188                 dev_err(&pdev->dev, "Failed to register pinctrl device\n");
1189                 return PTR_ERR(pctl->pctldev);
1190         }
1191
1192         return 0;
1193 }
1194
1195 static int oxnas_gpio_probe(struct platform_device *pdev)
1196 {
1197         struct device_node *np = pdev->dev.of_node;
1198         struct of_phandle_args pinspec;
1199         struct oxnas_gpio_bank *bank;
1200         unsigned int id, ngpios;
1201         int irq, ret;
1202         struct gpio_irq_chip *girq;
1203
1204         if (of_parse_phandle_with_fixed_args(np, "gpio-ranges",
1205                                              3, 0, &pinspec)) {
1206                 dev_err(&pdev->dev, "gpio-ranges property not found\n");
1207                 return -EINVAL;
1208         }
1209
1210         id = pinspec.args[1] / PINS_PER_BANK;
1211         ngpios = pinspec.args[2];
1212
1213         if (id >= ARRAY_SIZE(oxnas_gpio_banks)) {
1214                 dev_err(&pdev->dev, "invalid gpio-ranges base arg\n");
1215                 return -EINVAL;
1216         }
1217
1218         if (ngpios > PINS_PER_BANK) {
1219                 dev_err(&pdev->dev, "invalid gpio-ranges count arg\n");
1220                 return -EINVAL;
1221         }
1222
1223         bank = &oxnas_gpio_banks[id];
1224
1225         bank->reg_base = devm_platform_ioremap_resource(pdev, 0);
1226         if (IS_ERR(bank->reg_base))
1227                 return PTR_ERR(bank->reg_base);
1228
1229         irq = platform_get_irq(pdev, 0);
1230         if (irq < 0)
1231                 return irq;
1232
1233         bank->id = id;
1234         bank->gpio_chip.parent = &pdev->dev;
1235         bank->gpio_chip.of_node = np;
1236         bank->gpio_chip.ngpio = ngpios;
1237         girq = &bank->gpio_chip.irq;
1238         girq->chip = &bank->irq_chip;
1239         girq->parent_handler = oxnas_gpio_irq_handler;
1240         girq->num_parents = 1;
1241         girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
1242                                      GFP_KERNEL);
1243         if (!girq->parents)
1244                 return -ENOMEM;
1245         girq->parents[0] = irq;
1246         girq->default_type = IRQ_TYPE_NONE;
1247         girq->handler = handle_level_irq;
1248
1249         ret = gpiochip_add_data(&bank->gpio_chip, bank);
1250         if (ret < 0) {
1251                 dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
1252                         id, ret);
1253                 return ret;
1254         }
1255
1256         return 0;
1257 }
1258
1259 static struct platform_driver oxnas_pinctrl_driver = {
1260         .driver = {
1261                 .name = "oxnas-pinctrl",
1262                 .of_match_table = oxnas_pinctrl_of_match,
1263                 .suppress_bind_attrs = true,
1264         },
1265         .probe = oxnas_pinctrl_probe,
1266 };
1267
1268 static const struct of_device_id oxnas_gpio_of_match[] = {
1269         { .compatible = "oxsemi,ox810se-gpio", },
1270         { .compatible = "oxsemi,ox820-gpio", },
1271         { },
1272 };
1273
1274 static struct platform_driver oxnas_gpio_driver = {
1275         .driver = {
1276                 .name = "oxnas-gpio",
1277                 .of_match_table = oxnas_gpio_of_match,
1278                 .suppress_bind_attrs = true,
1279         },
1280         .probe = oxnas_gpio_probe,
1281 };
1282
1283 static int __init oxnas_gpio_register(void)
1284 {
1285         return platform_driver_register(&oxnas_gpio_driver);
1286 }
1287 arch_initcall(oxnas_gpio_register);
1288
1289 static int __init oxnas_pinctrl_register(void)
1290 {
1291         return platform_driver_register(&oxnas_pinctrl_driver);
1292 }
1293 arch_initcall(oxnas_pinctrl_register);