1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Microsemi/Microchip SoCs serial gpio driver
5 * Author: Lars Povlsen <lars.povlsen@microchip.com>
7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/clk.h>
13 #include <linux/gpio/driver.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/module.h>
17 #include <linux/pinctrl/pinmux.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/reset.h>
26 #define SGPIO_BITS_PER_WORD 32
27 #define SGPIO_MAX_BITS 4
28 #define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */
51 SGPIO_FLAGS_HAS_IRQ = BIT(0),
54 struct sgpio_properties {
60 #define SGPIO_LUTON_AUTO_REPEAT BIT(5)
61 #define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2)
62 #define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0)
63 #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)
65 #define SGPIO_OCELOT_AUTO_REPEAT BIT(10)
66 #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)
67 #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)
68 #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)
70 #define SGPIO_SPARX5_AUTO_REPEAT BIT(6)
71 #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)
72 #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)
73 #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)
75 #define SGPIO_MASTER_INTR_ENA BIT(0)
77 #define SGPIO_INT_TRG_LEVEL 0
78 #define SGPIO_INT_TRG_EDGE 1
79 #define SGPIO_INT_TRG_EDGE_FALL 2
80 #define SGPIO_INT_TRG_EDGE_RISE 3
82 #define SGPIO_TRG_LEVEL_HIGH 0
83 #define SGPIO_TRG_LEVEL_LOW 1
85 static const struct sgpio_properties properties_luton = {
86 .arch = SGPIO_ARCH_LUTON,
87 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
90 static const struct sgpio_properties properties_ocelot = {
91 .arch = SGPIO_ARCH_OCELOT,
92 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
95 static const struct sgpio_properties properties_sparx5 = {
96 .arch = SGPIO_ARCH_SPARX5,
97 .flags = SGPIO_FLAGS_HAS_IRQ,
98 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 },
101 static const char * const functions[] = { "gpio" };
104 struct sgpio_priv *priv;
106 struct gpio_chip gpio;
107 struct pinctrl_desc pctl_desc;
112 struct sgpio_bank in;
113 struct sgpio_bank out;
118 const struct sgpio_properties *properties;
121 struct sgpio_port_addr {
126 static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin,
127 struct sgpio_port_addr *addr)
129 addr->port = pin / priv->bitcount;
130 addr->bit = pin % priv->bitcount;
133 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit)
135 return bit + port * priv->bitcount;
138 static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off)
140 return (priv->properties->regoff[rno] + off) *
141 regmap_get_reg_stride(priv->regs);
144 static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off)
146 u32 addr = sgpio_get_addr(priv, rno, off);
150 ret = regmap_read(priv->regs, addr, &val);
151 WARN_ONCE(ret, "error reading sgpio reg %d\n", ret);
156 static void sgpio_writel(struct sgpio_priv *priv,
157 u32 val, u32 rno, u32 off)
159 u32 addr = sgpio_get_addr(priv, rno, off);
162 ret = regmap_write(priv->regs, addr, val);
163 WARN_ONCE(ret, "error writing sgpio reg %d\n", ret);
166 static inline void sgpio_clrsetbits(struct sgpio_priv *priv,
167 u32 rno, u32 off, u32 clear, u32 set)
169 u32 val = sgpio_readl(priv, rno, off);
174 sgpio_writel(priv, val, rno, off);
177 static inline void sgpio_configure_bitstream(struct sgpio_priv *priv)
179 int width = priv->bitcount - 1;
182 switch (priv->properties->arch) {
183 case SGPIO_ARCH_LUTON:
184 clr = SGPIO_LUTON_PORT_WIDTH;
185 set = SGPIO_LUTON_AUTO_REPEAT |
186 FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width);
188 case SGPIO_ARCH_OCELOT:
189 clr = SGPIO_OCELOT_PORT_WIDTH;
190 set = SGPIO_OCELOT_AUTO_REPEAT |
191 FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width);
193 case SGPIO_ARCH_SPARX5:
194 clr = SGPIO_SPARX5_PORT_WIDTH;
195 set = SGPIO_SPARX5_AUTO_REPEAT |
196 FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width);
201 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set);
204 static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq)
208 switch (priv->properties->arch) {
209 case SGPIO_ARCH_LUTON:
210 clr = SGPIO_LUTON_CLK_FREQ;
211 set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq);
213 case SGPIO_ARCH_OCELOT:
214 clr = SGPIO_OCELOT_CLK_FREQ;
215 set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq);
217 case SGPIO_ARCH_SPARX5:
218 clr = SGPIO_SPARX5_CLK_FREQ;
219 set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq);
224 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set);
227 static void sgpio_output_set(struct sgpio_priv *priv,
228 struct sgpio_port_addr *addr,
231 unsigned int bit = SGPIO_SRC_BITS * addr->bit;
234 switch (priv->properties->arch) {
235 case SGPIO_ARCH_LUTON:
236 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit));
237 set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit);
239 case SGPIO_ARCH_OCELOT:
240 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit));
241 set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit);
243 case SGPIO_ARCH_SPARX5:
244 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit));
245 set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit);
250 sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set);
253 static int sgpio_output_get(struct sgpio_priv *priv,
254 struct sgpio_port_addr *addr)
256 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port);
257 unsigned int bit = SGPIO_SRC_BITS * addr->bit;
259 switch (priv->properties->arch) {
260 case SGPIO_ARCH_LUTON:
261 val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval);
263 case SGPIO_ARCH_OCELOT:
264 val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval);
266 case SGPIO_ARCH_SPARX5:
267 val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval);
273 return !!(val & BIT(bit));
276 static int sgpio_input_get(struct sgpio_priv *priv,
277 struct sgpio_port_addr *addr)
279 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port));
282 static int sgpio_pinconf_get(struct pinctrl_dev *pctldev,
283 unsigned int pin, unsigned long *config)
285 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
286 u32 param = pinconf_to_config_param(*config);
287 struct sgpio_priv *priv = bank->priv;
288 struct sgpio_port_addr addr;
291 sgpio_pin_to_addr(priv, pin, &addr);
294 case PIN_CONFIG_INPUT_ENABLE:
295 val = bank->is_input;
298 case PIN_CONFIG_OUTPUT_ENABLE:
299 val = !bank->is_input;
302 case PIN_CONFIG_OUTPUT:
305 val = sgpio_output_get(priv, &addr);
312 *config = pinconf_to_config_packed(param, val);
317 static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
318 unsigned long *configs, unsigned int num_configs)
320 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
321 struct sgpio_priv *priv = bank->priv;
322 struct sgpio_port_addr addr;
326 sgpio_pin_to_addr(priv, pin, &addr);
328 for (cfg = 0; cfg < num_configs; cfg++) {
329 param = pinconf_to_config_param(configs[cfg]);
330 arg = pinconf_to_config_argument(configs[cfg]);
333 case PIN_CONFIG_OUTPUT:
336 sgpio_output_set(priv, &addr, arg);
347 static const struct pinconf_ops sgpio_confops = {
349 .pin_config_get = sgpio_pinconf_get,
350 .pin_config_set = sgpio_pinconf_set,
351 .pin_config_config_dbg_show = pinconf_generic_dump_config,
354 static int sgpio_get_functions_count(struct pinctrl_dev *pctldev)
359 static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev,
360 unsigned int function)
365 static int sgpio_get_function_groups(struct pinctrl_dev *pctldev,
366 unsigned int function,
367 const char *const **groups,
368 unsigned *const num_groups)
371 *num_groups = ARRAY_SIZE(functions);
376 static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev,
377 unsigned int selector, unsigned int group)
382 static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev,
383 struct pinctrl_gpio_range *range,
384 unsigned int pin, bool input)
386 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
388 return (input == bank->is_input) ? 0 : -EINVAL;
391 static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev,
392 struct pinctrl_gpio_range *range,
395 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
396 struct sgpio_priv *priv = bank->priv;
397 struct sgpio_port_addr addr;
399 sgpio_pin_to_addr(priv, offset, &addr);
401 if ((priv->ports & BIT(addr.port)) == 0) {
402 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n",
403 addr.port, addr.bit);
410 static const struct pinmux_ops sgpio_pmx_ops = {
411 .get_functions_count = sgpio_get_functions_count,
412 .get_function_name = sgpio_get_function_name,
413 .get_function_groups = sgpio_get_function_groups,
414 .set_mux = sgpio_pinmux_set_mux,
415 .gpio_set_direction = sgpio_gpio_set_direction,
416 .gpio_request_enable = sgpio_gpio_request_enable,
419 static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev)
421 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
423 return bank->pctl_desc.npins;
426 static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev,
429 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
431 return bank->pctl_desc.pins[group].name;
434 static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev,
436 const unsigned int **pins,
437 unsigned int *num_pins)
439 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
441 *pins = &bank->pctl_desc.pins[group].number;
447 static const struct pinctrl_ops sgpio_pctl_ops = {
448 .get_groups_count = sgpio_pctl_get_groups_count,
449 .get_group_name = sgpio_pctl_get_group_name,
450 .get_group_pins = sgpio_pctl_get_group_pins,
451 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
452 .dt_free_map = pinconf_generic_dt_free_map,
455 static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio)
457 struct sgpio_bank *bank = gpiochip_get_data(gc);
459 /* Fixed-position function */
460 return bank->is_input ? 0 : -EINVAL;
463 static int microchip_sgpio_direction_output(struct gpio_chip *gc,
464 unsigned int gpio, int value)
466 struct sgpio_bank *bank = gpiochip_get_data(gc);
467 struct sgpio_priv *priv = bank->priv;
468 struct sgpio_port_addr addr;
470 /* Fixed-position function */
474 sgpio_pin_to_addr(priv, gpio, &addr);
476 sgpio_output_set(priv, &addr, value);
481 static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
483 struct sgpio_bank *bank = gpiochip_get_data(gc);
485 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
488 static void microchip_sgpio_set_value(struct gpio_chip *gc,
489 unsigned int gpio, int value)
491 microchip_sgpio_direction_output(gc, gpio, value);
494 static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio)
496 struct sgpio_bank *bank = gpiochip_get_data(gc);
497 struct sgpio_priv *priv = bank->priv;
498 struct sgpio_port_addr addr;
500 sgpio_pin_to_addr(priv, gpio, &addr);
502 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr);
505 static int microchip_sgpio_of_xlate(struct gpio_chip *gc,
506 const struct of_phandle_args *gpiospec,
509 struct sgpio_bank *bank = gpiochip_get_data(gc);
510 struct sgpio_priv *priv = bank->priv;
514 * Note that the SGIO pin is defined by *2* numbers, a port
515 * number between 0 and 31, and a bit index, 0 to 3.
517 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD ||
518 gpiospec->args[1] > priv->bitcount)
521 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]);
527 *flags = gpiospec->args[2];
532 static int microchip_sgpio_get_ports(struct sgpio_priv *priv)
534 const char *range_property_name = "microchip,sgpio-port-ranges";
535 struct device *dev = priv->dev;
536 u32 range_params[64];
539 /* Calculate port mask */
540 nranges = device_property_count_u32(dev, range_property_name);
541 if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) {
542 dev_err(dev, "%s port range: '%s' property\n",
543 nranges == -EINVAL ? "Missing" : "Invalid",
544 range_property_name);
548 ret = device_property_read_u32_array(dev, range_property_name,
549 range_params, nranges);
551 dev_err(dev, "failed to parse '%s' property: %d\n",
552 range_property_name, ret);
555 for (i = 0; i < nranges; i += 2) {
558 start = range_params[i];
559 end = range_params[i + 1];
560 if (start > end || end >= SGPIO_BITS_PER_WORD) {
561 dev_err(dev, "Ill-formed port-range [%d:%d]\n",
564 priv->ports |= GENMASK(end, start);
570 static void microchip_sgpio_irq_settype(struct irq_data *data,
574 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
575 struct sgpio_bank *bank = gpiochip_get_data(chip);
576 unsigned int gpio = irqd_to_hwirq(data);
577 struct sgpio_port_addr addr;
580 sgpio_pin_to_addr(bank->priv, gpio, &addr);
582 /* Disable interrupt while changing type */
583 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
584 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
586 /* Type value spread over 2 registers sets: low, high bit */
587 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,
588 BIT(addr.port), (!!(type & 0x1)) << addr.port);
589 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit,
590 BIT(addr.port), (!!(type & 0x2)) << addr.port);
592 if (type == SGPIO_INT_TRG_LEVEL)
593 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit,
594 BIT(addr.port), polarity << addr.port);
596 /* Possibly re-enable interrupts */
597 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);
600 static void microchip_sgpio_irq_setreg(struct irq_data *data,
604 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
605 struct sgpio_bank *bank = gpiochip_get_data(chip);
606 unsigned int gpio = irqd_to_hwirq(data);
607 struct sgpio_port_addr addr;
609 sgpio_pin_to_addr(bank->priv, gpio, &addr);
612 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0);
614 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port));
617 static void microchip_sgpio_irq_mask(struct irq_data *data)
619 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true);
622 static void microchip_sgpio_irq_unmask(struct irq_data *data)
624 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false);
627 static void microchip_sgpio_irq_ack(struct irq_data *data)
629 microchip_sgpio_irq_setreg(data, REG_INT_ACK, false);
632 static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)
634 type &= IRQ_TYPE_SENSE_MASK;
637 case IRQ_TYPE_EDGE_BOTH:
638 irq_set_handler_locked(data, handle_edge_irq);
639 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0);
641 case IRQ_TYPE_EDGE_RISING:
642 irq_set_handler_locked(data, handle_edge_irq);
643 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0);
645 case IRQ_TYPE_EDGE_FALLING:
646 irq_set_handler_locked(data, handle_edge_irq);
647 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0);
649 case IRQ_TYPE_LEVEL_HIGH:
650 irq_set_handler_locked(data, handle_level_irq);
651 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH);
653 case IRQ_TYPE_LEVEL_LOW:
654 irq_set_handler_locked(data, handle_level_irq);
655 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW);
664 static const struct irq_chip microchip_sgpio_irqchip = {
666 .irq_mask = microchip_sgpio_irq_mask,
667 .irq_ack = microchip_sgpio_irq_ack,
668 .irq_unmask = microchip_sgpio_irq_unmask,
669 .irq_set_type = microchip_sgpio_irq_set_type,
672 static void sgpio_irq_handler(struct irq_desc *desc)
674 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
675 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
676 struct sgpio_bank *bank = gpiochip_get_data(chip);
677 struct sgpio_priv *priv = bank->priv;
681 for (bit = 0; bit < priv->bitcount; bit++) {
682 val = sgpio_readl(priv, REG_INT_IDENT, bit);
686 chained_irq_enter(parent_chip, desc);
688 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {
689 gpio = sgpio_addr_to_pin(priv, port, bit);
690 generic_handle_domain_irq(chip->irq.domain, gpio);
693 chained_irq_exit(parent_chip, desc);
697 static int microchip_sgpio_register_bank(struct device *dev,
698 struct sgpio_priv *priv,
699 struct fwnode_handle *fwnode,
702 struct pinctrl_pin_desc *pins;
703 struct pinctrl_desc *pctl_desc;
704 struct pinctrl_dev *pctldev;
705 struct sgpio_bank *bank;
706 struct gpio_chip *gc;
710 /* Get overall bank struct */
711 bank = (bankno == 0) ? &priv->in : &priv->out;
714 if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) {
715 dev_info(dev, "failed to get number of gpios for bank%d\n",
720 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD;
721 if (priv->bitcount > SGPIO_MAX_BITS) {
722 dev_err(dev, "Bit width exceeds maximum (%d)\n",
727 pctl_desc = &bank->pctl_desc;
728 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput",
730 bank->is_input ? "in" : "out");
731 pctl_desc->pctlops = &sgpio_pctl_ops;
732 pctl_desc->pmxops = &sgpio_pmx_ops;
733 pctl_desc->confops = &sgpio_confops;
734 pctl_desc->owner = THIS_MODULE;
736 pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL);
740 pctl_desc->npins = ngpios;
741 pctl_desc->pins = pins;
743 for (i = 0; i < ngpios; i++) {
744 struct sgpio_port_addr addr;
746 sgpio_pin_to_addr(priv, i, &addr);
749 pins[i].name = devm_kasprintf(dev, GFP_KERNEL,
751 bank->is_input ? 'I' : 'O',
752 addr.port, addr.bit);
757 pctldev = devm_pinctrl_register(dev, pctl_desc, bank);
759 return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n");
762 gc->label = pctl_desc->name;
764 gc->of_node = to_of_node(fwnode);
765 gc->owner = THIS_MODULE;
766 gc->get_direction = microchip_sgpio_get_direction;
767 gc->direction_input = microchip_sgpio_direction_input;
768 gc->direction_output = microchip_sgpio_direction_output;
769 gc->get = microchip_sgpio_get_value;
770 gc->set = microchip_sgpio_set_value;
771 gc->request = gpiochip_generic_request;
772 gc->free = gpiochip_generic_free;
773 gc->of_xlate = microchip_sgpio_of_xlate;
774 gc->of_gpio_n_cells = 3;
778 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
779 int irq = fwnode_irq_get(fwnode, 0);
782 struct gpio_irq_chip *girq = &gc->irq;
784 girq->chip = devm_kmemdup(dev, µchip_sgpio_irqchip,
785 sizeof(microchip_sgpio_irqchip),
789 girq->parent_handler = sgpio_irq_handler;
790 girq->num_parents = 1;
791 girq->parents = devm_kcalloc(dev, 1,
792 sizeof(*girq->parents),
796 girq->parents[0] = irq;
797 girq->default_type = IRQ_TYPE_NONE;
798 girq->handler = handle_bad_irq;
800 /* Disable all individual pins */
801 for (i = 0; i < SGPIO_MAX_BITS; i++)
802 sgpio_writel(priv, 0, REG_INT_ENABLE, i);
804 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA);
808 ret = devm_gpiochip_add_data(dev, gc, bank);
810 dev_err(dev, "Failed to register: ret %d\n", ret);
815 static int microchip_sgpio_probe(struct platform_device *pdev)
817 int div_clock = 0, ret, port, i, nbanks;
818 struct device *dev = &pdev->dev;
819 struct fwnode_handle *fwnode;
820 struct reset_control *reset;
821 struct sgpio_priv *priv;
825 struct regmap_config regmap_config = {
831 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
837 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
839 return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n");
840 reset_control_reset(reset);
842 clk = devm_clk_get(dev, NULL);
844 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n");
846 div_clock = clk_get_rate(clk);
847 if (device_property_read_u32(dev, "bus-frequency", &priv->clock))
848 priv->clock = 12500000;
849 if (priv->clock == 0 || priv->clock > (div_clock / 2)) {
850 dev_err(dev, "Invalid frequency %d\n", priv->clock);
854 regs = devm_platform_ioremap_resource(pdev, 0);
856 return PTR_ERR(regs);
858 priv->regs = devm_regmap_init_mmio(dev, regs, ®map_config);
859 if (IS_ERR(priv->regs))
860 return PTR_ERR(priv->regs);
862 priv->properties = device_get_match_data(dev);
863 priv->in.is_input = true;
865 /* Get rest of device properties */
866 ret = microchip_sgpio_get_ports(priv);
870 nbanks = device_get_child_node_count(dev);
872 dev_err(dev, "Must have 2 banks (have %d)\n", nbanks);
877 device_for_each_child_node(dev, fwnode) {
878 ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++);
880 fwnode_handle_put(fwnode);
885 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) {
886 dev_err(dev, "Banks must have same GPIO count\n");
890 sgpio_configure_bitstream(priv);
892 val = max(2U, div_clock / priv->clock);
893 sgpio_configure_clock(priv, val);
895 for (port = 0; port < SGPIO_BITS_PER_WORD; port++)
896 sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
897 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
902 static const struct of_device_id microchip_sgpio_gpio_of_match[] = {
904 .compatible = "microchip,sparx5-sgpio",
905 .data = &properties_sparx5,
907 .compatible = "mscc,luton-sgpio",
908 .data = &properties_luton,
910 .compatible = "mscc,ocelot-sgpio",
911 .data = &properties_ocelot,
917 static struct platform_driver microchip_sgpio_pinctrl_driver = {
919 .name = "pinctrl-microchip-sgpio",
920 .of_match_table = microchip_sgpio_gpio_of_match,
921 .suppress_bind_attrs = true,
923 .probe = microchip_sgpio_probe,
925 builtin_platform_driver(microchip_sgpio_pinctrl_driver);