drivers/pinctrl/pinctrl-imx.c

   1 /*
   2  * Core driver for the imx pin controller
   3  *
   4  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   5  * Copyright (C) 2012 Linaro Ltd.
   6  *
   7  * Author: Dong Aisheng <dong.aisheng@linaro.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pinctrl/machine.h>
  22 #include <linux/pinctrl/pinconf.h>
  23 #include <linux/pinctrl/pinctrl.h>
  24 #include <linux/pinctrl/pinmux.h>
  25 #include <linux/slab.h>
  26
  27 #include "core.h"
  28 #include "pinctrl-imx.h"
  29
  30 #define IMX_PMX_DUMP(info, p, m, c, n)                  \
  31 {                                                       \
  32         int i, j;                                       \
  33         printk(KERN_DEBUG "Format: Pin Mux Config\n");  \
  34         for (i = 0; i < n; i++) {                       \
  35                 j = p[i];                               \
  36                 printk(KERN_DEBUG "%s %d 0x%lx\n",      \
  37                         info->pins[j].name,             \
  38                         m[i], c[i]);                    \
  39         }                                               \
  40 }
  41
  42 /* The bits in CONFIG cell defined in binding doc*/
  43 #define IMX_NO_PAD_CTL  0x80000000      /* no pin config need */
  44 #define IMX_PAD_SION 0x40000000         /* set SION */
  45
  46 /**
  47  * @dev: a pointer back to containing device
  48  * @base: the offset to the controller in virtual memory
  49  */
  50 struct imx_pinctrl {
  51         struct device *dev;
  52         struct pinctrl_dev *pctl;
  53         void __iomem *base;
  54         const struct imx_pinctrl_soc_info *info;
  55 };
  56
  57 static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
  58                                 const struct imx_pinctrl_soc_info *info,
  59                                 const char *name)
  60 {
  61         const struct imx_pin_group *grp = NULL;
  62         int i;
  63
  64         for (i = 0; i < info->ngroups; i++) {
  65                 if (!strcmp(info->groups[i].name, name)) {
  66                         grp = &info->groups[i];
  67                         break;
  68                 }
  69         }
  70
  71         return grp;
  72 }
  73
  74 static int imx_get_groups_count(struct pinctrl_dev *pctldev)
  75 {
  76         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  77         const struct imx_pinctrl_soc_info *info = ipctl->info;
  78
  79         return info->ngroups;
  80 }
  81
  82 static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
  83                                        unsigned selector)
  84 {
  85         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  86         const struct imx_pinctrl_soc_info *info = ipctl->info;
  87
  88         return info->groups[selector].name;
  89 }
  90
  91 static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
  92                                const unsigned **pins,
  93                                unsigned *npins)
  94 {
  95         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  96         const struct imx_pinctrl_soc_info *info = ipctl->info;
  97
  98         if (selector >= info->ngroups)
  99                 return -EINVAL;
 100
 101         *pins = info->groups[selector].pins;
 102         *npins = info->groups[selector].npins;
 103
 104         return 0;
 105 }
 106
 107 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 108                    unsigned offset)
 109 {
 110         seq_printf(s, "%s", dev_name(pctldev->dev));
 111 }
 112
 113 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
 114                         struct device_node *np,
 115                         struct pinctrl_map **map, unsigned *num_maps)
 116 {
 117         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 118         const struct imx_pinctrl_soc_info *info = ipctl->info;
 119         const struct imx_pin_group *grp;
 120         struct pinctrl_map *new_map;
 121         struct device_node *parent;
 122         int map_num = 1;
 123         int i, j;
 124
 125         /*
 126          * first find the group of this node and check if we need create
 127          * config maps for pins
 128          */
 129         grp = imx_pinctrl_find_group_by_name(info, np->name);
 130         if (!grp) {
 131                 dev_err(info->dev, "unable to find group for node %s\n",
 132                         np->name);
 133                 return -EINVAL;
 134         }
 135
 136         for (i = 0; i < grp->npins; i++) {
 137                 if (!(grp->configs[i] & IMX_NO_PAD_CTL))
 138                         map_num++;
 139         }
 140
 141         new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
 142         if (!new_map)
 143                 return -ENOMEM;
 144
 145         *map = new_map;
 146         *num_maps = map_num;
 147
 148         /* create mux map */
 149         parent = of_get_parent(np);
 150         if (!parent) {
 151                 kfree(new_map);
 152                 return -EINVAL;
 153         }
 154         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 155         new_map[0].data.mux.function = parent->name;
 156         new_map[0].data.mux.group = np->name;
 157         of_node_put(parent);
 158
 159         /* create config map */
 160         new_map++;
 161         for (i = j = 0; i < grp->npins; i++) {
 162                 if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
 163                         new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
 164                         new_map[j].data.configs.group_or_pin =
 165                                         pin_get_name(pctldev, grp->pins[i]);
 166                         new_map[j].data.configs.configs = &grp->configs[i];
 167                         new_map[j].data.configs.num_configs = 1;
 168                         j++;
 169                 }
 170         }
 171
 172         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 173                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 174
 175         return 0;
 176 }
 177
 178 static void imx_dt_free_map(struct pinctrl_dev *pctldev,
 179                                 struct pinctrl_map *map, unsigned num_maps)
 180 {
 181         kfree(map);
 182 }
 183
 184 static const struct pinctrl_ops imx_pctrl_ops = {
 185         .get_groups_count = imx_get_groups_count,
 186         .get_group_name = imx_get_group_name,
 187         .get_group_pins = imx_get_group_pins,
 188         .pin_dbg_show = imx_pin_dbg_show,
 189         .dt_node_to_map = imx_dt_node_to_map,
 190         .dt_free_map = imx_dt_free_map,
 191
 192 };
 193
 194 static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 195                            unsigned group)
 196 {
 197         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 198         const struct imx_pinctrl_soc_info *info = ipctl->info;
 199         const struct imx_pin_reg *pin_reg;
 200         const unsigned *pins, *mux, *input_val;
 201         u16 *input_reg;
 202         unsigned int npins, pin_id;
 203         int i;
 204
 205         /*
 206          * Configure the mux mode for each pin in the group for a specific
 207          * function.
 208          */
 209         pins = info->groups[group].pins;
 210         npins = info->groups[group].npins;
 211         mux = info->groups[group].mux_mode;
 212         input_val = info->groups[group].input_val;
 213         input_reg = info->groups[group].input_reg;
 214
 215         WARN_ON(!pins || !npins || !mux || !input_val || !input_reg);
 216
 217         dev_dbg(ipctl->dev, "enable function %s group %s\n",
 218                 info->functions[selector].name, info->groups[group].name);
 219
 220         for (i = 0; i < npins; i++) {
 221                 pin_id = pins[i];
 222                 pin_reg = &info->pin_regs[pin_id];
 223
 224                 if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
 225                         dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
 226                                 info->pins[pin_id].name);
 227                         return -EINVAL;
 228                 }
 229
 230                 if (info->flags & SHARE_MUX_CONF_REG) {
 231                         u32 reg;
 232                         reg = readl(ipctl->base + pin_reg->mux_reg);
 233                         reg &= ~(0x7 << 20);
 234                         reg |= (mux[i] << 20);
 235                         writel(reg, ipctl->base + pin_reg->mux_reg);
 236                 } else {
 237                         writel(mux[i], ipctl->base + pin_reg->mux_reg);
 238                 }
 239                 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 240                         pin_reg->mux_reg, mux[i]);
 241
 242                 /*
 243                  * If the select input value begins with 0xff, it's a quirky
 244                  * select input and the value should be interpreted as below.
 245                  *     31     23      15      7        0
 246                  *     | 0xff | shift | width | select |
 247                  * It's used to work around the problem that the select
 248                  * input for some pin is not implemented in the select
 249                  * input register but in some general purpose register.
 250                  * We encode the select input value, width and shift of
 251                  * the bit field into input_val cell of pin function ID
 252                  * in device tree, and then decode them here for setting
 253                  * up the select input bits in general purpose register.
 254                  */
 255                 if (input_val[i] >> 24 == 0xff) {
 256                         u32 val = input_val[i];
 257                         u8 select = val & 0xff;
 258                         u8 width = (val >> 8) & 0xff;
 259                         u8 shift = (val >> 16) & 0xff;
 260                         u32 mask = ((1 << width) - 1) << shift;
 261                         /*
 262                          * The input_reg[i] here is actually some IOMUXC general
 263                          * purpose register, not regular select input register.
 264                          */
 265                         val = readl(ipctl->base + input_reg[i]);
 266                         val &= ~mask;
 267                         val |= select << shift;
 268                         writel(val, ipctl->base + input_reg[i]);
 269                 } else if (input_reg[i]) {
 270                         /*
 271                          * Regular select input register can never be at offset
 272                          * 0, and we only print register value for regular case.
 273                          */
 274                         writel(input_val[i], ipctl->base + input_reg[i]);
 275                         dev_dbg(ipctl->dev,
 276                                 "==>select_input: offset 0x%x val 0x%x\n",
 277                                 input_reg[i], input_val[i]);
 278                 }
 279         }
 280
 281         return 0;
 282 }
 283
 284 static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 285 {
 286         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 287         const struct imx_pinctrl_soc_info *info = ipctl->info;
 288
 289         return info->nfunctions;
 290 }
 291
 292 static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
 293                                           unsigned selector)
 294 {
 295         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 296         const struct imx_pinctrl_soc_info *info = ipctl->info;
 297
 298         return info->functions[selector].name;
 299 }
 300
 301 static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 302                                const char * const **groups,
 303                                unsigned * const num_groups)
 304 {
 305         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 306         const struct imx_pinctrl_soc_info *info = ipctl->info;
 307
 308         *groups = info->functions[selector].groups;
 309         *num_groups = info->functions[selector].num_groups;
 310
 311         return 0;
 312 }
 313
 314 static const struct pinmux_ops imx_pmx_ops = {
 315         .get_functions_count = imx_pmx_get_funcs_count,
 316         .get_function_name = imx_pmx_get_func_name,
 317         .get_function_groups = imx_pmx_get_groups,
 318         .enable = imx_pmx_enable,
 319 };
 320
 321 static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 322                              unsigned pin_id, unsigned long *config)
 323 {
 324         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 325         const struct imx_pinctrl_soc_info *info = ipctl->info;
 326         const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 327
 328         if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
 329                 dev_err(info->dev, "Pin(%s) does not support config function\n",
 330                         info->pins[pin_id].name);
 331                 return -EINVAL;
 332         }
 333
 334         *config = readl(ipctl->base + pin_reg->conf_reg);
 335
 336         if (info->flags & SHARE_MUX_CONF_REG)
 337                 *config &= 0xffff;
 338
 339         return 0;
 340 }
 341
 342 static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 343                              unsigned pin_id, unsigned long config)
 344 {
 345         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 346         const struct imx_pinctrl_soc_info *info = ipctl->info;
 347         const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 348
 349         if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
 350                 dev_err(info->dev, "Pin(%s) does not support config function\n",
 351                         info->pins[pin_id].name);
 352                 return -EINVAL;
 353         }
 354
 355         dev_dbg(ipctl->dev, "pinconf set pin %s\n",
 356                 info->pins[pin_id].name);
 357
 358         if (info->flags & SHARE_MUX_CONF_REG) {
 359                 u32 reg;
 360                 reg = readl(ipctl->base + pin_reg->conf_reg);
 361                 reg &= ~0xffff;
 362                 reg |= config;
 363                 writel(reg, ipctl->base + pin_reg->conf_reg);
 364         } else {
 365                 writel(config, ipctl->base + pin_reg->conf_reg);
 366         }
 367         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
 368                 pin_reg->conf_reg, config);
 369
 370         return 0;
 371 }
 372
 373 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 374                                    struct seq_file *s, unsigned pin_id)
 375 {
 376         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 377         const struct imx_pinctrl_soc_info *info = ipctl->info;
 378         const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 379         unsigned long config;
 380
 381         if (!pin_reg || !pin_reg->conf_reg) {
 382                 seq_printf(s, "N/A");
 383                 return;
 384         }
 385
 386         config = readl(ipctl->base + pin_reg->conf_reg);
 387         seq_printf(s, "0x%lx", config);
 388 }
 389
 390 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 391                                          struct seq_file *s, unsigned group)
 392 {
 393         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 394         const struct imx_pinctrl_soc_info *info = ipctl->info;
 395         struct imx_pin_group *grp;
 396         unsigned long config;
 397         const char *name;
 398         int i, ret;
 399
 400         if (group > info->ngroups)
 401                 return;
 402
 403         seq_printf(s, "\n");
 404         grp = &info->groups[group];
 405         for (i = 0; i < grp->npins; i++) {
 406                 name = pin_get_name(pctldev, grp->pins[i]);
 407                 ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
 408                 if (ret)
 409                         return;
 410                 seq_printf(s, "%s: 0x%lx", name, config);
 411         }
 412 }
 413
 414 static const struct pinconf_ops imx_pinconf_ops = {
 415         .pin_config_get = imx_pinconf_get,
 416         .pin_config_set = imx_pinconf_set,
 417         .pin_config_dbg_show = imx_pinconf_dbg_show,
 418         .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
 419 };
 420
 421 static struct pinctrl_desc imx_pinctrl_desc = {
 422         .pctlops = &imx_pctrl_ops,
 423         .pmxops = &imx_pmx_ops,
 424         .confops = &imx_pinconf_ops,
 425         .owner = THIS_MODULE,
 426 };
 427
 428 /*
 429  * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
 430  * 1 u32 CONFIG, so 24 types in total for each pin.
 431  */
 432 #define FSL_PIN_SIZE 24
 433 #define SHARE_FSL_PIN_SIZE 20
 434
 435 static int imx_pinctrl_parse_groups(struct device_node *np,
 436                                     struct imx_pin_group *grp,
 437                                     struct imx_pinctrl_soc_info *info,
 438                                     u32 index)
 439 {
 440         int size, pin_size;
 441         const __be32 *list;
 442         int i;
 443         u32 config;
 444
 445         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 446
 447         if (info->flags & SHARE_MUX_CONF_REG)
 448                 pin_size = SHARE_FSL_PIN_SIZE;
 449         else
 450                 pin_size = FSL_PIN_SIZE;
 451         /* Initialise group */
 452         grp->name = np->name;
 453
 454         /*
 455          * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
 456          * do sanity check and calculate pins number
 457          */
 458         list = of_get_property(np, "fsl,pins", &size);
 459         if (!list) {
 460                 dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
 461                 return -EINVAL;
 462         }
 463
 464         /* we do not check return since it's safe node passed down */
 465         if (!size || size % pin_size) {
 466                 dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name);
 467                 return -EINVAL;
 468         }
 469
 470         grp->npins = size / pin_size;
 471         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 472                                 GFP_KERNEL);
 473         grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 474                                 GFP_KERNEL);
 475         grp->input_reg = devm_kzalloc(info->dev, grp->npins * sizeof(u16),
 476                                 GFP_KERNEL);
 477         grp->input_val = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 478                                 GFP_KERNEL);
 479         grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
 480                                 GFP_KERNEL);
 481         for (i = 0; i < grp->npins; i++) {
 482                 u32 mux_reg = be32_to_cpu(*list++);
 483                 u32 conf_reg;
 484                 unsigned int pin_id;
 485                 struct imx_pin_reg *pin_reg;
 486
 487                 if (info->flags & SHARE_MUX_CONF_REG)
 488                         conf_reg = mux_reg;
 489                 else
 490                         conf_reg = be32_to_cpu(*list++);
 491
 492                 pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
 493                 pin_reg = &info->pin_regs[pin_id];
 494                 grp->pins[i] = pin_id;
 495                 pin_reg->mux_reg = mux_reg;
 496                 pin_reg->conf_reg = conf_reg;
 497                 grp->input_reg[i] = be32_to_cpu(*list++);
 498                 grp->mux_mode[i] = be32_to_cpu(*list++);
 499                 grp->input_val[i] = be32_to_cpu(*list++);
 500
 501                 /* SION bit is in mux register */
 502                 config = be32_to_cpu(*list++);
 503                 if (config & IMX_PAD_SION)
 504                         grp->mux_mode[i] |= IOMUXC_CONFIG_SION;
 505                 grp->configs[i] = config & ~IMX_PAD_SION;
 506         }
 507
 508 #ifdef DEBUG
 509         IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
 510 #endif
 511
 512         return 0;
 513 }
 514
 515 static int imx_pinctrl_parse_functions(struct device_node *np,
 516                                        struct imx_pinctrl_soc_info *info,
 517                                        u32 index)
 518 {
 519         struct device_node *child;
 520         struct imx_pmx_func *func;
 521         struct imx_pin_group *grp;
 522         static u32 grp_index;
 523         u32 i = 0;
 524
 525         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
 526
 527         func = &info->functions[index];
 528
 529         /* Initialise function */
 530         func->name = np->name;
 531         func->num_groups = of_get_child_count(np);
 532         if (func->num_groups <= 0) {
 533                 dev_err(info->dev, "no groups defined in %s\n", np->full_name);
 534                 return -EINVAL;
 535         }
 536         func->groups = devm_kzalloc(info->dev,
 537                         func->num_groups * sizeof(char *), GFP_KERNEL);
 538
 539         for_each_child_of_node(np, child) {
 540                 func->groups[i] = child->name;
 541                 grp = &info->groups[grp_index++];
 542                 imx_pinctrl_parse_groups(child, grp, info, i++);
 543         }
 544
 545         return 0;
 546 }
 547
 548 static int imx_pinctrl_probe_dt(struct platform_device *pdev,
 549                                 struct imx_pinctrl_soc_info *info)
 550 {
 551         struct device_node *np = pdev->dev.of_node;
 552         struct device_node *child;
 553         int ret;
 554         u32 nfuncs = 0;
 555         u32 i = 0;
 556
 557         if (!np)
 558                 return -ENODEV;
 559
 560         nfuncs = of_get_child_count(np);
 561         if (nfuncs <= 0) {
 562                 dev_err(&pdev->dev, "no functions defined\n");
 563                 return -EINVAL;
 564         }
 565
 566         info->nfunctions = nfuncs;
 567         info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
 568                                         GFP_KERNEL);
 569         if (!info->functions)
 570                 return -ENOMEM;
 571
 572         info->ngroups = 0;
 573         for_each_child_of_node(np, child)
 574                 info->ngroups += of_get_child_count(child);
 575         info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
 576                                         GFP_KERNEL);
 577         if (!info->groups)
 578                 return -ENOMEM;
 579
 580         for_each_child_of_node(np, child) {
 581                 ret = imx_pinctrl_parse_functions(child, info, i++);
 582                 if (ret) {
 583                         dev_err(&pdev->dev, "failed to parse function\n");
 584                         return ret;
 585                 }
 586         }
 587
 588         return 0;
 589 }
 590
 591 int imx_pinctrl_probe(struct platform_device *pdev,
 592                       struct imx_pinctrl_soc_info *info)
 593 {
 594         struct imx_pinctrl *ipctl;
 595         struct resource *res;
 596         int ret;
 597
 598         if (!info || !info->pins || !info->npins) {
 599                 dev_err(&pdev->dev, "wrong pinctrl info\n");
 600                 return -EINVAL;
 601         }
 602         info->dev = &pdev->dev;
 603
 604         /* Create state holders etc for this driver */
 605         ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
 606         if (!ipctl)
 607                 return -ENOMEM;
 608
 609         info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) *
 610                                       info->npins, GFP_KERNEL);
 611         if (!info->pin_regs)
 612                 return -ENOMEM;
 613
 614         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 615         ipctl->base = devm_ioremap_resource(&pdev->dev, res);
 616         if (IS_ERR(ipctl->base))
 617                 return PTR_ERR(ipctl->base);
 618
 619         imx_pinctrl_desc.name = dev_name(&pdev->dev);
 620         imx_pinctrl_desc.pins = info->pins;
 621         imx_pinctrl_desc.npins = info->npins;
 622
 623         ret = imx_pinctrl_probe_dt(pdev, info);
 624         if (ret) {
 625                 dev_err(&pdev->dev, "fail to probe dt properties\n");
 626                 return ret;
 627         }
 628
 629         ipctl->info = info;
 630         ipctl->dev = info->dev;
 631         platform_set_drvdata(pdev, ipctl);
 632         ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
 633         if (!ipctl->pctl) {
 634                 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
 635                 return -EINVAL;
 636         }
 637
 638         dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
 639
 640         return 0;
 641 }
 642
 643 int imx_pinctrl_remove(struct platform_device *pdev)
 644 {
 645         struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
 646
 647         pinctrl_unregister(ipctl->pctl);
 648
 649         return 0;
 650 }