drivers/pinctrl/pinctrl-cy8c95x0.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support
   4  *
   5  * Copyright (C) 2022 9elements GmbH
   6  * Authors: Patrick Rudolph <patrick.rudolph@9elements.com>
   7  *          Naresh Solanki <Naresh.Solanki@9elements.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/bitmap.h>
  12 #include <linux/dmi.h>
  13 #include <linux/gpio/driver.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/i2c.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/mod_devicetable.h>
  19 #include <linux/module.h>
  20 #include <linux/property.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/consumer.h>
  23
  24 #include <linux/pinctrl/pinctrl.h>
  25 #include <linux/pinctrl/pinconf.h>
  26 #include <linux/pinctrl/pinconf-generic.h>
  27 #include <linux/pinctrl/pinmux.h>
  28
  29 /* Fast access registers */
  30 #define CY8C95X0_INPUT          0x00
  31 #define CY8C95X0_OUTPUT         0x08
  32 #define CY8C95X0_INTSTATUS      0x10
  33
  34 #define CY8C95X0_INPUT_(x)      (CY8C95X0_INPUT + (x))
  35 #define CY8C95X0_OUTPUT_(x)     (CY8C95X0_OUTPUT + (x))
  36 #define CY8C95X0_INTSTATUS_(x)  (CY8C95X0_INTSTATUS + (x))
  37
  38 /* Port Select configures the port */
  39 #define CY8C95X0_PORTSEL        0x18
  40 /* Port settings, write PORTSEL first */
  41 #define CY8C95X0_INTMASK        0x19
  42 #define CY8C95X0_PWMSEL         0x1A
  43 #define CY8C95X0_INVERT         0x1B
  44 #define CY8C95X0_DIRECTION      0x1C
  45 /* Drive mode register change state on writing '1' */
  46 #define CY8C95X0_DRV_PU         0x1D
  47 #define CY8C95X0_DRV_PD         0x1E
  48 #define CY8C95X0_DRV_ODH        0x1F
  49 #define CY8C95X0_DRV_ODL        0x20
  50 #define CY8C95X0_DRV_PP_FAST    0x21
  51 #define CY8C95X0_DRV_PP_SLOW    0x22
  52 #define CY8C95X0_DRV_HIZ        0x23
  53 #define CY8C95X0_DEVID          0x2E
  54 #define CY8C95X0_WATCHDOG       0x2F
  55 #define CY8C95X0_COMMAND        0x30
  56
  57 #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))
  58
  59 static const struct i2c_device_id cy8c95x0_id[] = {
  60         { "cy8c9520", 20, },
  61         { "cy8c9540", 40, },
  62         { "cy8c9560", 60, },
  63         { }
  64 };
  65 MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
  66
  67 #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))
  68
  69 static const struct of_device_id cy8c95x0_dt_ids[] = {
  70         { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), },
  71         { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), },
  72         { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), },
  73         { }
  74 };
  75 MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);
  76
  77 static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true };
  78
  79 static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = {
  80         { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
  81         { }
  82 };
  83
  84 static int cy8c95x0_acpi_get_irq(struct device *dev)
  85 {
  86         int ret;
  87
  88         ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios);
  89         if (ret)
  90                 dev_warn(dev, "can't add GPIO ACPI mapping\n");
  91
  92         ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0);
  93         if (ret < 0)
  94                 return ret;
  95
  96         dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
  97         return ret;
  98 }
  99
 100 static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
 101         {
 102                 /*
 103                  * On Intel Galileo Gen 1 board the IRQ pin is provided
 104                  * as an absolute number instead of being relative.
 105                  * Since first controller (gpio-sch.c) and second
 106                  * (gpio-dwapb.c) are at the fixed bases, we may safely
 107                  * refer to the number in the global space to get an IRQ
 108                  * out of it.
 109                  */
 110                 .matches = {
 111                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
 112                 },
 113         },
 114         {}
 115 };
 116
 117 #define MAX_BANK 8
 118 #define BANK_SZ 8
 119 #define MAX_LINE        (MAX_BANK * BANK_SZ)
 120
 121 #define CY8C95X0_GPIO_MASK              GENMASK(7, 0)
 122
 123 /**
 124  * struct cy8c95x0_pinctrl - driver data
 125  * @regmap:         Device's regmap
 126  * @irq_lock:       IRQ bus lock
 127  * @i2c_lock:       Mutex for the device internal mux register
 128  * @irq_mask:       I/O bits affected by interrupts
 129  * @irq_trig_raise: I/O bits affected by raising voltage level
 130  * @irq_trig_fall:  I/O bits affected by falling voltage level
 131  * @irq_trig_low:   I/O bits affected by a low voltage level
 132  * @irq_trig_high:  I/O bits affected by a high voltage level
 133  * @push_pull:      I/O bits configured as push pull driver
 134  * @shiftmask:      Mask used to compensate for Gport2 width
 135  * @nport:          Number of Gports in this chip
 136  * @gpio_chip:      gpiolib chip
 137  * @driver_data:    private driver data
 138  * @regulator:      Pointer to the regulator for the IC
 139  * @dev:            struct device
 140  * @pctldev:        pin controller device
 141  * @pinctrl_desc:   pin controller description
 142  * @name:           Chip controller name
 143  * @tpin:           Total number of pins
 144  */
 145 struct cy8c95x0_pinctrl {
 146         struct regmap *regmap;
 147         struct mutex irq_lock;
 148         struct mutex i2c_lock;
 149         DECLARE_BITMAP(irq_mask, MAX_LINE);
 150         DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
 151         DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
 152         DECLARE_BITMAP(irq_trig_low, MAX_LINE);
 153         DECLARE_BITMAP(irq_trig_high, MAX_LINE);
 154         DECLARE_BITMAP(push_pull, MAX_LINE);
 155         DECLARE_BITMAP(shiftmask, MAX_LINE);
 156         int nport;
 157         struct gpio_chip gpio_chip;
 158         unsigned long driver_data;
 159         struct regulator *regulator;
 160         struct device *dev;
 161         struct pinctrl_dev *pctldev;
 162         struct pinctrl_desc pinctrl_desc;
 163         char name[32];
 164         unsigned int tpin;
 165 };
 166
 167 static const struct pinctrl_pin_desc cy8c9560_pins[] = {
 168         PINCTRL_PIN(0, "gp00"),
 169         PINCTRL_PIN(1, "gp01"),
 170         PINCTRL_PIN(2, "gp02"),
 171         PINCTRL_PIN(3, "gp03"),
 172         PINCTRL_PIN(4, "gp04"),
 173         PINCTRL_PIN(5, "gp05"),
 174         PINCTRL_PIN(6, "gp06"),
 175         PINCTRL_PIN(7, "gp07"),
 176
 177         PINCTRL_PIN(8, "gp10"),
 178         PINCTRL_PIN(9, "gp11"),
 179         PINCTRL_PIN(10, "gp12"),
 180         PINCTRL_PIN(11, "gp13"),
 181         PINCTRL_PIN(12, "gp14"),
 182         PINCTRL_PIN(13, "gp15"),
 183         PINCTRL_PIN(14, "gp16"),
 184         PINCTRL_PIN(15, "gp17"),
 185
 186         PINCTRL_PIN(16, "gp20"),
 187         PINCTRL_PIN(17, "gp21"),
 188         PINCTRL_PIN(18, "gp22"),
 189         PINCTRL_PIN(19, "gp23"),
 190
 191         PINCTRL_PIN(20, "gp30"),
 192         PINCTRL_PIN(21, "gp31"),
 193         PINCTRL_PIN(22, "gp32"),
 194         PINCTRL_PIN(23, "gp33"),
 195         PINCTRL_PIN(24, "gp34"),
 196         PINCTRL_PIN(25, "gp35"),
 197         PINCTRL_PIN(26, "gp36"),
 198         PINCTRL_PIN(27, "gp37"),
 199
 200         PINCTRL_PIN(28, "gp40"),
 201         PINCTRL_PIN(29, "gp41"),
 202         PINCTRL_PIN(30, "gp42"),
 203         PINCTRL_PIN(31, "gp43"),
 204         PINCTRL_PIN(32, "gp44"),
 205         PINCTRL_PIN(33, "gp45"),
 206         PINCTRL_PIN(34, "gp46"),
 207         PINCTRL_PIN(35, "gp47"),
 208
 209         PINCTRL_PIN(36, "gp50"),
 210         PINCTRL_PIN(37, "gp51"),
 211         PINCTRL_PIN(38, "gp52"),
 212         PINCTRL_PIN(39, "gp53"),
 213         PINCTRL_PIN(40, "gp54"),
 214         PINCTRL_PIN(41, "gp55"),
 215         PINCTRL_PIN(42, "gp56"),
 216         PINCTRL_PIN(43, "gp57"),
 217
 218         PINCTRL_PIN(44, "gp60"),
 219         PINCTRL_PIN(45, "gp61"),
 220         PINCTRL_PIN(46, "gp62"),
 221         PINCTRL_PIN(47, "gp63"),
 222         PINCTRL_PIN(48, "gp64"),
 223         PINCTRL_PIN(49, "gp65"),
 224         PINCTRL_PIN(50, "gp66"),
 225         PINCTRL_PIN(51, "gp67"),
 226
 227         PINCTRL_PIN(52, "gp70"),
 228         PINCTRL_PIN(53, "gp71"),
 229         PINCTRL_PIN(54, "gp72"),
 230         PINCTRL_PIN(55, "gp73"),
 231         PINCTRL_PIN(56, "gp74"),
 232         PINCTRL_PIN(57, "gp75"),
 233         PINCTRL_PIN(58, "gp76"),
 234         PINCTRL_PIN(59, "gp77"),
 235 };
 236
 237 static const char * const cy8c95x0_groups[] = {
 238         "gp00",
 239         "gp01",
 240         "gp02",
 241         "gp03",
 242         "gp04",
 243         "gp05",
 244         "gp06",
 245         "gp07",
 246
 247         "gp10",
 248         "gp11",
 249         "gp12",
 250         "gp13",
 251         "gp14",
 252         "gp15",
 253         "gp16",
 254         "gp17",
 255
 256         "gp20",
 257         "gp21",
 258         "gp22",
 259         "gp23",
 260
 261         "gp30",
 262         "gp31",
 263         "gp32",
 264         "gp33",
 265         "gp34",
 266         "gp35",
 267         "gp36",
 268         "gp37",
 269
 270         "gp40",
 271         "gp41",
 272         "gp42",
 273         "gp43",
 274         "gp44",
 275         "gp45",
 276         "gp46",
 277         "gp47",
 278
 279         "gp50",
 280         "gp51",
 281         "gp52",
 282         "gp53",
 283         "gp54",
 284         "gp55",
 285         "gp56",
 286         "gp57",
 287
 288         "gp60",
 289         "gp61",
 290         "gp62",
 291         "gp63",
 292         "gp64",
 293         "gp65",
 294         "gp66",
 295         "gp67",
 296
 297         "gp70",
 298         "gp71",
 299         "gp72",
 300         "gp73",
 301         "gp74",
 302         "gp75",
 303         "gp76",
 304         "gp77",
 305 };
 306
 307 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin)
 308 {
 309         /* Account for GPORT2 which only has 4 bits */
 310         return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ;
 311 }
 312
 313 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)
 314 {
 315         /* Account for GPORT2 which only has 4 bits */
 316         return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ);
 317 }
 318
 319 static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
 320 {
 321         switch (reg) {
 322         case 0x24 ... 0x27:
 323                 return false;
 324         default:
 325                 return true;
 326         }
 327 }
 328
 329 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)
 330 {
 331         switch (reg) {
 332         case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
 333                 return false;
 334         case CY8C95X0_DEVID:
 335                 return false;
 336         case 0x24 ... 0x27:
 337                 return false;
 338         default:
 339                 return true;
 340         }
 341 }
 342
 343 static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg)
 344 {
 345         switch (reg) {
 346         case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
 347         case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
 348         case CY8C95X0_INTMASK:
 349         case CY8C95X0_INVERT:
 350         case CY8C95X0_PWMSEL:
 351         case CY8C95X0_DIRECTION:
 352         case CY8C95X0_DRV_PU:
 353         case CY8C95X0_DRV_PD:
 354         case CY8C95X0_DRV_ODH:
 355         case CY8C95X0_DRV_ODL:
 356         case CY8C95X0_DRV_PP_FAST:
 357         case CY8C95X0_DRV_PP_SLOW:
 358         case CY8C95X0_DRV_HIZ:
 359                 return true;
 360         default:
 361                 return false;
 362         }
 363 }
 364
 365 static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg)
 366 {
 367         switch (reg) {
 368         case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
 369                 return true;
 370         default:
 371                 return false;
 372         }
 373 }
 374
 375 static const struct reg_default cy8c95x0_reg_defaults[] = {
 376         { CY8C95X0_OUTPUT_(0), GENMASK(7, 0) },
 377         { CY8C95X0_OUTPUT_(1), GENMASK(7, 0) },
 378         { CY8C95X0_OUTPUT_(2), GENMASK(7, 0) },
 379         { CY8C95X0_OUTPUT_(3), GENMASK(7, 0) },
 380         { CY8C95X0_OUTPUT_(4), GENMASK(7, 0) },
 381         { CY8C95X0_OUTPUT_(5), GENMASK(7, 0) },
 382         { CY8C95X0_OUTPUT_(6), GENMASK(7, 0) },
 383         { CY8C95X0_OUTPUT_(7), GENMASK(7, 0) },
 384         { CY8C95X0_PORTSEL, 0 },
 385         { CY8C95X0_PWMSEL, 0 },
 386 };
 387
 388 static const struct regmap_config cy8c95x0_i2c_regmap = {
 389         .reg_bits = 8,
 390         .val_bits = 8,
 391
 392         .reg_defaults = cy8c95x0_reg_defaults,
 393         .num_reg_defaults = ARRAY_SIZE(cy8c95x0_reg_defaults),
 394
 395         .readable_reg = cy8c95x0_readable_register,
 396         .writeable_reg = cy8c95x0_writeable_register,
 397         .volatile_reg = cy8c95x0_volatile_register,
 398         .precious_reg = cy8c95x0_precious_register,
 399
 400         .cache_type = REGCACHE_FLAT,
 401         .max_register = CY8C95X0_COMMAND,
 402 };
 403
 404 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
 405                                     unsigned long *val, unsigned long *mask)
 406 {
 407         DECLARE_BITMAP(tmask, MAX_LINE);
 408         DECLARE_BITMAP(tval, MAX_LINE);
 409         int write_val;
 410         int ret = 0;
 411         int i, off = 0;
 412         u8 bits;
 413
 414         /* Add the 4 bit gap of Gport2 */
 415         bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
 416         bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
 417         bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
 418
 419         bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
 420         bitmap_shift_left(tval, tval, 4, MAX_LINE);
 421         bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
 422
 423         mutex_lock(&chip->i2c_lock);
 424         for (i = 0; i < chip->nport; i++) {
 425                 /* Skip over unused banks */
 426                 bits = bitmap_get_value8(tmask, i * BANK_SZ);
 427                 if (!bits)
 428                         continue;
 429
 430                 switch (reg) {
 431                 /* Muxed registers */
 432                 case CY8C95X0_INTMASK:
 433                 case CY8C95X0_PWMSEL:
 434                 case CY8C95X0_INVERT:
 435                 case CY8C95X0_DIRECTION:
 436                 case CY8C95X0_DRV_PU:
 437                 case CY8C95X0_DRV_PD:
 438                 case CY8C95X0_DRV_ODH:
 439                 case CY8C95X0_DRV_ODL:
 440                 case CY8C95X0_DRV_PP_FAST:
 441                 case CY8C95X0_DRV_PP_SLOW:
 442                 case CY8C95X0_DRV_HIZ:
 443                         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i);
 444                         if (ret < 0)
 445                                 goto out;
 446                         off = reg;
 447                         break;
 448                 /* Direct access registers */
 449                 case CY8C95X0_INPUT:
 450                 case CY8C95X0_OUTPUT:
 451                 case CY8C95X0_INTSTATUS:
 452                         off = reg + i;
 453                         break;
 454                 default:
 455                         ret = -EINVAL;
 456                         goto out;
 457                 }
 458
 459                 write_val = bitmap_get_value8(tval, i * BANK_SZ);
 460
 461                 ret = regmap_update_bits(chip->regmap, off, bits, write_val);
 462                 if (ret < 0)
 463                         goto out;
 464         }
 465 out:
 466         mutex_unlock(&chip->i2c_lock);
 467
 468         if (ret < 0)
 469                 dev_err(chip->dev, "failed writing register %d: err %d\n", off, ret);
 470
 471         return ret;
 472 }
 473
 474 static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
 475                                    unsigned long *val, unsigned long *mask)
 476 {
 477         DECLARE_BITMAP(tmask, MAX_LINE);
 478         DECLARE_BITMAP(tval, MAX_LINE);
 479         DECLARE_BITMAP(tmp, MAX_LINE);
 480         int read_val;
 481         int ret = 0;
 482         int i, off = 0;
 483         u8 bits;
 484
 485         /* Add the 4 bit gap of Gport2 */
 486         bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
 487         bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
 488         bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
 489
 490         bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
 491         bitmap_shift_left(tval, tval, 4, MAX_LINE);
 492         bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
 493
 494         mutex_lock(&chip->i2c_lock);
 495         for (i = 0; i < chip->nport; i++) {
 496                 /* Skip over unused banks */
 497                 bits = bitmap_get_value8(tmask, i * BANK_SZ);
 498                 if (!bits)
 499                         continue;
 500
 501                 switch (reg) {
 502                 /* Muxed registers */
 503                 case CY8C95X0_INTMASK:
 504                 case CY8C95X0_PWMSEL:
 505                 case CY8C95X0_INVERT:
 506                 case CY8C95X0_DIRECTION:
 507                 case CY8C95X0_DRV_PU:
 508                 case CY8C95X0_DRV_PD:
 509                 case CY8C95X0_DRV_ODH:
 510                 case CY8C95X0_DRV_ODL:
 511                 case CY8C95X0_DRV_PP_FAST:
 512                 case CY8C95X0_DRV_PP_SLOW:
 513                 case CY8C95X0_DRV_HIZ:
 514                         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i);
 515                         if (ret < 0)
 516                                 goto out;
 517                         off = reg;
 518                         break;
 519                 /* Direct access registers */
 520                 case CY8C95X0_INPUT:
 521                 case CY8C95X0_OUTPUT:
 522                 case CY8C95X0_INTSTATUS:
 523                         off = reg + i;
 524                         break;
 525                 default:
 526                         ret = -EINVAL;
 527                         goto out;
 528                 }
 529
 530                 ret = regmap_read(chip->regmap, off, &read_val);
 531                 if (ret < 0)
 532                         goto out;
 533
 534                 read_val &= bits;
 535                 read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits;
 536                 bitmap_set_value8(tval, read_val, i * BANK_SZ);
 537         }
 538
 539         /* Fill the 4 bit gap of Gport2 */
 540         bitmap_shift_right(tmp, tval, 4, MAX_LINE);
 541         bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE);
 542
 543 out:
 544         mutex_unlock(&chip->i2c_lock);
 545
 546         if (ret < 0)
 547                 dev_err(chip->dev, "failed reading register %d: err %d\n", off, ret);
 548
 549         return ret;
 550 }
 551
 552 static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off)
 553 {
 554         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 555         u8 port = cypress_get_port(chip, off);
 556         u8 bit = cypress_get_pin_mask(chip, off);
 557         int ret;
 558
 559         mutex_lock(&chip->i2c_lock);
 560         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 561         if (ret)
 562                 goto out;
 563
 564         ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit);
 565         if (ret)
 566                 goto out;
 567
 568         if (test_bit(off, chip->push_pull)) {
 569                 /*
 570                  * Disable driving the pin by forcing it to HighZ. Only setting the
 571                  * direction register isn't sufficient in Push-Pull mode.
 572                  */
 573                 ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit);
 574                 if (ret)
 575                         goto out;
 576                 clear_bit(off, chip->push_pull);
 577         }
 578
 579 out:
 580         mutex_unlock(&chip->i2c_lock);
 581
 582         return ret;
 583 }
 584
 585 static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc,
 586                                           unsigned int off, int val)
 587 {
 588         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 589         u8 port = cypress_get_port(chip, off);
 590         u8 outreg = CY8C95X0_OUTPUT_(port);
 591         u8 bit = cypress_get_pin_mask(chip, off);
 592         int ret;
 593
 594         /* Set output level */
 595         ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
 596         if (ret)
 597                 return ret;
 598
 599         mutex_lock(&chip->i2c_lock);
 600         /* Select port... */
 601         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 602         if (ret)
 603                 goto out;
 604
 605         /* ...then direction */
 606         ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, 0);
 607
 608 out:
 609         mutex_unlock(&chip->i2c_lock);
 610
 611         return ret;
 612 }
 613
 614 static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)
 615 {
 616         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 617         u8 inreg = CY8C95X0_INPUT_(cypress_get_port(chip, off));
 618         u8 bit = cypress_get_pin_mask(chip, off);
 619         u32 reg_val;
 620         int ret;
 621
 622         ret = regmap_read(chip->regmap, inreg, &reg_val);
 623         if (ret < 0) {
 624                 /*
 625                  * NOTE:
 626                  * Diagnostic already emitted; that's all we should
 627                  * do unless gpio_*_value_cansleep() calls become different
 628                  * from their nonsleeping siblings (and report faults).
 629                  */
 630                 return 0;
 631         }
 632
 633         return !!(reg_val & bit);
 634 }
 635
 636 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off,
 637                                     int val)
 638 {
 639         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 640         u8 outreg = CY8C95X0_OUTPUT_(cypress_get_port(chip, off));
 641         u8 bit = cypress_get_pin_mask(chip, off);
 642
 643         regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
 644 }
 645
 646 static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
 647 {
 648         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 649         u8 port = cypress_get_port(chip, off);
 650         u8 bit = cypress_get_pin_mask(chip, off);
 651         u32 reg_val;
 652         int ret;
 653
 654         mutex_lock(&chip->i2c_lock);
 655
 656         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 657         if (ret < 0)
 658                 goto out;
 659
 660         ret = regmap_read(chip->regmap, CY8C95X0_DIRECTION, &reg_val);
 661         if (ret < 0)
 662                 goto out;
 663
 664         mutex_unlock(&chip->i2c_lock);
 665
 666         if (reg_val & bit)
 667                 return GPIO_LINE_DIRECTION_IN;
 668
 669         return GPIO_LINE_DIRECTION_OUT;
 670 out:
 671         mutex_unlock(&chip->i2c_lock);
 672         return ret;
 673 }
 674
 675 static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,
 676                                     unsigned int off,
 677                                     unsigned long *config)
 678 {
 679         enum pin_config_param param = pinconf_to_config_param(*config);
 680         u8 port = cypress_get_port(chip, off);
 681         u8 bit = cypress_get_pin_mask(chip, off);
 682         unsigned int reg;
 683         u32 reg_val;
 684         u16 arg = 0;
 685         int ret;
 686
 687         mutex_lock(&chip->i2c_lock);
 688
 689         /* Select port */
 690         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 691         if (ret < 0)
 692                 goto out;
 693
 694         switch (param) {
 695         case PIN_CONFIG_BIAS_PULL_UP:
 696                 reg = CY8C95X0_DRV_PU;
 697                 break;
 698         case PIN_CONFIG_BIAS_PULL_DOWN:
 699                 reg = CY8C95X0_DRV_PD;
 700                 break;
 701         case PIN_CONFIG_BIAS_DISABLE:
 702                 reg = CY8C95X0_DRV_HIZ;
 703                 break;
 704         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 705                 reg = CY8C95X0_DRV_ODL;
 706                 break;
 707         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 708                 reg = CY8C95X0_DRV_ODH;
 709                 break;
 710         case PIN_CONFIG_DRIVE_PUSH_PULL:
 711                 reg = CY8C95X0_DRV_PP_FAST;
 712                 break;
 713         case PIN_CONFIG_INPUT_ENABLE:
 714                 reg = CY8C95X0_DIRECTION;
 715                 break;
 716         case PIN_CONFIG_MODE_PWM:
 717                 reg = CY8C95X0_PWMSEL;
 718                 break;
 719         case PIN_CONFIG_OUTPUT:
 720                 reg = CY8C95X0_OUTPUT_(port);
 721                 break;
 722         case PIN_CONFIG_OUTPUT_ENABLE:
 723                 reg = CY8C95X0_DIRECTION;
 724                 break;
 725
 726         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 727         case PIN_CONFIG_BIAS_BUS_HOLD:
 728         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 729         case PIN_CONFIG_DRIVE_STRENGTH:
 730         case PIN_CONFIG_DRIVE_STRENGTH_UA:
 731         case PIN_CONFIG_INPUT_DEBOUNCE:
 732         case PIN_CONFIG_INPUT_SCHMITT:
 733         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 734         case PIN_CONFIG_MODE_LOW_POWER:
 735         case PIN_CONFIG_PERSIST_STATE:
 736         case PIN_CONFIG_POWER_SOURCE:
 737         case PIN_CONFIG_SKEW_DELAY:
 738         case PIN_CONFIG_SLEEP_HARDWARE_STATE:
 739         case PIN_CONFIG_SLEW_RATE:
 740         default:
 741                 ret = -ENOTSUPP;
 742                 goto out;
 743         }
 744         /*
 745          * Writing 1 to one of the drive mode registers will automatically
 746          * clear conflicting set bits in the other drive mode registers.
 747          */
 748         ret = regmap_read(chip->regmap, reg, &reg_val);
 749         if (reg_val & bit)
 750                 arg = 1;
 751
 752         *config = pinconf_to_config_packed(param, (u16)arg);
 753 out:
 754         mutex_unlock(&chip->i2c_lock);
 755
 756         return ret;
 757 }
 758
 759 static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
 760                                     unsigned int off,
 761                                     unsigned long config)
 762 {
 763         u8 port = cypress_get_port(chip, off);
 764         u8 bit = cypress_get_pin_mask(chip, off);
 765         unsigned long param = pinconf_to_config_param(config);
 766         unsigned int reg;
 767         int ret;
 768
 769         mutex_lock(&chip->i2c_lock);
 770
 771         /* Select port */
 772         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 773         if (ret < 0)
 774                 goto out;
 775
 776         switch (param) {
 777         case PIN_CONFIG_BIAS_PULL_UP:
 778                 clear_bit(off, chip->push_pull);
 779                 reg = CY8C95X0_DRV_PU;
 780                 break;
 781         case PIN_CONFIG_BIAS_PULL_DOWN:
 782                 clear_bit(off, chip->push_pull);
 783                 reg = CY8C95X0_DRV_PD;
 784                 break;
 785         case PIN_CONFIG_BIAS_DISABLE:
 786                 clear_bit(off, chip->push_pull);
 787                 reg = CY8C95X0_DRV_HIZ;
 788                 break;
 789         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 790                 clear_bit(off, chip->push_pull);
 791                 reg = CY8C95X0_DRV_ODL;
 792                 break;
 793         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 794                 clear_bit(off, chip->push_pull);
 795                 reg = CY8C95X0_DRV_ODH;
 796                 break;
 797         case PIN_CONFIG_DRIVE_PUSH_PULL:
 798                 set_bit(off, chip->push_pull);
 799                 reg = CY8C95X0_DRV_PP_FAST;
 800                 break;
 801         case PIN_CONFIG_MODE_PWM:
 802                 reg = CY8C95X0_PWMSEL;
 803                 break;
 804         default:
 805                 ret = -ENOTSUPP;
 806                 goto out;
 807         }
 808         /*
 809          * Writing 1 to one of the drive mode registers will automatically
 810          * clear conflicting set bits in the other drive mode registers.
 811          */
 812         ret = regmap_write_bits(chip->regmap, reg, bit, bit);
 813
 814 out:
 815         mutex_unlock(&chip->i2c_lock);
 816         return ret;
 817 }
 818
 819 static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc,
 820                                       unsigned long *mask, unsigned long *bits)
 821 {
 822         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 823
 824         return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask);
 825 }
 826
 827 static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc,
 828                                        unsigned long *mask, unsigned long *bits)
 829 {
 830         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 831
 832         cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask);
 833 }
 834
 835 static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc)
 836 {
 837         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 838         struct device *dev = chip->dev;
 839         int ret;
 840
 841         ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin);
 842         if (ret)
 843                 dev_err(dev, "failed to add GPIO pin range\n");
 844
 845         return ret;
 846 }
 847
 848 static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip)
 849 {
 850         struct gpio_chip *gc = &chip->gpio_chip;
 851
 852         gc->direction_input  = cy8c95x0_gpio_direction_input;
 853         gc->direction_output = cy8c95x0_gpio_direction_output;
 854         gc->get = cy8c95x0_gpio_get_value;
 855         gc->set = cy8c95x0_gpio_set_value;
 856         gc->get_direction = cy8c95x0_gpio_get_direction;
 857         gc->get_multiple = cy8c95x0_gpio_get_multiple;
 858         gc->set_multiple = cy8c95x0_gpio_set_multiple;
 859         gc->set_config = gpiochip_generic_config,
 860         gc->can_sleep = true;
 861         gc->add_pin_ranges = cy8c95x0_add_pin_ranges;
 862
 863         gc->base = -1;
 864         gc->ngpio = chip->tpin;
 865
 866         gc->parent = chip->dev;
 867         gc->owner = THIS_MODULE;
 868         gc->names = NULL;
 869
 870         gc->label = dev_name(chip->dev);
 871
 872         return devm_gpiochip_add_data(chip->dev, gc, chip);
 873 }
 874
 875 static void cy8c95x0_irq_mask(struct irq_data *d)
 876 {
 877         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 878         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 879         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 880
 881         set_bit(hwirq, chip->irq_mask);
 882         gpiochip_disable_irq(gc, hwirq);
 883 }
 884
 885 static void cy8c95x0_irq_unmask(struct irq_data *d)
 886 {
 887         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 888         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 889         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 890
 891         gpiochip_enable_irq(gc, hwirq);
 892         clear_bit(hwirq, chip->irq_mask);
 893 }
 894
 895 static void cy8c95x0_irq_bus_lock(struct irq_data *d)
 896 {
 897         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 898         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 899
 900         mutex_lock(&chip->irq_lock);
 901 }
 902
 903 static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d)
 904 {
 905         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 906         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 907         DECLARE_BITMAP(ones, MAX_LINE);
 908         DECLARE_BITMAP(irq_mask, MAX_LINE);
 909         DECLARE_BITMAP(reg_direction, MAX_LINE);
 910
 911         bitmap_fill(ones, MAX_LINE);
 912
 913         cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones);
 914
 915         /* Switch direction to input if needed */
 916         cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask);
 917         bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE);
 918         bitmap_complement(irq_mask, irq_mask, MAX_LINE);
 919
 920         /* Look for any newly setup interrupt */
 921         cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask);
 922
 923         mutex_unlock(&chip->irq_lock);
 924 }
 925
 926 static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type)
 927 {
 928         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 929         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 930         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 931         unsigned int trig_type;
 932
 933         switch (type) {
 934         case IRQ_TYPE_EDGE_RISING:
 935         case IRQ_TYPE_EDGE_FALLING:
 936         case IRQ_TYPE_EDGE_BOTH:
 937                 trig_type = type;
 938                 break;
 939         case IRQ_TYPE_LEVEL_HIGH:
 940                 trig_type = IRQ_TYPE_EDGE_RISING;
 941                 break;
 942         case IRQ_TYPE_LEVEL_LOW:
 943                 trig_type = IRQ_TYPE_EDGE_FALLING;
 944                 break;
 945         default:
 946                 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type);
 947                 return -EINVAL;
 948         }
 949
 950         assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING);
 951         assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING);
 952         assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW);
 953         assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH);
 954
 955         return 0;
 956 }
 957
 958 static void cy8c95x0_irq_shutdown(struct irq_data *d)
 959 {
 960         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 961         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 962         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 963
 964         clear_bit(hwirq, chip->irq_trig_raise);
 965         clear_bit(hwirq, chip->irq_trig_fall);
 966         clear_bit(hwirq, chip->irq_trig_low);
 967         clear_bit(hwirq, chip->irq_trig_high);
 968 }
 969
 970 static const struct irq_chip cy8c95x0_irqchip = {
 971         .name = "cy8c95x0-irq",
 972         .irq_mask = cy8c95x0_irq_mask,
 973         .irq_unmask = cy8c95x0_irq_unmask,
 974         .irq_bus_lock = cy8c95x0_irq_bus_lock,
 975         .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock,
 976         .irq_set_type = cy8c95x0_irq_set_type,
 977         .irq_shutdown = cy8c95x0_irq_shutdown,
 978         .flags = IRQCHIP_IMMUTABLE,
 979         GPIOCHIP_IRQ_RESOURCE_HELPERS,
 980 };
 981
 982 static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending)
 983 {
 984         DECLARE_BITMAP(ones, MAX_LINE);
 985         DECLARE_BITMAP(cur_stat, MAX_LINE);
 986         DECLARE_BITMAP(new_stat, MAX_LINE);
 987         DECLARE_BITMAP(trigger, MAX_LINE);
 988
 989         bitmap_fill(ones, MAX_LINE);
 990
 991         /* Read the current interrupt status from the device */
 992         if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones))
 993                 return false;
 994
 995         /* Check latched inputs */
 996         if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger))
 997                 return false;
 998
 999         /* Apply filter for rising/falling edge selection */
1000         bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise,
1001                        cur_stat, MAX_LINE);
1002
1003         bitmap_and(pending, new_stat, trigger, MAX_LINE);
1004
1005         return !bitmap_empty(pending, MAX_LINE);
1006 }
1007
1008 static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid)
1009 {
1010         struct cy8c95x0_pinctrl *chip = devid;
1011         struct gpio_chip *gc = &chip->gpio_chip;
1012         DECLARE_BITMAP(pending, MAX_LINE);
1013         int nested_irq, level;
1014         bool ret;
1015
1016         ret = cy8c95x0_irq_pending(chip, pending);
1017         if (!ret)
1018                 return IRQ_RETVAL(0);
1019
1020         ret = 0;
1021         for_each_set_bit(level, pending, MAX_LINE) {
1022                 /* Already accounted for 4bit gap in GPort2 */
1023                 nested_irq = irq_find_mapping(gc->irq.domain, level);
1024
1025                 if (unlikely(nested_irq <= 0)) {
1026                         dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
1027                         continue;
1028                 }
1029
1030                 if (test_bit(level, chip->irq_trig_low))
1031                         while (!cy8c95x0_gpio_get_value(gc, level))
1032                                 handle_nested_irq(nested_irq);
1033                 else if (test_bit(level, chip->irq_trig_high))
1034                         while (cy8c95x0_gpio_get_value(gc, level))
1035                                 handle_nested_irq(nested_irq);
1036                 else
1037                         handle_nested_irq(nested_irq);
1038
1039                 ret = 1;
1040         }
1041
1042         return IRQ_RETVAL(ret);
1043 }
1044
1045 static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
1046 {
1047         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1048
1049         return chip->tpin;
1050 }
1051
1052 static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
1053                                                    unsigned int group)
1054 {
1055         return cy8c95x0_groups[group];
1056 }
1057
1058 static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1059                                            unsigned int group,
1060                                            const unsigned int **pins,
1061                                            unsigned int *num_pins)
1062 {
1063         *pins = &cy8c9560_pins[group].number;
1064         *num_pins = 1;
1065         return 0;
1066 }
1067
1068 static const char *cy8c95x0_get_fname(unsigned int selector)
1069 {
1070         if (selector == 0)
1071                 return "gpio";
1072         else
1073                 return "pwm";
1074 }
1075
1076 static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1077                                   unsigned int pin)
1078 {
1079         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1080         DECLARE_BITMAP(mask, MAX_LINE);
1081         DECLARE_BITMAP(pwm, MAX_LINE);
1082
1083         bitmap_zero(mask, MAX_LINE);
1084         __set_bit(pin, mask);
1085
1086         if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) {
1087                 seq_puts(s, "not available");
1088                 return;
1089         }
1090
1091         seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm)));
1092 }
1093
1094 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = {
1095         .get_groups_count = cy8c95x0_pinctrl_get_groups_count,
1096         .get_group_name = cy8c95x0_pinctrl_get_group_name,
1097         .get_group_pins = cy8c95x0_pinctrl_get_group_pins,
1098 #ifdef CONFIG_OF
1099         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1100         .dt_free_map = pinconf_generic_dt_free_map,
1101 #endif
1102         .pin_dbg_show = cy8c95x0_pin_dbg_show,
1103 };
1104
1105 static const char *cy8c95x0_get_functions_name(struct pinctrl_dev *pctldev, unsigned int selector)
1106 {
1107         return cy8c95x0_get_fname(selector);
1108 }
1109
1110 static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev)
1111 {
1112         return 2;
1113 }
1114
1115 static int cy8c95x0_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
1116                                const char * const **groups,
1117                                unsigned int * const num_groups)
1118 {
1119         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1120
1121         *groups = cy8c95x0_groups;
1122         *num_groups = chip->tpin;
1123         return 0;
1124 }
1125
1126 static int cy8c95x0_pinmux_cfg(struct cy8c95x0_pinctrl *chip,
1127                                unsigned int val,
1128                                unsigned long off)
1129 {
1130         u8 port = cypress_get_port(chip, off);
1131         u8 bit = cypress_get_pin_mask(chip, off);
1132         int ret;
1133
1134         /* Select port */
1135         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
1136         if (ret < 0)
1137                 return ret;
1138
1139         ret = regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, val ? bit : 0);
1140         if (ret < 0)
1141                 return ret;
1142
1143         /* Set direction to output & set output to 1 so that PWM can work */
1144         ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit);
1145         if (ret < 0)
1146                 return ret;
1147
1148         return regmap_write_bits(chip->regmap, CY8C95X0_OUTPUT_(port), bit, bit);
1149 }
1150
1151 static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1152                             unsigned int group)
1153 {
1154         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1155
1156         return cy8c95x0_pinmux_cfg(chip, selector, group);
1157 }
1158
1159 static const struct pinmux_ops cy8c95x0_pmxops = {
1160         .get_functions_count = cy8c95x0_get_functions_count,
1161         .get_function_name = cy8c95x0_get_functions_name,
1162         .get_function_groups = cy8c95x0_get_groups,
1163         .set_mux = cy8c95x0_set_mux,
1164         .strict = true,
1165 };
1166
1167 static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1168                                 unsigned long *config)
1169 {
1170         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1171
1172         return cy8c95x0_gpio_get_pincfg(chip, pin, config);
1173 }
1174
1175 static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1176                                 unsigned long *configs, unsigned int num_configs)
1177 {
1178         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1179         int ret = 0;
1180         int i;
1181
1182         for (i = 0; i < num_configs; i++) {
1183                 ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]);
1184                 if (ret)
1185                         return ret;
1186         }
1187
1188         return ret;
1189 }
1190
1191 static const struct pinconf_ops cy8c95x0_pinconf_ops = {
1192         .pin_config_get = cy8c95x0_pinconf_get,
1193         .pin_config_set = cy8c95x0_pinconf_set,
1194         .is_generic = true,
1195 };
1196
1197 static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq)
1198 {
1199         struct gpio_irq_chip *girq = &chip->gpio_chip.irq;
1200         DECLARE_BITMAP(pending_irqs, MAX_LINE);
1201         int ret;
1202
1203         mutex_init(&chip->irq_lock);
1204
1205         bitmap_zero(pending_irqs, MAX_LINE);
1206
1207         /* Read IRQ status register to clear all pending interrupts */
1208         ret = cy8c95x0_irq_pending(chip, pending_irqs);
1209         if (ret) {
1210                 dev_err(chip->dev, "failed to clear irq status register\n");
1211                 return ret;
1212         }
1213
1214         /* Mask all interrupts */
1215         bitmap_fill(chip->irq_mask, MAX_LINE);
1216
1217         gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip);
1218
1219         /* This will let us handle the parent IRQ in the driver */
1220         girq->parent_handler = NULL;
1221         girq->num_parents = 0;
1222         girq->parents = NULL;
1223         girq->default_type = IRQ_TYPE_NONE;
1224         girq->handler = handle_simple_irq;
1225         girq->threaded = true;
1226
1227         ret = devm_request_threaded_irq(chip->dev, irq,
1228                                         NULL, cy8c95x0_irq_handler,
1229                                         IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH,
1230                                         dev_name(chip->dev), chip);
1231         if (ret) {
1232                 dev_err(chip->dev, "failed to request irq %d\n", irq);
1233                 return ret;
1234         }
1235         dev_info(chip->dev, "Registered threaded IRQ\n");
1236
1237         return 0;
1238 }
1239
1240 static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip)
1241 {
1242         struct pinctrl_desc *pd = &chip->pinctrl_desc;
1243
1244         pd->pctlops = &cy8c95x0_pinctrl_ops;
1245         pd->confops = &cy8c95x0_pinconf_ops;
1246         pd->pmxops = &cy8c95x0_pmxops;
1247         pd->name = dev_name(chip->dev);
1248         pd->pins = cy8c9560_pins;
1249         pd->npins = chip->tpin;
1250         pd->owner = THIS_MODULE;
1251
1252         chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip);
1253         if (IS_ERR(chip->pctldev))
1254                 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev),
1255                         "can't register controller\n");
1256
1257         return 0;
1258 }
1259
1260 static int cy8c95x0_detect(struct i2c_client *client,
1261                            struct i2c_board_info *info)
1262 {
1263         struct i2c_adapter *adapter = client->adapter;
1264         int ret;
1265         const char *name;
1266
1267         if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1268                 return -ENODEV;
1269
1270         ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID);
1271         if (ret < 0)
1272                 return ret;
1273         switch (ret & GENMASK(7, 4)) {
1274         case 0x20:
1275                 name = cy8c95x0_id[0].name;
1276                 break;
1277         case 0x40:
1278                 name = cy8c95x0_id[1].name;
1279                 break;
1280         case 0x60:
1281                 name = cy8c95x0_id[2].name;
1282                 break;
1283         default:
1284                 return -ENODEV;
1285         }
1286
1287         dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr);
1288         strscpy(info->type, name, I2C_NAME_SIZE);
1289
1290         return 0;
1291 }
1292
1293 static int cy8c95x0_probe(struct i2c_client *client)
1294 {
1295         struct cy8c95x0_pinctrl *chip;
1296         struct regulator *reg;
1297         int ret;
1298
1299         chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
1300         if (!chip)
1301                 return -ENOMEM;
1302
1303         chip->dev = &client->dev;
1304
1305         /* Set the device type */
1306         chip->driver_data = (unsigned long)device_get_match_data(&client->dev);
1307         if (!chip->driver_data)
1308                 chip->driver_data = i2c_match_id(cy8c95x0_id, client)->driver_data;
1309         if (!chip->driver_data)
1310                 return -ENODEV;
1311
1312         i2c_set_clientdata(client, chip);
1313
1314         chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
1315         chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
1316
1317         switch (chip->tpin) {
1318         case 20:
1319                 strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE);
1320                 break;
1321         case 40:
1322                 strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE);
1323                 break;
1324         case 60:
1325                 strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE);
1326                 break;
1327         default:
1328                 return -ENODEV;
1329         }
1330
1331         reg = devm_regulator_get(&client->dev, "vdd");
1332         if (IS_ERR(reg)) {
1333                 if (PTR_ERR(reg) == -EPROBE_DEFER)
1334                         return -EPROBE_DEFER;
1335         } else {
1336                 ret = regulator_enable(reg);
1337                 if (ret) {
1338                         dev_err(&client->dev, "failed to enable regulator vdd: %d\n", ret);
1339                         return ret;
1340                 }
1341                 chip->regulator = reg;
1342         }
1343
1344         chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap);
1345         if (IS_ERR(chip->regmap)) {
1346                 ret = PTR_ERR(chip->regmap);
1347                 goto err_exit;
1348         }
1349
1350         bitmap_zero(chip->push_pull, MAX_LINE);
1351         bitmap_zero(chip->shiftmask, MAX_LINE);
1352         bitmap_set(chip->shiftmask, 0, 20);
1353         mutex_init(&chip->i2c_lock);
1354
1355         if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) {
1356                 ret = cy8c95x0_acpi_get_irq(&client->dev);
1357                 if (ret > 0)
1358                         client->irq = ret;
1359         }
1360
1361         if (client->irq) {
1362                 ret = cy8c95x0_irq_setup(chip, client->irq);
1363                 if (ret)
1364                         goto err_exit;
1365         }
1366
1367         ret = cy8c95x0_setup_pinctrl(chip);
1368         if (ret)
1369                 goto err_exit;
1370
1371         ret = cy8c95x0_setup_gpiochip(chip);
1372         if (ret)
1373                 goto err_exit;
1374
1375         return 0;
1376
1377 err_exit:
1378         if (!IS_ERR_OR_NULL(chip->regulator))
1379                 regulator_disable(chip->regulator);
1380         return ret;
1381 }
1382
1383 static void cy8c95x0_remove(struct i2c_client *client)
1384 {
1385         struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client);
1386
1387         if (!IS_ERR_OR_NULL(chip->regulator))
1388                 regulator_disable(chip->regulator);
1389 }
1390
1391 static const struct acpi_device_id cy8c95x0_acpi_ids[] = {
1392         { "INT3490", 40, },
1393         { }
1394 };
1395 MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids);
1396
1397 static struct i2c_driver cy8c95x0_driver = {
1398         .driver = {
1399                 .name   = "cy8c95x0-pinctrl",
1400                 .of_match_table = cy8c95x0_dt_ids,
1401                 .acpi_match_table = cy8c95x0_acpi_ids,
1402         },
1403         .probe_new      = cy8c95x0_probe,
1404         .remove         = cy8c95x0_remove,
1405         .id_table       = cy8c95x0_id,
1406         .detect         = cy8c95x0_detect,
1407 };
1408 module_i2c_driver(cy8c95x0_driver);
1409
1410 MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>");
1411 MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>");
1412 MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0");
1413 MODULE_LICENSE("GPL");