drivers/pinctrl/pinctrl-cy8c95x0.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support
   4  *
   5  * Copyright (C) 2022 9elements GmbH
   6  * Authors: Patrick Rudolph <patrick.rudolph@9elements.com>
   7  *          Naresh Solanki <Naresh.Solanki@9elements.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/bitmap.h>
  12 #include <linux/dmi.h>
  13 #include <linux/gpio/driver.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/i2c.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/mod_devicetable.h>
  19 #include <linux/module.h>
  20 #include <linux/property.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/seq_file.h>
  24
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/pinctrl/pinconf.h>
  27 #include <linux/pinctrl/pinconf-generic.h>
  28 #include <linux/pinctrl/pinctrl.h>
  29 #include <linux/pinctrl/pinmux.h>
  30
  31 /* Fast access registers */
  32 #define CY8C95X0_INPUT          0x00
  33 #define CY8C95X0_OUTPUT         0x08
  34 #define CY8C95X0_INTSTATUS      0x10
  35
  36 #define CY8C95X0_INPUT_(x)      (CY8C95X0_INPUT + (x))
  37 #define CY8C95X0_OUTPUT_(x)     (CY8C95X0_OUTPUT + (x))
  38 #define CY8C95X0_INTSTATUS_(x)  (CY8C95X0_INTSTATUS + (x))
  39
  40 /* Port Select configures the port */
  41 #define CY8C95X0_PORTSEL        0x18
  42 /* Port settings, write PORTSEL first */
  43 #define CY8C95X0_INTMASK        0x19
  44 #define CY8C95X0_PWMSEL         0x1A
  45 #define CY8C95X0_INVERT         0x1B
  46 #define CY8C95X0_DIRECTION      0x1C
  47 /* Drive mode register change state on writing '1' */
  48 #define CY8C95X0_DRV_PU         0x1D
  49 #define CY8C95X0_DRV_PD         0x1E
  50 #define CY8C95X0_DRV_ODH        0x1F
  51 #define CY8C95X0_DRV_ODL        0x20
  52 #define CY8C95X0_DRV_PP_FAST    0x21
  53 #define CY8C95X0_DRV_PP_SLOW    0x22
  54 #define CY8C95X0_DRV_HIZ        0x23
  55 #define CY8C95X0_DEVID          0x2E
  56 #define CY8C95X0_WATCHDOG       0x2F
  57 #define CY8C95X0_COMMAND        0x30
  58
  59 #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))
  60
  61 static const struct i2c_device_id cy8c95x0_id[] = {
  62         { "cy8c9520", 20, },
  63         { "cy8c9540", 40, },
  64         { "cy8c9560", 60, },
  65         { }
  66 };
  67 MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
  68
  69 #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))
  70
  71 static const struct of_device_id cy8c95x0_dt_ids[] = {
  72         { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), },
  73         { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), },
  74         { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), },
  75         { }
  76 };
  77 MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);
  78
  79 static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true };
  80
  81 static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = {
  82         { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
  83         { }
  84 };
  85
  86 static int cy8c95x0_acpi_get_irq(struct device *dev)
  87 {
  88         int ret;
  89
  90         ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios);
  91         if (ret)
  92                 dev_warn(dev, "can't add GPIO ACPI mapping\n");
  93
  94         ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0);
  95         if (ret < 0)
  96                 return ret;
  97
  98         dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
  99         return ret;
 100 }
 101
 102 static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
 103         {
 104                 /*
 105                  * On Intel Galileo Gen 1 board the IRQ pin is provided
 106                  * as an absolute number instead of being relative.
 107                  * Since first controller (gpio-sch.c) and second
 108                  * (gpio-dwapb.c) are at the fixed bases, we may safely
 109                  * refer to the number in the global space to get an IRQ
 110                  * out of it.
 111                  */
 112                 .matches = {
 113                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
 114                 },
 115         },
 116         {}
 117 };
 118
 119 #define MAX_BANK 8
 120 #define BANK_SZ 8
 121 #define MAX_LINE        (MAX_BANK * BANK_SZ)
 122
 123 #define CY8C95X0_GPIO_MASK              GENMASK(7, 0)
 124
 125 /**
 126  * struct cy8c95x0_pinctrl - driver data
 127  * @regmap:         Device's regmap
 128  * @irq_lock:       IRQ bus lock
 129  * @i2c_lock:       Mutex for the device internal mux register
 130  * @irq_mask:       I/O bits affected by interrupts
 131  * @irq_trig_raise: I/O bits affected by raising voltage level
 132  * @irq_trig_fall:  I/O bits affected by falling voltage level
 133  * @irq_trig_low:   I/O bits affected by a low voltage level
 134  * @irq_trig_high:  I/O bits affected by a high voltage level
 135  * @push_pull:      I/O bits configured as push pull driver
 136  * @shiftmask:      Mask used to compensate for Gport2 width
 137  * @nport:          Number of Gports in this chip
 138  * @gpio_chip:      gpiolib chip
 139  * @driver_data:    private driver data
 140  * @regulator:      Pointer to the regulator for the IC
 141  * @dev:            struct device
 142  * @pctldev:        pin controller device
 143  * @pinctrl_desc:   pin controller description
 144  * @name:           Chip controller name
 145  * @tpin:           Total number of pins
 146  */
 147 struct cy8c95x0_pinctrl {
 148         struct regmap *regmap;
 149         struct mutex irq_lock;
 150         struct mutex i2c_lock;
 151         DECLARE_BITMAP(irq_mask, MAX_LINE);
 152         DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
 153         DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
 154         DECLARE_BITMAP(irq_trig_low, MAX_LINE);
 155         DECLARE_BITMAP(irq_trig_high, MAX_LINE);
 156         DECLARE_BITMAP(push_pull, MAX_LINE);
 157         DECLARE_BITMAP(shiftmask, MAX_LINE);
 158         int nport;
 159         struct gpio_chip gpio_chip;
 160         unsigned long driver_data;
 161         struct regulator *regulator;
 162         struct device *dev;
 163         struct pinctrl_dev *pctldev;
 164         struct pinctrl_desc pinctrl_desc;
 165         char name[32];
 166         unsigned int tpin;
 167         struct gpio_desc *gpio_reset;
 168 };
 169
 170 static const struct pinctrl_pin_desc cy8c9560_pins[] = {
 171         PINCTRL_PIN(0, "gp00"),
 172         PINCTRL_PIN(1, "gp01"),
 173         PINCTRL_PIN(2, "gp02"),
 174         PINCTRL_PIN(3, "gp03"),
 175         PINCTRL_PIN(4, "gp04"),
 176         PINCTRL_PIN(5, "gp05"),
 177         PINCTRL_PIN(6, "gp06"),
 178         PINCTRL_PIN(7, "gp07"),
 179
 180         PINCTRL_PIN(8, "gp10"),
 181         PINCTRL_PIN(9, "gp11"),
 182         PINCTRL_PIN(10, "gp12"),
 183         PINCTRL_PIN(11, "gp13"),
 184         PINCTRL_PIN(12, "gp14"),
 185         PINCTRL_PIN(13, "gp15"),
 186         PINCTRL_PIN(14, "gp16"),
 187         PINCTRL_PIN(15, "gp17"),
 188
 189         PINCTRL_PIN(16, "gp20"),
 190         PINCTRL_PIN(17, "gp21"),
 191         PINCTRL_PIN(18, "gp22"),
 192         PINCTRL_PIN(19, "gp23"),
 193
 194         PINCTRL_PIN(20, "gp30"),
 195         PINCTRL_PIN(21, "gp31"),
 196         PINCTRL_PIN(22, "gp32"),
 197         PINCTRL_PIN(23, "gp33"),
 198         PINCTRL_PIN(24, "gp34"),
 199         PINCTRL_PIN(25, "gp35"),
 200         PINCTRL_PIN(26, "gp36"),
 201         PINCTRL_PIN(27, "gp37"),
 202
 203         PINCTRL_PIN(28, "gp40"),
 204         PINCTRL_PIN(29, "gp41"),
 205         PINCTRL_PIN(30, "gp42"),
 206         PINCTRL_PIN(31, "gp43"),
 207         PINCTRL_PIN(32, "gp44"),
 208         PINCTRL_PIN(33, "gp45"),
 209         PINCTRL_PIN(34, "gp46"),
 210         PINCTRL_PIN(35, "gp47"),
 211
 212         PINCTRL_PIN(36, "gp50"),
 213         PINCTRL_PIN(37, "gp51"),
 214         PINCTRL_PIN(38, "gp52"),
 215         PINCTRL_PIN(39, "gp53"),
 216         PINCTRL_PIN(40, "gp54"),
 217         PINCTRL_PIN(41, "gp55"),
 218         PINCTRL_PIN(42, "gp56"),
 219         PINCTRL_PIN(43, "gp57"),
 220
 221         PINCTRL_PIN(44, "gp60"),
 222         PINCTRL_PIN(45, "gp61"),
 223         PINCTRL_PIN(46, "gp62"),
 224         PINCTRL_PIN(47, "gp63"),
 225         PINCTRL_PIN(48, "gp64"),
 226         PINCTRL_PIN(49, "gp65"),
 227         PINCTRL_PIN(50, "gp66"),
 228         PINCTRL_PIN(51, "gp67"),
 229
 230         PINCTRL_PIN(52, "gp70"),
 231         PINCTRL_PIN(53, "gp71"),
 232         PINCTRL_PIN(54, "gp72"),
 233         PINCTRL_PIN(55, "gp73"),
 234         PINCTRL_PIN(56, "gp74"),
 235         PINCTRL_PIN(57, "gp75"),
 236         PINCTRL_PIN(58, "gp76"),
 237         PINCTRL_PIN(59, "gp77"),
 238 };
 239
 240 static const char * const cy8c95x0_groups[] = {
 241         "gp00",
 242         "gp01",
 243         "gp02",
 244         "gp03",
 245         "gp04",
 246         "gp05",
 247         "gp06",
 248         "gp07",
 249
 250         "gp10",
 251         "gp11",
 252         "gp12",
 253         "gp13",
 254         "gp14",
 255         "gp15",
 256         "gp16",
 257         "gp17",
 258
 259         "gp20",
 260         "gp21",
 261         "gp22",
 262         "gp23",
 263
 264         "gp30",
 265         "gp31",
 266         "gp32",
 267         "gp33",
 268         "gp34",
 269         "gp35",
 270         "gp36",
 271         "gp37",
 272
 273         "gp40",
 274         "gp41",
 275         "gp42",
 276         "gp43",
 277         "gp44",
 278         "gp45",
 279         "gp46",
 280         "gp47",
 281
 282         "gp50",
 283         "gp51",
 284         "gp52",
 285         "gp53",
 286         "gp54",
 287         "gp55",
 288         "gp56",
 289         "gp57",
 290
 291         "gp60",
 292         "gp61",
 293         "gp62",
 294         "gp63",
 295         "gp64",
 296         "gp65",
 297         "gp66",
 298         "gp67",
 299
 300         "gp70",
 301         "gp71",
 302         "gp72",
 303         "gp73",
 304         "gp74",
 305         "gp75",
 306         "gp76",
 307         "gp77",
 308 };
 309
 310 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin)
 311 {
 312         /* Account for GPORT2 which only has 4 bits */
 313         return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ;
 314 }
 315
 316 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)
 317 {
 318         /* Account for GPORT2 which only has 4 bits */
 319         return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ);
 320 }
 321
 322 static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
 323 {
 324         switch (reg) {
 325         case 0x24 ... 0x27:
 326                 return false;
 327         default:
 328                 return true;
 329         }
 330 }
 331
 332 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)
 333 {
 334         switch (reg) {
 335         case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
 336                 return false;
 337         case CY8C95X0_DEVID:
 338                 return false;
 339         case 0x24 ... 0x27:
 340                 return false;
 341         default:
 342                 return true;
 343         }
 344 }
 345
 346 static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg)
 347 {
 348         switch (reg) {
 349         case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
 350         case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
 351         case CY8C95X0_INTMASK:
 352         case CY8C95X0_INVERT:
 353         case CY8C95X0_PWMSEL:
 354         case CY8C95X0_DIRECTION:
 355         case CY8C95X0_DRV_PU:
 356         case CY8C95X0_DRV_PD:
 357         case CY8C95X0_DRV_ODH:
 358         case CY8C95X0_DRV_ODL:
 359         case CY8C95X0_DRV_PP_FAST:
 360         case CY8C95X0_DRV_PP_SLOW:
 361         case CY8C95X0_DRV_HIZ:
 362                 return true;
 363         default:
 364                 return false;
 365         }
 366 }
 367
 368 static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg)
 369 {
 370         switch (reg) {
 371         case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
 372                 return true;
 373         default:
 374                 return false;
 375         }
 376 }
 377
 378 static const struct reg_default cy8c95x0_reg_defaults[] = {
 379         { CY8C95X0_OUTPUT_(0), GENMASK(7, 0) },
 380         { CY8C95X0_OUTPUT_(1), GENMASK(7, 0) },
 381         { CY8C95X0_OUTPUT_(2), GENMASK(7, 0) },
 382         { CY8C95X0_OUTPUT_(3), GENMASK(7, 0) },
 383         { CY8C95X0_OUTPUT_(4), GENMASK(7, 0) },
 384         { CY8C95X0_OUTPUT_(5), GENMASK(7, 0) },
 385         { CY8C95X0_OUTPUT_(6), GENMASK(7, 0) },
 386         { CY8C95X0_OUTPUT_(7), GENMASK(7, 0) },
 387         { CY8C95X0_PORTSEL, 0 },
 388         { CY8C95X0_PWMSEL, 0 },
 389 };
 390
 391 static const struct regmap_config cy8c95x0_i2c_regmap = {
 392         .reg_bits = 8,
 393         .val_bits = 8,
 394
 395         .reg_defaults = cy8c95x0_reg_defaults,
 396         .num_reg_defaults = ARRAY_SIZE(cy8c95x0_reg_defaults),
 397
 398         .readable_reg = cy8c95x0_readable_register,
 399         .writeable_reg = cy8c95x0_writeable_register,
 400         .volatile_reg = cy8c95x0_volatile_register,
 401         .precious_reg = cy8c95x0_precious_register,
 402
 403         .cache_type = REGCACHE_FLAT,
 404         .max_register = CY8C95X0_COMMAND,
 405 };
 406
 407 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
 408                                     unsigned long *val, unsigned long *mask)
 409 {
 410         DECLARE_BITMAP(tmask, MAX_LINE);
 411         DECLARE_BITMAP(tval, MAX_LINE);
 412         int write_val;
 413         int ret = 0;
 414         int i, off = 0;
 415         u8 bits;
 416
 417         /* Add the 4 bit gap of Gport2 */
 418         bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
 419         bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
 420         bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
 421
 422         bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
 423         bitmap_shift_left(tval, tval, 4, MAX_LINE);
 424         bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
 425
 426         mutex_lock(&chip->i2c_lock);
 427         for (i = 0; i < chip->nport; i++) {
 428                 /* Skip over unused banks */
 429                 bits = bitmap_get_value8(tmask, i * BANK_SZ);
 430                 if (!bits)
 431                         continue;
 432
 433                 switch (reg) {
 434                 /* Muxed registers */
 435                 case CY8C95X0_INTMASK:
 436                 case CY8C95X0_PWMSEL:
 437                 case CY8C95X0_INVERT:
 438                 case CY8C95X0_DIRECTION:
 439                 case CY8C95X0_DRV_PU:
 440                 case CY8C95X0_DRV_PD:
 441                 case CY8C95X0_DRV_ODH:
 442                 case CY8C95X0_DRV_ODL:
 443                 case CY8C95X0_DRV_PP_FAST:
 444                 case CY8C95X0_DRV_PP_SLOW:
 445                 case CY8C95X0_DRV_HIZ:
 446                         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i);
 447                         if (ret < 0)
 448                                 goto out;
 449                         off = reg;
 450                         break;
 451                 /* Direct access registers */
 452                 case CY8C95X0_INPUT:
 453                 case CY8C95X0_OUTPUT:
 454                 case CY8C95X0_INTSTATUS:
 455                         off = reg + i;
 456                         break;
 457                 default:
 458                         ret = -EINVAL;
 459                         goto out;
 460                 }
 461
 462                 write_val = bitmap_get_value8(tval, i * BANK_SZ);
 463
 464                 ret = regmap_update_bits(chip->regmap, off, bits, write_val);
 465                 if (ret < 0)
 466                         goto out;
 467         }
 468 out:
 469         mutex_unlock(&chip->i2c_lock);
 470
 471         if (ret < 0)
 472                 dev_err(chip->dev, "failed writing register %d: err %d\n", off, ret);
 473
 474         return ret;
 475 }
 476
 477 static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
 478                                    unsigned long *val, unsigned long *mask)
 479 {
 480         DECLARE_BITMAP(tmask, MAX_LINE);
 481         DECLARE_BITMAP(tval, MAX_LINE);
 482         DECLARE_BITMAP(tmp, MAX_LINE);
 483         int read_val;
 484         int ret = 0;
 485         int i, off = 0;
 486         u8 bits;
 487
 488         /* Add the 4 bit gap of Gport2 */
 489         bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
 490         bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
 491         bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
 492
 493         bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
 494         bitmap_shift_left(tval, tval, 4, MAX_LINE);
 495         bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
 496
 497         mutex_lock(&chip->i2c_lock);
 498         for (i = 0; i < chip->nport; i++) {
 499                 /* Skip over unused banks */
 500                 bits = bitmap_get_value8(tmask, i * BANK_SZ);
 501                 if (!bits)
 502                         continue;
 503
 504                 switch (reg) {
 505                 /* Muxed registers */
 506                 case CY8C95X0_INTMASK:
 507                 case CY8C95X0_PWMSEL:
 508                 case CY8C95X0_INVERT:
 509                 case CY8C95X0_DIRECTION:
 510                 case CY8C95X0_DRV_PU:
 511                 case CY8C95X0_DRV_PD:
 512                 case CY8C95X0_DRV_ODH:
 513                 case CY8C95X0_DRV_ODL:
 514                 case CY8C95X0_DRV_PP_FAST:
 515                 case CY8C95X0_DRV_PP_SLOW:
 516                 case CY8C95X0_DRV_HIZ:
 517                         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i);
 518                         if (ret < 0)
 519                                 goto out;
 520                         off = reg;
 521                         break;
 522                 /* Direct access registers */
 523                 case CY8C95X0_INPUT:
 524                 case CY8C95X0_OUTPUT:
 525                 case CY8C95X0_INTSTATUS:
 526                         off = reg + i;
 527                         break;
 528                 default:
 529                         ret = -EINVAL;
 530                         goto out;
 531                 }
 532
 533                 ret = regmap_read(chip->regmap, off, &read_val);
 534                 if (ret < 0)
 535                         goto out;
 536
 537                 read_val &= bits;
 538                 read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits;
 539                 bitmap_set_value8(tval, read_val, i * BANK_SZ);
 540         }
 541
 542         /* Fill the 4 bit gap of Gport2 */
 543         bitmap_shift_right(tmp, tval, 4, MAX_LINE);
 544         bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE);
 545
 546 out:
 547         mutex_unlock(&chip->i2c_lock);
 548
 549         if (ret < 0)
 550                 dev_err(chip->dev, "failed reading register %d: err %d\n", off, ret);
 551
 552         return ret;
 553 }
 554
 555 static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off)
 556 {
 557         return pinctrl_gpio_direction_input(gc->base + off);
 558 }
 559
 560 static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc,
 561                                           unsigned int off, int val)
 562 {
 563         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 564         u8 port = cypress_get_port(chip, off);
 565         u8 outreg = CY8C95X0_OUTPUT_(port);
 566         u8 bit = cypress_get_pin_mask(chip, off);
 567         int ret;
 568
 569         /* Set output level */
 570         ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
 571         if (ret)
 572                 return ret;
 573
 574         return pinctrl_gpio_direction_output(gc->base + off);
 575 }
 576
 577 static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)
 578 {
 579         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 580         u8 inreg = CY8C95X0_INPUT_(cypress_get_port(chip, off));
 581         u8 bit = cypress_get_pin_mask(chip, off);
 582         u32 reg_val;
 583         int ret;
 584
 585         ret = regmap_read(chip->regmap, inreg, &reg_val);
 586         if (ret < 0) {
 587                 /*
 588                  * NOTE:
 589                  * Diagnostic already emitted; that's all we should
 590                  * do unless gpio_*_value_cansleep() calls become different
 591                  * from their nonsleeping siblings (and report faults).
 592                  */
 593                 return 0;
 594         }
 595
 596         return !!(reg_val & bit);
 597 }
 598
 599 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off,
 600                                     int val)
 601 {
 602         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 603         u8 outreg = CY8C95X0_OUTPUT_(cypress_get_port(chip, off));
 604         u8 bit = cypress_get_pin_mask(chip, off);
 605
 606         regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
 607 }
 608
 609 static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
 610 {
 611         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 612         u8 port = cypress_get_port(chip, off);
 613         u8 bit = cypress_get_pin_mask(chip, off);
 614         u32 reg_val;
 615         int ret;
 616
 617         mutex_lock(&chip->i2c_lock);
 618
 619         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 620         if (ret < 0)
 621                 goto out;
 622
 623         ret = regmap_read(chip->regmap, CY8C95X0_DIRECTION, &reg_val);
 624         if (ret < 0)
 625                 goto out;
 626
 627         mutex_unlock(&chip->i2c_lock);
 628
 629         if (reg_val & bit)
 630                 return GPIO_LINE_DIRECTION_IN;
 631
 632         return GPIO_LINE_DIRECTION_OUT;
 633 out:
 634         mutex_unlock(&chip->i2c_lock);
 635         return ret;
 636 }
 637
 638 static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,
 639                                     unsigned int off,
 640                                     unsigned long *config)
 641 {
 642         enum pin_config_param param = pinconf_to_config_param(*config);
 643         u8 port = cypress_get_port(chip, off);
 644         u8 bit = cypress_get_pin_mask(chip, off);
 645         unsigned int reg;
 646         u32 reg_val;
 647         u16 arg = 0;
 648         int ret;
 649
 650         mutex_lock(&chip->i2c_lock);
 651
 652         /* Select port */
 653         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 654         if (ret < 0)
 655                 goto out;
 656
 657         switch (param) {
 658         case PIN_CONFIG_BIAS_PULL_UP:
 659                 reg = CY8C95X0_DRV_PU;
 660                 break;
 661         case PIN_CONFIG_BIAS_PULL_DOWN:
 662                 reg = CY8C95X0_DRV_PD;
 663                 break;
 664         case PIN_CONFIG_BIAS_DISABLE:
 665                 reg = CY8C95X0_DRV_HIZ;
 666                 break;
 667         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 668                 reg = CY8C95X0_DRV_ODL;
 669                 break;
 670         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 671                 reg = CY8C95X0_DRV_ODH;
 672                 break;
 673         case PIN_CONFIG_DRIVE_PUSH_PULL:
 674                 reg = CY8C95X0_DRV_PP_FAST;
 675                 break;
 676         case PIN_CONFIG_INPUT_ENABLE:
 677                 reg = CY8C95X0_DIRECTION;
 678                 break;
 679         case PIN_CONFIG_MODE_PWM:
 680                 reg = CY8C95X0_PWMSEL;
 681                 break;
 682         case PIN_CONFIG_OUTPUT:
 683                 reg = CY8C95X0_OUTPUT_(port);
 684                 break;
 685         case PIN_CONFIG_OUTPUT_ENABLE:
 686                 reg = CY8C95X0_DIRECTION;
 687                 break;
 688
 689         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 690         case PIN_CONFIG_BIAS_BUS_HOLD:
 691         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 692         case PIN_CONFIG_DRIVE_STRENGTH:
 693         case PIN_CONFIG_DRIVE_STRENGTH_UA:
 694         case PIN_CONFIG_INPUT_DEBOUNCE:
 695         case PIN_CONFIG_INPUT_SCHMITT:
 696         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 697         case PIN_CONFIG_MODE_LOW_POWER:
 698         case PIN_CONFIG_PERSIST_STATE:
 699         case PIN_CONFIG_POWER_SOURCE:
 700         case PIN_CONFIG_SKEW_DELAY:
 701         case PIN_CONFIG_SLEEP_HARDWARE_STATE:
 702         case PIN_CONFIG_SLEW_RATE:
 703         default:
 704                 ret = -ENOTSUPP;
 705                 goto out;
 706         }
 707         /*
 708          * Writing 1 to one of the drive mode registers will automatically
 709          * clear conflicting set bits in the other drive mode registers.
 710          */
 711         ret = regmap_read(chip->regmap, reg, &reg_val);
 712         if (reg_val & bit)
 713                 arg = 1;
 714
 715         *config = pinconf_to_config_packed(param, (u16)arg);
 716 out:
 717         mutex_unlock(&chip->i2c_lock);
 718
 719         return ret;
 720 }
 721
 722 static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
 723                                     unsigned int off,
 724                                     unsigned long config)
 725 {
 726         u8 port = cypress_get_port(chip, off);
 727         u8 bit = cypress_get_pin_mask(chip, off);
 728         unsigned long param = pinconf_to_config_param(config);
 729         unsigned int reg;
 730         int ret;
 731
 732         mutex_lock(&chip->i2c_lock);
 733
 734         /* Select port */
 735         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 736         if (ret < 0)
 737                 goto out;
 738
 739         switch (param) {
 740         case PIN_CONFIG_BIAS_PULL_UP:
 741                 __clear_bit(off, chip->push_pull);
 742                 reg = CY8C95X0_DRV_PU;
 743                 break;
 744         case PIN_CONFIG_BIAS_PULL_DOWN:
 745                 __clear_bit(off, chip->push_pull);
 746                 reg = CY8C95X0_DRV_PD;
 747                 break;
 748         case PIN_CONFIG_BIAS_DISABLE:
 749                 __clear_bit(off, chip->push_pull);
 750                 reg = CY8C95X0_DRV_HIZ;
 751                 break;
 752         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 753                 __clear_bit(off, chip->push_pull);
 754                 reg = CY8C95X0_DRV_ODL;
 755                 break;
 756         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 757                 __clear_bit(off, chip->push_pull);
 758                 reg = CY8C95X0_DRV_ODH;
 759                 break;
 760         case PIN_CONFIG_DRIVE_PUSH_PULL:
 761                 __set_bit(off, chip->push_pull);
 762                 reg = CY8C95X0_DRV_PP_FAST;
 763                 break;
 764         case PIN_CONFIG_MODE_PWM:
 765                 reg = CY8C95X0_PWMSEL;
 766                 break;
 767         default:
 768                 ret = -ENOTSUPP;
 769                 goto out;
 770         }
 771         /*
 772          * Writing 1 to one of the drive mode registers will automatically
 773          * clear conflicting set bits in the other drive mode registers.
 774          */
 775         ret = regmap_write_bits(chip->regmap, reg, bit, bit);
 776
 777 out:
 778         mutex_unlock(&chip->i2c_lock);
 779         return ret;
 780 }
 781
 782 static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc,
 783                                       unsigned long *mask, unsigned long *bits)
 784 {
 785         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 786
 787         return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask);
 788 }
 789
 790 static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc,
 791                                        unsigned long *mask, unsigned long *bits)
 792 {
 793         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 794
 795         cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask);
 796 }
 797
 798 static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc)
 799 {
 800         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 801         struct device *dev = chip->dev;
 802         int ret;
 803
 804         ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin);
 805         if (ret)
 806                 dev_err(dev, "failed to add GPIO pin range\n");
 807
 808         return ret;
 809 }
 810
 811 static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip)
 812 {
 813         struct gpio_chip *gc = &chip->gpio_chip;
 814
 815         gc->request = gpiochip_generic_request;
 816         gc->free = gpiochip_generic_free;
 817         gc->direction_input  = cy8c95x0_gpio_direction_input;
 818         gc->direction_output = cy8c95x0_gpio_direction_output;
 819         gc->get = cy8c95x0_gpio_get_value;
 820         gc->set = cy8c95x0_gpio_set_value;
 821         gc->get_direction = cy8c95x0_gpio_get_direction;
 822         gc->get_multiple = cy8c95x0_gpio_get_multiple;
 823         gc->set_multiple = cy8c95x0_gpio_set_multiple;
 824         gc->set_config = gpiochip_generic_config,
 825         gc->can_sleep = true;
 826         gc->add_pin_ranges = cy8c95x0_add_pin_ranges;
 827
 828         gc->base = -1;
 829         gc->ngpio = chip->tpin;
 830
 831         gc->parent = chip->dev;
 832         gc->owner = THIS_MODULE;
 833         gc->names = NULL;
 834
 835         gc->label = dev_name(chip->dev);
 836
 837         return devm_gpiochip_add_data(chip->dev, gc, chip);
 838 }
 839
 840 static void cy8c95x0_irq_mask(struct irq_data *d)
 841 {
 842         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 843         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 844         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 845
 846         set_bit(hwirq, chip->irq_mask);
 847         gpiochip_disable_irq(gc, hwirq);
 848 }
 849
 850 static void cy8c95x0_irq_unmask(struct irq_data *d)
 851 {
 852         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 853         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 854         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 855
 856         gpiochip_enable_irq(gc, hwirq);
 857         clear_bit(hwirq, chip->irq_mask);
 858 }
 859
 860 static void cy8c95x0_irq_bus_lock(struct irq_data *d)
 861 {
 862         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 863         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 864
 865         mutex_lock(&chip->irq_lock);
 866 }
 867
 868 static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d)
 869 {
 870         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 871         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 872         DECLARE_BITMAP(ones, MAX_LINE);
 873         DECLARE_BITMAP(irq_mask, MAX_LINE);
 874         DECLARE_BITMAP(reg_direction, MAX_LINE);
 875
 876         bitmap_fill(ones, MAX_LINE);
 877
 878         cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones);
 879
 880         /* Switch direction to input if needed */
 881         cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask);
 882         bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE);
 883         bitmap_complement(irq_mask, irq_mask, MAX_LINE);
 884
 885         /* Look for any newly setup interrupt */
 886         cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask);
 887
 888         mutex_unlock(&chip->irq_lock);
 889 }
 890
 891 static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type)
 892 {
 893         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 894         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 895         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 896         unsigned int trig_type;
 897
 898         switch (type) {
 899         case IRQ_TYPE_EDGE_RISING:
 900         case IRQ_TYPE_EDGE_FALLING:
 901         case IRQ_TYPE_EDGE_BOTH:
 902                 trig_type = type;
 903                 break;
 904         case IRQ_TYPE_LEVEL_HIGH:
 905                 trig_type = IRQ_TYPE_EDGE_RISING;
 906                 break;
 907         case IRQ_TYPE_LEVEL_LOW:
 908                 trig_type = IRQ_TYPE_EDGE_FALLING;
 909                 break;
 910         default:
 911                 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type);
 912                 return -EINVAL;
 913         }
 914
 915         assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING);
 916         assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING);
 917         assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW);
 918         assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH);
 919
 920         return 0;
 921 }
 922
 923 static void cy8c95x0_irq_shutdown(struct irq_data *d)
 924 {
 925         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 926         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 927         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 928
 929         clear_bit(hwirq, chip->irq_trig_raise);
 930         clear_bit(hwirq, chip->irq_trig_fall);
 931         clear_bit(hwirq, chip->irq_trig_low);
 932         clear_bit(hwirq, chip->irq_trig_high);
 933 }
 934
 935 static const struct irq_chip cy8c95x0_irqchip = {
 936         .name = "cy8c95x0-irq",
 937         .irq_mask = cy8c95x0_irq_mask,
 938         .irq_unmask = cy8c95x0_irq_unmask,
 939         .irq_bus_lock = cy8c95x0_irq_bus_lock,
 940         .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock,
 941         .irq_set_type = cy8c95x0_irq_set_type,
 942         .irq_shutdown = cy8c95x0_irq_shutdown,
 943         .flags = IRQCHIP_IMMUTABLE,
 944         GPIOCHIP_IRQ_RESOURCE_HELPERS,
 945 };
 946
 947 static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending)
 948 {
 949         DECLARE_BITMAP(ones, MAX_LINE);
 950         DECLARE_BITMAP(cur_stat, MAX_LINE);
 951         DECLARE_BITMAP(new_stat, MAX_LINE);
 952         DECLARE_BITMAP(trigger, MAX_LINE);
 953
 954         bitmap_fill(ones, MAX_LINE);
 955
 956         /* Read the current interrupt status from the device */
 957         if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones))
 958                 return false;
 959
 960         /* Check latched inputs */
 961         if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger))
 962                 return false;
 963
 964         /* Apply filter for rising/falling edge selection */
 965         bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise,
 966                        cur_stat, MAX_LINE);
 967
 968         bitmap_and(pending, new_stat, trigger, MAX_LINE);
 969
 970         return !bitmap_empty(pending, MAX_LINE);
 971 }
 972
 973 static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid)
 974 {
 975         struct cy8c95x0_pinctrl *chip = devid;
 976         struct gpio_chip *gc = &chip->gpio_chip;
 977         DECLARE_BITMAP(pending, MAX_LINE);
 978         int nested_irq, level;
 979         bool ret;
 980
 981         ret = cy8c95x0_irq_pending(chip, pending);
 982         if (!ret)
 983                 return IRQ_RETVAL(0);
 984
 985         ret = 0;
 986         for_each_set_bit(level, pending, MAX_LINE) {
 987                 /* Already accounted for 4bit gap in GPort2 */
 988                 nested_irq = irq_find_mapping(gc->irq.domain, level);
 989
 990                 if (unlikely(nested_irq <= 0)) {
 991                         dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
 992                         continue;
 993                 }
 994
 995                 if (test_bit(level, chip->irq_trig_low))
 996                         while (!cy8c95x0_gpio_get_value(gc, level))
 997                                 handle_nested_irq(nested_irq);
 998                 else if (test_bit(level, chip->irq_trig_high))
 999                         while (cy8c95x0_gpio_get_value(gc, level))
1000                                 handle_nested_irq(nested_irq);
1001                 else
1002                         handle_nested_irq(nested_irq);
1003
1004                 ret = 1;
1005         }
1006
1007         return IRQ_RETVAL(ret);
1008 }
1009
1010 static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
1011 {
1012         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1013
1014         return chip->tpin;
1015 }
1016
1017 static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
1018                                                    unsigned int group)
1019 {
1020         return cy8c95x0_groups[group];
1021 }
1022
1023 static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1024                                            unsigned int group,
1025                                            const unsigned int **pins,
1026                                            unsigned int *num_pins)
1027 {
1028         *pins = &cy8c9560_pins[group].number;
1029         *num_pins = 1;
1030         return 0;
1031 }
1032
1033 static const char *cy8c95x0_get_fname(unsigned int selector)
1034 {
1035         if (selector == 0)
1036                 return "gpio";
1037         else
1038                 return "pwm";
1039 }
1040
1041 static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1042                                   unsigned int pin)
1043 {
1044         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1045         DECLARE_BITMAP(mask, MAX_LINE);
1046         DECLARE_BITMAP(pwm, MAX_LINE);
1047
1048         bitmap_zero(mask, MAX_LINE);
1049         __set_bit(pin, mask);
1050
1051         if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) {
1052                 seq_puts(s, "not available");
1053                 return;
1054         }
1055
1056         seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm)));
1057 }
1058
1059 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = {
1060         .get_groups_count = cy8c95x0_pinctrl_get_groups_count,
1061         .get_group_name = cy8c95x0_pinctrl_get_group_name,
1062         .get_group_pins = cy8c95x0_pinctrl_get_group_pins,
1063 #ifdef CONFIG_OF
1064         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1065         .dt_free_map = pinconf_generic_dt_free_map,
1066 #endif
1067         .pin_dbg_show = cy8c95x0_pin_dbg_show,
1068 };
1069
1070 static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector)
1071 {
1072         return cy8c95x0_get_fname(selector);
1073 }
1074
1075 static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev)
1076 {
1077         return 2;
1078 }
1079
1080 static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
1081                                         const char * const **groups,
1082                                         unsigned int * const num_groups)
1083 {
1084         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1085
1086         *groups = cy8c95x0_groups;
1087         *num_groups = chip->tpin;
1088         return 0;
1089 }
1090
1091 static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode)
1092 {
1093         u8 port = cypress_get_port(chip, off);
1094         u8 bit = cypress_get_pin_mask(chip, off);
1095         int ret;
1096
1097         /* Select port */
1098         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
1099         if (ret < 0)
1100                 return ret;
1101
1102         return regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, mode ? bit : 0);
1103 }
1104
1105 static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip,
1106                                 unsigned int selector, unsigned int group)
1107 {
1108         u8 port = cypress_get_port(chip, group);
1109         u8 bit = cypress_get_pin_mask(chip, group);
1110         int ret;
1111
1112         ret = cy8c95x0_set_mode(chip, group, selector);
1113         if (ret < 0)
1114                 return ret;
1115
1116         if (selector == 0)
1117                 return 0;
1118
1119         /* Set direction to output & set output to 1 so that PWM can work */
1120         ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit);
1121         if (ret < 0)
1122                 return ret;
1123
1124         return regmap_write_bits(chip->regmap, CY8C95X0_OUTPUT_(port), bit, bit);
1125 }
1126
1127 static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1128                             unsigned int group)
1129 {
1130         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1131         int ret;
1132
1133         mutex_lock(&chip->i2c_lock);
1134         ret = cy8c95x0_pinmux_mode(chip, selector, group);
1135         mutex_unlock(&chip->i2c_lock);
1136
1137         return ret;
1138 }
1139
1140 static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev,
1141                                         struct pinctrl_gpio_range *range,
1142                                         unsigned int pin)
1143 {
1144         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1145         int ret;
1146
1147         mutex_lock(&chip->i2c_lock);
1148         ret = cy8c95x0_set_mode(chip, pin, false);
1149         mutex_unlock(&chip->i2c_lock);
1150
1151         return ret;
1152 }
1153
1154 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
1155                                      unsigned int pin, bool input)
1156 {
1157         u8 port = cypress_get_port(chip, pin);
1158         u8 bit = cypress_get_pin_mask(chip, pin);
1159         int ret;
1160
1161         /* Select port... */
1162         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
1163         if (ret)
1164                 return ret;
1165
1166         /* ...then direction */
1167         ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, input ? bit : 0);
1168         if (ret)
1169                 return ret;
1170
1171         /*
1172          * Disable driving the pin by forcing it to HighZ. Only setting
1173          * the direction register isn't sufficient in Push-Pull mode.
1174          */
1175         if (input && test_bit(pin, chip->push_pull)) {
1176                 ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit);
1177                 if (ret)
1178                         return ret;
1179
1180                 __clear_bit(pin, chip->push_pull);
1181         }
1182
1183         return 0;
1184 }
1185
1186 static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev,
1187                                        struct pinctrl_gpio_range *range,
1188                                        unsigned int pin, bool input)
1189 {
1190         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1191         int ret;
1192
1193         mutex_lock(&chip->i2c_lock);
1194         ret = cy8c95x0_pinmux_direction(chip, pin, input);
1195         mutex_unlock(&chip->i2c_lock);
1196
1197         return ret;
1198 }
1199
1200 static const struct pinmux_ops cy8c95x0_pmxops = {
1201         .get_functions_count = cy8c95x0_get_functions_count,
1202         .get_function_name = cy8c95x0_get_function_name,
1203         .get_function_groups = cy8c95x0_get_function_groups,
1204         .set_mux = cy8c95x0_set_mux,
1205         .gpio_request_enable = cy8c95x0_gpio_request_enable,
1206         .gpio_set_direction = cy8c95x0_gpio_set_direction,
1207         .strict = true,
1208 };
1209
1210 static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1211                                 unsigned long *config)
1212 {
1213         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1214
1215         return cy8c95x0_gpio_get_pincfg(chip, pin, config);
1216 }
1217
1218 static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1219                                 unsigned long *configs, unsigned int num_configs)
1220 {
1221         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1222         int ret = 0;
1223         int i;
1224
1225         for (i = 0; i < num_configs; i++) {
1226                 ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]);
1227                 if (ret)
1228                         return ret;
1229         }
1230
1231         return ret;
1232 }
1233
1234 static const struct pinconf_ops cy8c95x0_pinconf_ops = {
1235         .pin_config_get = cy8c95x0_pinconf_get,
1236         .pin_config_set = cy8c95x0_pinconf_set,
1237         .is_generic = true,
1238 };
1239
1240 static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq)
1241 {
1242         struct gpio_irq_chip *girq = &chip->gpio_chip.irq;
1243         DECLARE_BITMAP(pending_irqs, MAX_LINE);
1244         int ret;
1245
1246         mutex_init(&chip->irq_lock);
1247
1248         bitmap_zero(pending_irqs, MAX_LINE);
1249
1250         /* Read IRQ status register to clear all pending interrupts */
1251         ret = cy8c95x0_irq_pending(chip, pending_irqs);
1252         if (ret) {
1253                 dev_err(chip->dev, "failed to clear irq status register\n");
1254                 return ret;
1255         }
1256
1257         /* Mask all interrupts */
1258         bitmap_fill(chip->irq_mask, MAX_LINE);
1259
1260         gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip);
1261
1262         /* This will let us handle the parent IRQ in the driver */
1263         girq->parent_handler = NULL;
1264         girq->num_parents = 0;
1265         girq->parents = NULL;
1266         girq->default_type = IRQ_TYPE_NONE;
1267         girq->handler = handle_simple_irq;
1268         girq->threaded = true;
1269
1270         ret = devm_request_threaded_irq(chip->dev, irq,
1271                                         NULL, cy8c95x0_irq_handler,
1272                                         IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH,
1273                                         dev_name(chip->dev), chip);
1274         if (ret) {
1275                 dev_err(chip->dev, "failed to request irq %d\n", irq);
1276                 return ret;
1277         }
1278         dev_info(chip->dev, "Registered threaded IRQ\n");
1279
1280         return 0;
1281 }
1282
1283 static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip)
1284 {
1285         struct pinctrl_desc *pd = &chip->pinctrl_desc;
1286
1287         pd->pctlops = &cy8c95x0_pinctrl_ops;
1288         pd->confops = &cy8c95x0_pinconf_ops;
1289         pd->pmxops = &cy8c95x0_pmxops;
1290         pd->name = dev_name(chip->dev);
1291         pd->pins = cy8c9560_pins;
1292         pd->npins = chip->tpin;
1293         pd->owner = THIS_MODULE;
1294
1295         chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip);
1296         if (IS_ERR(chip->pctldev))
1297                 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev),
1298                         "can't register controller\n");
1299
1300         return 0;
1301 }
1302
1303 static int cy8c95x0_detect(struct i2c_client *client,
1304                            struct i2c_board_info *info)
1305 {
1306         struct i2c_adapter *adapter = client->adapter;
1307         int ret;
1308         const char *name;
1309
1310         if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1311                 return -ENODEV;
1312
1313         ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID);
1314         if (ret < 0)
1315                 return ret;
1316         switch (ret & GENMASK(7, 4)) {
1317         case 0x20:
1318                 name = cy8c95x0_id[0].name;
1319                 break;
1320         case 0x40:
1321                 name = cy8c95x0_id[1].name;
1322                 break;
1323         case 0x60:
1324                 name = cy8c95x0_id[2].name;
1325                 break;
1326         default:
1327                 return -ENODEV;
1328         }
1329
1330         dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr);
1331         strscpy(info->type, name, I2C_NAME_SIZE);
1332
1333         return 0;
1334 }
1335
1336 static int cy8c95x0_probe(struct i2c_client *client)
1337 {
1338         struct cy8c95x0_pinctrl *chip;
1339         struct regulator *reg;
1340         int ret;
1341
1342         chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
1343         if (!chip)
1344                 return -ENOMEM;
1345
1346         chip->dev = &client->dev;
1347
1348         /* Set the device type */
1349         chip->driver_data = (unsigned long)device_get_match_data(&client->dev);
1350         if (!chip->driver_data)
1351                 chip->driver_data = i2c_match_id(cy8c95x0_id, client)->driver_data;
1352         if (!chip->driver_data)
1353                 return -ENODEV;
1354
1355         i2c_set_clientdata(client, chip);
1356
1357         chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
1358         chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
1359
1360         switch (chip->tpin) {
1361         case 20:
1362                 strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE);
1363                 break;
1364         case 40:
1365                 strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE);
1366                 break;
1367         case 60:
1368                 strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE);
1369                 break;
1370         default:
1371                 return -ENODEV;
1372         }
1373
1374         reg = devm_regulator_get(&client->dev, "vdd");
1375         if (IS_ERR(reg)) {
1376                 if (PTR_ERR(reg) == -EPROBE_DEFER)
1377                         return -EPROBE_DEFER;
1378         } else {
1379                 ret = regulator_enable(reg);
1380                 if (ret) {
1381                         dev_err(&client->dev, "failed to enable regulator vdd: %d\n", ret);
1382                         return ret;
1383                 }
1384                 chip->regulator = reg;
1385         }
1386
1387         /* bring the chip out of reset if reset pin is provided */
1388         chip->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH);
1389         if (IS_ERR(chip->gpio_reset)) {
1390                 ret = dev_err_probe(chip->dev, PTR_ERR(chip->gpio_reset),
1391                                     "Failed to get GPIO 'reset'\n");
1392                 goto err_exit;
1393         } else if (chip->gpio_reset) {
1394                 usleep_range(1000, 2000);
1395                 gpiod_set_value_cansleep(chip->gpio_reset, 0);
1396                 usleep_range(250000, 300000);
1397
1398                 gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET");
1399         }
1400
1401         chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap);
1402         if (IS_ERR(chip->regmap)) {
1403                 ret = PTR_ERR(chip->regmap);
1404                 goto err_exit;
1405         }
1406
1407         bitmap_zero(chip->push_pull, MAX_LINE);
1408         bitmap_zero(chip->shiftmask, MAX_LINE);
1409         bitmap_set(chip->shiftmask, 0, 20);
1410         mutex_init(&chip->i2c_lock);
1411
1412         if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) {
1413                 ret = cy8c95x0_acpi_get_irq(&client->dev);
1414                 if (ret > 0)
1415                         client->irq = ret;
1416         }
1417
1418         if (client->irq) {
1419                 ret = cy8c95x0_irq_setup(chip, client->irq);
1420                 if (ret)
1421                         goto err_exit;
1422         }
1423
1424         ret = cy8c95x0_setup_pinctrl(chip);
1425         if (ret)
1426                 goto err_exit;
1427
1428         ret = cy8c95x0_setup_gpiochip(chip);
1429         if (ret)
1430                 goto err_exit;
1431
1432         return 0;
1433
1434 err_exit:
1435         if (!IS_ERR_OR_NULL(chip->regulator))
1436                 regulator_disable(chip->regulator);
1437         return ret;
1438 }
1439
1440 static void cy8c95x0_remove(struct i2c_client *client)
1441 {
1442         struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client);
1443
1444         if (!IS_ERR_OR_NULL(chip->regulator))
1445                 regulator_disable(chip->regulator);
1446 }
1447
1448 static const struct acpi_device_id cy8c95x0_acpi_ids[] = {
1449         { "INT3490", 40, },
1450         { }
1451 };
1452 MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids);
1453
1454 static struct i2c_driver cy8c95x0_driver = {
1455         .driver = {
1456                 .name   = "cy8c95x0-pinctrl",
1457                 .of_match_table = cy8c95x0_dt_ids,
1458                 .acpi_match_table = cy8c95x0_acpi_ids,
1459         },
1460         .probe          = cy8c95x0_probe,
1461         .remove         = cy8c95x0_remove,
1462         .id_table       = cy8c95x0_id,
1463         .detect         = cy8c95x0_detect,
1464 };
1465 module_i2c_driver(cy8c95x0_driver);
1466
1467 MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>");
1468 MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>");
1469 MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0");
1470 MODULE_LICENSE("GPL");