drivers/pinctrl/pinctrl-cy8c95x0.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support
   4  *
   5  * Copyright (C) 2022 9elements GmbH
   6  * Author: Patrick Rudolph <patrick.rudolph@9elements.com>
   7  * Author: Naresh Solanki <Naresh.Solanki@9elements.com>
   8  */
   9
  10 #include <linux/bitmap.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/i2c.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinconf.h>
  21 #include <linux/pinctrl/pinconf-generic.h>
  22 #include <linux/pinctrl/pinmux.h>
  23 #include <linux/regmap.h>
  24 #include <linux/regulator/consumer.h>
  25
  26 /* Fast access registers */
  27 #define CY8C95X0_INPUT          0x00
  28 #define CY8C95X0_OUTPUT         0x08
  29 #define CY8C95X0_INTSTATUS      0x10
  30
  31 #define CY8C95X0_INPUT_(x)      (CY8C95X0_INPUT + (x))
  32 #define CY8C95X0_OUTPUT_(x)     (CY8C95X0_OUTPUT + (x))
  33 #define CY8C95X0_INTSTATUS_(x)  (CY8C95X0_INTSTATUS + (x))
  34
  35 /* Port Select configures the port */
  36 #define CY8C95X0_PORTSEL        0x18
  37 /* port settings, write PORTSEL first */
  38 #define CY8C95X0_INTMASK        0x19
  39 #define CY8C95X0_PWMSEL         0x1A
  40 #define CY8C95X0_INVERT         0x1B
  41 #define CY8C95X0_DIRECTION      0x1C
  42 /* Drive mode register change state on writing '1' */
  43 #define CY8C95X0_DRV_PU         0x1D
  44 #define CY8C95X0_DRV_PD         0x1E
  45 #define CY8C95X0_DRV_ODH        0x1F
  46 #define CY8C95X0_DRV_ODL        0x20
  47 #define CY8C95X0_DRV_PP_FAST    0x21
  48 #define CY8C95X0_DRV_PP_SLOW    0x22
  49 #define CY8C95X0_DRV_HIZ        0x23
  50 #define CY8C95X0_DEVID          0x2E
  51 #define CY8C95X0_WATCHDOG       0x2F
  52 #define CY8C95X0_COMMAND        0x30
  53
  54 #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))
  55
  56 static const struct i2c_device_id cy8c95x0_id[] = {
  57         { "cy8c9520", 20, },
  58         { "cy8c9540", 40, },
  59         { "cy8c9560", 60, },
  60         { }
  61 };
  62 MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
  63
  64 #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))
  65
  66 static const struct of_device_id cy8c95x0_dt_ids[] = {
  67         { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), },
  68         { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), },
  69         { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), },
  70         { }
  71 };
  72
  73 MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);
  74
  75 #define MAX_BANK 8
  76 #define BANK_SZ 8
  77 #define MAX_LINE        (MAX_BANK * BANK_SZ)
  78
  79 #define CY8C95X0_GPIO_MASK              GENMASK(7, 0)
  80
  81 /**
  82  * struct cy8c95x0_pinctrl - driver data
  83  * @regmap:         Device's regmap
  84  * @irq_lock:       IRQ bus lock
  85  * @i2c_lock:       Mutex for the device internal mux register
  86  * @irq_mask:       I/O bits affected by interrupts
  87  * @irq_trig_raise: I/O bits affected by raising voltage level
  88  * @irq_trig_fall:  I/O bits affected by falling voltage level
  89  * @irq_trig_low:   I/O bits affected by a low voltage level
  90  * @irq_trig_high:  I/O bits affected by a high voltage level
  91  * @push_pull:      I/O bits configured as push pull driver
  92  * @shiftmask:      Mask used to compensate for Gport2 width
  93  * @nport:          Number of Gports in this chip
  94  * @gpio_chip:      gpiolib chip
  95  * @driver_data:    private driver data
  96  * @regulator:      Pointer to the regulator for the IC
  97  * @dev:            struct device
  98  * @pctldev:        pin controller device
  99  * @pinctrl_desc:   pin controller description
 100  * @name:           Chip controller name
 101  * @tpin:           Total number of pins
 102  */
 103 struct cy8c95x0_pinctrl {
 104         struct regmap *regmap;
 105         struct mutex irq_lock;
 106         struct mutex i2c_lock;
 107         DECLARE_BITMAP(irq_mask, MAX_LINE);
 108         DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
 109         DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
 110         DECLARE_BITMAP(irq_trig_low, MAX_LINE);
 111         DECLARE_BITMAP(irq_trig_high, MAX_LINE);
 112         DECLARE_BITMAP(push_pull, MAX_LINE);
 113         DECLARE_BITMAP(shiftmask, MAX_LINE);
 114         int nport;
 115         struct gpio_chip gpio_chip;
 116         unsigned long driver_data;
 117         struct regulator *regulator;
 118         struct device *dev;
 119         struct pinctrl_dev *pctldev;
 120         struct pinctrl_desc pinctrl_desc;
 121         char name[32];
 122         unsigned int tpin;
 123 };
 124
 125 static const struct pinctrl_pin_desc cy8c9560_pins[] = {
 126         PINCTRL_PIN(0, "gp00"),
 127         PINCTRL_PIN(1, "gp01"),
 128         PINCTRL_PIN(2, "gp02"),
 129         PINCTRL_PIN(3, "gp03"),
 130         PINCTRL_PIN(4, "gp04"),
 131         PINCTRL_PIN(5, "gp05"),
 132         PINCTRL_PIN(6, "gp06"),
 133         PINCTRL_PIN(7, "gp07"),
 134
 135         PINCTRL_PIN(8, "gp10"),
 136         PINCTRL_PIN(9, "gp11"),
 137         PINCTRL_PIN(10, "gp12"),
 138         PINCTRL_PIN(11, "gp13"),
 139         PINCTRL_PIN(12, "gp14"),
 140         PINCTRL_PIN(13, "gp15"),
 141         PINCTRL_PIN(14, "gp16"),
 142         PINCTRL_PIN(15, "gp17"),
 143
 144         PINCTRL_PIN(16, "gp20"),
 145         PINCTRL_PIN(17, "gp21"),
 146         PINCTRL_PIN(18, "gp22"),
 147         PINCTRL_PIN(19, "gp23"),
 148
 149         PINCTRL_PIN(20, "gp30"),
 150         PINCTRL_PIN(21, "gp31"),
 151         PINCTRL_PIN(22, "gp32"),
 152         PINCTRL_PIN(23, "gp33"),
 153         PINCTRL_PIN(24, "gp34"),
 154         PINCTRL_PIN(25, "gp35"),
 155         PINCTRL_PIN(26, "gp36"),
 156         PINCTRL_PIN(27, "gp37"),
 157
 158         PINCTRL_PIN(28, "gp40"),
 159         PINCTRL_PIN(29, "gp41"),
 160         PINCTRL_PIN(30, "gp42"),
 161         PINCTRL_PIN(31, "gp43"),
 162         PINCTRL_PIN(32, "gp44"),
 163         PINCTRL_PIN(33, "gp45"),
 164         PINCTRL_PIN(34, "gp46"),
 165         PINCTRL_PIN(35, "gp47"),
 166
 167         PINCTRL_PIN(36, "gp50"),
 168         PINCTRL_PIN(37, "gp51"),
 169         PINCTRL_PIN(38, "gp52"),
 170         PINCTRL_PIN(39, "gp53"),
 171         PINCTRL_PIN(40, "gp54"),
 172         PINCTRL_PIN(41, "gp55"),
 173         PINCTRL_PIN(42, "gp56"),
 174         PINCTRL_PIN(43, "gp57"),
 175
 176         PINCTRL_PIN(44, "gp60"),
 177         PINCTRL_PIN(45, "gp61"),
 178         PINCTRL_PIN(46, "gp62"),
 179         PINCTRL_PIN(47, "gp63"),
 180         PINCTRL_PIN(48, "gp64"),
 181         PINCTRL_PIN(49, "gp65"),
 182         PINCTRL_PIN(50, "gp66"),
 183         PINCTRL_PIN(51, "gp67"),
 184
 185         PINCTRL_PIN(52, "gp70"),
 186         PINCTRL_PIN(53, "gp71"),
 187         PINCTRL_PIN(54, "gp72"),
 188         PINCTRL_PIN(55, "gp73"),
 189         PINCTRL_PIN(56, "gp74"),
 190         PINCTRL_PIN(57, "gp75"),
 191         PINCTRL_PIN(58, "gp76"),
 192         PINCTRL_PIN(59, "gp77"),
 193 };
 194
 195 static const char * const cy8c95x0_groups[] = {
 196         "gp00",
 197         "gp01",
 198         "gp02",
 199         "gp03",
 200         "gp04",
 201         "gp05",
 202         "gp06",
 203         "gp07",
 204
 205         "gp10",
 206         "gp11",
 207         "gp12",
 208         "gp13",
 209         "gp14",
 210         "gp15",
 211         "gp16",
 212         "gp17",
 213
 214         "gp20",
 215         "gp21",
 216         "gp22",
 217         "gp23",
 218
 219         "gp30",
 220         "gp31",
 221         "gp32",
 222         "gp33",
 223         "gp34",
 224         "gp35",
 225         "gp36",
 226         "gp37",
 227
 228         "gp40",
 229         "gp41",
 230         "gp42",
 231         "gp43",
 232         "gp44",
 233         "gp45",
 234         "gp46",
 235         "gp47",
 236
 237         "gp50",
 238         "gp51",
 239         "gp52",
 240         "gp53",
 241         "gp54",
 242         "gp55",
 243         "gp56",
 244         "gp57",
 245
 246         "gp60",
 247         "gp61",
 248         "gp62",
 249         "gp63",
 250         "gp64",
 251         "gp65",
 252         "gp66",
 253         "gp67",
 254
 255         "gp70",
 256         "gp71",
 257         "gp72",
 258         "gp73",
 259         "gp74",
 260         "gp75",
 261         "gp76",
 262         "gp77",
 263 };
 264
 265 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin)
 266 {
 267         /* Account for GPORT2 which only has 4 bits */
 268         return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ;
 269 }
 270
 271 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)
 272 {
 273         /* Account for GPORT2 which only has 4 bits */
 274         return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ);
 275 }
 276
 277 static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
 278 {
 279         switch (reg) {
 280         case 0x24 ... 0x27:
 281                 return false;
 282         }
 283
 284         return true;
 285 }
 286
 287 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)
 288 {
 289         switch (reg) {
 290         case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
 291                 return false;
 292         case CY8C95X0_DEVID:
 293                 return false;
 294         case 0x24 ... 0x27:
 295                 return false;
 296         }
 297
 298         return true;
 299 }
 300
 301 static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg)
 302 {
 303         switch (reg) {
 304         case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
 305         case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
 306         case CY8C95X0_INTMASK:
 307         case CY8C95X0_INVERT:
 308         case CY8C95X0_PWMSEL:
 309         case CY8C95X0_DIRECTION:
 310         case CY8C95X0_DRV_PU:
 311         case CY8C95X0_DRV_PD:
 312         case CY8C95X0_DRV_ODH:
 313         case CY8C95X0_DRV_ODL:
 314         case CY8C95X0_DRV_PP_FAST:
 315         case CY8C95X0_DRV_PP_SLOW:
 316         case CY8C95X0_DRV_HIZ:
 317                 return true;
 318         }
 319
 320         return false;
 321 }
 322
 323 static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg)
 324 {
 325         switch (reg) {
 326         case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
 327                 return true;
 328         }
 329
 330         return false;
 331 }
 332
 333 static const struct reg_default cy8c95x0_reg_defaults[] = {
 334         { CY8C95X0_OUTPUT_(0), 0xff },
 335         { CY8C95X0_OUTPUT_(1), 0xff },
 336         { CY8C95X0_OUTPUT_(2), 0xff },
 337         { CY8C95X0_OUTPUT_(3), 0xff },
 338         { CY8C95X0_OUTPUT_(4), 0xff },
 339         { CY8C95X0_OUTPUT_(5), 0xff },
 340         { CY8C95X0_OUTPUT_(6), 0xff },
 341         { CY8C95X0_OUTPUT_(7), 0xff },
 342         { CY8C95X0_PORTSEL, 0 },
 343         { CY8C95X0_PWMSEL, 0 },
 344 };
 345
 346 static const struct regmap_config cy8c95x0_i2c_regmap = {
 347         .reg_bits = 8,
 348         .val_bits = 8,
 349
 350         .reg_defaults = cy8c95x0_reg_defaults,
 351         .num_reg_defaults = ARRAY_SIZE(cy8c95x0_reg_defaults),
 352
 353         .readable_reg = cy8c95x0_readable_register,
 354         .writeable_reg = cy8c95x0_writeable_register,
 355         .volatile_reg = cy8c95x0_volatile_register,
 356         .precious_reg = cy8c95x0_precious_register,
 357
 358         .cache_type = REGCACHE_FLAT,
 359         .max_register = CY8C95X0_COMMAND,
 360 };
 361
 362 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
 363                                     unsigned long *val, unsigned long *mask)
 364 {
 365         DECLARE_BITMAP(tmask, MAX_LINE);
 366         DECLARE_BITMAP(tval, MAX_LINE);
 367         int write_val;
 368         int ret = 0;
 369         int i, off = 0;
 370         u8 bits;
 371
 372         /* Add the 4 bit gap of Gport2 */
 373         bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
 374         bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
 375         bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
 376
 377         bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
 378         bitmap_shift_left(tval, tval, 4, MAX_LINE);
 379         bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
 380
 381         mutex_lock(&chip->i2c_lock);
 382         for (i = 0; i < chip->nport; i++) {
 383                 /* Skip over unused banks */
 384                 bits = bitmap_get_value8(tmask, i * BANK_SZ);
 385                 if (!bits)
 386                         continue;
 387
 388                 switch (reg) {
 389                 /* muxed registers */
 390                 case CY8C95X0_INTMASK:
 391                 case CY8C95X0_PWMSEL:
 392                 case CY8C95X0_INVERT:
 393                 case CY8C95X0_DIRECTION:
 394                 case CY8C95X0_DRV_PU:
 395                 case CY8C95X0_DRV_PD:
 396                 case CY8C95X0_DRV_ODH:
 397                 case CY8C95X0_DRV_ODL:
 398                 case CY8C95X0_DRV_PP_FAST:
 399                 case CY8C95X0_DRV_PP_SLOW:
 400                 case CY8C95X0_DRV_HIZ:
 401                         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i);
 402                         if (ret < 0)
 403                                 goto out;
 404                         off = reg;
 405                         break;
 406                 /* direct access registers */
 407                 case CY8C95X0_INPUT:
 408                 case CY8C95X0_OUTPUT:
 409                 case CY8C95X0_INTSTATUS:
 410                         off = reg + i;
 411                         break;
 412                 default:
 413                         ret = -EINVAL;
 414                         goto out;
 415                 }
 416
 417                 write_val = bitmap_get_value8(tval, i * BANK_SZ);
 418
 419                 ret = regmap_update_bits(chip->regmap, off, bits, write_val);
 420                 if (ret < 0)
 421                         goto out;
 422         }
 423 out:
 424         mutex_unlock(&chip->i2c_lock);
 425
 426         if (ret < 0)
 427                 dev_err(chip->dev, "failed writing register %d: err %d\n", off, ret);
 428
 429         return ret;
 430 }
 431
 432 static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
 433                                    unsigned long *val, unsigned long *mask)
 434 {
 435         DECLARE_BITMAP(tmask, MAX_LINE);
 436         DECLARE_BITMAP(tval, MAX_LINE);
 437         DECLARE_BITMAP(tmp, MAX_LINE);
 438         int read_val;
 439         int ret = 0;
 440         int i, off = 0;
 441         u8 bits;
 442
 443         /* Add the 4 bit gap of Gport2 */
 444         bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
 445         bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
 446         bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
 447
 448         bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
 449         bitmap_shift_left(tval, tval, 4, MAX_LINE);
 450         bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
 451
 452         mutex_lock(&chip->i2c_lock);
 453         for (i = 0; i < chip->nport; i++) {
 454                 /* Skip over unused banks */
 455                 bits = bitmap_get_value8(tmask, i * BANK_SZ);
 456                 if (!bits)
 457                         continue;
 458
 459                 switch (reg) {
 460                 /* muxed registers */
 461                 case CY8C95X0_INTMASK:
 462                 case CY8C95X0_PWMSEL:
 463                 case CY8C95X0_INVERT:
 464                 case CY8C95X0_DIRECTION:
 465                 case CY8C95X0_DRV_PU:
 466                 case CY8C95X0_DRV_PD:
 467                 case CY8C95X0_DRV_ODH:
 468                 case CY8C95X0_DRV_ODL:
 469                 case CY8C95X0_DRV_PP_FAST:
 470                 case CY8C95X0_DRV_PP_SLOW:
 471                 case CY8C95X0_DRV_HIZ:
 472                         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i);
 473                         if (ret < 0)
 474                                 goto out;
 475                         off = reg;
 476                         break;
 477                 /* direct access registers */
 478                 case CY8C95X0_INPUT:
 479                 case CY8C95X0_OUTPUT:
 480                 case CY8C95X0_INTSTATUS:
 481                         off = reg + i;
 482                         break;
 483                 default:
 484                         ret = -EINVAL;
 485                         goto out;
 486                 }
 487
 488                 ret = regmap_read(chip->regmap, off, &read_val);
 489                 if (ret < 0)
 490                         goto out;
 491
 492                 read_val &= bits;
 493                 read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits;
 494                 bitmap_set_value8(tval, read_val, i * BANK_SZ);
 495         }
 496
 497         /* Fill the 4 bit gap of Gport2 */
 498         bitmap_shift_right(tmp, tval, 4, MAX_LINE);
 499         bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE);
 500
 501 out:
 502         mutex_unlock(&chip->i2c_lock);
 503
 504         if (ret < 0)
 505                 dev_err(chip->dev, "failed reading register %d: err %d\n", off, ret);
 506
 507         return ret;
 508 }
 509
 510 static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off)
 511 {
 512         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 513         u8 port = cypress_get_port(chip, off);
 514         u8 bit = cypress_get_pin_mask(chip, off);
 515         int ret;
 516
 517         mutex_lock(&chip->i2c_lock);
 518         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 519         if (ret)
 520                 goto out;
 521
 522         ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit);
 523         if (ret)
 524                 goto out;
 525
 526         if (test_bit(off, chip->push_pull)) {
 527                 /*
 528                  * Disable driving the pin by forcing it to HighZ. Only setting the
 529                  * direction register isn't sufficient in Push-Pull mode.
 530                  */
 531                 ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit);
 532                 if (ret)
 533                         goto out;
 534                 clear_bit(off, chip->push_pull);
 535         }
 536
 537 out:
 538         mutex_unlock(&chip->i2c_lock);
 539
 540         return ret;
 541 }
 542
 543 static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc,
 544                                           unsigned int off, int val)
 545 {
 546         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 547         u8 port = cypress_get_port(chip, off);
 548         u8 outreg = CY8C95X0_OUTPUT_(port);
 549         u8 bit = cypress_get_pin_mask(chip, off);
 550         int ret;
 551
 552         /* set output level */
 553         ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
 554         if (ret)
 555                 return ret;
 556
 557         mutex_lock(&chip->i2c_lock);
 558         /* select port */
 559         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 560         if (ret)
 561                 goto out;
 562
 563         /* then direction */
 564         ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, 0);
 565
 566 out:
 567         mutex_unlock(&chip->i2c_lock);
 568
 569         return ret;
 570 }
 571
 572 static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)
 573 {
 574         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 575         u8 inreg = CY8C95X0_INPUT_(cypress_get_port(chip, off));
 576         u8 bit = cypress_get_pin_mask(chip, off);
 577         u32 reg_val;
 578         int ret;
 579
 580         ret = regmap_read(chip->regmap, inreg, &reg_val);
 581         if (ret < 0) {
 582                 /*
 583                  * NOTE:
 584                  * diagnostic already emitted; that's all we should
 585                  * do unless gpio_*_value_cansleep() calls become different
 586                  * from their nonsleeping siblings (and report faults).
 587                  */
 588                 return 0;
 589         }
 590
 591         return !!(reg_val & bit);
 592 }
 593
 594 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off,
 595                                     int val)
 596 {
 597         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 598         u8 outreg = CY8C95X0_OUTPUT_(cypress_get_port(chip, off));
 599         u8 bit = cypress_get_pin_mask(chip, off);
 600
 601         regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
 602 }
 603
 604 static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
 605 {
 606         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 607         u8 port = cypress_get_port(chip, off);
 608         u8 bit = cypress_get_pin_mask(chip, off);
 609         u32 reg_val;
 610         int ret;
 611
 612         mutex_lock(&chip->i2c_lock);
 613
 614         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 615         if (ret < 0)
 616                 goto out;
 617
 618         ret = regmap_read(chip->regmap, CY8C95X0_DIRECTION, &reg_val);
 619         if (ret < 0)
 620                 goto out;
 621
 622         mutex_unlock(&chip->i2c_lock);
 623
 624         if (reg_val & bit)
 625                 return GPIO_LINE_DIRECTION_IN;
 626
 627         return GPIO_LINE_DIRECTION_OUT;
 628 out:
 629         mutex_unlock(&chip->i2c_lock);
 630         return ret;
 631 }
 632
 633 static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,
 634                                     unsigned int off,
 635                                     unsigned long *config)
 636 {
 637         enum pin_config_param param = pinconf_to_config_param(*config);
 638         u8 port = cypress_get_port(chip, off);
 639         u8 bit = cypress_get_pin_mask(chip, off);
 640         unsigned int reg;
 641         u32 reg_val;
 642         u16 arg = 0;
 643         int ret;
 644
 645         mutex_lock(&chip->i2c_lock);
 646
 647         /* select port */
 648         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 649         if (ret < 0)
 650                 goto out;
 651
 652         switch (param) {
 653         case PIN_CONFIG_BIAS_PULL_UP:
 654                 reg = CY8C95X0_DRV_PU;
 655                 break;
 656         case PIN_CONFIG_BIAS_PULL_DOWN:
 657                 reg = CY8C95X0_DRV_PD;
 658                 break;
 659         case PIN_CONFIG_BIAS_DISABLE:
 660                 reg = CY8C95X0_DRV_HIZ;
 661                 break;
 662         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 663                 reg = CY8C95X0_DRV_ODL;
 664                 break;
 665         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 666                 reg = CY8C95X0_DRV_ODH;
 667                 break;
 668         case PIN_CONFIG_DRIVE_PUSH_PULL:
 669                 reg = CY8C95X0_DRV_PP_FAST;
 670                 break;
 671         case PIN_CONFIG_INPUT_ENABLE:
 672                 reg = CY8C95X0_DIRECTION;
 673                 break;
 674         case PIN_CONFIG_MODE_PWM:
 675                 reg = CY8C95X0_PWMSEL;
 676                 break;
 677         case PIN_CONFIG_OUTPUT:
 678                 reg = CY8C95X0_OUTPUT_(port);
 679                 break;
 680         case PIN_CONFIG_OUTPUT_ENABLE:
 681                 reg = CY8C95X0_DIRECTION;
 682                 break;
 683
 684         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 685         case PIN_CONFIG_BIAS_BUS_HOLD:
 686         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 687         case PIN_CONFIG_DRIVE_STRENGTH:
 688         case PIN_CONFIG_DRIVE_STRENGTH_UA:
 689         case PIN_CONFIG_INPUT_DEBOUNCE:
 690         case PIN_CONFIG_INPUT_SCHMITT:
 691         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 692         case PIN_CONFIG_MODE_LOW_POWER:
 693         case PIN_CONFIG_PERSIST_STATE:
 694         case PIN_CONFIG_POWER_SOURCE:
 695         case PIN_CONFIG_SKEW_DELAY:
 696         case PIN_CONFIG_SLEEP_HARDWARE_STATE:
 697         case PIN_CONFIG_SLEW_RATE:
 698         default:
 699                 ret = -ENOTSUPP;
 700                 goto out;
 701         }
 702         /* Writing 1 to one of the drive mode registers will automatically
 703          * clear conflicting set bits in the other drive mode registers.
 704          */
 705         ret = regmap_read(chip->regmap, reg, &reg_val);
 706         if (reg_val & bit)
 707                 arg = 1;
 708
 709         *config = pinconf_to_config_packed(param, (u16)arg);
 710 out:
 711         mutex_unlock(&chip->i2c_lock);
 712
 713         return ret;
 714 }
 715
 716 static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
 717                                     unsigned int off,
 718                                     unsigned long config)
 719 {
 720         u8 port = cypress_get_port(chip, off);
 721         u8 bit = cypress_get_pin_mask(chip, off);
 722         unsigned long param = pinconf_to_config_param(config);
 723         unsigned int reg;
 724         int ret;
 725
 726         mutex_lock(&chip->i2c_lock);
 727
 728         /* select port */
 729         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
 730         if (ret < 0)
 731                 goto out;
 732
 733         switch (param) {
 734         case PIN_CONFIG_BIAS_PULL_UP:
 735                 clear_bit(off, chip->push_pull);
 736                 reg = CY8C95X0_DRV_PU;
 737                 break;
 738         case PIN_CONFIG_BIAS_PULL_DOWN:
 739                 clear_bit(off, chip->push_pull);
 740                 reg = CY8C95X0_DRV_PD;
 741                 break;
 742         case PIN_CONFIG_BIAS_DISABLE:
 743                 clear_bit(off, chip->push_pull);
 744                 reg = CY8C95X0_DRV_HIZ;
 745                 break;
 746         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 747                 clear_bit(off, chip->push_pull);
 748                 reg = CY8C95X0_DRV_ODL;
 749                 break;
 750         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 751                 clear_bit(off, chip->push_pull);
 752                 reg = CY8C95X0_DRV_ODH;
 753                 break;
 754         case PIN_CONFIG_DRIVE_PUSH_PULL:
 755                 set_bit(off, chip->push_pull);
 756                 reg = CY8C95X0_DRV_PP_FAST;
 757                 break;
 758         case PIN_CONFIG_MODE_PWM:
 759                 reg = CY8C95X0_PWMSEL;
 760                 break;
 761         default:
 762                 ret = -ENOTSUPP;
 763                 goto out;
 764         }
 765         /* Writing 1 to one of the drive mode registers will automatically
 766          * clear conflicting set bits in the other drive mode registers.
 767          */
 768         ret = regmap_write_bits(chip->regmap, reg, bit, bit);
 769
 770 out:
 771         mutex_unlock(&chip->i2c_lock);
 772         return ret;
 773 }
 774
 775 static int cy8c95x0_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
 776                                     unsigned long config)
 777 {
 778         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 779         unsigned long arg = pinconf_to_config_argument(config);
 780
 781         switch (pinconf_to_config_param(config)) {
 782         case PIN_CONFIG_INPUT_ENABLE:
 783                 return cy8c95x0_gpio_direction_input(gc, offset);
 784         case PIN_CONFIG_OUTPUT:
 785                 return cy8c95x0_gpio_direction_output(gc, offset, arg);
 786         case PIN_CONFIG_MODE_PWM:
 787         case PIN_CONFIG_BIAS_PULL_UP:
 788         case PIN_CONFIG_BIAS_PULL_DOWN:
 789         case PIN_CONFIG_BIAS_DISABLE:
 790         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 791         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 792         case PIN_CONFIG_DRIVE_PUSH_PULL:
 793                 return cy8c95x0_gpio_set_pincfg(chip, offset, config);
 794         default:
 795                 return -ENOTSUPP;
 796         }
 797 }
 798
 799 static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc,
 800                                       unsigned long *mask, unsigned long *bits)
 801 {
 802         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 803
 804         return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask);
 805 }
 806
 807 static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc,
 808                                        unsigned long *mask, unsigned long *bits)
 809 {
 810         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 811
 812         cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask);
 813 }
 814
 815 static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip, int ngpio)
 816 {
 817         struct gpio_chip *gc = &chip->gpio_chip;
 818
 819         gc->direction_input  = cy8c95x0_gpio_direction_input;
 820         gc->direction_output = cy8c95x0_gpio_direction_output;
 821         gc->get = cy8c95x0_gpio_get_value;
 822         gc->set = cy8c95x0_gpio_set_value;
 823         gc->get_direction = cy8c95x0_gpio_get_direction;
 824         gc->get_multiple = cy8c95x0_gpio_get_multiple;
 825         gc->set_multiple = cy8c95x0_gpio_set_multiple;
 826         gc->set_config = cy8c95x0_gpio_set_config;
 827         gc->can_sleep = true;
 828
 829         gc->base = -1;
 830         gc->ngpio = ngpio;
 831
 832         gc->parent = chip->dev;
 833         gc->owner = THIS_MODULE;
 834         gc->names = NULL;
 835
 836         gc->label = dev_name(chip->dev);
 837
 838         return devm_gpiochip_add_data(chip->dev, gc, chip);
 839 }
 840
 841 static void cy8c95x0_irq_mask(struct irq_data *d)
 842 {
 843         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 844         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 845         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 846
 847         set_bit(hwirq, chip->irq_mask);
 848         gpiochip_disable_irq(gc, hwirq);
 849 }
 850
 851 static void cy8c95x0_irq_unmask(struct irq_data *d)
 852 {
 853         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 854         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 855         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 856
 857         gpiochip_enable_irq(gc, hwirq);
 858         clear_bit(hwirq, chip->irq_mask);
 859 }
 860
 861 static void cy8c95x0_irq_bus_lock(struct irq_data *d)
 862 {
 863         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 864         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 865
 866         mutex_lock(&chip->irq_lock);
 867 }
 868
 869 static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d)
 870 {
 871         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 872         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 873         DECLARE_BITMAP(ones, MAX_LINE);
 874         DECLARE_BITMAP(irq_mask, MAX_LINE);
 875         DECLARE_BITMAP(reg_direction, MAX_LINE);
 876
 877         bitmap_fill(ones, MAX_LINE);
 878
 879         cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones);
 880
 881         /* Switch direction to input if needed */
 882         cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask);
 883         bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE);
 884         bitmap_complement(irq_mask, irq_mask, MAX_LINE);
 885
 886         /* Look for any newly setup interrupt */
 887         cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask);
 888
 889         mutex_unlock(&chip->irq_lock);
 890 }
 891
 892 static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type)
 893 {
 894         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 895         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 896         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 897         unsigned int trig_type;
 898
 899         switch (type) {
 900         case IRQ_TYPE_EDGE_RISING:
 901         case IRQ_TYPE_EDGE_FALLING:
 902         case IRQ_TYPE_EDGE_BOTH:
 903                 trig_type = type;
 904                 break;
 905         case IRQ_TYPE_LEVEL_HIGH:
 906                 trig_type = IRQ_TYPE_EDGE_RISING;
 907                 break;
 908         case IRQ_TYPE_LEVEL_LOW:
 909                 trig_type = IRQ_TYPE_EDGE_FALLING;
 910                 break;
 911         default:
 912                 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type);
 913                 return -EINVAL;
 914         }
 915
 916         assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING);
 917         assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING);
 918         assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW);
 919         assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH);
 920
 921         return 0;
 922 }
 923
 924 static void cy8c95x0_irq_shutdown(struct irq_data *d)
 925 {
 926         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 927         struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
 928         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 929
 930         clear_bit(hwirq, chip->irq_trig_raise);
 931         clear_bit(hwirq, chip->irq_trig_fall);
 932         clear_bit(hwirq, chip->irq_trig_low);
 933         clear_bit(hwirq, chip->irq_trig_high);
 934 }
 935
 936 static const struct irq_chip cy8c95x0_irqchip = {
 937         .name = "cy8c95x0-irq",
 938         .irq_mask = cy8c95x0_irq_mask,
 939         .irq_unmask = cy8c95x0_irq_unmask,
 940         .irq_bus_lock = cy8c95x0_irq_bus_lock,
 941         .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock,
 942         .irq_set_type = cy8c95x0_irq_set_type,
 943         .irq_shutdown = cy8c95x0_irq_shutdown,
 944         .flags = IRQCHIP_IMMUTABLE,
 945         GPIOCHIP_IRQ_RESOURCE_HELPERS,
 946 };
 947
 948 static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending)
 949 {
 950         DECLARE_BITMAP(ones, MAX_LINE);
 951         DECLARE_BITMAP(cur_stat, MAX_LINE);
 952         DECLARE_BITMAP(new_stat, MAX_LINE);
 953         DECLARE_BITMAP(trigger, MAX_LINE);
 954
 955         bitmap_fill(ones, MAX_LINE);
 956
 957         /* Read the current interrupt status from the device */
 958         if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones))
 959                 return false;
 960
 961         /* Check latched inputs */
 962         if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger))
 963                 return false;
 964
 965         /* Apply filter for rising/falling edge selection */
 966         bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise,
 967                        cur_stat, MAX_LINE);
 968
 969         bitmap_and(pending, new_stat, trigger, MAX_LINE);
 970
 971         return !bitmap_empty(pending, MAX_LINE);
 972 }
 973
 974 static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid)
 975 {
 976         struct cy8c95x0_pinctrl *chip = devid;
 977         struct gpio_chip *gc = &chip->gpio_chip;
 978         DECLARE_BITMAP(pending, MAX_LINE);
 979         int nested_irq, level;
 980         bool ret;
 981
 982         ret = cy8c95x0_irq_pending(chip, pending);
 983         if (!ret)
 984                 return IRQ_RETVAL(0);
 985
 986         ret = 0;
 987         for_each_set_bit(level, pending, MAX_LINE) {
 988                 /* Already accounted for 4bit gap in GPort2 */
 989                 nested_irq = irq_find_mapping(gc->irq.domain, level);
 990
 991                 if (unlikely(nested_irq <= 0)) {
 992                         dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
 993                         continue;
 994                 }
 995
 996                 if (test_bit(level, chip->irq_trig_low))
 997                         while (!cy8c95x0_gpio_get_value(gc, level))
 998                                 handle_nested_irq(nested_irq);
 999                 else if (test_bit(level, chip->irq_trig_high))
1000                         while (cy8c95x0_gpio_get_value(gc, level))
1001                                 handle_nested_irq(nested_irq);
1002                 else
1003                         handle_nested_irq(nested_irq);
1004
1005                 ret = 1;
1006         }
1007
1008         return IRQ_RETVAL(ret);
1009 }
1010
1011 static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
1012 {
1013         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1014
1015         return chip->tpin;
1016 }
1017
1018 static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
1019                                                    unsigned int group)
1020 {
1021         return cy8c95x0_groups[group];
1022 }
1023
1024 static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1025                                            unsigned int group,
1026                                            const unsigned int **pins,
1027                                            unsigned int *num_pins)
1028 {
1029         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1030
1031         if (group >= chip->tpin) {
1032                 *pins = NULL;
1033                 *num_pins = 0;
1034                 return 0;
1035         }
1036
1037         *pins = &cy8c9560_pins[group].number;
1038         *num_pins = 1;
1039         return 0;
1040 }
1041
1042 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = {
1043         .get_groups_count = cy8c95x0_pinctrl_get_groups_count,
1044         .get_group_name = cy8c95x0_pinctrl_get_group_name,
1045         .get_group_pins = cy8c95x0_pinctrl_get_group_pins,
1046         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1047         .dt_free_map = pinconf_generic_dt_free_map,
1048 };
1049
1050 static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev)
1051 {
1052         return 2;
1053 }
1054
1055 static const char *cy8c95x0_get_fname(struct pinctrl_dev *pctldev, unsigned int selector)
1056 {
1057         if (selector == 0)
1058                 return "gpio";
1059         else
1060                 return "pwm";
1061 }
1062
1063 static int cy8c95x0_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
1064                                const char * const **groups,
1065                                unsigned int * const num_groups)
1066 {
1067         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1068
1069         *groups = cy8c95x0_groups;
1070         *num_groups = chip->tpin;
1071         return 0;
1072 }
1073
1074 static int cy8c95x0_pinmux_cfg(struct cy8c95x0_pinctrl *chip,
1075                                unsigned int val,
1076                                unsigned long off)
1077 {
1078         u8 port = cypress_get_port(chip, off);
1079         u8 bit = cypress_get_pin_mask(chip, off);
1080         int ret;
1081
1082         /* select port */
1083         ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
1084         if (ret < 0)
1085                 return ret;
1086
1087         ret = regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, val ? bit : 0);
1088         if (ret < 0)
1089                 return ret;
1090
1091         /* Set direction to output & set output to 1 so that PWM can work */
1092         ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit);
1093         if (ret < 0)
1094                 return ret;
1095
1096         return regmap_write_bits(chip->regmap, CY8C95X0_OUTPUT_(port), bit, bit);
1097 }
1098
1099 static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1100                             unsigned int group)
1101 {
1102         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1103
1104         if (group >= chip->tpin)
1105                 return -EINVAL;
1106
1107         return cy8c95x0_pinmux_cfg(chip, selector, group);
1108 }
1109
1110 static const struct pinmux_ops cy8c95x0_pmxops = {
1111         .get_functions_count = cy8c95x0_get_functions_count,
1112         .get_function_name = cy8c95x0_get_fname,
1113         .get_function_groups = cy8c95x0_get_groups,
1114         .set_mux = cy8c95x0_set_mux,
1115         .strict = true,
1116 };
1117
1118 static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1119                                 unsigned long *config)
1120 {
1121         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1122
1123         return cy8c95x0_gpio_get_pincfg(chip, pin, config);
1124 }
1125
1126 static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1127                                 unsigned long *configs, unsigned int num_configs)
1128 {
1129         struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1130         int ret = 0;
1131         int i;
1132
1133         if (WARN_ON(pin >= chip->tpin))
1134                 return -EINVAL;
1135
1136         for (i = 0; i < num_configs; i++) {
1137                 ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]);
1138                 if (ret)
1139                         return ret;
1140         }
1141
1142         return ret;
1143 }
1144
1145 static const struct pinconf_ops cy8c95x0_pinconf_ops = {
1146         .pin_config_get = cy8c95x0_pinconf_get,
1147         .pin_config_set = cy8c95x0_pinconf_set,
1148         .is_generic = true,
1149 };
1150
1151 static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq)
1152 {
1153         struct gpio_irq_chip *girq = &chip->gpio_chip.irq;
1154         DECLARE_BITMAP(pending_irqs, MAX_LINE);
1155         int ret;
1156
1157         mutex_init(&chip->irq_lock);
1158
1159         bitmap_zero(pending_irqs, MAX_LINE);
1160
1161         /* Read IRQ status register to clear all pending interrupts */
1162         ret = cy8c95x0_irq_pending(chip, pending_irqs);
1163         if (ret) {
1164                 dev_err(chip->dev, "failed to clear irq status register\n");
1165                 return ret;
1166         }
1167
1168         /* Mask all interrupts */
1169         bitmap_fill(chip->irq_mask, MAX_LINE);
1170
1171         gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip);
1172
1173         /* This will let us handle the parent IRQ in the driver */
1174         girq->parent_handler = NULL;
1175         girq->num_parents = 0;
1176         girq->parents = NULL;
1177         girq->default_type = IRQ_TYPE_NONE;
1178         girq->handler = handle_simple_irq;
1179         girq->threaded = true;
1180
1181         ret = devm_request_threaded_irq(chip->dev, irq,
1182                                         NULL, cy8c95x0_irq_handler,
1183                                         IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH,
1184                                         dev_name(chip->dev), chip);
1185         if (ret) {
1186                 dev_err(chip->dev, "failed to request irq %d\n", irq);
1187                 return ret;
1188         }
1189         dev_info(chip->dev, "Registered threaded IRQ\n");
1190
1191         return 0;
1192 }
1193
1194 static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip)
1195 {
1196         struct pinctrl_desc *pd = &chip->pinctrl_desc;
1197
1198         pd->pctlops = &cy8c95x0_pinctrl_ops;
1199         pd->confops = &cy8c95x0_pinconf_ops;
1200         pd->pmxops = &cy8c95x0_pmxops;
1201         pd->npins = chip->gpio_chip.ngpio;
1202         pd->name = devm_kasprintf(chip->dev, GFP_KERNEL, "pinctrl-%s",
1203                                   chip->name);
1204         pd->pins = cy8c9560_pins;
1205         pd->npins = chip->tpin;
1206         pd->owner = THIS_MODULE;
1207         chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip);
1208
1209         if (IS_ERR(chip->pctldev))
1210                 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev),
1211                         "can't register controller\n");
1212         return 0;
1213 }
1214
1215 static int device_cy8c95x0_init(struct cy8c95x0_pinctrl *chip)
1216 {
1217         DECLARE_BITMAP(ones, MAX_LINE);
1218         DECLARE_BITMAP(zeros, MAX_LINE);
1219         int ret;
1220
1221         /* Set all pins to input. This is the POR default. */
1222         bitmap_fill(ones, MAX_LINE);
1223         ret = cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, ones);
1224         if (ret) {
1225                 dev_err(chip->dev, "Failed to set pins to input\n");
1226                 return ret;
1227         }
1228
1229         bitmap_zero(zeros, MAX_LINE);
1230         ret = cy8c95x0_write_regs_mask(chip, CY8C95X0_INVERT, zeros, ones);
1231         if (ret) {
1232                 dev_err(chip->dev, "Failed to set polarity inversion\n");
1233                 return ret;
1234         }
1235
1236         return 0;
1237 }
1238
1239 static int cy8c95x0_detect(struct i2c_client *client,
1240                            struct i2c_board_info *info)
1241 {
1242         struct i2c_adapter *adapter = client->adapter;
1243         int ret;
1244         const char *name;
1245
1246         if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1247                 return -ENODEV;
1248
1249         ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID);
1250         if (ret < 0)
1251                 return ret;
1252         switch (ret & 0xf0) {
1253         case 0x20:
1254                 name = cy8c95x0_id[0].name;
1255                 break;
1256         case 0x40:
1257                 name = cy8c95x0_id[1].name;
1258                 break;
1259         case 0x60:
1260                 name = cy8c95x0_id[2].name;
1261                 break;
1262         default:
1263                 return -ENODEV;
1264         }
1265
1266         dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr);
1267         strscpy(info->type, name, I2C_NAME_SIZE);
1268
1269         return 0;
1270 }
1271
1272 static int cy8c95x0_probe(struct i2c_client *client)
1273 {
1274         struct cy8c95x0_pinctrl *chip;
1275         struct regulator *reg;
1276         int ret;
1277
1278         chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
1279         if (!chip)
1280                 return -ENOMEM;
1281
1282         chip->dev = &client->dev;
1283
1284         /* Set the device type */
1285         if (client->dev.of_node)
1286                 chip->driver_data = (unsigned long)of_device_get_match_data(&client->dev);
1287         else
1288                 chip->driver_data = i2c_match_id(cy8c95x0_id, client)->driver_data;
1289
1290         if (!chip->driver_data)
1291                 return -ENODEV;
1292
1293         i2c_set_clientdata(client, chip);
1294
1295         chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
1296         chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
1297
1298         switch (chip->tpin) {
1299         case 20:
1300                 strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE);
1301                 break;
1302         case 40:
1303                 strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE);
1304                 break;
1305         case 60:
1306                 strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE);
1307                 break;
1308         }
1309
1310         reg = devm_regulator_get(&client->dev, "vdd");
1311         if (IS_ERR(reg)) {
1312                 if (PTR_ERR(reg) == -EPROBE_DEFER)
1313                         return -EPROBE_DEFER;
1314         } else {
1315                 ret = regulator_enable(reg);
1316                 if (ret) {
1317                         dev_err(&client->dev, "failed to enable regulator vdd: %d\n", ret);
1318                         return ret;
1319                 }
1320                 chip->regulator = reg;
1321         }
1322
1323         chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap);
1324         if (IS_ERR(chip->regmap)) {
1325                 ret = PTR_ERR(chip->regmap);
1326                 goto err_exit;
1327         }
1328
1329         bitmap_zero(chip->push_pull, MAX_LINE);
1330         bitmap_zero(chip->shiftmask, MAX_LINE);
1331         bitmap_set(chip->shiftmask, 0, 20);
1332         mutex_init(&chip->i2c_lock);
1333
1334         ret = device_cy8c95x0_init(chip);
1335         if (ret)
1336                 goto err_exit;
1337
1338         if (client->irq) {
1339                 ret = cy8c95x0_irq_setup(chip, client->irq);
1340                 if (ret)
1341                         goto err_exit;
1342         }
1343
1344         ret = cy8c95x0_setup_gpiochip(chip, chip->tpin);
1345         if (ret)
1346                 goto err_exit;
1347
1348         ret = cy8c95x0_setup_pinctrl(chip);
1349         if (ret)
1350                 goto err_exit;
1351
1352         return 0;
1353
1354 err_exit:
1355         if (!IS_ERR_OR_NULL(chip->regulator))
1356                 regulator_disable(chip->regulator);
1357         return ret;
1358 }
1359
1360 static void cy8c95x0_remove(struct i2c_client *client)
1361 {
1362         struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client);
1363
1364         if (!IS_ERR_OR_NULL(chip->regulator))
1365                 regulator_disable(chip->regulator);
1366 }
1367
1368 static struct i2c_driver cy8c95x0_driver = {
1369         .driver = {
1370                 .name   = "cy8c95x0-pinctrl",
1371                 .of_match_table = cy8c95x0_dt_ids,
1372         },
1373         .probe_new      = cy8c95x0_probe,
1374         .remove         = cy8c95x0_remove,
1375         .id_table       = cy8c95x0_id,
1376         .detect         = cy8c95x0_detect,
1377 };
1378
1379 module_i2c_driver(cy8c95x0_driver);
1380
1381 MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>");
1382 MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>");
1383 MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0");
1384 MODULE_LICENSE("GPL");