2 * at91 pinctrl driver based on at91 pinmux core
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/err.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/slab.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/irqchip/chained_irq.h>
23 #include <linux/gpio.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28 /* Since we request GPIOs from ourself */
29 #include <linux/pinctrl/consumer.h>
31 #include <mach/hardware.h>
32 #include <mach/at91_pio.h>
36 #define MAX_NB_GPIO_PER_BANK 32
38 struct at91_pinctrl_mux_ops;
40 struct at91_gpio_chip {
41 struct gpio_chip chip;
42 struct pinctrl_gpio_range range;
43 struct at91_gpio_chip *next; /* Bank sharing same clock */
44 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
45 int pioc_virq; /* PIO bank Linux virtual interrupt */
46 int pioc_idx; /* PIO bank index */
47 void __iomem *regbase; /* PIO bank virtual address */
48 struct clk *clock; /* associated clock */
49 struct irq_domain *domain; /* associated irq domain */
50 struct at91_pinctrl_mux_ops *ops; /* ops */
53 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
55 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
57 static int gpio_banks;
59 #define PULL_UP (1 << 0)
60 #define MULTI_DRIVE (1 << 1)
61 #define DEGLITCH (1 << 2)
62 #define PULL_DOWN (1 << 3)
63 #define DIS_SCHMIT (1 << 4)
64 #define DEBOUNCE (1 << 16)
65 #define DEBOUNCE_VAL_SHIFT 17
66 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
69 * struct at91_pmx_func - describes AT91 pinmux functions
70 * @name: the name of this specific function
71 * @groups: corresponding pin groups
72 * @ngroups: the number of groups
74 struct at91_pmx_func {
82 AT91_MUX_PERIPH_A = 1,
83 AT91_MUX_PERIPH_B = 2,
84 AT91_MUX_PERIPH_C = 3,
85 AT91_MUX_PERIPH_D = 4,
89 * struct at91_pmx_pin - describes an At91 pin mux
90 * @bank: the bank of the pin
91 * @pin: the pin number in the @bank
92 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
93 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
103 * struct at91_pin_group - describes an At91 pin group
104 * @name: the name of this specific pin group
105 * @pins_conf: the mux mode for each pin in this group. The size of this
106 * array is the same as pins.
107 * @pins: an array of discrete physical pins used in this group, taken
108 * from the driver-local pin enumeration space
109 * @npins: the number of pins in this group array, i.e. the number of
110 * elements in .pins so we can iterate over that array
112 struct at91_pin_group {
114 struct at91_pmx_pin *pins_conf;
120 * struct at91_pinctrl_mux_ops - describes an At91 mux ops group
121 * on new IP with support for periph C and D the way to mux in
122 * periph A and B has changed
123 * So provide the right call back
124 * if not present means the IP does not support it
125 * @get_periph: return the periph mode configured
126 * @mux_A_periph: mux as periph A
127 * @mux_B_periph: mux as periph B
128 * @mux_C_periph: mux as periph C
129 * @mux_D_periph: mux as periph D
130 * @get_deglitch: get deglitch status
131 * @set_deglitch: enable/disable deglitch
132 * @get_debounce: get debounce status
133 * @set_debounce: enable/disable debounce
134 * @get_pulldown: get pulldown status
135 * @set_pulldown: enable/disable pulldown
136 * @get_schmitt_trig: get schmitt trigger status
137 * @disable_schmitt_trig: disable schmitt trigger
138 * @irq_type: return irq type
140 struct at91_pinctrl_mux_ops {
141 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
142 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
143 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
144 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
145 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
146 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
147 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on);
148 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
149 void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div);
150 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
151 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on);
152 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
153 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
155 int (*irq_type)(struct irq_data *d, unsigned type);
158 static int gpio_irq_type(struct irq_data *d, unsigned type);
159 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
161 struct at91_pinctrl {
163 struct pinctrl_dev *pctl;
170 struct at91_pmx_func *functions;
173 struct at91_pin_group *groups;
176 struct at91_pinctrl_mux_ops *ops;
179 static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
180 const struct at91_pinctrl *info,
183 const struct at91_pin_group *grp = NULL;
186 for (i = 0; i < info->ngroups; i++) {
187 if (strcmp(info->groups[i].name, name))
190 grp = &info->groups[i];
191 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
198 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
200 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
202 return info->ngroups;
205 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
208 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
210 return info->groups[selector].name;
213 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
214 const unsigned **pins,
217 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
219 if (selector >= info->ngroups)
222 *pins = info->groups[selector].pins;
223 *npins = info->groups[selector].npins;
228 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
231 seq_printf(s, "%s", dev_name(pctldev->dev));
234 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
235 struct device_node *np,
236 struct pinctrl_map **map, unsigned *num_maps)
238 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
239 const struct at91_pin_group *grp;
240 struct pinctrl_map *new_map;
241 struct device_node *parent;
246 * first find the group of this node and check if we need create
247 * config maps for pins
249 grp = at91_pinctrl_find_group_by_name(info, np->name);
251 dev_err(info->dev, "unable to find group for node %s\n",
256 map_num += grp->npins;
257 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
265 parent = of_get_parent(np);
267 devm_kfree(pctldev->dev, new_map);
270 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
271 new_map[0].data.mux.function = parent->name;
272 new_map[0].data.mux.group = np->name;
275 /* create config map */
277 for (i = 0; i < grp->npins; i++) {
278 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
279 new_map[i].data.configs.group_or_pin =
280 pin_get_name(pctldev, grp->pins[i]);
281 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
282 new_map[i].data.configs.num_configs = 1;
285 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
286 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
291 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
292 struct pinctrl_map *map, unsigned num_maps)
296 static const struct pinctrl_ops at91_pctrl_ops = {
297 .get_groups_count = at91_get_groups_count,
298 .get_group_name = at91_get_group_name,
299 .get_group_pins = at91_get_group_pins,
300 .pin_dbg_show = at91_pin_dbg_show,
301 .dt_node_to_map = at91_dt_node_to_map,
302 .dt_free_map = at91_dt_free_map,
305 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
308 return gpio_chips[bank]->regbase;
311 static inline int pin_to_bank(unsigned pin)
313 return pin /= MAX_NB_GPIO_PER_BANK;
316 static unsigned pin_to_mask(unsigned int pin)
321 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
323 writel_relaxed(mask, pio + PIO_IDR);
326 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
328 return (readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1;
331 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
333 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
336 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
338 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
341 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
343 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
346 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
348 writel_relaxed(mask, pio + PIO_ASR);
351 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
353 writel_relaxed(mask, pio + PIO_BSR);
356 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
359 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
361 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
365 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
367 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
369 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
373 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
375 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
376 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
379 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
381 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
382 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
385 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
389 if (readl_relaxed(pio + PIO_PSR) & mask)
390 return AT91_MUX_GPIO;
392 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
393 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
398 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
402 if (readl_relaxed(pio + PIO_PSR) & mask)
403 return AT91_MUX_GPIO;
405 select = readl_relaxed(pio + PIO_ABSR) & mask;
410 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
412 return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1;
415 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
417 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
420 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
423 __raw_writel(mask, pio + PIO_IFSCDR);
424 at91_mux_set_deglitch(pio, mask, is_on);
427 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
429 *div = __raw_readl(pio + PIO_SCDR);
431 return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1;
434 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
438 __raw_writel(mask, pio + PIO_IFSCER);
439 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
440 __raw_writel(mask, pio + PIO_IFER);
442 __raw_writel(mask, pio + PIO_IFDR);
446 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
448 return (__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1;
451 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
453 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
456 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
458 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
461 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
463 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
466 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
467 .get_periph = at91_mux_get_periph,
468 .mux_A_periph = at91_mux_set_A_periph,
469 .mux_B_periph = at91_mux_set_B_periph,
470 .get_deglitch = at91_mux_get_deglitch,
471 .set_deglitch = at91_mux_set_deglitch,
472 .irq_type = gpio_irq_type,
475 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
476 .get_periph = at91_mux_pio3_get_periph,
477 .mux_A_periph = at91_mux_pio3_set_A_periph,
478 .mux_B_periph = at91_mux_pio3_set_B_periph,
479 .mux_C_periph = at91_mux_pio3_set_C_periph,
480 .mux_D_periph = at91_mux_pio3_set_D_periph,
481 .get_deglitch = at91_mux_get_deglitch,
482 .set_deglitch = at91_mux_pio3_set_deglitch,
483 .get_debounce = at91_mux_pio3_get_debounce,
484 .set_debounce = at91_mux_pio3_set_debounce,
485 .get_pulldown = at91_mux_pio3_get_pulldown,
486 .set_pulldown = at91_mux_pio3_set_pulldown,
487 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
488 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
489 .irq_type = alt_gpio_irq_type,
492 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
495 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
496 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
498 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
499 pin->bank + 'A', pin->pin, pin->conf);
503 static int pin_check_config(struct at91_pinctrl *info, const char *name,
504 int index, const struct at91_pmx_pin *pin)
508 /* check if it's a valid config */
509 if (pin->bank >= info->nbanks) {
510 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
511 name, index, pin->bank, info->nbanks);
515 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
516 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
517 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
526 if (mux >= info->nmux) {
527 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
528 name, index, mux, info->nmux);
532 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
533 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
534 name, index, mux, pin->bank + 'A', pin->pin);
541 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
543 writel_relaxed(mask, pio + PIO_PDR);
546 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
548 writel_relaxed(mask, pio + PIO_PER);
549 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
552 static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
555 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
556 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
557 const struct at91_pmx_pin *pin;
558 uint32_t npins = info->groups[group].npins;
563 dev_dbg(info->dev, "enable function %s group %s\n",
564 info->functions[selector].name, info->groups[group].name);
566 /* first check that all the pins of the group are valid with a valid
568 for (i = 0; i < npins; i++) {
570 ret = pin_check_config(info, info->groups[group].name, i, pin);
575 for (i = 0; i < npins; i++) {
577 at91_pin_dbg(info->dev, pin);
578 pio = pin_to_controller(info, pin->bank);
579 mask = pin_to_mask(pin->pin);
580 at91_mux_disable_interrupt(pio, mask);
583 at91_mux_gpio_enable(pio, mask, 1);
585 case AT91_MUX_PERIPH_A:
586 info->ops->mux_A_periph(pio, mask);
588 case AT91_MUX_PERIPH_B:
589 info->ops->mux_B_periph(pio, mask);
591 case AT91_MUX_PERIPH_C:
592 if (!info->ops->mux_C_periph)
594 info->ops->mux_C_periph(pio, mask);
596 case AT91_MUX_PERIPH_D:
597 if (!info->ops->mux_D_periph)
599 info->ops->mux_D_periph(pio, mask);
603 at91_mux_gpio_disable(pio, mask);
609 static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
612 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
613 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
614 const struct at91_pmx_pin *pin;
615 uint32_t npins = info->groups[group].npins;
620 for (i = 0; i < npins; i++) {
622 at91_pin_dbg(info->dev, pin);
623 pio = pin_to_controller(info, pin->bank);
624 mask = pin_to_mask(pin->pin);
625 at91_mux_gpio_enable(pio, mask, 1);
629 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
631 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
633 return info->nfunctions;
636 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
639 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
641 return info->functions[selector].name;
644 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
645 const char * const **groups,
646 unsigned * const num_groups)
648 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
650 *groups = info->functions[selector].groups;
651 *num_groups = info->functions[selector].ngroups;
656 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
657 struct pinctrl_gpio_range *range,
660 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
661 struct at91_gpio_chip *at91_chip;
662 struct gpio_chip *chip;
666 dev_err(npct->dev, "invalid range\n");
670 dev_err(npct->dev, "missing GPIO chip in range\n");
674 at91_chip = container_of(chip, struct at91_gpio_chip, chip);
676 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
678 mask = 1 << (offset - chip->base);
680 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
681 offset, 'A' + range->id, offset - chip->base, mask);
683 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
688 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
689 struct pinctrl_gpio_range *range,
692 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
694 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
695 /* Set the pin to some default state, GPIO is usually default */
698 static const struct pinmux_ops at91_pmx_ops = {
699 .get_functions_count = at91_pmx_get_funcs_count,
700 .get_function_name = at91_pmx_get_func_name,
701 .get_function_groups = at91_pmx_get_groups,
702 .enable = at91_pmx_enable,
703 .disable = at91_pmx_disable,
704 .gpio_request_enable = at91_gpio_request_enable,
705 .gpio_disable_free = at91_gpio_disable_free,
708 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
709 unsigned pin_id, unsigned long *config)
711 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
716 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config);
717 pio = pin_to_controller(info, pin_to_bank(pin_id));
718 pin = pin_id % MAX_NB_GPIO_PER_BANK;
720 if (at91_mux_get_multidrive(pio, pin))
721 *config |= MULTI_DRIVE;
723 if (at91_mux_get_pullup(pio, pin))
726 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
728 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
729 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
730 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
731 *config |= PULL_DOWN;
732 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
733 *config |= DIS_SCHMIT;
738 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
739 unsigned pin_id, unsigned long config)
741 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
745 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config);
746 pio = pin_to_controller(info, pin_to_bank(pin_id));
747 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
749 if (config & PULL_UP && config & PULL_DOWN)
752 at91_mux_set_pullup(pio, mask, config & PULL_UP);
753 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
754 if (info->ops->set_deglitch)
755 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
756 if (info->ops->set_debounce)
757 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
758 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
759 if (info->ops->set_pulldown)
760 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
761 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
762 info->ops->disable_schmitt_trig(pio, mask);
767 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
768 struct seq_file *s, unsigned pin_id)
773 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
774 struct seq_file *s, unsigned group)
778 static const struct pinconf_ops at91_pinconf_ops = {
779 .pin_config_get = at91_pinconf_get,
780 .pin_config_set = at91_pinconf_set,
781 .pin_config_dbg_show = at91_pinconf_dbg_show,
782 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
785 static struct pinctrl_desc at91_pinctrl_desc = {
786 .pctlops = &at91_pctrl_ops,
787 .pmxops = &at91_pmx_ops,
788 .confops = &at91_pinconf_ops,
789 .owner = THIS_MODULE,
792 static const char *gpio_compat = "atmel,at91rm9200-gpio";
794 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
795 struct device_node *np)
797 struct device_node *child;
799 for_each_child_of_node(np, child) {
800 if (of_device_is_compatible(child, gpio_compat)) {
804 info->ngroups += of_get_child_count(child);
809 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
810 struct device_node *np)
816 list = of_get_property(np, "atmel,mux-mask", &size);
818 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
822 size /= sizeof(*list);
823 if (!size || size % info->nbanks) {
824 dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
827 info->nmux = size / info->nbanks;
829 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
830 if (!info->mux_mask) {
831 dev_err(info->dev, "could not alloc mux_mask\n");
835 ret = of_property_read_u32_array(np, "atmel,mux-mask",
836 info->mux_mask, size);
838 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
842 static int at91_pinctrl_parse_groups(struct device_node *np,
843 struct at91_pin_group *grp,
844 struct at91_pinctrl *info, u32 index)
846 struct at91_pmx_pin *pin;
851 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
853 /* Initialise group */
854 grp->name = np->name;
857 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
858 * do sanity check and calculate pins number
860 list = of_get_property(np, "atmel,pins", &size);
861 /* we do not check return since it's safe node passed down */
862 size /= sizeof(*list);
863 if (!size || size % 4) {
864 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
868 grp->npins = size / 4;
869 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
871 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
873 if (!grp->pins_conf || !grp->pins)
876 for (i = 0, j = 0; i < size; i += 4, j++) {
877 pin->bank = be32_to_cpu(*list++);
878 pin->pin = be32_to_cpu(*list++);
879 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
880 pin->mux = be32_to_cpu(*list++);
881 pin->conf = be32_to_cpu(*list++);
883 at91_pin_dbg(info->dev, pin);
890 static int at91_pinctrl_parse_functions(struct device_node *np,
891 struct at91_pinctrl *info, u32 index)
893 struct device_node *child;
894 struct at91_pmx_func *func;
895 struct at91_pin_group *grp;
897 static u32 grp_index;
900 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
902 func = &info->functions[index];
904 /* Initialise function */
905 func->name = np->name;
906 func->ngroups = of_get_child_count(np);
907 if (func->ngroups <= 0) {
908 dev_err(info->dev, "no groups defined\n");
911 func->groups = devm_kzalloc(info->dev,
912 func->ngroups * sizeof(char *), GFP_KERNEL);
916 for_each_child_of_node(np, child) {
917 func->groups[i] = child->name;
918 grp = &info->groups[grp_index++];
919 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
927 static struct of_device_id at91_pinctrl_of_match[] = {
928 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
929 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
933 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
934 struct at91_pinctrl *info)
939 struct device_node *np = pdev->dev.of_node;
940 struct device_node *child;
945 info->dev = &pdev->dev;
946 info->ops = (struct at91_pinctrl_mux_ops *)
947 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
948 at91_pinctrl_child_count(info, np);
950 if (info->nbanks < 1) {
951 dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
955 ret = at91_pinctrl_mux_mask(info, np);
959 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
961 dev_dbg(&pdev->dev, "mux-mask\n");
962 tmp = info->mux_mask;
963 for (i = 0; i < info->nbanks; i++) {
964 for (j = 0; j < info->nmux; j++, tmp++) {
965 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
969 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
970 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
971 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
973 if (!info->functions)
976 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
981 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
982 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
983 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
987 for_each_child_of_node(np, child) {
988 if (of_device_is_compatible(child, gpio_compat))
990 ret = at91_pinctrl_parse_functions(child, info, i++);
992 dev_err(&pdev->dev, "failed to parse function\n");
1000 static int at91_pinctrl_probe(struct platform_device *pdev)
1002 struct at91_pinctrl *info;
1003 struct pinctrl_pin_desc *pdesc;
1006 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1010 ret = at91_pinctrl_probe_dt(pdev, info);
1015 * We need all the GPIO drivers to probe FIRST, or we will not be able
1016 * to obtain references to the struct gpio_chip * for them, and we
1017 * need this to proceed.
1019 for (i = 0; i < info->nbanks; i++) {
1020 if (!gpio_chips[i]) {
1021 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1022 devm_kfree(&pdev->dev, info);
1023 return -EPROBE_DEFER;
1027 at91_pinctrl_desc.name = dev_name(&pdev->dev);
1028 at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
1029 at91_pinctrl_desc.pins = pdesc =
1030 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1032 if (!at91_pinctrl_desc.pins)
1035 for (i = 0 , k = 0; i < info->nbanks; i++) {
1036 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1038 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1043 platform_set_drvdata(pdev, info);
1044 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
1047 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1052 /* We will handle a range of GPIO pins */
1053 for (i = 0; i < info->nbanks; i++)
1054 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1056 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1064 static int at91_pinctrl_remove(struct platform_device *pdev)
1066 struct at91_pinctrl *info = platform_get_drvdata(pdev);
1068 pinctrl_unregister(info->pctl);
1073 static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
1076 * Map back to global GPIO space and request muxing, the direction
1077 * parameter does not matter for this controller.
1079 int gpio = chip->base + offset;
1080 int bank = chip->base / chip->ngpio;
1082 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
1083 'A' + bank, offset, gpio);
1085 return pinctrl_request_gpio(gpio);
1088 static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
1090 int gpio = chip->base + offset;
1092 pinctrl_free_gpio(gpio);
1095 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1097 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1098 void __iomem *pio = at91_gpio->regbase;
1099 unsigned mask = 1 << offset;
1101 writel_relaxed(mask, pio + PIO_ODR);
1105 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1107 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1108 void __iomem *pio = at91_gpio->regbase;
1109 unsigned mask = 1 << offset;
1112 pdsr = readl_relaxed(pio + PIO_PDSR);
1113 return (pdsr & mask) != 0;
1116 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1119 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1120 void __iomem *pio = at91_gpio->regbase;
1121 unsigned mask = 1 << offset;
1123 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1126 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1129 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1130 void __iomem *pio = at91_gpio->regbase;
1131 unsigned mask = 1 << offset;
1133 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1134 writel_relaxed(mask, pio + PIO_OER);
1139 static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1141 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1144 if (offset < chip->ngpio)
1145 virq = irq_create_mapping(at91_gpio->domain, offset);
1149 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
1150 chip->label, offset + chip->base, virq);
1154 #ifdef CONFIG_DEBUG_FS
1155 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1159 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1160 void __iomem *pio = at91_gpio->regbase;
1162 for (i = 0; i < chip->ngpio; i++) {
1163 unsigned pin = chip->base + i;
1164 unsigned mask = pin_to_mask(pin);
1165 const char *gpio_label;
1168 gpio_label = gpiochip_is_requested(chip, i);
1171 mode = at91_gpio->ops->get_periph(pio, mask);
1172 seq_printf(s, "[%s] GPIO%s%d: ",
1173 gpio_label, chip->label, i);
1174 if (mode == AT91_MUX_GPIO) {
1175 pdsr = readl_relaxed(pio + PIO_PDSR);
1177 seq_printf(s, "[gpio] %s\n",
1181 seq_printf(s, "[periph %c]\n",
1187 #define at91_gpio_dbg_show NULL
1190 /* Several AIC controller irqs are dispatched through this GPIO handler.
1191 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1192 * at91_set_gpio_input() then maybe enable its glitch filter.
1193 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1195 * First implementation always triggers on rising and falling edges
1196 * whereas the newer PIO3 can be additionally configured to trigger on
1197 * level, edge with any polarity.
1199 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1200 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1201 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1204 static void gpio_irq_mask(struct irq_data *d)
1206 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1207 void __iomem *pio = at91_gpio->regbase;
1208 unsigned mask = 1 << d->hwirq;
1211 writel_relaxed(mask, pio + PIO_IDR);
1214 static void gpio_irq_unmask(struct irq_data *d)
1216 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1217 void __iomem *pio = at91_gpio->regbase;
1218 unsigned mask = 1 << d->hwirq;
1221 writel_relaxed(mask, pio + PIO_IER);
1224 static int gpio_irq_type(struct irq_data *d, unsigned type)
1228 case IRQ_TYPE_EDGE_BOTH:
1235 /* Alternate irq type for PIO3 support */
1236 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1238 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1239 void __iomem *pio = at91_gpio->regbase;
1240 unsigned mask = 1 << d->hwirq;
1243 case IRQ_TYPE_EDGE_RISING:
1244 irq_set_handler(d->irq, handle_simple_irq);
1245 writel_relaxed(mask, pio + PIO_ESR);
1246 writel_relaxed(mask, pio + PIO_REHLSR);
1248 case IRQ_TYPE_EDGE_FALLING:
1249 irq_set_handler(d->irq, handle_simple_irq);
1250 writel_relaxed(mask, pio + PIO_ESR);
1251 writel_relaxed(mask, pio + PIO_FELLSR);
1253 case IRQ_TYPE_LEVEL_LOW:
1254 irq_set_handler(d->irq, handle_level_irq);
1255 writel_relaxed(mask, pio + PIO_LSR);
1256 writel_relaxed(mask, pio + PIO_FELLSR);
1258 case IRQ_TYPE_LEVEL_HIGH:
1259 irq_set_handler(d->irq, handle_level_irq);
1260 writel_relaxed(mask, pio + PIO_LSR);
1261 writel_relaxed(mask, pio + PIO_REHLSR);
1263 case IRQ_TYPE_EDGE_BOTH:
1265 * disable additional interrupt modes:
1266 * fall back to default behavior
1268 irq_set_handler(d->irq, handle_simple_irq);
1269 writel_relaxed(mask, pio + PIO_AIMDR);
1273 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1277 /* enable additional interrupt modes */
1278 writel_relaxed(mask, pio + PIO_AIMER);
1285 static u32 wakeups[MAX_GPIO_BANKS];
1286 static u32 backups[MAX_GPIO_BANKS];
1288 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1290 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1291 unsigned bank = at91_gpio->pioc_idx;
1292 unsigned mask = 1 << d->hwirq;
1294 if (unlikely(bank >= MAX_GPIO_BANKS))
1298 wakeups[bank] |= mask;
1300 wakeups[bank] &= ~mask;
1302 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1307 void at91_pinctrl_gpio_suspend(void)
1311 for (i = 0; i < gpio_banks; i++) {
1317 pio = gpio_chips[i]->regbase;
1319 backups[i] = __raw_readl(pio + PIO_IMR);
1320 __raw_writel(backups[i], pio + PIO_IDR);
1321 __raw_writel(wakeups[i], pio + PIO_IER);
1324 clk_unprepare(gpio_chips[i]->clock);
1325 clk_disable(gpio_chips[i]->clock);
1327 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1333 void at91_pinctrl_gpio_resume(void)
1337 for (i = 0; i < gpio_banks; i++) {
1343 pio = gpio_chips[i]->regbase;
1346 if (clk_prepare(gpio_chips[i]->clock) == 0)
1347 clk_enable(gpio_chips[i]->clock);
1350 __raw_writel(wakeups[i], pio + PIO_IDR);
1351 __raw_writel(backups[i], pio + PIO_IER);
1356 #define gpio_irq_set_wake NULL
1357 #endif /* CONFIG_PM */
1359 static struct irq_chip gpio_irqchip = {
1361 .irq_disable = gpio_irq_mask,
1362 .irq_mask = gpio_irq_mask,
1363 .irq_unmask = gpio_irq_unmask,
1364 /* .irq_set_type is set dynamically */
1365 .irq_set_wake = gpio_irq_set_wake,
1368 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1370 struct irq_chip *chip = irq_desc_get_chip(desc);
1371 struct irq_data *idata = irq_desc_get_irq_data(desc);
1372 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
1373 void __iomem *pio = at91_gpio->regbase;
1377 chained_irq_enter(chip, desc);
1379 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1380 * When there none are pending, we're finished unless we need
1381 * to process multiple banks (like ID_PIOCDE on sam9263).
1383 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1385 if (!at91_gpio->next)
1387 at91_gpio = at91_gpio->next;
1388 pio = at91_gpio->regbase;
1392 for_each_set_bit(n, &isr, BITS_PER_LONG) {
1393 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
1396 chained_irq_exit(chip, desc);
1397 /* now it may re-trigger */
1401 * This lock class tells lockdep that GPIO irqs are in a different
1402 * category than their parents, so it won't report false recursion.
1404 static struct lock_class_key gpio_lock_class;
1406 static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
1409 struct at91_gpio_chip *at91_gpio = h->host_data;
1410 void __iomem *pio = at91_gpio->regbase;
1413 irq_set_lockdep_class(virq, &gpio_lock_class);
1416 * Can use the "simple" and not "edge" handler since it's
1417 * shorter, and the AIC handles interrupts sanely.
1419 irq_set_chip(virq, &gpio_irqchip);
1420 if ((at91_gpio->ops == &at91sam9x5_ops) &&
1421 (readl_relaxed(pio + PIO_AIMMR) & mask) &&
1422 (readl_relaxed(pio + PIO_ELSR) & mask))
1423 irq_set_handler(virq, handle_level_irq);
1425 irq_set_handler(virq, handle_simple_irq);
1426 set_irq_flags(virq, IRQF_VALID);
1427 irq_set_chip_data(virq, at91_gpio);
1432 static int at91_gpio_irq_domain_xlate(struct irq_domain *d,
1433 struct device_node *ctrlr,
1434 const u32 *intspec, unsigned int intsize,
1435 irq_hw_number_t *out_hwirq,
1436 unsigned int *out_type)
1438 struct at91_gpio_chip *at91_gpio = d->host_data;
1440 int pin = at91_gpio->chip.base + intspec[0];
1442 if (WARN_ON(intsize < 2))
1444 *out_hwirq = intspec[0];
1445 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
1447 ret = gpio_request(pin, ctrlr->full_name);
1451 ret = gpio_direction_input(pin);
1458 static struct irq_domain_ops at91_gpio_ops = {
1459 .map = at91_gpio_irq_map,
1460 .xlate = at91_gpio_irq_domain_xlate,
1463 static int at91_gpio_of_irq_setup(struct device_node *node,
1464 struct at91_gpio_chip *at91_gpio)
1466 struct at91_gpio_chip *prev = NULL;
1467 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1469 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1471 /* Setup proper .irq_set_type function */
1472 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1474 /* Disable irqs of this PIO controller */
1475 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1477 /* Setup irq domain */
1478 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
1479 &at91_gpio_ops, at91_gpio);
1480 if (!at91_gpio->domain)
1481 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
1482 at91_gpio->pioc_idx);
1484 /* Setup chained handler */
1485 if (at91_gpio->pioc_idx)
1486 prev = gpio_chips[at91_gpio->pioc_idx - 1];
1488 /* The toplevel handler handles one bank of GPIOs, except
1489 * on some SoC it can handles up to three...
1490 * We only set up the handler for the first of the list.
1492 if (prev && prev->next == at91_gpio)
1495 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
1496 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
1501 /* This structure is replicated for each GPIO block allocated at probe time */
1502 static struct gpio_chip at91_gpio_template = {
1503 .request = at91_gpio_request,
1504 .free = at91_gpio_free,
1505 .direction_input = at91_gpio_direction_input,
1506 .get = at91_gpio_get,
1507 .direction_output = at91_gpio_direction_output,
1508 .set = at91_gpio_set,
1509 .to_irq = at91_gpio_to_irq,
1510 .dbg_show = at91_gpio_dbg_show,
1512 .ngpio = MAX_NB_GPIO_PER_BANK,
1515 static void at91_gpio_probe_fixup(void)
1518 struct at91_gpio_chip *at91_gpio, *last = NULL;
1520 for (i = 0; i < gpio_banks; i++) {
1521 at91_gpio = gpio_chips[i];
1524 * GPIO controller are grouped on some SoC:
1525 * PIOC, PIOD and PIOE can share the same IRQ line
1527 if (last && last->pioc_virq == at91_gpio->pioc_virq)
1528 last->next = at91_gpio;
1533 static struct of_device_id at91_gpio_of_match[] = {
1534 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1535 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1539 static int at91_gpio_probe(struct platform_device *pdev)
1541 struct device_node *np = pdev->dev.of_node;
1542 struct resource *res;
1543 struct at91_gpio_chip *at91_chip = NULL;
1544 struct gpio_chip *chip;
1545 struct pinctrl_gpio_range *range;
1548 int alias_idx = of_alias_get_id(np, "gpio");
1552 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1553 if (gpio_chips[alias_idx]) {
1558 irq = platform_get_irq(pdev, 0);
1564 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1570 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1571 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1572 if (IS_ERR(at91_chip->regbase)) {
1573 ret = PTR_ERR(at91_chip->regbase);
1577 at91_chip->ops = (struct at91_pinctrl_mux_ops *)
1578 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1579 at91_chip->pioc_virq = irq;
1580 at91_chip->pioc_idx = alias_idx;
1582 at91_chip->clock = clk_get(&pdev->dev, NULL);
1583 if (IS_ERR(at91_chip->clock)) {
1584 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1588 if (clk_prepare(at91_chip->clock))
1591 /* enable PIO controller's clock */
1592 if (clk_enable(at91_chip->clock)) {
1593 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1597 at91_chip->chip = at91_gpio_template;
1599 chip = &at91_chip->chip;
1601 chip->label = dev_name(&pdev->dev);
1602 chip->dev = &pdev->dev;
1603 chip->owner = THIS_MODULE;
1604 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1606 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1607 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1608 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1609 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1611 chip->ngpio = ngpio;
1614 names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
1622 for (i = 0; i < chip->ngpio; i++)
1623 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1625 chip->names = (const char *const *)names;
1627 range = &at91_chip->range;
1628 range->name = chip->label;
1629 range->id = alias_idx;
1630 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1632 range->npins = chip->ngpio;
1635 ret = gpiochip_add(chip);
1639 gpio_chips[alias_idx] = at91_chip;
1640 gpio_banks = max(gpio_banks, alias_idx + 1);
1642 at91_gpio_probe_fixup();
1644 at91_gpio_of_irq_setup(np, at91_chip);
1646 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1651 clk_unprepare(at91_chip->clock);
1653 clk_put(at91_chip->clock);
1655 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1660 static struct platform_driver at91_gpio_driver = {
1662 .name = "gpio-at91",
1663 .owner = THIS_MODULE,
1664 .of_match_table = of_match_ptr(at91_gpio_of_match),
1666 .probe = at91_gpio_probe,
1669 static struct platform_driver at91_pinctrl_driver = {
1671 .name = "pinctrl-at91",
1672 .owner = THIS_MODULE,
1673 .of_match_table = of_match_ptr(at91_pinctrl_of_match),
1675 .probe = at91_pinctrl_probe,
1676 .remove = at91_pinctrl_remove,
1679 static int __init at91_pinctrl_init(void)
1683 ret = platform_driver_register(&at91_gpio_driver);
1686 return platform_driver_register(&at91_pinctrl_driver);
1688 arch_initcall(at91_pinctrl_init);
1690 static void __exit at91_pinctrl_exit(void)
1692 platform_driver_unregister(&at91_pinctrl_driver);
1695 module_exit(at91_pinctrl_exit);
1696 MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1697 MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1698 MODULE_LICENSE("GPL v2");