1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91 pinctrl driver based on at91 pinmux core
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/init.h>
12 #include <linux/of_device.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/slab.h>
16 #include <linux/interrupt.h>
18 #include <linux/gpio/driver.h>
19 #include <linux/pinctrl/machine.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 /* Since we request GPIOs from ourself */
24 #include <linux/pinctrl/consumer.h>
26 #include <soc/at91/pm.h>
28 #include "pinctrl-at91.h"
31 #define MAX_GPIO_BANKS 5
32 #define MAX_NB_GPIO_PER_BANK 32
34 struct at91_pinctrl_mux_ops;
37 * struct at91_gpio_chip: at91 gpio chip
40 * @next: bank sharing same clock
41 * @pioc_hwirq: PIO bank interrupt identifier on AIC
42 * @pioc_virq: PIO bank Linux virtual interrupt
43 * @pioc_idx: PIO bank index
44 * @regbase: PIO bank virtual address
45 * @clock: associated clock
46 * @ops: at91 pinctrl mux ops
48 struct at91_gpio_chip {
49 struct gpio_chip chip;
50 struct pinctrl_gpio_range range;
51 struct at91_gpio_chip *next;
55 void __iomem *regbase;
57 const struct at91_pinctrl_mux_ops *ops;
60 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
62 static int gpio_banks;
64 #define PULL_UP (1 << 0)
65 #define MULTI_DRIVE (1 << 1)
66 #define DEGLITCH (1 << 2)
67 #define PULL_DOWN (1 << 3)
68 #define DIS_SCHMIT (1 << 4)
69 #define DRIVE_STRENGTH_SHIFT 5
70 #define DRIVE_STRENGTH_MASK 0x3
71 #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
72 #define OUTPUT (1 << 7)
73 #define OUTPUT_VAL_SHIFT 8
74 #define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
75 #define SLEWRATE_SHIFT 9
76 #define SLEWRATE_MASK 0x1
77 #define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
78 #define DEBOUNCE (1 << 16)
79 #define DEBOUNCE_VAL_SHIFT 17
80 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
83 * These defines will translated the dt binding settings to our internal
84 * settings. They are not necessarily the same value as the register setting.
85 * The actual drive strength current of low, medium and high must be looked up
86 * from the corresponding device datasheet. This value is different for pins
87 * that are even in the same banks. It is also dependent on VCC.
88 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
89 * strength when there is no dt config for it.
91 enum drive_strength_bit {
92 DRIVE_STRENGTH_BIT_DEF,
93 DRIVE_STRENGTH_BIT_LOW,
94 DRIVE_STRENGTH_BIT_MED,
95 DRIVE_STRENGTH_BIT_HI,
98 #define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
106 #define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
109 * struct at91_pmx_func - describes AT91 pinmux functions
110 * @name: the name of this specific function
111 * @groups: corresponding pin groups
112 * @ngroups: the number of groups
114 struct at91_pmx_func {
122 AT91_MUX_PERIPH_A = 1,
123 AT91_MUX_PERIPH_B = 2,
124 AT91_MUX_PERIPH_C = 3,
125 AT91_MUX_PERIPH_D = 4,
129 * struct at91_pmx_pin - describes an At91 pin mux
130 * @bank: the bank of the pin
131 * @pin: the pin number in the @bank
132 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
133 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
135 struct at91_pmx_pin {
143 * struct at91_pin_group - describes an At91 pin group
144 * @name: the name of this specific pin group
145 * @pins_conf: the mux mode for each pin in this group. The size of this
146 * array is the same as pins.
147 * @pins: an array of discrete physical pins used in this group, taken
148 * from the driver-local pin enumeration space
149 * @npins: the number of pins in this group array, i.e. the number of
150 * elements in .pins so we can iterate over that array
152 struct at91_pin_group {
154 struct at91_pmx_pin *pins_conf;
160 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
161 * on new IP with support for periph C and D the way to mux in
162 * periph A and B has changed
163 * So provide the right call back
164 * if not present means the IP does not support it
165 * @get_periph: return the periph mode configured
166 * @mux_A_periph: mux as periph A
167 * @mux_B_periph: mux as periph B
168 * @mux_C_periph: mux as periph C
169 * @mux_D_periph: mux as periph D
170 * @get_deglitch: get deglitch status
171 * @set_deglitch: enable/disable deglitch
172 * @get_debounce: get debounce status
173 * @set_debounce: enable/disable debounce
174 * @get_pulldown: get pulldown status
175 * @set_pulldown: enable/disable pulldown
176 * @get_schmitt_trig: get schmitt trigger status
177 * @disable_schmitt_trig: disable schmitt trigger
178 * @get_drivestrength: get driver strength
179 * @set_drivestrength: set driver strength
180 * @get_slewrate: get slew rate
181 * @set_slewrate: set slew rate
182 * @irq_type: return irq type
184 struct at91_pinctrl_mux_ops {
185 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
186 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
187 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
188 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
189 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
190 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
191 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
192 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
193 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
194 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
195 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
196 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
197 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
198 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
199 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
201 unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
202 void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
204 int (*irq_type)(struct irq_data *d, unsigned type);
207 static int gpio_irq_type(struct irq_data *d, unsigned type);
208 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
210 struct at91_pinctrl {
212 struct pinctrl_dev *pctl;
219 struct at91_pmx_func *functions;
222 struct at91_pin_group *groups;
225 const struct at91_pinctrl_mux_ops *ops;
228 static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
229 const struct at91_pinctrl *info,
232 const struct at91_pin_group *grp = NULL;
235 for (i = 0; i < info->ngroups; i++) {
236 if (strcmp(info->groups[i].name, name))
239 grp = &info->groups[i];
240 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
247 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
249 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
251 return info->ngroups;
254 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
257 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
259 return info->groups[selector].name;
262 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
263 const unsigned **pins,
266 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
268 if (selector >= info->ngroups)
271 *pins = info->groups[selector].pins;
272 *npins = info->groups[selector].npins;
277 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
280 seq_printf(s, "%s", dev_name(pctldev->dev));
283 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
284 struct device_node *np,
285 struct pinctrl_map **map, unsigned *num_maps)
287 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
288 const struct at91_pin_group *grp;
289 struct pinctrl_map *new_map;
290 struct device_node *parent;
295 * first find the group of this node and check if we need to create
296 * config maps for pins
298 grp = at91_pinctrl_find_group_by_name(info, np->name);
300 dev_err(info->dev, "unable to find group for node %pOFn\n",
305 map_num += grp->npins;
306 new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
315 parent = of_get_parent(np);
317 devm_kfree(pctldev->dev, new_map);
320 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
321 new_map[0].data.mux.function = parent->name;
322 new_map[0].data.mux.group = np->name;
325 /* create config map */
327 for (i = 0; i < grp->npins; i++) {
328 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
329 new_map[i].data.configs.group_or_pin =
330 pin_get_name(pctldev, grp->pins[i]);
331 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
332 new_map[i].data.configs.num_configs = 1;
335 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
336 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
341 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
342 struct pinctrl_map *map, unsigned num_maps)
346 static const struct pinctrl_ops at91_pctrl_ops = {
347 .get_groups_count = at91_get_groups_count,
348 .get_group_name = at91_get_group_name,
349 .get_group_pins = at91_get_group_pins,
350 .pin_dbg_show = at91_pin_dbg_show,
351 .dt_node_to_map = at91_dt_node_to_map,
352 .dt_free_map = at91_dt_free_map,
355 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
358 if (!gpio_chips[bank])
361 return gpio_chips[bank]->regbase;
364 static inline int pin_to_bank(unsigned pin)
366 return pin /= MAX_NB_GPIO_PER_BANK;
369 static unsigned pin_to_mask(unsigned int pin)
374 static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
376 /* return the shift value for a pin for "two bit" per pin registers,
377 * i.e. drive strength */
378 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
379 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
382 static unsigned sama5d3_get_drive_register(unsigned int pin)
384 /* drive strength is split between two registers
385 * with two bits per pin */
386 return (pin >= MAX_NB_GPIO_PER_BANK/2)
387 ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
390 static unsigned at91sam9x5_get_drive_register(unsigned int pin)
392 /* drive strength is split between two registers
393 * with two bits per pin */
394 return (pin >= MAX_NB_GPIO_PER_BANK/2)
395 ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
398 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
400 writel_relaxed(mask, pio + PIO_IDR);
403 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
405 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
408 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
411 writel_relaxed(mask, pio + PIO_PPDDR);
413 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
416 static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val)
418 *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1;
419 return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1;
422 static void at91_mux_set_output(void __iomem *pio, unsigned int mask,
423 bool is_on, bool val)
425 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
426 writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
429 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
431 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
434 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
436 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
439 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
441 writel_relaxed(mask, pio + PIO_ASR);
444 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
446 writel_relaxed(mask, pio + PIO_BSR);
449 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
452 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
454 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
458 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
460 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
462 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
466 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
468 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
469 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
472 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
474 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
475 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
478 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
482 if (readl_relaxed(pio + PIO_PSR) & mask)
483 return AT91_MUX_GPIO;
485 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
486 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
491 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
495 if (readl_relaxed(pio + PIO_PSR) & mask)
496 return AT91_MUX_GPIO;
498 select = readl_relaxed(pio + PIO_ABSR) & mask;
503 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
505 return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
508 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
510 writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
513 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
515 if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
516 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
521 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
524 writel_relaxed(mask, pio + PIO_IFSCDR);
525 at91_mux_set_deglitch(pio, mask, is_on);
528 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
530 *div = readl_relaxed(pio + PIO_SCDR);
532 return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
533 ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
536 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
540 writel_relaxed(mask, pio + PIO_IFSCER);
541 writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
542 writel_relaxed(mask, pio + PIO_IFER);
544 writel_relaxed(mask, pio + PIO_IFSCDR);
547 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
549 return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
552 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
555 writel_relaxed(mask, pio + PIO_PUDR);
557 writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
560 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
562 writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
565 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
567 return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
570 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
572 unsigned tmp = readl_relaxed(reg);
574 tmp = tmp >> two_bit_pin_value_shift_amount(pin);
576 return tmp & DRIVE_STRENGTH_MASK;
579 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
582 unsigned tmp = read_drive_strength(pio +
583 sama5d3_get_drive_register(pin), pin);
585 /* SAMA5 strength is 1:1 with our defines,
586 * except 0 is equivalent to low per datasheet */
588 tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
593 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
596 unsigned tmp = read_drive_strength(pio +
597 at91sam9x5_get_drive_register(pin), pin);
599 /* strength is inverse in SAM9x5s hardware with the pinctrl defines
600 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
601 tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
606 static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
609 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
612 return DRIVE_STRENGTH_BIT_HI;
614 return DRIVE_STRENGTH_BIT_LOW;
617 static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
619 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
621 if ((tmp & BIT(pin)))
622 return SLEWRATE_BIT_ENA;
624 return SLEWRATE_BIT_DIS;
627 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
629 unsigned tmp = readl_relaxed(reg);
630 unsigned shift = two_bit_pin_value_shift_amount(pin);
632 tmp &= ~(DRIVE_STRENGTH_MASK << shift);
633 tmp |= strength << shift;
635 writel_relaxed(tmp, reg);
638 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
641 /* do nothing if setting is zero */
645 /* strength is 1 to 1 with setting for SAMA5 */
646 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
649 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
652 /* do nothing if setting is zero */
656 /* strength is inverse on SAM9x5s with our defines
657 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
658 setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
660 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
664 static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
669 if (setting <= DRIVE_STRENGTH_BIT_DEF ||
670 setting == DRIVE_STRENGTH_BIT_MED ||
671 setting > DRIVE_STRENGTH_BIT_HI)
674 tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
676 /* Strength is 0: low, 1: hi */
677 if (setting == DRIVE_STRENGTH_BIT_LOW)
682 writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
685 static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
690 if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
693 tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
695 if (setting == SLEWRATE_BIT_DIS)
700 writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
703 static const struct at91_pinctrl_mux_ops at91rm9200_ops = {
704 .get_periph = at91_mux_get_periph,
705 .mux_A_periph = at91_mux_set_A_periph,
706 .mux_B_periph = at91_mux_set_B_periph,
707 .get_deglitch = at91_mux_get_deglitch,
708 .set_deglitch = at91_mux_set_deglitch,
709 .irq_type = gpio_irq_type,
712 static const struct at91_pinctrl_mux_ops at91sam9x5_ops = {
713 .get_periph = at91_mux_pio3_get_periph,
714 .mux_A_periph = at91_mux_pio3_set_A_periph,
715 .mux_B_periph = at91_mux_pio3_set_B_periph,
716 .mux_C_periph = at91_mux_pio3_set_C_periph,
717 .mux_D_periph = at91_mux_pio3_set_D_periph,
718 .get_deglitch = at91_mux_pio3_get_deglitch,
719 .set_deglitch = at91_mux_pio3_set_deglitch,
720 .get_debounce = at91_mux_pio3_get_debounce,
721 .set_debounce = at91_mux_pio3_set_debounce,
722 .get_pulldown = at91_mux_pio3_get_pulldown,
723 .set_pulldown = at91_mux_pio3_set_pulldown,
724 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
725 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
726 .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
727 .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
728 .irq_type = alt_gpio_irq_type,
731 static const struct at91_pinctrl_mux_ops sam9x60_ops = {
732 .get_periph = at91_mux_pio3_get_periph,
733 .mux_A_periph = at91_mux_pio3_set_A_periph,
734 .mux_B_periph = at91_mux_pio3_set_B_periph,
735 .mux_C_periph = at91_mux_pio3_set_C_periph,
736 .mux_D_periph = at91_mux_pio3_set_D_periph,
737 .get_deglitch = at91_mux_pio3_get_deglitch,
738 .set_deglitch = at91_mux_pio3_set_deglitch,
739 .get_debounce = at91_mux_pio3_get_debounce,
740 .set_debounce = at91_mux_pio3_set_debounce,
741 .get_pulldown = at91_mux_pio3_get_pulldown,
742 .set_pulldown = at91_mux_pio3_set_pulldown,
743 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
744 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
745 .get_drivestrength = at91_mux_sam9x60_get_drivestrength,
746 .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
747 .get_slewrate = at91_mux_sam9x60_get_slewrate,
748 .set_slewrate = at91_mux_sam9x60_set_slewrate,
749 .irq_type = alt_gpio_irq_type,
752 static const struct at91_pinctrl_mux_ops sama5d3_ops = {
753 .get_periph = at91_mux_pio3_get_periph,
754 .mux_A_periph = at91_mux_pio3_set_A_periph,
755 .mux_B_periph = at91_mux_pio3_set_B_periph,
756 .mux_C_periph = at91_mux_pio3_set_C_periph,
757 .mux_D_periph = at91_mux_pio3_set_D_periph,
758 .get_deglitch = at91_mux_pio3_get_deglitch,
759 .set_deglitch = at91_mux_pio3_set_deglitch,
760 .get_debounce = at91_mux_pio3_get_debounce,
761 .set_debounce = at91_mux_pio3_set_debounce,
762 .get_pulldown = at91_mux_pio3_get_pulldown,
763 .set_pulldown = at91_mux_pio3_set_pulldown,
764 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
765 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
766 .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
767 .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
768 .irq_type = alt_gpio_irq_type,
771 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
774 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
775 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
777 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
778 pin->bank + 'A', pin->pin, pin->conf);
782 static int pin_check_config(struct at91_pinctrl *info, const char *name,
783 int index, const struct at91_pmx_pin *pin)
787 /* check if it's a valid config */
788 if (pin->bank >= gpio_banks) {
789 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
790 name, index, pin->bank, gpio_banks);
794 if (!gpio_chips[pin->bank]) {
795 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
796 name, index, pin->bank);
800 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
801 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
802 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
811 if (mux >= info->nmux) {
812 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
813 name, index, mux, info->nmux);
817 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
818 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
819 name, index, mux, pin->bank + 'A', pin->pin);
826 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
828 writel_relaxed(mask, pio + PIO_PDR);
831 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
833 writel_relaxed(mask, pio + PIO_PER);
834 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
837 static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
840 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
841 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
842 const struct at91_pmx_pin *pin;
843 uint32_t npins = info->groups[group].npins;
848 dev_dbg(info->dev, "enable function %s group %s\n",
849 info->functions[selector].name, info->groups[group].name);
851 /* first check that all the pins of the group are valid with a valid
853 for (i = 0; i < npins; i++) {
855 ret = pin_check_config(info, info->groups[group].name, i, pin);
860 for (i = 0; i < npins; i++) {
862 at91_pin_dbg(info->dev, pin);
863 pio = pin_to_controller(info, pin->bank);
868 mask = pin_to_mask(pin->pin);
869 at91_mux_disable_interrupt(pio, mask);
872 at91_mux_gpio_enable(pio, mask, 1);
874 case AT91_MUX_PERIPH_A:
875 info->ops->mux_A_periph(pio, mask);
877 case AT91_MUX_PERIPH_B:
878 info->ops->mux_B_periph(pio, mask);
880 case AT91_MUX_PERIPH_C:
881 if (!info->ops->mux_C_periph)
883 info->ops->mux_C_periph(pio, mask);
885 case AT91_MUX_PERIPH_D:
886 if (!info->ops->mux_D_periph)
888 info->ops->mux_D_periph(pio, mask);
892 at91_mux_gpio_disable(pio, mask);
898 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
900 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
902 return info->nfunctions;
905 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
908 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
910 return info->functions[selector].name;
913 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
914 const char * const **groups,
915 unsigned * const num_groups)
917 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
919 *groups = info->functions[selector].groups;
920 *num_groups = info->functions[selector].ngroups;
925 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
926 struct pinctrl_gpio_range *range,
929 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
930 struct at91_gpio_chip *at91_chip;
931 struct gpio_chip *chip;
935 dev_err(npct->dev, "invalid range\n");
939 dev_err(npct->dev, "missing GPIO chip in range\n");
943 at91_chip = gpiochip_get_data(chip);
945 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
947 mask = 1 << (offset - chip->base);
949 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
950 offset, 'A' + range->id, offset - chip->base, mask);
952 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
957 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
958 struct pinctrl_gpio_range *range,
961 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
963 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
964 /* Set the pin to some default state, GPIO is usually default */
967 static const struct pinmux_ops at91_pmx_ops = {
968 .get_functions_count = at91_pmx_get_funcs_count,
969 .get_function_name = at91_pmx_get_func_name,
970 .get_function_groups = at91_pmx_get_groups,
971 .set_mux = at91_pmx_set,
972 .gpio_request_enable = at91_gpio_request_enable,
973 .gpio_disable_free = at91_gpio_disable_free,
976 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
977 unsigned pin_id, unsigned long *config)
979 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
986 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
987 pio = pin_to_controller(info, pin_to_bank(pin_id));
992 pin = pin_id % MAX_NB_GPIO_PER_BANK;
994 if (at91_mux_get_multidrive(pio, pin))
995 *config |= MULTI_DRIVE;
997 if (at91_mux_get_pullup(pio, pin))
1000 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
1001 *config |= DEGLITCH;
1002 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
1003 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
1004 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
1005 *config |= PULL_DOWN;
1006 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
1007 *config |= DIS_SCHMIT;
1008 if (info->ops->get_drivestrength)
1009 *config |= (info->ops->get_drivestrength(pio, pin)
1010 << DRIVE_STRENGTH_SHIFT);
1011 if (info->ops->get_slewrate)
1012 *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
1013 if (at91_mux_get_output(pio, pin, &out))
1014 *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
1019 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
1020 unsigned pin_id, unsigned long *configs,
1021 unsigned num_configs)
1023 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1027 unsigned long config;
1030 for (i = 0; i < num_configs; i++) {
1031 config = configs[i];
1034 "%s:%d, pin_id=%d, config=0x%lx",
1035 __func__, __LINE__, pin_id, config);
1036 pio = pin_to_controller(info, pin_to_bank(pin_id));
1041 pin = pin_id % MAX_NB_GPIO_PER_BANK;
1042 mask = pin_to_mask(pin);
1044 if (config & PULL_UP && config & PULL_DOWN)
1047 at91_mux_set_output(pio, mask, config & OUTPUT,
1048 (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
1049 at91_mux_set_pullup(pio, mask, config & PULL_UP);
1050 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
1051 if (info->ops->set_deglitch)
1052 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
1053 if (info->ops->set_debounce)
1054 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
1055 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
1056 if (info->ops->set_pulldown)
1057 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
1058 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
1059 info->ops->disable_schmitt_trig(pio, mask);
1060 if (info->ops->set_drivestrength)
1061 info->ops->set_drivestrength(pio, pin,
1062 (config & DRIVE_STRENGTH)
1063 >> DRIVE_STRENGTH_SHIFT);
1064 if (info->ops->set_slewrate)
1065 info->ops->set_slewrate(pio, pin,
1066 (config & SLEWRATE) >> SLEWRATE_SHIFT);
1068 } /* for each config */
1073 #define DBG_SHOW_FLAG(flag) do { \
1074 if (config & flag) { \
1077 seq_puts(s, #flag); \
1082 #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \
1083 if ((config & mask) == flag) { \
1086 seq_puts(s, #name); \
1091 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1092 struct seq_file *s, unsigned pin_id)
1094 unsigned long config;
1095 int val, num_conf = 0;
1097 at91_pinconf_get(pctldev, pin_id, &config);
1099 DBG_SHOW_FLAG(MULTI_DRIVE);
1100 DBG_SHOW_FLAG(PULL_UP);
1101 DBG_SHOW_FLAG(PULL_DOWN);
1102 DBG_SHOW_FLAG(DIS_SCHMIT);
1103 DBG_SHOW_FLAG(DEGLITCH);
1104 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
1105 DRIVE_STRENGTH_LOW);
1106 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
1107 DRIVE_STRENGTH_MED);
1108 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
1110 DBG_SHOW_FLAG(SLEWRATE);
1111 DBG_SHOW_FLAG(DEBOUNCE);
1112 if (config & DEBOUNCE) {
1113 val = config >> DEBOUNCE_VAL_SHIFT;
1114 seq_printf(s, "(%d)", val);
1120 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
1121 struct seq_file *s, unsigned group)
1125 static const struct pinconf_ops at91_pinconf_ops = {
1126 .pin_config_get = at91_pinconf_get,
1127 .pin_config_set = at91_pinconf_set,
1128 .pin_config_dbg_show = at91_pinconf_dbg_show,
1129 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
1132 static struct pinctrl_desc at91_pinctrl_desc = {
1133 .pctlops = &at91_pctrl_ops,
1134 .pmxops = &at91_pmx_ops,
1135 .confops = &at91_pinconf_ops,
1136 .owner = THIS_MODULE,
1139 static const char *gpio_compat = "atmel,at91rm9200-gpio";
1141 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
1142 struct device_node *np)
1144 struct device_node *child;
1146 for_each_child_of_node(np, child) {
1147 if (of_device_is_compatible(child, gpio_compat)) {
1148 if (of_device_is_available(child))
1149 info->nactive_banks++;
1152 info->ngroups += of_get_child_count(child);
1157 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1158 struct device_node *np)
1164 list = of_get_property(np, "atmel,mux-mask", &size);
1166 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1170 size /= sizeof(*list);
1171 if (!size || size % gpio_banks) {
1172 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1175 info->nmux = size / gpio_banks;
1177 info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32),
1179 if (!info->mux_mask)
1182 ret = of_property_read_u32_array(np, "atmel,mux-mask",
1183 info->mux_mask, size);
1185 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1189 static int at91_pinctrl_parse_groups(struct device_node *np,
1190 struct at91_pin_group *grp,
1191 struct at91_pinctrl *info, u32 index)
1193 struct at91_pmx_pin *pin;
1198 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
1200 /* Initialise group */
1201 grp->name = np->name;
1204 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1205 * do sanity check and calculate pins number
1207 list = of_get_property(np, "atmel,pins", &size);
1208 /* we do not check return since it's safe node passed down */
1209 size /= sizeof(*list);
1210 if (!size || size % 4) {
1211 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1215 grp->npins = size / 4;
1216 pin = grp->pins_conf = devm_kcalloc(info->dev,
1218 sizeof(struct at91_pmx_pin),
1220 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
1222 if (!grp->pins_conf || !grp->pins)
1225 for (i = 0, j = 0; i < size; i += 4, j++) {
1226 pin->bank = be32_to_cpu(*list++);
1227 pin->pin = be32_to_cpu(*list++);
1228 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1229 pin->mux = be32_to_cpu(*list++);
1230 pin->conf = be32_to_cpu(*list++);
1232 at91_pin_dbg(info->dev, pin);
1239 static int at91_pinctrl_parse_functions(struct device_node *np,
1240 struct at91_pinctrl *info, u32 index)
1242 struct device_node *child;
1243 struct at91_pmx_func *func;
1244 struct at91_pin_group *grp;
1246 static u32 grp_index;
1249 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
1251 func = &info->functions[index];
1253 /* Initialise function */
1254 func->name = np->name;
1255 func->ngroups = of_get_child_count(np);
1256 if (func->ngroups == 0) {
1257 dev_err(info->dev, "no groups defined\n");
1260 func->groups = devm_kcalloc(info->dev,
1261 func->ngroups, sizeof(char *), GFP_KERNEL);
1265 for_each_child_of_node(np, child) {
1266 func->groups[i] = child->name;
1267 grp = &info->groups[grp_index++];
1268 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1278 static const struct of_device_id at91_pinctrl_of_match[] = {
1279 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1280 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1281 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1282 { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
1286 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1287 struct at91_pinctrl *info)
1292 struct device_node *np = pdev->dev.of_node;
1293 struct device_node *child;
1298 info->dev = &pdev->dev;
1299 info->ops = (const struct at91_pinctrl_mux_ops *)
1300 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1301 at91_pinctrl_child_count(info, np);
1303 if (gpio_banks < 1) {
1304 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
1308 ret = at91_pinctrl_mux_mask(info, np);
1312 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1314 dev_dbg(&pdev->dev, "mux-mask\n");
1315 tmp = info->mux_mask;
1316 for (i = 0; i < gpio_banks; i++) {
1317 for (j = 0; j < info->nmux; j++, tmp++) {
1318 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1322 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1323 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1324 info->functions = devm_kcalloc(&pdev->dev,
1326 sizeof(struct at91_pmx_func),
1328 if (!info->functions)
1331 info->groups = devm_kcalloc(&pdev->dev,
1333 sizeof(struct at91_pin_group),
1338 dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
1339 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1340 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1344 for_each_child_of_node(np, child) {
1345 if (of_device_is_compatible(child, gpio_compat))
1347 ret = at91_pinctrl_parse_functions(child, info, i++);
1349 dev_err(&pdev->dev, "failed to parse function\n");
1358 static int at91_pinctrl_probe(struct platform_device *pdev)
1360 struct at91_pinctrl *info;
1361 struct pinctrl_pin_desc *pdesc;
1362 int ret, i, j, k, ngpio_chips_enabled = 0;
1364 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1368 ret = at91_pinctrl_probe_dt(pdev, info);
1373 * We need all the GPIO drivers to probe FIRST, or we will not be able
1374 * to obtain references to the struct gpio_chip * for them, and we
1375 * need this to proceed.
1377 for (i = 0; i < gpio_banks; i++)
1379 ngpio_chips_enabled++;
1381 if (ngpio_chips_enabled < info->nactive_banks) {
1382 dev_warn(&pdev->dev,
1383 "All GPIO chips are not registered yet (%d/%d)\n",
1384 ngpio_chips_enabled, info->nactive_banks);
1385 devm_kfree(&pdev->dev, info);
1386 return -EPROBE_DEFER;
1389 at91_pinctrl_desc.name = dev_name(&pdev->dev);
1390 at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1391 at91_pinctrl_desc.pins = pdesc =
1392 devm_kcalloc(&pdev->dev,
1393 at91_pinctrl_desc.npins, sizeof(*pdesc),
1396 if (!at91_pinctrl_desc.pins)
1399 for (i = 0, k = 0; i < gpio_banks; i++) {
1400 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1402 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1407 platform_set_drvdata(pdev, info);
1408 info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc,
1411 if (IS_ERR(info->pctl)) {
1412 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1413 return PTR_ERR(info->pctl);
1416 /* We will handle a range of GPIO pins */
1417 for (i = 0; i < gpio_banks; i++)
1419 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1421 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1426 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1428 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1429 void __iomem *pio = at91_gpio->regbase;
1430 unsigned mask = 1 << offset;
1433 osr = readl_relaxed(pio + PIO_OSR);
1435 return GPIO_LINE_DIRECTION_OUT;
1437 return GPIO_LINE_DIRECTION_IN;
1440 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1442 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1443 void __iomem *pio = at91_gpio->regbase;
1444 unsigned mask = 1 << offset;
1446 writel_relaxed(mask, pio + PIO_ODR);
1450 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1452 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1453 void __iomem *pio = at91_gpio->regbase;
1454 unsigned mask = 1 << offset;
1457 pdsr = readl_relaxed(pio + PIO_PDSR);
1458 return (pdsr & mask) != 0;
1461 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1464 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1465 void __iomem *pio = at91_gpio->regbase;
1466 unsigned mask = 1 << offset;
1468 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1471 static void at91_gpio_set_multiple(struct gpio_chip *chip,
1472 unsigned long *mask, unsigned long *bits)
1474 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1475 void __iomem *pio = at91_gpio->regbase;
1477 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1478 /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1479 uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
1480 uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
1482 writel_relaxed(set_mask, pio + PIO_SODR);
1483 writel_relaxed(clear_mask, pio + PIO_CODR);
1486 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1489 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1490 void __iomem *pio = at91_gpio->regbase;
1491 unsigned mask = 1 << offset;
1493 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1494 writel_relaxed(mask, pio + PIO_OER);
1499 #ifdef CONFIG_DEBUG_FS
1500 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1504 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1505 void __iomem *pio = at91_gpio->regbase;
1506 const char *gpio_label;
1508 for_each_requested_gpio(chip, i, gpio_label) {
1509 unsigned mask = pin_to_mask(i);
1511 mode = at91_gpio->ops->get_periph(pio, mask);
1512 seq_printf(s, "[%s] GPIO%s%d: ",
1513 gpio_label, chip->label, i);
1514 if (mode == AT91_MUX_GPIO) {
1515 seq_printf(s, "[gpio] ");
1516 seq_printf(s, "%s ",
1517 readl_relaxed(pio + PIO_OSR) & mask ?
1518 "output" : "input");
1519 seq_printf(s, "%s\n",
1520 readl_relaxed(pio + PIO_PDSR) & mask ?
1523 seq_printf(s, "[periph %c]\n",
1529 #define at91_gpio_dbg_show NULL
1532 /* Several AIC controller irqs are dispatched through this GPIO handler.
1533 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1534 * at91_set_gpio_input() then maybe enable its glitch filter.
1535 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1537 * First implementation always triggers on rising and falling edges
1538 * whereas the newer PIO3 can be additionally configured to trigger on
1539 * level, edge with any polarity.
1541 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1542 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1543 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1546 static void gpio_irq_mask(struct irq_data *d)
1548 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1549 void __iomem *pio = at91_gpio->regbase;
1550 unsigned mask = 1 << d->hwirq;
1553 writel_relaxed(mask, pio + PIO_IDR);
1556 static void gpio_irq_unmask(struct irq_data *d)
1558 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1559 void __iomem *pio = at91_gpio->regbase;
1560 unsigned mask = 1 << d->hwirq;
1563 writel_relaxed(mask, pio + PIO_IER);
1566 static int gpio_irq_type(struct irq_data *d, unsigned type)
1570 case IRQ_TYPE_EDGE_BOTH:
1577 /* Alternate irq type for PIO3 support */
1578 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1580 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1581 void __iomem *pio = at91_gpio->regbase;
1582 unsigned mask = 1 << d->hwirq;
1585 case IRQ_TYPE_EDGE_RISING:
1586 irq_set_handler_locked(d, handle_simple_irq);
1587 writel_relaxed(mask, pio + PIO_ESR);
1588 writel_relaxed(mask, pio + PIO_REHLSR);
1590 case IRQ_TYPE_EDGE_FALLING:
1591 irq_set_handler_locked(d, handle_simple_irq);
1592 writel_relaxed(mask, pio + PIO_ESR);
1593 writel_relaxed(mask, pio + PIO_FELLSR);
1595 case IRQ_TYPE_LEVEL_LOW:
1596 irq_set_handler_locked(d, handle_level_irq);
1597 writel_relaxed(mask, pio + PIO_LSR);
1598 writel_relaxed(mask, pio + PIO_FELLSR);
1600 case IRQ_TYPE_LEVEL_HIGH:
1601 irq_set_handler_locked(d, handle_level_irq);
1602 writel_relaxed(mask, pio + PIO_LSR);
1603 writel_relaxed(mask, pio + PIO_REHLSR);
1605 case IRQ_TYPE_EDGE_BOTH:
1607 * disable additional interrupt modes:
1608 * fall back to default behavior
1610 irq_set_handler_locked(d, handle_simple_irq);
1611 writel_relaxed(mask, pio + PIO_AIMDR);
1615 pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq);
1619 /* enable additional interrupt modes */
1620 writel_relaxed(mask, pio + PIO_AIMER);
1625 static void gpio_irq_ack(struct irq_data *d)
1627 /* the interrupt is already cleared before by reading ISR */
1630 static u32 wakeups[MAX_GPIO_BANKS];
1631 static u32 backups[MAX_GPIO_BANKS];
1633 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1635 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1636 unsigned bank = at91_gpio->pioc_idx;
1637 unsigned mask = 1 << d->hwirq;
1639 if (unlikely(bank >= MAX_GPIO_BANKS))
1643 wakeups[bank] |= mask;
1645 wakeups[bank] &= ~mask;
1647 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1652 void at91_pinctrl_gpio_suspend(void)
1656 for (i = 0; i < gpio_banks; i++) {
1662 pio = gpio_chips[i]->regbase;
1664 backups[i] = readl_relaxed(pio + PIO_IMR);
1665 writel_relaxed(backups[i], pio + PIO_IDR);
1666 writel_relaxed(wakeups[i], pio + PIO_IER);
1669 clk_disable_unprepare(gpio_chips[i]->clock);
1671 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1676 void at91_pinctrl_gpio_resume(void)
1680 for (i = 0; i < gpio_banks; i++) {
1686 pio = gpio_chips[i]->regbase;
1689 clk_prepare_enable(gpio_chips[i]->clock);
1691 writel_relaxed(wakeups[i], pio + PIO_IDR);
1692 writel_relaxed(backups[i], pio + PIO_IER);
1696 static void gpio_irq_handler(struct irq_desc *desc)
1698 struct irq_chip *chip = irq_desc_get_chip(desc);
1699 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1700 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
1701 void __iomem *pio = at91_gpio->regbase;
1705 chained_irq_enter(chip, desc);
1707 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1708 * When there are none pending, we're finished unless we need
1709 * to process multiple banks (like ID_PIOCDE on sam9263).
1711 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1713 if (!at91_gpio->next)
1715 at91_gpio = at91_gpio->next;
1716 pio = at91_gpio->regbase;
1717 gpio_chip = &at91_gpio->chip;
1721 for_each_set_bit(n, &isr, BITS_PER_LONG)
1722 generic_handle_domain_irq(gpio_chip->irq.domain, n);
1724 chained_irq_exit(chip, desc);
1725 /* now it may re-trigger */
1728 static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1729 struct at91_gpio_chip *at91_gpio)
1731 struct gpio_chip *gpiochip_prev = NULL;
1732 struct at91_gpio_chip *prev = NULL;
1733 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1734 struct irq_chip *gpio_irqchip;
1735 struct gpio_irq_chip *girq;
1738 gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip),
1743 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1745 gpio_irqchip->name = "GPIO";
1746 gpio_irqchip->irq_ack = gpio_irq_ack;
1747 gpio_irqchip->irq_disable = gpio_irq_mask;
1748 gpio_irqchip->irq_mask = gpio_irq_mask;
1749 gpio_irqchip->irq_unmask = gpio_irq_unmask;
1750 gpio_irqchip->irq_set_wake = pm_ptr(gpio_irq_set_wake);
1751 gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
1753 /* Disable irqs of this PIO controller */
1754 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1757 * Let the generic code handle this edge IRQ, the chained
1758 * handler will perform the actual work of handling the parent
1761 girq = &at91_gpio->chip.irq;
1762 girq->chip = gpio_irqchip;
1763 girq->default_type = IRQ_TYPE_NONE;
1764 girq->handler = handle_edge_irq;
1767 * The top level handler handles one bank of GPIOs, except
1768 * on some SoC it can handle up to three...
1769 * We only set up the handler for the first of the list.
1771 gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1772 if (!gpiochip_prev) {
1773 girq->parent_handler = gpio_irq_handler;
1774 girq->num_parents = 1;
1775 girq->parents = devm_kcalloc(&pdev->dev, 1,
1776 sizeof(*girq->parents),
1780 girq->parents[0] = at91_gpio->pioc_virq;
1784 prev = gpiochip_get_data(gpiochip_prev);
1785 /* we can only have 2 banks before */
1786 for (i = 0; i < 2; i++) {
1790 prev->next = at91_gpio;
1798 /* This structure is replicated for each GPIO block allocated at probe time */
1799 static const struct gpio_chip at91_gpio_template = {
1800 .request = gpiochip_generic_request,
1801 .free = gpiochip_generic_free,
1802 .get_direction = at91_gpio_get_direction,
1803 .direction_input = at91_gpio_direction_input,
1804 .get = at91_gpio_get,
1805 .direction_output = at91_gpio_direction_output,
1806 .set = at91_gpio_set,
1807 .set_multiple = at91_gpio_set_multiple,
1808 .dbg_show = at91_gpio_dbg_show,
1810 .ngpio = MAX_NB_GPIO_PER_BANK,
1813 static const struct of_device_id at91_gpio_of_match[] = {
1814 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1815 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1816 { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
1820 static int at91_gpio_probe(struct platform_device *pdev)
1822 struct device_node *np = pdev->dev.of_node;
1823 struct at91_gpio_chip *at91_chip = NULL;
1824 struct gpio_chip *chip;
1825 struct pinctrl_gpio_range *range;
1828 int alias_idx = of_alias_get_id(np, "gpio");
1832 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1833 if (gpio_chips[alias_idx]) {
1838 irq = platform_get_irq(pdev, 0);
1844 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1850 at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0);
1851 if (IS_ERR(at91_chip->regbase)) {
1852 ret = PTR_ERR(at91_chip->regbase);
1856 at91_chip->ops = (const struct at91_pinctrl_mux_ops *)
1857 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1858 at91_chip->pioc_virq = irq;
1859 at91_chip->pioc_idx = alias_idx;
1861 at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
1862 if (IS_ERR(at91_chip->clock)) {
1863 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1864 ret = PTR_ERR(at91_chip->clock);
1868 ret = clk_prepare_enable(at91_chip->clock);
1870 dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n");
1871 goto clk_enable_err;
1874 at91_chip->chip = at91_gpio_template;
1876 chip = &at91_chip->chip;
1877 chip->label = dev_name(&pdev->dev);
1878 chip->parent = &pdev->dev;
1879 chip->owner = THIS_MODULE;
1880 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1882 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1883 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1884 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1885 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1887 chip->ngpio = ngpio;
1890 names = devm_kcalloc(&pdev->dev, chip->ngpio, sizeof(char *),
1895 goto clk_enable_err;
1898 for (i = 0; i < chip->ngpio; i++)
1899 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1901 chip->names = (const char *const *)names;
1903 range = &at91_chip->range;
1904 range->name = chip->label;
1905 range->id = alias_idx;
1906 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1908 range->npins = chip->ngpio;
1911 ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1913 goto gpiochip_add_err;
1915 ret = gpiochip_add_data(chip, at91_chip);
1917 goto gpiochip_add_err;
1919 gpio_chips[alias_idx] = at91_chip;
1920 gpio_banks = max(gpio_banks, alias_idx + 1);
1922 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1928 clk_disable_unprepare(at91_chip->clock);
1930 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1935 static struct platform_driver at91_gpio_driver = {
1937 .name = "gpio-at91",
1938 .of_match_table = at91_gpio_of_match,
1940 .probe = at91_gpio_probe,
1943 static struct platform_driver at91_pinctrl_driver = {
1945 .name = "pinctrl-at91",
1946 .of_match_table = at91_pinctrl_of_match,
1948 .probe = at91_pinctrl_probe,
1951 static struct platform_driver * const drivers[] = {
1953 &at91_pinctrl_driver,
1956 static int __init at91_pinctrl_init(void)
1958 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1960 arch_initcall(at91_pinctrl_init);