1 // SPDX-License-Identifier: GPL-2.0+
3 * Atmel PIO4 pinctrl driver
5 * Copyright (C) 2016 Atmel Corporation
6 * Wenyou.Yang <wenyou.yang@atmel.com>
11 #include <asm/global_data.h>
12 #include <dm/device-internal.h>
14 #include <dm/pinctrl.h>
15 #include <linux/bitops.h>
17 #include <linux/err.h>
18 #include <dm/uclass-internal.h>
19 #include <mach/atmel_pio4.h>
21 DECLARE_GLOBAL_DATA_PTR;
25 * In order to not introduce confusion between Atmel PIO groups and pinctrl
26 * framework groups, Atmel PIO groups will be called banks.
29 struct atmel_pio4_plat {
30 struct atmel_pio4_port *reg_base;
31 unsigned int slew_rate_support;
35 * Table keeping track of the pinctrl driver's slew rate support and the
36 * corresponding index into the struct udevice_id of the gpio_atmel_pio4 GPIO
37 * driver. This has been done in order to align the DT of U-Boot with the DT of
38 * Linux. In Linux, a phandle from a '-gpio' DT property is linked to the
39 * pinctrl driver, unlike U-Boot which redirects this phandle to a corresponding
40 * UCLASS_GPIO driver. Thus, in order to link the two, a hook to the bind method
41 * of the pinctrl driver in U-Boot has been added. This bind method will attach
42 * the GPIO driver to the pinctrl DT node using this table.
43 * @slew_rate_support pinctrl driver's slew rate support
44 * @gdidx index into the GPIO driver's struct udevide_id
45 * (needed in order to properly bind with driver_data)
48 struct atmel_pinctrl_data {
49 unsigned int slew_rate_support;
53 static const struct pinconf_param conf_params[] = {
54 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
55 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
56 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
57 { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
58 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
59 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
60 { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
61 { "atmel,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
62 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0},
65 static u32 atmel_pinctrl_get_pinconf(struct udevice *config,
66 struct atmel_pio4_plat *plat)
68 const struct pinconf_param *params;
69 u32 param, arg, conf = 0;
73 for (i = 0; i < ARRAY_SIZE(conf_params); i++) {
74 params = &conf_params[i];
75 if (!dev_read_prop(config, params->property, NULL))
78 param = params->param;
79 arg = params->default_value;
81 /* Keep slew rate enabled by default. */
82 if (plat->slew_rate_support)
86 case PIN_CONFIG_BIAS_DISABLE:
87 conf &= (~ATMEL_PIO_PUEN_MASK);
88 conf &= (~ATMEL_PIO_PDEN_MASK);
90 case PIN_CONFIG_BIAS_PULL_UP:
91 conf |= ATMEL_PIO_PUEN_MASK;
93 case PIN_CONFIG_BIAS_PULL_DOWN:
94 conf |= ATMEL_PIO_PDEN_MASK;
96 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
98 conf &= (~ATMEL_PIO_OPD_MASK);
100 conf |= ATMEL_PIO_OPD_MASK;
102 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
104 conf |= ATMEL_PIO_SCHMITT_MASK;
106 conf &= (~ATMEL_PIO_SCHMITT_MASK);
108 case PIN_CONFIG_INPUT_DEBOUNCE:
110 conf &= (~ATMEL_PIO_IFEN_MASK);
111 conf &= (~ATMEL_PIO_IFSCEN_MASK);
113 conf |= ATMEL_PIO_IFEN_MASK;
114 conf |= ATMEL_PIO_IFSCEN_MASK;
117 case PIN_CONFIG_DRIVE_STRENGTH:
118 dev_read_u32(config, params->property, &val);
119 conf &= (~ATMEL_PIO_DRVSTR_MASK);
120 conf |= (val << ATMEL_PIO_DRVSTR_OFFSET)
121 & ATMEL_PIO_DRVSTR_MASK;
123 case PIN_CONFIG_SLEW_RATE:
124 if (!plat->slew_rate_support)
127 dev_read_u32(config, params->property, &val);
128 /* And disable it if requested. */
130 conf &= ~ATMEL_PIO_SR;
133 printf("%s: Unsupported configuration parameter: %u\n",
142 static inline struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
145 struct atmel_pio4_plat *plat = dev_get_plat(dev);
146 struct atmel_pio4_port *bank_base =
147 (struct atmel_pio4_port *)((u32)plat->reg_base +
148 ATMEL_PIO_BANK_OFFSET * bank);
153 #define MAX_PINMUX_ENTRIES 40
155 static int atmel_process_config_dev(struct udevice *dev, struct udevice *config)
157 struct atmel_pio4_plat *plat = dev_get_plat(dev);
158 int node = dev_of_offset(config);
159 struct atmel_pio4_port *bank_base;
160 u32 offset, func, bank, line;
161 u32 cells[MAX_PINMUX_ENTRIES];
165 conf = atmel_pinctrl_get_pinconf(config, plat);
168 * The only case where this function returns a negative error value
169 * is when there is no "pinmux" property attached to this node
171 count = fdtdec_get_int_array_count(gd->fdt_blob, node, "pinmux",
172 cells, ARRAY_SIZE(cells));
176 if (count > MAX_PINMUX_ENTRIES)
179 for (i = 0 ; i < count; i++) {
180 offset = ATMEL_GET_PIN_NO(cells[i]);
181 func = ATMEL_GET_PIN_FUNC(cells[i]);
183 bank = ATMEL_PIO_BANK(offset);
184 line = ATMEL_PIO_LINE(offset);
186 bank_base = atmel_pio4_bank_base(dev, bank);
188 writel(BIT(line), &bank_base->mskr);
189 conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
190 conf |= (func & ATMEL_PIO_CFGR_FUNC_MASK);
191 writel(conf, &bank_base->cfgr);
197 static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config)
199 int node = dev_of_offset(config);
200 struct udevice *subconfig;
201 int subnode, subnode_count = 0, ret;
204 * If this function returns a negative error code then that means
205 * that either the "pinmux" property of the node is missing, which is
206 * the case for pinctrl nodes that do not have all the pins with the
207 * same configuration and are split in multiple subnodes, or something
208 * else went wrong and we have to stop. For the latter case, it would
209 * mean that the node failed even though it has no subnodes.
211 ret = atmel_process_config_dev(dev, config);
216 * If we reach here, it means that the subnode pinctrl's DT has multiple
217 * subnodes. If it does not, then something else went wrong in the
218 * previous call to atmel_process_config_dev.
220 fdt_for_each_subnode(subnode, gd->fdt_blob, node) {
221 /* Get subnode as an udevice */
222 ret = uclass_find_device_by_of_offset(UCLASS_PINCONFIG, subnode,
228 * If this time the function returns an error code on a subnode
229 * then something is totally wrong so abort.
231 ret = atmel_process_config_dev(dev, subconfig);
239 * If we somehow got here and we do not have any subnodes, abort.
247 const struct pinctrl_ops atmel_pinctrl_ops = {
248 .set_state = atmel_pinctrl_set_state,
251 static int atmel_pinctrl_probe(struct udevice *dev)
253 struct atmel_pio4_plat *plat = dev_get_plat(dev);
254 struct atmel_pinctrl_data *priv = (struct atmel_pinctrl_data *)dev_get_driver_data(dev);
255 fdt_addr_t addr_base;
257 addr_base = dev_read_addr(dev);
258 if (addr_base == FDT_ADDR_T_NONE)
261 plat->reg_base = (struct atmel_pio4_port *)addr_base;
262 plat->slew_rate_support = priv->slew_rate_support;
267 static int atmel_pinctrl_bind(struct udevice *dev)
271 ofnode node = dev_ofnode(dev);
272 struct atmel_pinctrl_data *priv = (struct atmel_pinctrl_data *)dev_get_driver_data(dev);
274 if (!IS_ENABLED(CONFIG_ATMEL_PIO4))
277 /* Obtain a handle to the GPIO driver */
278 drv = lists_driver_lookup_name("gpio_atmel_pio4");
283 * Bind the GPIO driver to the pinctrl DT node, together
284 * with its corresponding driver_data.
286 return device_bind_with_driver_data(dev, drv, drv->name,
287 drv->of_match[priv->gdidx].data,
291 static const struct atmel_pinctrl_data atmel_sama5d2_pinctrl_data = {
295 static const struct atmel_pinctrl_data microchip_sama7g5_pinctrl_data = {
296 .slew_rate_support = 1,
300 static const struct udevice_id atmel_pinctrl_match[] = {
301 { .compatible = "atmel,sama5d2-pinctrl",
302 .data = (ulong)&atmel_sama5d2_pinctrl_data, },
303 { .compatible = "microchip,sama7g5-pinctrl",
304 .data = (ulong)µchip_sama7g5_pinctrl_data, },
308 U_BOOT_DRIVER(atmel_pinctrl) = {
309 .name = "pinctrl_atmel_pio4",
310 .id = UCLASS_PINCTRL,
311 .of_match = atmel_pinctrl_match,
312 .bind = atmel_pinctrl_bind,
313 .probe = atmel_pinctrl_probe,
314 .plat_auto = sizeof(struct atmel_pio4_plat),
315 .ops = &atmel_pinctrl_ops,