1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
8 #include <dm/device_compat.h>
11 #include <linux/err.h>
13 #include <dm/pinctrl.h>
15 #include "pinctrl-mxs.h"
17 DECLARE_GLOBAL_DATA_PTR;
19 struct mxs_pinctrl_priv {
21 const struct mxs_regs *regs;
24 static unsigned long mxs_dt_node_to_map(struct udevice *conf)
26 unsigned long config = 0;
30 ret = dev_read_u32(conf, "fsl,drive-strength", &val);
32 config = val | MA_PRESENT;
34 ret = dev_read_u32(conf, "fsl,voltage", &val);
36 config |= val << VOL_SHIFT | VOL_PRESENT;
38 ret = dev_read_u32(conf, "fsl,pull-up", &val);
40 config |= val << PULL_SHIFT | PULL_PRESENT;
45 static int mxs_pinctrl_set_mux(struct udevice *dev, u32 val, int bank, int pin)
47 struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
48 int muxsel = MUXID_TO_MUXSEL(val), shift;
51 reg = iomux->base + iomux->regs->muxsel;
52 reg += bank * 0x20 + pin / 16 * 0x10;
55 mxs_pinctrl_rmwl(muxsel, 0x3, shift, reg);
56 debug(" mux %d,", muxsel);
61 static int mxs_pinctrl_set_state(struct udevice *dev, struct udevice *conf)
63 struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
64 u32 *pin_data, val, ma, vol, pull;
65 int npins, size, i, ret;
68 debug("\n%s: set state: %s\n", __func__, conf->name);
70 size = dev_read_size(conf, "fsl,pinmux-ids");
74 if (!size || size % sizeof(int)) {
75 dev_err(dev, "Invalid fsl,pinmux-ids property in %s\n",
80 npins = size / sizeof(int);
82 pin_data = devm_kzalloc(dev, size, 0);
86 ret = dev_read_u32_array(conf, "fsl,pinmux-ids", pin_data, npins);
88 dev_err(dev, "Error reading pin data.\n");
89 devm_kfree(dev, pin_data);
93 config = mxs_dt_node_to_map(conf);
95 ma = CONFIG_TO_MA(config);
96 vol = CONFIG_TO_VOL(config);
97 pull = CONFIG_TO_PULL(config);
99 for (i = 0; i < npins; i++) {
100 int pinid, bank, pin, shift;
105 pinid = MUXID_TO_PINID(val);
106 bank = PINID_TO_BANK(pinid);
107 pin = PINID_TO_PIN(pinid);
109 debug("(val: 0x%x) pin %d,", val, pinid);
111 mxs_pinctrl_set_mux(dev, val, bank, pin);
113 debug(" ma: %d, vol: %d, pull: %d\n", ma, vol, pull);
116 reg = iomux->base + iomux->regs->drive;
117 reg += bank * 0x40 + pin / 8 * 0x10;
120 if (config & MA_PRESENT) {
122 mxs_pinctrl_rmwl(ma, 0x3, shift, reg);
126 if (config & VOL_PRESENT) {
127 shift = pin % 8 * 4 + 2;
129 writel(1 << shift, reg + SET);
131 writel(1 << shift, reg + CLR);
135 if (config & PULL_PRESENT) {
136 reg = iomux->base + iomux->regs->pull;
140 writel(1 << shift, reg + SET);
142 writel(1 << shift, reg + CLR);
146 devm_kfree(dev, pin_data);
150 static struct pinctrl_ops mxs_pinctrl_ops = {
151 .set_state = mxs_pinctrl_set_state,
154 static int mxs_pinctrl_probe(struct udevice *dev)
156 struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
158 iomux->base = dev_read_addr_ptr(dev);
159 iomux->regs = (struct mxs_regs *)dev_get_driver_data(dev);
164 static const struct mxs_regs imx23_regs = {
170 static const struct mxs_regs imx28_regs = {
176 static const struct udevice_id mxs_pinctrl_match[] = {
177 { .compatible = "fsl,imx23-pinctrl", .data = (ulong)&imx23_regs },
178 { .compatible = "fsl,imx28-pinctrl", .data = (ulong)&imx28_regs },
182 U_BOOT_DRIVER(mxs_pinctrl) = {
183 .name = "mxs-pinctrl",
184 .id = UCLASS_PINCTRL,
185 .of_match = of_match_ptr(mxs_pinctrl_match),
186 .probe = mxs_pinctrl_probe,
187 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
188 .bind = dm_scan_fdt_dev,
190 .priv_auto_alloc_size = sizeof(struct mxs_pinctrl_priv),
191 .ops = &mxs_pinctrl_ops,