2 * Copyright (C) ST-Ericsson SA 2013
4 * Author: Patrice Chotard <patrice.chotard@st.com>
5 * License terms: GNU General Public License (GPL) version 2
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/types.h>
13 #include <linux/slab.h>
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/err.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/gpio.h>
21 #include <linux/irq.h>
22 #include <linux/irqdomain.h>
23 #include <linux/interrupt.h>
24 #include <linux/bitops.h>
25 #include <linux/mfd/abx500.h>
26 #include <linux/mfd/abx500/ab8500.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/pinctrl/machine.h>
34 #include "pinctrl-abx500.h"
36 #include "../pinconf.h"
37 #include "../pinctrl-utils.h"
40 * The AB9540 and AB8540 GPIO support are extended versions
41 * of the AB8500 GPIO support.
42 * The AB9540 supports an additional (7th) register so that
43 * more GPIO may be configured and used.
44 * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
45 * internal pull-up and pull-down capabilities.
49 * GPIO registers offset
52 #define AB8500_GPIO_SEL1_REG 0x00
53 #define AB8500_GPIO_SEL2_REG 0x01
54 #define AB8500_GPIO_SEL3_REG 0x02
55 #define AB8500_GPIO_SEL4_REG 0x03
56 #define AB8500_GPIO_SEL5_REG 0x04
57 #define AB8500_GPIO_SEL6_REG 0x05
58 #define AB9540_GPIO_SEL7_REG 0x06
60 #define AB8500_GPIO_DIR1_REG 0x10
61 #define AB8500_GPIO_DIR2_REG 0x11
62 #define AB8500_GPIO_DIR3_REG 0x12
63 #define AB8500_GPIO_DIR4_REG 0x13
64 #define AB8500_GPIO_DIR5_REG 0x14
65 #define AB8500_GPIO_DIR6_REG 0x15
66 #define AB9540_GPIO_DIR7_REG 0x16
68 #define AB8500_GPIO_OUT1_REG 0x20
69 #define AB8500_GPIO_OUT2_REG 0x21
70 #define AB8500_GPIO_OUT3_REG 0x22
71 #define AB8500_GPIO_OUT4_REG 0x23
72 #define AB8500_GPIO_OUT5_REG 0x24
73 #define AB8500_GPIO_OUT6_REG 0x25
74 #define AB9540_GPIO_OUT7_REG 0x26
76 #define AB8500_GPIO_PUD1_REG 0x30
77 #define AB8500_GPIO_PUD2_REG 0x31
78 #define AB8500_GPIO_PUD3_REG 0x32
79 #define AB8500_GPIO_PUD4_REG 0x33
80 #define AB8500_GPIO_PUD5_REG 0x34
81 #define AB8500_GPIO_PUD6_REG 0x35
82 #define AB9540_GPIO_PUD7_REG 0x36
84 #define AB8500_GPIO_IN1_REG 0x40
85 #define AB8500_GPIO_IN2_REG 0x41
86 #define AB8500_GPIO_IN3_REG 0x42
87 #define AB8500_GPIO_IN4_REG 0x43
88 #define AB8500_GPIO_IN5_REG 0x44
89 #define AB8500_GPIO_IN6_REG 0x45
90 #define AB9540_GPIO_IN7_REG 0x46
91 #define AB8540_GPIO_VINSEL_REG 0x47
92 #define AB8540_GPIO_PULL_UPDOWN_REG 0x48
93 #define AB8500_GPIO_ALTFUN_REG 0x50
94 #define AB8540_GPIO_PULL_UPDOWN_MASK 0x03
95 #define AB8540_GPIO_VINSEL_MASK 0x03
96 #define AB8540_GPIOX_VBAT_START 51
97 #define AB8540_GPIOX_VBAT_END 54
99 #define ABX500_GPIO_INPUT 0
100 #define ABX500_GPIO_OUTPUT 1
102 struct abx500_pinctrl {
104 struct pinctrl_dev *pctldev;
105 struct abx500_pinctrl_soc_data *soc;
106 struct gpio_chip chip;
107 struct ab8500 *parent;
108 struct abx500_gpio_irq_cluster *irq_cluster;
109 int irq_cluster_size;
113 * to_abx500_pinctrl() - get the pointer to abx500_pinctrl
114 * @chip: Member of the structure abx500_pinctrl
116 static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip)
118 return container_of(chip, struct abx500_pinctrl, chip);
121 static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
122 unsigned offset, bool *bit)
124 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
130 ret = abx500_get_register_interruptible(pct->dev,
131 AB8500_MISC, reg, &val);
133 *bit = !!(val & BIT(pos));
137 "%s read reg =%x, offset=%x failed (%d)\n",
138 __func__, reg, offset, ret);
143 static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
144 unsigned offset, int val)
146 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
151 ret = abx500_mask_and_set_register_interruptible(pct->dev,
152 AB8500_MISC, reg, BIT(pos), val << pos);
154 dev_err(pct->dev, "%s write reg, %x offset %x failed (%d)\n",
155 __func__, reg, offset, ret);
161 * abx500_gpio_get() - Get the particular GPIO value
163 * @offset: GPIO number to read
165 static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
167 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
170 u8 gpio_offset = offset - 1;
173 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
174 gpio_offset, &is_out);
179 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG,
182 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
186 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
193 static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
195 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
198 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
200 dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret);
203 static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset,
204 enum abx500_gpio_pull_updown *pull_updown)
209 struct pullud *pullud;
211 if (!pct->soc->pullud) {
212 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
218 pullud = pct->soc->pullud;
220 if ((offset < pullud->first_pin)
221 || (offset > pullud->last_pin)) {
226 ret = abx500_get_register_interruptible(pct->dev,
227 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val);
229 pos = (offset - pullud->first_pin) << 1;
230 *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK;
234 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
239 static int abx500_set_pull_updown(struct abx500_pinctrl *pct,
240 int offset, enum abx500_gpio_pull_updown val)
244 struct pullud *pullud;
246 if (!pct->soc->pullud) {
247 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
253 pullud = pct->soc->pullud;
255 if ((offset < pullud->first_pin)
256 || (offset > pullud->last_pin)) {
260 pos = (offset - pullud->first_pin) << 1;
262 ret = abx500_mask_and_set_register_interruptible(pct->dev,
263 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
264 AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos);
268 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
273 static bool abx500_pullud_supported(struct gpio_chip *chip, unsigned gpio)
275 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
276 struct pullud *pullud = pct->soc->pullud;
279 gpio >= pullud->first_pin &&
280 gpio <= pullud->last_pin);
283 static int abx500_gpio_direction_output(struct gpio_chip *chip,
287 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
291 /* set direction as output */
292 ret = abx500_gpio_set_bits(chip,
293 AB8500_GPIO_DIR1_REG,
299 /* disable pull down */
300 ret = abx500_gpio_set_bits(chip,
301 AB8500_GPIO_PUD1_REG,
303 ABX500_GPIO_PULL_NONE);
307 /* if supported, disable both pull down and pull up */
309 if (abx500_pullud_supported(chip, gpio)) {
310 ret = abx500_set_pull_updown(pct,
312 ABX500_GPIO_PULL_NONE);
316 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
320 /* set the output as 1 or 0 */
321 return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
324 static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
326 /* set the register as input */
327 return abx500_gpio_set_bits(chip,
328 AB8500_GPIO_DIR1_REG,
333 static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
335 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
336 /* The AB8500 GPIO numbers are off by one */
337 int gpio = offset + 1;
341 for (i = 0; i < pct->irq_cluster_size; i++) {
342 struct abx500_gpio_irq_cluster *cluster =
343 &pct->irq_cluster[i];
345 if (gpio >= cluster->start && gpio <= cluster->end) {
347 * The ABx500 GPIO's associated IRQs are clustered together
348 * throughout the interrupt numbers at irregular intervals.
349 * To solve this quandry, we have placed the read-in values
350 * into the cluster information table.
352 hwirq = gpio - cluster->start + cluster->to_irq;
353 return irq_create_mapping(pct->parent->domain, hwirq);
360 static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
361 unsigned gpio, int alt_setting)
363 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
364 struct alternate_functions af = pct->soc->alternate_functions[gpio];
369 const char *modes[] = {
370 [ABX500_DEFAULT] = "default",
371 [ABX500_ALT_A] = "altA",
372 [ABX500_ALT_B] = "altB",
373 [ABX500_ALT_C] = "altC",
377 if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) ||
378 ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) ||
379 ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) {
380 dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio,
385 /* on ABx5xx, there is no GPIO0, so adjust the offset */
388 switch (alt_setting) {
391 * for ABx5xx family, default mode is always selected by
392 * writing 0 to GPIOSELx register, except for pins which
393 * support at least ALT_B mode, default mode is selected
394 * by writing 1 to GPIOSELx register
397 if (af.alt_bit1 != UNUSED)
400 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
406 * for ABx5xx family, alt_a mode is always selected by
407 * writing 1 to GPIOSELx register, except for pins which
408 * support at least ALT_B mode, alt_a mode is selected
409 * by writing 0 to GPIOSELx register and 0 in ALTFUNC
412 if (af.alt_bit1 != UNUSED) {
413 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
418 ret = abx500_gpio_set_bits(chip,
419 AB8500_GPIO_ALTFUN_REG,
421 !!(af.alta_val & BIT(0)));
425 if (af.alt_bit2 != UNUSED)
426 ret = abx500_gpio_set_bits(chip,
427 AB8500_GPIO_ALTFUN_REG,
429 !!(af.alta_val & BIT(1)));
431 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
436 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
441 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
442 af.alt_bit1, !!(af.altb_val & BIT(0)));
446 if (af.alt_bit2 != UNUSED)
447 ret = abx500_gpio_set_bits(chip,
448 AB8500_GPIO_ALTFUN_REG,
450 !!(af.altb_val & BIT(1)));
454 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
459 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
460 af.alt_bit2, !!(af.altc_val & BIT(0)));
464 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
465 af.alt_bit2, !!(af.altc_val & BIT(1)));
469 dev_dbg(pct->dev, "unknown alt_setting %d\n", alt_setting);
475 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
480 static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
487 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
488 struct alternate_functions af = pct->soc->alternate_functions[gpio];
489 /* on ABx5xx, there is no GPIO0, so adjust the offset */
490 unsigned offset = gpio - 1;
494 * if gpiosel_bit is set to unused,
495 * it means no GPIO or special case
497 if (af.gpiosel_bit == UNUSED)
498 return ABX500_DEFAULT;
500 /* read GpioSelx register */
501 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8),
502 af.gpiosel_bit, &bit_mode);
509 if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) ||
510 (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) {
512 "alt_bitX value not in correct range (-1 to 7)\n");
516 /* if alt_bit2 is used, alt_bit1 must be used too */
517 if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
519 "if alt_bit2 is used, alt_bit1 can't be unused\n");
523 /* check if pin use AlternateFunction register */
524 if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED))
527 * if pin GPIOSEL bit is set and pin supports alternate function,
528 * it means DEFAULT mode
531 return ABX500_DEFAULT;
534 * pin use the AlternatFunction register
535 * read alt_bit1 value
537 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
538 af.alt_bit1, &alt_bit1);
542 if (af.alt_bit2 != UNUSED) {
543 /* read alt_bit2 value */
544 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
552 mode = (alt_bit2 << 1) + alt_bit1;
553 if (mode == af.alta_val)
555 else if (mode == af.altb_val)
561 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
565 #ifdef CONFIG_DEBUG_FS
567 #include <linux/seq_file.h>
569 static void abx500_gpio_dbg_show_one(struct seq_file *s,
570 struct pinctrl_dev *pctldev,
571 struct gpio_chip *chip,
572 unsigned offset, unsigned gpio)
574 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
575 const char *label = gpiochip_is_requested(chip, offset - 1);
576 u8 gpio_offset = offset - 1;
580 enum abx500_gpio_pull_updown pud = 0;
583 const char *modes[] = {
584 [ABX500_DEFAULT] = "default",
585 [ABX500_ALT_A] = "altA",
586 [ABX500_ALT_B] = "altB",
587 [ABX500_ALT_C] = "altC",
590 const char *pull_up_down[] = {
591 [ABX500_GPIO_PULL_DOWN] = "pull down",
592 [ABX500_GPIO_PULL_NONE] = "pull none",
593 [ABX500_GPIO_PULL_NONE + 1] = "pull none",
594 [ABX500_GPIO_PULL_UP] = "pull up",
597 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
598 gpio_offset, &is_out);
602 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s",
603 gpio, label ?: "(none)",
604 is_out ? "out" : "in ");
607 if (abx500_pullud_supported(chip, offset)) {
608 ret = abx500_get_pull_updown(pct, offset, &pud);
612 seq_printf(s, " %-9s", pull_up_down[pud]);
614 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG,
619 seq_printf(s, " %-9s", pull_up_down[pd]);
622 seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo");
624 mode = abx500_get_mode(pctldev, chip, offset);
626 seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]);
630 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
633 static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
636 unsigned gpio = chip->base;
637 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
638 struct pinctrl_dev *pctldev = pct->pctldev;
640 for (i = 0; i < chip->ngpio; i++, gpio++) {
641 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
642 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
648 static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
649 struct pinctrl_dev *pctldev,
650 struct gpio_chip *chip,
651 unsigned offset, unsigned gpio)
654 #define abx500_gpio_dbg_show NULL
657 static struct gpio_chip abx500gpio_chip = {
658 .label = "abx500-gpio",
659 .owner = THIS_MODULE,
660 .request = gpiochip_generic_request,
661 .free = gpiochip_generic_free,
662 .direction_input = abx500_gpio_direction_input,
663 .get = abx500_gpio_get,
664 .direction_output = abx500_gpio_direction_output,
665 .set = abx500_gpio_set,
666 .to_irq = abx500_gpio_to_irq,
667 .dbg_show = abx500_gpio_dbg_show,
670 static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
672 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
674 return pct->soc->nfunctions;
677 static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
680 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
682 return pct->soc->functions[function].name;
685 static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
687 const char * const **groups,
688 unsigned * const num_groups)
690 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
692 *groups = pct->soc->functions[function].groups;
693 *num_groups = pct->soc->functions[function].ngroups;
698 static int abx500_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
701 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
702 struct gpio_chip *chip = &pct->chip;
703 const struct abx500_pingroup *g;
707 g = &pct->soc->groups[group];
708 if (g->altsetting < 0)
711 dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins);
713 for (i = 0; i < g->npins; i++) {
714 dev_dbg(pct->dev, "setting pin %d to altsetting %d\n",
715 g->pins[i], g->altsetting);
717 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
721 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
726 static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
727 struct pinctrl_gpio_range *range,
730 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
731 const struct abx500_pinrange *p;
736 * Different ranges have different ways to enable GPIO function on a
737 * pin, so refer back to our local range type, where we handily define
738 * what altfunc enables GPIO for a certain pin.
740 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
741 p = &pct->soc->gpio_ranges[i];
742 if ((offset >= p->offset) &&
743 (offset < (p->offset + p->npins)))
747 if (i == pct->soc->gpio_num_ranges) {
748 dev_err(pct->dev, "%s failed to locate range\n", __func__);
752 dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n",
755 ret = abx500_set_mode(pct->pctldev, &pct->chip,
758 dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
763 static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
764 struct pinctrl_gpio_range *range,
769 static const struct pinmux_ops abx500_pinmux_ops = {
770 .get_functions_count = abx500_pmx_get_funcs_cnt,
771 .get_function_name = abx500_pmx_get_func_name,
772 .get_function_groups = abx500_pmx_get_func_groups,
773 .set_mux = abx500_pmx_set,
774 .gpio_request_enable = abx500_gpio_request_enable,
775 .gpio_disable_free = abx500_gpio_disable_free,
778 static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
780 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
782 return pct->soc->ngroups;
785 static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
788 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
790 return pct->soc->groups[selector].name;
793 static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
795 const unsigned **pins,
798 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
800 *pins = pct->soc->groups[selector].pins;
801 *num_pins = pct->soc->groups[selector].npins;
806 static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
807 struct seq_file *s, unsigned offset)
809 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
810 struct gpio_chip *chip = &pct->chip;
812 abx500_gpio_dbg_show_one(s, pctldev, chip, offset,
813 chip->base + offset - 1);
816 static int abx500_dt_add_map_mux(struct pinctrl_map **map,
817 unsigned *reserved_maps,
818 unsigned *num_maps, const char *group,
819 const char *function)
821 if (*num_maps == *reserved_maps)
824 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
825 (*map)[*num_maps].data.mux.group = group;
826 (*map)[*num_maps].data.mux.function = function;
832 static int abx500_dt_add_map_configs(struct pinctrl_map **map,
833 unsigned *reserved_maps,
834 unsigned *num_maps, const char *group,
835 unsigned long *configs, unsigned num_configs)
837 unsigned long *dup_configs;
839 if (*num_maps == *reserved_maps)
842 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
847 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
849 (*map)[*num_maps].data.configs.group_or_pin = group;
850 (*map)[*num_maps].data.configs.configs = dup_configs;
851 (*map)[*num_maps].data.configs.num_configs = num_configs;
857 static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev,
858 const char *pin_name)
861 struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
863 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
864 for (i = 0; i < npct->soc->npins; i++)
865 if (npct->soc->pins[i].number == pin_number)
866 return npct->soc->pins[i].name;
870 static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
871 struct device_node *np,
872 struct pinctrl_map **map,
873 unsigned *reserved_maps,
877 const char *function = NULL;
878 unsigned long *configs;
879 unsigned int nconfigs = 0;
880 struct property *prop;
882 ret = of_property_read_string(np, "function", &function);
886 ret = of_property_count_strings(np, "groups");
890 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
895 of_property_for_each_string(np, "groups", prop, group) {
896 ret = abx500_dt_add_map_mux(map, reserved_maps,
897 num_maps, group, function);
903 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &nconfigs);
905 const char *gpio_name;
908 ret = of_property_count_strings(np, "pins");
912 ret = pinctrl_utils_reserve_map(pctldev, map,
918 of_property_for_each_string(np, "pins", prop, pin) {
919 gpio_name = abx500_find_pin_name(pctldev, pin);
921 ret = abx500_dt_add_map_configs(map, reserved_maps,
922 num_maps, gpio_name, configs, 1);
932 static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev,
933 struct device_node *np_config,
934 struct pinctrl_map **map, unsigned *num_maps)
936 unsigned reserved_maps;
937 struct device_node *np;
944 for_each_child_of_node(np_config, np) {
945 ret = abx500_dt_subnode_to_map(pctldev, np, map,
946 &reserved_maps, num_maps);
948 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
956 static const struct pinctrl_ops abx500_pinctrl_ops = {
957 .get_groups_count = abx500_get_groups_cnt,
958 .get_group_name = abx500_get_group_name,
959 .get_group_pins = abx500_get_group_pins,
960 .pin_dbg_show = abx500_pin_dbg_show,
961 .dt_node_to_map = abx500_dt_node_to_map,
962 .dt_free_map = pinctrl_utils_dt_free_map,
965 static int abx500_pin_config_get(struct pinctrl_dev *pctldev,
967 unsigned long *config)
972 static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
974 unsigned long *configs,
975 unsigned num_configs)
977 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
978 struct gpio_chip *chip = &pct->chip;
982 enum pin_config_param param;
983 enum pin_config_param argument;
985 for (i = 0; i < num_configs; i++) {
986 param = pinconf_to_config_param(configs[i]);
987 argument = pinconf_to_config_argument(configs[i]);
989 dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n",
991 (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
992 (param == PIN_CONFIG_OUTPUT) ?
993 (argument ? "high" : "low") :
994 (argument ? "pull up" : "pull down"));
996 /* on ABx500, there is no GPIO0, so adjust the offset */
1000 case PIN_CONFIG_BIAS_DISABLE:
1001 ret = abx500_gpio_direction_input(chip, offset);
1005 * Some chips only support pull down, while some
1006 * actually support both pull up and pull down. Such
1007 * chips have a "pullud" range specified for the pins
1008 * that support both features. If the pin is not
1009 * within that range, we fall back to the old bit set
1010 * that only support pull down.
1012 if (abx500_pullud_supported(chip, pin))
1013 ret = abx500_set_pull_updown(pct,
1015 ABX500_GPIO_PULL_NONE);
1017 /* Chip only supports pull down */
1018 ret = abx500_gpio_set_bits(chip,
1019 AB8500_GPIO_PUD1_REG, offset,
1020 ABX500_GPIO_PULL_NONE);
1023 case PIN_CONFIG_BIAS_PULL_DOWN:
1024 ret = abx500_gpio_direction_input(chip, offset);
1028 * if argument = 1 set the pull down
1029 * else clear the pull down
1030 * Some chips only support pull down, while some
1031 * actually support both pull up and pull down. Such
1032 * chips have a "pullud" range specified for the pins
1033 * that support both features. If the pin is not
1034 * within that range, we fall back to the old bit set
1035 * that only support pull down.
1037 if (abx500_pullud_supported(chip, pin))
1038 ret = abx500_set_pull_updown(pct,
1040 argument ? ABX500_GPIO_PULL_DOWN :
1041 ABX500_GPIO_PULL_NONE);
1043 /* Chip only supports pull down */
1044 ret = abx500_gpio_set_bits(chip,
1045 AB8500_GPIO_PUD1_REG,
1047 argument ? ABX500_GPIO_PULL_DOWN :
1048 ABX500_GPIO_PULL_NONE);
1051 case PIN_CONFIG_BIAS_PULL_UP:
1052 ret = abx500_gpio_direction_input(chip, offset);
1056 * if argument = 1 set the pull up
1057 * else clear the pull up
1059 ret = abx500_gpio_direction_input(chip, offset);
1061 * Some chips only support pull down, while some
1062 * actually support both pull up and pull down. Such
1063 * chips have a "pullud" range specified for the pins
1064 * that support both features. If the pin is not
1065 * within that range, do nothing
1067 if (abx500_pullud_supported(chip, pin))
1068 ret = abx500_set_pull_updown(pct,
1070 argument ? ABX500_GPIO_PULL_UP :
1071 ABX500_GPIO_PULL_NONE);
1074 case PIN_CONFIG_OUTPUT:
1075 ret = abx500_gpio_direction_output(chip, offset,
1080 dev_err(chip->dev, "illegal configuration requested\n");
1082 } /* for each config */
1085 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
1090 static const struct pinconf_ops abx500_pinconf_ops = {
1091 .pin_config_get = abx500_pin_config_get,
1092 .pin_config_set = abx500_pin_config_set,
1096 static struct pinctrl_desc abx500_pinctrl_desc = {
1097 .name = "pinctrl-abx500",
1098 .pctlops = &abx500_pinctrl_ops,
1099 .pmxops = &abx500_pinmux_ops,
1100 .confops = &abx500_pinconf_ops,
1101 .owner = THIS_MODULE,
1104 static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
1106 unsigned int lowest = 0;
1107 unsigned int highest = 0;
1108 unsigned int npins = 0;
1112 * Compute number of GPIOs from the last SoC gpio range descriptors
1113 * These ranges may include "holes" but the GPIO number space shall
1114 * still be homogeneous, so we need to detect and account for any
1115 * such holes so that these are included in the number of GPIO pins.
1117 for (i = 0; i < soc->gpio_num_ranges; i++) {
1120 const struct abx500_pinrange *p;
1122 p = &soc->gpio_ranges[i];
1124 gend = p->offset + p->npins - 1;
1127 /* First iteration, set start values */
1131 if (gstart < lowest)
1137 /* this gives the absolute number of pins */
1138 npins = highest - lowest + 1;
1142 static const struct of_device_id abx500_gpio_match[] = {
1143 { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, },
1144 { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
1145 { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
1146 { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
1150 static int abx500_gpio_probe(struct platform_device *pdev)
1152 struct device_node *np = pdev->dev.of_node;
1153 const struct of_device_id *match;
1154 struct abx500_pinctrl *pct;
1155 unsigned int id = -1;
1160 dev_err(&pdev->dev, "gpio dt node missing\n");
1164 pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
1168 "failed to allocate memory for pct\n");
1172 pct->dev = &pdev->dev;
1173 pct->parent = dev_get_drvdata(pdev->dev.parent);
1174 pct->chip = abx500gpio_chip;
1175 pct->chip.dev = &pdev->dev;
1176 pct->chip.base = -1; /* Dynamic allocation */
1178 match = of_match_device(abx500_gpio_match, &pdev->dev);
1180 dev_err(&pdev->dev, "gpio dt not matching\n");
1183 id = (unsigned long)match->data;
1185 /* Poke in other ASIC variants here */
1187 case PINCTRL_AB8500:
1188 abx500_pinctrl_ab8500_init(&pct->soc);
1190 case PINCTRL_AB8540:
1191 abx500_pinctrl_ab8540_init(&pct->soc);
1193 case PINCTRL_AB9540:
1194 abx500_pinctrl_ab9540_init(&pct->soc);
1196 case PINCTRL_AB8505:
1197 abx500_pinctrl_ab8505_init(&pct->soc);
1200 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id);
1205 dev_err(&pdev->dev, "Invalid SOC data\n");
1209 pct->chip.ngpio = abx500_get_gpio_num(pct->soc);
1210 pct->irq_cluster = pct->soc->gpio_irq_cluster;
1211 pct->irq_cluster_size = pct->soc->ngpio_irq_cluster;
1213 ret = gpiochip_add(&pct->chip);
1215 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
1218 dev_info(&pdev->dev, "added gpiochip\n");
1220 abx500_pinctrl_desc.pins = pct->soc->pins;
1221 abx500_pinctrl_desc.npins = pct->soc->npins;
1222 pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct);
1223 if (IS_ERR(pct->pctldev)) {
1225 "could not register abx500 pinctrl driver\n");
1226 ret = PTR_ERR(pct->pctldev);
1229 dev_info(&pdev->dev, "registered pin controller\n");
1231 /* We will handle a range of GPIO pins */
1232 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
1233 const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i];
1235 ret = gpiochip_add_pin_range(&pct->chip,
1236 dev_name(&pdev->dev),
1237 p->offset - 1, p->offset, p->npins);
1242 platform_set_drvdata(pdev, pct);
1243 dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n");
1248 gpiochip_remove(&pct->chip);
1253 * abx500_gpio_remove() - remove Ab8500-gpio driver
1254 * @pdev: Platform device registered
1256 static int abx500_gpio_remove(struct platform_device *pdev)
1258 struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
1260 gpiochip_remove(&pct->chip);
1264 static struct platform_driver abx500_gpio_driver = {
1266 .name = "abx500-gpio",
1267 .of_match_table = abx500_gpio_match,
1269 .probe = abx500_gpio_probe,
1270 .remove = abx500_gpio_remove,
1273 static int __init abx500_gpio_init(void)
1275 return platform_driver_register(&abx500_gpio_driver);
1277 core_initcall(abx500_gpio_init);
1279 MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
1280 MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO");
1281 MODULE_ALIAS("platform:abx500-gpio");
1282 MODULE_LICENSE("GPL v2");