1 /* SPDX-License-Identifier: GPL-2.0+
3 * Pinctrl driver for Nexell SoCs
4 * (C) Copyright 2016 Nexell
5 * Bongyu, KOO <freestyle@nexell.co.kr>
9 #ifndef __PINCTRL_NEXELL_H_
10 #define __PINCTRL_NEXELL_H_
13 * struct nexell_pin_bank_data: represent a controller pin-bank data.
14 * @offset: starting offset of the pin-bank registers.
15 * @nr_pins: number of pins included in this bank.
16 * @name: name to be prefixed for each pin in this pin bank.
18 struct nexell_pin_bank_data {
25 #define NEXELL_PIN_BANK(pins, reg, id) \
33 * struct nexell_pin_ctrl: represent a pin controller.
34 * @pin_banks: list of pin banks included in this controller.
35 * @nr_banks: number of pin banks.
37 struct nexell_pin_ctrl {
38 const struct nexell_pin_bank_data *pin_banks;
43 * struct nexell_pinctrl_priv: nexell pin controller driver private data
44 * @pin_ctrl: pin controller bank information.
45 * @base: base address of the pin controller instance.
47 struct nexell_pinctrl_priv {
48 const struct nexell_pin_ctrl *pin_ctrl;
53 * struct nexell_pinctrl_config_data: configuration for a peripheral.
54 * @offset: offset of the config registers in the controller.
55 * @mask: value of the register to be masked with.
56 * @value: new value to be programmed.
58 struct nexell_pinctrl_config_data {
59 const unsigned int offset;
60 const unsigned int mask;
61 const unsigned int value;
64 unsigned long pin_to_bank_base(struct udevice *dev, const char *pin_name,
66 int nexell_pinctrl_probe(struct udevice *dev);
68 #endif /* __PINCTRL_NEXELL_H_ */